CN118446171A - Automatic inspection method for through hole and connector pin of printed circuit board - Google Patents
Automatic inspection method for through hole and connector pin of printed circuit board Download PDFInfo
- Publication number
- CN118446171A CN118446171A CN202310080554.6A CN202310080554A CN118446171A CN 118446171 A CN118446171 A CN 118446171A CN 202310080554 A CN202310080554 A CN 202310080554A CN 118446171 A CN118446171 A CN 118446171A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- design data
- inspection
- board design
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007689 inspection Methods 0.000 title claims abstract description 206
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000012216 screening Methods 0.000 claims abstract description 22
- 239000011800 void material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002775 capsule Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Structure Of Printed Boards (AREA)
Abstract
A through hole of a printed circuit board and a connector pin automatic checking method relate to the technical field of PCB, which is implemented by a computer device and comprises the following steps: (A) Obtaining at least one target circuit board design data from the plurality of circuit board design data according to the inspection and screening data; (B) Determining that the at least one target circuit board design data corresponds to a type of via group or a type of connector pin; (C) When the type corresponding to the through hole group is judged, generating at least one through hole group inspection result information according to the target circuit board design data and at least one through hole group inspection rule for each target circuit board design data; and (D) when the type corresponding to the connector pin is determined, generating connector pin inspection result information for each target circuit board design data according to the target circuit board design data and a connector pin inspection rule.
Description
Technical Field
The invention relates to the technical field of PCB (printed circuit board), in particular to an automatic inspection method for through holes and connector pins of a printed circuit board.
Background
In a typical printed circuit board (Printed circuit board, PCB) layout (layout), a problem of discontinuous impedance is often caused by touching through holes (via) and connector pins (connector pins), so after the PCB design is completed, SI engineers need to check the through holes and the connector pins in a visual manner to ensure that the through holes and the connector pins are properly designed.
However, the number of through holes and connector pins on the PCB is very large, and the missing situation is unavoidable when the inspection is performed manually.
Disclosure of Invention
Therefore, an object of the present invention is to provide an automatic inspection method for through holes and connector pins of a printed circuit board.
Thus, the present invention provides an automatic inspection method for through holes and connector pins of a printed circuit board, implemented by a computer device, wherein a plurality of circuit board design data, an inspection screening data, at least one through hole group inspection rule and a connector pin inspection rule are stored in the circuit board, wherein the circuit board design data corresponds to a through hole group or a connector pin electrically connected by a differential pair circuit, the inspection screening data includes a designated type, and the designated type is a through hole group type or a connector pin type, the method comprises the following steps: (A) Obtaining at least one piece of target circuit board design data conforming to the inspection screening data from the circuit board design data according to the inspection screening data; (B) Determining that the at least one target circuit board design data corresponds to the via group type or the connector pin type; (C) When it is determined that the at least one target circuit board design data corresponds to the type of the through hole group, generating at least one through hole group inspection result information corresponding to the target circuit board design data according to the target circuit board design data and the at least one through hole group inspection rule for each target circuit board design data, wherein the at least one through hole group inspection result information corresponds to the at least one through hole group inspection rule respectively; and (D) when the at least one target circuit board design data is determined to correspond to the connector pin type, generating connector pin inspection result information corresponding to the target circuit board design data according to the target circuit board design data and the connector pin inspection rule for each target circuit board design data.
Preferably, each circuit board design data further includes an impedance value, the inspection screening data further includes a specified line name and a specified impedance value, wherein in the step (a), the line name of the at least one target circuit board design data includes the specified line name, and the impedance value of the at least one target circuit board design data is the same as the specified impedance value.
Preferably, the computer device further stores a plurality of via group inspection default data corresponding to the via groups, respectively, the computer device stores a via group inspection rule, the via group inspection rule is whether at least one avoidance area size parameter and at least one via center distance of a circuit board design data conform to a target via group inspection default data, each circuit board design data corresponding to the via groups includes at least one through layer number code related to the number of layers through which the differential pair circuit passes, at least one avoidance area size parameter corresponding to the at least one through layer number code, and at least one via center distance corresponding to the at least one through layer number code, each via group inspection default data includes an ideal avoidance area size parameter and an ideal via center distance, wherein the step (C) includes the following steps: (C-1) obtaining at least one target via group inspection default data corresponding to the at least one target circuit board design data, respectively, from the via group inspection default data; and (C-2) comparing, for each target circuit board design data, whether at least one avoidance region size parameter of the target circuit board design data is consistent with an ideal avoidance region size parameter of the target through hole inspection default data, and comparing whether at least one through hole center distance of the target circuit board design data is consistent with an ideal through hole center distance of the target through hole inspection default data, so as to generate through hole group inspection result information.
Preferably, in the substep (C-2), if the at least one avoidance area size parameter is consistent with the ideal avoidance area size parameter and the at least one through hole center distance is consistent with the ideal through hole center distance, the through hole group inspection result information indicates a pass; and if one of the at least one avoidance area size parameter is inconsistent with the ideal avoidance area size parameter or one of the at least one through hole center distances is inconsistent with the ideal through hole center distance, the through hole group inspection result information indicates an error.
Preferably, the computer device stores a through-hole group checking rule, each circuit board setup data includes at least one passing layer number code related to the number of layers passed by the differential pair circuit, a plurality of all layer number codes related to all layer numbers of the printed circuit board, and a plurality of layer number codes located in a clearance area, each all layer number code corresponds to a board layer type, the through-hole group checking rule is a plurality of all layer number codes of circuit board design data, and the layer number codes corresponding to a plurality of through-hole groups check whether the layer number codes of the board layer type are included in the layer number codes located in a plurality of clearance areas of the circuit board design data except at least one passing layer number code of the circuit board design data, wherein the step (C) includes the following sub-steps: (C-1) for each target circuit board design data, subtracting the at least one pass layer number code from the layer number codes of the target circuit board design data to obtain a plurality of candidate inspection layer number codes, and screening a plurality of inspection layer number codes corresponding to the inspection layer types of the through hole group inspection layer types from the candidate inspection layer numbers; and (C-2) for each target circuit board design data, determining whether the inspection layer number codes are included in the layer number codes of the plurality of headroom areas of the target circuit board design data to generate a via group inspection result information.
Preferably, in the substep (C-2), if the number of inspection layers is included in the number of layers code of the headroom, the through-hole group inspection result information indicates a pass, and if the number of inspection layers is not included in the number of layers code of the headroom, the through-hole group inspection result information indicates an error.
Preferably, the computer device further stores a plurality of default data for checking via groups corresponding to the via groups, the computer device stores a first via group checking rule and a second via group checking rule, each circuit board set includes at least one pass layer number code corresponding to the number of the pass layers of the differential pair circuit, a plurality of all layer number codes corresponding to all the layers of the printed circuit board, and a plurality of clear area place layer numbers, each layer number code corresponds to a board layer type, the first via group checking rule is a default data for checking whether at least one avoidance area size parameter and at least one via center distance of one circuit board design data meet a target via group, each circuit board design data corresponding to the via group includes at least one pass layer number code corresponding to the number of the pass layers of the differential pair circuit, at least one avoidance area size parameter corresponding to the at least one pass layer number code, and at least one via center distance corresponding to the at least one pass layer number code, each via group checking rule includes an ideal avoidance area data and a board layer number type, and a plurality of via layer number data include at least one step (the clear area type, the first via group includes a plurality of layer number data and the step C is a plurality of step C, the circuit board design data includes the step C and the step C is included in the ideal layer number code and the step C is included: (C-1) obtaining at least one target via group inspection default data corresponding to the at least one target circuit board design data, respectively, from the via group inspection default data; (C-2) for each target circuit board design data, generating a first via group inspection result information corresponding to the target circuit board design data according to the target circuit board design data, a target via inspection default data corresponding to the target circuit board design data, and the first via group inspection rule; and (C-3) checking default data for each target through hole, and generating second through hole group checking result information corresponding to the target circuit board design data according to the target circuit board design data and the second through hole group checking rule.
Preferably, each circuit board design data includes at least one passing layer number code related to the number of passing layers of the differential pair circuit, a plurality of all layer number codes related to all layer numbers of the printed circuit board, and a plurality of layer number codes located in a headroom region, each of the all layer number codes corresponding to a board layer type, the at least one passing layer number code having a starting point layer number code related to a checking starting point layer number preset for the differential pair circuit, the connector pin checking rule being a plurality of all layer number codes of circuit board design data, a starting point layer number code adjacent to the circuit board design data and conforming to a target all layer number code of a connector pin checking board layer type being included in a plurality of layer number codes located in a headroom region of the circuit board design data, wherein the step (D) includes the following sub steps: (D-1) for each target circuit board design data, obtaining an inspection layer number code adjacent to the starting point layer number code and corresponding to the connector pin inspection board layer type according to the starting point layer number code of the target circuit board design data; and (D-2) for each target circuit board design data, determining whether the inspection layer number codes are included in the layer number codes of the plurality of headroom areas of the target circuit board design data, so as to generate the connector pin inspection result information.
Preferably, in the sub-step (D-2), if the inspection layer number code is included in the layer number code of the headroom areas, the connector pin inspection result information indicates passing, and if the inspection layer number code is not included in the layer number code of the headroom areas, the connector pin inspection result information indicates an error.
The invention has the following effects: the computer device is used for judging that the at least one target circuit board design data corresponds to the type of the through hole group or the type of the connector pin, so that the at least one through hole group inspection result information or the connector pin inspection result information is automatically generated for each target circuit board design data, thereby greatly saving the time of manual inspection and reducing the probability of error occurrence.
Drawings
Other features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the drawings, in which:
FIG. 1 is a block diagram illustrating a computer system for implementing one embodiment of a method for automatically inspecting through-holes and connector pins of a printed circuit board according to the present invention;
FIG. 2 is a flow chart illustrating the embodiment of the method for automatically inspecting through holes and connector pins of a printed circuit board of the present invention;
FIG. 3 is a flow chart that assists in illustrating the sub-steps of step 25 of FIG. 2; and
Fig. 4 is a flowchart that assists in illustrating the sub-steps of step 26 of fig. 2.
The reference numerals in the figures illustrate: 11. a storage unit; 12. a processing unit; 21-26, namely, the steps; 251 and 252, substeps; 261 and 262, substeps.
Detailed Description
Before the present invention is described in detail, it is noted that in the following description, like components are denoted by the same reference numerals.
Referring to fig. 1, a computer system for implementing an embodiment of the method for automatically inspecting through holes and connector pins of a printed circuit board according to the present invention is illustrated, the computer system including a storage unit 11, and a processing unit 12 electrically connected to the storage unit 11. The computer system is, for example, a desktop computer, a tablet computer, a notebook computer, a server, a smart phone, but not limited to, wherein the Through Hole (Via) is a Blind Hole (Blind Via), a buried Hole (Buried Via), a combination of the two (at the same coordinate), or a Through Hole (Through Hole Via), but not limited to the above.
The storage unit 11 stores a plurality of circuit board design data corresponding to a plurality of via groups and a plurality of connector pins, a plurality of via group inspection default data corresponding to the via groups, an inspection screening data, a first via group inspection rule, a second via group inspection rule, and a connector pin inspection rule.
Each circuit board design data corresponds to a set of vias or a connector pin to which a differential pair of wires are electrically connected. Each circuit board set-up data packet comprises a circuit name, an impedance value, coordinate information of the through hole group or the connector pin on the printed circuit board, at least one passing layer number code of the layer number of the differential pair circuit, a plurality of all layer number codes of all layer numbers of the printed circuit board, and a layer number code of a plurality of clearance areas. The at least one pass layer number code has a start point layer number code of an inspection start point layer number preset relative to the differential pair circuit, wherein the inspection start point layer number is an electric connection position between the differential pair circuit and the through hole group or the connector pin.
It should be noted that, since the differential pair circuit is two parallel signal lines with approximately equal length, one signal line transmits a positive signal, and the other signal line transmits a negative signal, each through hole group has a through hole for passing the signal lines.
It should be noted that, in this embodiment, the printed circuit board has 12 layers, and all the layer numbers are, for example, top, L2, L3, L4, L5, L6, L7, L8, L9, L11, and Bottom, each layer number corresponds to a board layer type, for example, a ground layer type, a power layer type, or a trace layer type, where L2 corresponds to a ground layer type, L4 corresponds to a power layer type, top, L3, L5 to L11, and Bottom layers correspond to trace layer types, and in other embodiments, the total layer number of the printed circuit board, and the board layer type corresponding to each layer number are slightly different according to the board layer configuration of each manufacturer, but not limited thereto.
If the circuit board design data corresponds to a through hole group electrically connected with a differential pair circuit, the circuit board design data further comprises at least one avoidance area size parameter corresponding to the at least one passing layer number code and at least one through hole center distance corresponding to the at least one passing layer number code.
The default data of the inspection of the through hole sets corresponds to the through hole sets respectively, and each default data of the inspection of the through hole sets comprises an ideal avoidance area size parameter and an ideal through hole center distance.
It should be noted that, in this embodiment, the avoidance area is in a capsule shape, and the avoidance area size parameter of the design data of the circuit boards and the ideal avoidance area size parameter of the default data of the inspection of the through hole sets are short axes of the avoidance area, but not limited thereto.
The inspection and screening data includes a specified line name, a specified type, and a specified impedance value.
The first through hole group checking rule is whether at least one avoidance area size parameter of circuit board design data and at least one through hole center distance accord with a target through hole group checking default data. The second through hole group checking rule is a number code of a plurality of clearance areas of the circuit board design data, and the number code of the corresponding through hole group checking plate layer type is contained in the number code of the circuit board design data except at least one passing number code of the circuit board design data, wherein the number code of the corresponding through hole group checking plate layer type is at least two of the routing layer type, the power layer type and the grounding layer type according to the impedance value of the corresponding differential pair circuit. In this embodiment, the specified impedance value of the differential pair circuit is 85 ohms, and the corresponding via group inspection board layer types include the power layer type and the ground layer type; in another embodiment, the impedance value corresponding to the differential pair line is 100 ohms, and the via group inspection board layer types corresponding to the differential pair line include all board layer types, that is, the via group inspection board layer types include a trace layer type, a power layer type, and a ground layer type. The connector pin inspection rule is a number code of all layers of circuit board design data, wherein the number code of all layers adjacent to a starting point of the circuit board design data and corresponding to a target number code of all layers of a connector pin inspection board layer type is included in a number code of all headroom areas of the circuit board design data, and the connector pin inspection board layer type is a ground layer.
It should be noted that, in the present embodiment, the circuit board design data is obtained from a circuit board wiring diagram file (PCB layout BRD file), the inspection screening data is set by a user, the user indicates the differential pair circuit to be inspected by setting at least one of a designated circuit name, a designated type, and a designated impedance value, the designated type is a through hole group type or a connector pin type, the clearance area is a clearance area which is located at a layer number other than the layer number of the differential pair circuit and is not provided with conductive material and corresponds to a position for isolating the through hole group or the connector pin, the avoidance area is an isolation area which is located at a layer number of the differential pair circuit and is not provided with conductive material for isolating a pad of the through hole group from other wires or blocks with conductive material, the clearance area and the avoidance area are e.g. an anti-pad (antipad), in other embodiments, the storage unit 11 also stores other circuit board design data which is different from the circuit board design data and is related to a plurality of other circuits other than the differential pair circuit lines, but not limited thereto.
Referring to fig. 1 and 2, the steps involved in the method for automatically inspecting the through-hole and the connector pin of the printed circuit board according to the present invention will be described below.
In step 21, the processing unit 12 obtains at least one target circuit board design data corresponding to the inspection screening data from the circuit board design data according to the inspection screening data.
In step 22, the processing unit 12 determines that the at least one target circuit board design data corresponds to the via group type or the connector pin type. When it is determined that the at least one target circuit board design data corresponds to the type of the through hole group, the flow proceeds to steps 23 and 25; when it is determined that the at least one target circuit board design data corresponds to the connector pin type, the flow proceeds to step 26.
In step 23, the processing unit 12 obtains at least one target via group inspection default data corresponding to the at least one target circuit board design data, respectively, from the via group inspection default data.
In step 24, for each target circuit board design data, the processing unit 12 generates a first through-hole set inspection result information corresponding to the target circuit board design data according to the target circuit board design data, a target through-hole inspection default data corresponding to the target circuit board design data, and the first through-hole set inspection rule.
In detail, for each target circuit board design data, the processing unit 12 compares whether at least one avoidance area size parameter of the target circuit board design data is consistent with an ideal avoidance area size parameter of the target through hole inspection default data, and compares whether at least one through hole center distance of the target circuit board design data is consistent with an ideal through hole center distance of the target through hole inspection default data, so as to generate the first through hole group inspection result information. And if the size parameter of the at least one avoidance area is consistent with the size parameter of the ideal avoidance area, and the center distance of the at least one through hole is consistent with the center distance of the ideal through hole, the first through hole group inspection result information indicates that the first through hole group inspection result information passes. If one of the at least one avoidance area size parameter is inconsistent with the ideal avoidance area size parameter or one of the at least one via center distances is inconsistent with the ideal via center distance, the first via group inspection result information indicates an error, and when the difference between the two is smaller than the error tolerance range during inspection and comparison, the two are still regarded as consistent, for example, if the difference is smaller than 1mil, the two are still judged to be consistent, and the error tolerance range can also be 2mils or 0.5mil, without limitation.
It should be noted that, in step 24, for each target circuit board design data, at least one pass layer number code of the target circuit board design data is the first inspection layer number code.
In step 25, for each target via inspection default data, the processing unit 12 generates a second via group inspection result information corresponding to the target circuit board design data according to the target circuit board design data and the second via group inspection rule.
Referring to fig. 3, step 25 includes the following sub-steps.
In sub-step 251, for each target circuit board design data, the processing unit 12 deducts the at least one pass layer number code from the layer number codes of the target circuit board design data to obtain a plurality of candidate inspection layer number codes, and then screens out a plurality of second inspection layer number codes corresponding to the inspection board layer types of the via group by the candidate inspection layer numbers.
In sub-step 252, for each target circuit board design data, the processing unit 12 determines whether the second inspection layer number codes are included in the layer number codes of the plurality of headroom areas of the target circuit board design data, so as to generate the second via group inspection result information. And if the second inspection layer number codes are not contained in the layer number codes of the clearance areas, the layer numbers corresponding to the second inspection layer number codes do not correspond to the clearance areas, and the second through hole group inspection result information indicates errors.
It should be noted that, in other embodiments, the storage unit 11 may store only the first via group inspection rule or the second via group inspection rule, that is, when it is determined that the at least one target circuit board design data corresponds to the via group type in step 22, the process proceeds to steps 23 and 24 only, generates only the first via group inspection result information, or proceeds to step 25 only, and generates only the second via group inspection result information.
In step 26, for each target circuit board design data, the processing unit 12 generates a connector pin inspection result information corresponding to the target circuit board design data according to the target circuit board design data and the connector pin inspection rule.
Referring to fig. 4, step 26 includes the following substeps.
In sub-step 261, for each target circuit board design data, the processing unit 12 obtains a third inspection layer number code, which is adjacent to the start point layer number code and corresponds to the connector pin inspection board layer type, according to the start point layer number code of the target circuit board design data.
In sub-step 262, for each target circuit board design data, the processing unit 12 determines whether the third inspection layer number code is included in the layer number codes of the plurality of headroom areas of the target circuit board design data to generate the connector pin inspection result information. And if the third checking layer number codes are not contained in the layer number codes of the clearance areas, the layer numbers corresponding to the third checking layer number codes do not correspond to the clearance areas, and the connector pin checking result information indicates errors.
It should be noted that, in the present embodiment, each inspection result information includes coordinate information of the circuit board design data corresponding to the inspection result information, a line name of the circuit board design data corresponding to the inspection result information, a start point layer number code of the circuit board design data corresponding to the inspection result information, at least one inspection layer number code, and an inspection result indicating passing or error, but not limited thereto.
For example, the specified line name of the inspection screening data is, for example, p5e—ssd, the specified type is, for example, a via group, and the specified impedance value is, for example, 85 ohms (a specified impedance value commonly used when differential pair wiring). In step 21, the processing unit 12 obtains a first target circuit board design data and a second target circuit board design data that match the inspection screening data. The circuit name of the first target circuit board design data is p5e_ssd0_rx_d (N/P <2 >), the coordinate information is (1037.35.38.01) and (1058.57.59.23), the passing layer number codes are Bottom and L11, that is, the first inspection layer number codes are Bottom and L11, the starting point layer number codes are Bottom, the layer number codes of the clearance area are Top, L2-10, the size parameters of the avoidance area at the first inspection layer number codes Bottom and L11 are 40mils, The center-to-center distance of the vias was 40mils. The line name of the second target circuit board design data is P5E_SSD0_RX_D (N/P <2 >), the coordinate information is (15243.74.37.74), and (15264.96.96), the number of pass layer code sets are Bottom, L6-7,9,11, that is, the first check layer codes are Bottom, L6-7,9,11, wherein the starting point plate layer codes are Bottom, the number of layers of the clearance area is Top, L2-5, L8, L10, the avoidance area size parameters of the first check layer codes are 40mils, The center-to-center distance of the vias was 40mils. In step 22, the processing unit 12 determines that the first target circuit board design data and the second target circuit board design data correspond to the type of the via group. In step 23, the processing unit 12 obtains first target board design data and second target board design data from the first target board design data and the second target board design data, respectively, the first target board design data and the second target board design data including the same ideal impedance of 85 ohms, an ideal via center distance of 40mils, and an ideal headroom size parameter of 40mils (hereinafter, 85/40/40). In step 24, for the first target circuit board design data, the processing unit 12 compares whether the area size parameters corresponding to the passing layer numbers of codes Bottom and L11 are all 40mils, and compares whether the center distances of the vias corresponding to the passing layer numbers of codes Bottom and L11 are all 40mils, so as to generate a first via group inspection result information (column 2 of table 1 below). Similarly, in step 24, for the second target circuit board design data, the processing unit 12 compares whether the avoidance area size parameters corresponding to the pass-layer numbers of codes Bottom, L6-7,9,11 are all 40mils, and compares whether the center distances of the vias corresponding to the pass-layer numbers of codes Bottom, L6-7,9,11 are all 40mils, so as to generate another first via group inspection result information (column 3 of table 1 below). Wherein ALL LAYERS PASS denotes that all layers examined pass. in step 25, for the first target circuit board design data, the processing unit 12 deducts the pass layer number codes L11 and Bottom from the all layer number codes Top, L2-11 and Bottom to obtain candidate check layer number codes Top, L2-10, and then screens out second check layer number codes L2, L4 corresponding to the through hole group check layer types (the specified impedance value is 85 omm, the corresponding through hole group check type is the ground layer type and the power layer type), and then determines the second check layer number codes L2, L4 is included in the headroom and has a layer number code Top, L2-10, to generate a second via group inspection result message (see Table 1, column 4). Similarly, in step 25, for the second target circuit board design data, the processing unit 12 deducts the pass layer number codes L6-7,9,11 and Bottom from the all layer number codes Top, L2-11 and Bottom to obtain candidate check layer number codes Top, L2-5 and 8, and then screens out the second check layer number codes L2 and L4 corresponding to the via group check layer types (the specified impedance value is 85 omum, the corresponding via group check type is the ground layer type and the power layer type) from the candidate check layer number tops, L2-5 and 8, and then determines the second check layer number codes L2, L4 is included in the headroom and has a layer number code Top, L2-10, to generate another second via group inspection result message (column 5 of Table 1 below).
TABLE 1
| Line name | Initial point layer number code | Coordinate information | Checking layer number codes | Inspection result |
| P5E_SSD0_RX_D(N/P<2>) | Bottom | (1037.35 38.01);(1058.57 59.23) | Bottom, L11 | 85/40/40/All Layers Pass |
| P5E_SSD0_RX_D(N/P<2>) | Bottom | (15243.74 37.74);(15264.96 58.96) | Bottom, L6-7,9,11 | 85/40/40/All Layers Pass |
| P5E_SSD0_RX_D(N/P<2>) | Bottom | (1037.35 38.01);(1058.57 59.23) | L2, 4 | Via Void Pass |
| P5E_SSD0_RX_D(N/P<2>) | Bottom | (15243.74 37.74);(15264.96 58.96) | L2, 4 | Via without Void |
For another example, the specified line name of the inspection screening data is, for example, p5e_ssd11, the specified type is, for example, connector pins, the specified impedance value is, for example, 85 ohms, a third target circuit board design data and a fourth target circuit board design data conforming to the inspection screening data are obtained in step 21. The line name of the third target circuit board design data is p5e_ssd11_c_tx_dn <2>, the coordinate information is (15644.41 626.62), the number of layers codes through the layer code and the start point layer code are Top, and the number of layers codes of the clearance area are L2-11 and Bottom. The line name of the fourth target circuit board design data is p5e_ssd11_c_tx_dp <2>, the coordinate information is (15644.41 626.62), the number of layers codes through the layer code and the start point layer code are Top, and the number of layers codes in the clearance area are L2-11 and Bottom. In step 22, the processing unit 12 determines that the third target circuit board design data and the fourth target circuit board design data correspond to the connector pin type. In step 26, for the third target circuit board design data, the processing unit 12 obtains a third inspection layer number code L2 adjacent to the start point layer number code Top and corresponding to the ground layer type, and determines whether the third inspection layer number code L2 is included in the layer number codes L2-11 and Bottom of the headroom areas to generate a connector pin inspection result information (column 2 of table 2 below). Similarly, in step 26, for the fourth target circuit board design data, the processing unit 12 obtains a third inspection layer number code L2 adjacent to the start point layer number code Top and corresponding to the ground layer type, and determines whether the third inspection layer number code L2 is included in the layer number codes L2-11 and Bottom of the headroom areas to generate another connector pin inspection result information (column 3 of table 2 below).
TABLE 2
| Line name | Initial point layer number code | Coordinate information | Checking layer number codes | Inspection result |
| P5E_SSD11_C_TX_DN<2> | top | (15612.91 626.62) | L2 | SMD Pin without Void |
| P5E_SSD11_C_TX_DP<2> | top | (15644.41 626.62) | L2 | SMD Pin without Void |
In summary, according to the method for automatically inspecting the through holes and the connector pins of the printed circuit board of the present invention, the processing unit 12 determines that the at least one target circuit board design data corresponds to the through hole group type or the connector pin type. When the at least one target circuit board design data corresponds to the type of the through hole group, the processing unit 12 obtains the at least one target through hole group inspection default data, so as to generate at least one first through hole group inspection result information according to the at least one target circuit board design data, the target through hole inspection default data corresponding to the at least one target circuit board design data, and the first through hole group inspection rule, and then generates at least one second through hole group inspection result information according to the at least one target circuit board design data and the second through hole group inspection rule. And when the at least one target circuit board design data corresponds to the connector pin type, generating at least one connector pin inspection result information according to the at least one target circuit board design data and the connector pin inspection rule. Therefore, the processing unit 12 automatically generates the inspection result, so as to save a great deal of time for manual inspection and reduce the probability of error occurrence, thereby truly achieving the purpose of the invention.
However, the foregoing is only illustrative of the present invention and is not to be construed as limiting the scope of the invention, which is defined by the appended claims and their equivalents.
Claims (9)
1. An automatic inspection method for through holes and connector pins of a printed circuit board is implemented by a computer device, wherein a plurality of circuit board design data corresponding to a plurality of through hole groups and a plurality of connector pins respectively, an inspection screening data, at least one through hole group inspection rule and a connector pin inspection rule are stored, each circuit board design data corresponds to a through hole group or a connector pin electrically connected by a differential pair circuit, the inspection screening data comprises a designated type, and the designated type is a through hole group type or a connector pin type, the method comprises the following steps:
(A) Obtaining at least one piece of target circuit board design data conforming to the inspection screening data from the circuit board design data according to the inspection screening data;
(B) Determining that the at least one target circuit board design data corresponds to the via group type or the connector pin type;
(C) When it is determined that the at least one target circuit board design data corresponds to the type of the through hole group, generating at least one through hole group inspection result information corresponding to the target circuit board design data according to the target circuit board design data and the at least one through hole group inspection rule for each target circuit board design data, wherein the at least one through hole group inspection result information corresponds to the at least one through hole group inspection rule respectively; and
(D) When it is determined that the at least one target circuit board design data corresponds to the connector pin type, for each target circuit board design data, connector pin inspection result information corresponding to the target circuit board design data is generated according to the target circuit board design data and the connector pin inspection rule.
2. The method of claim 1, wherein each circuit board design data further comprises an impedance value, the inspection and screening data further comprises a specified circuit name and a specified impedance value, wherein in step (a), the circuit name of the at least one target circuit board design data comprises the specified circuit name, and the impedance value of the at least one target circuit board design data is the same as the specified impedance value.
3. The method of claim 1, wherein the computer device further stores a plurality of via group inspection default data corresponding to the via groups, respectively, the computer device stores a via group inspection rule, the via group inspection rule being whether at least one avoidance area size parameter and at least one via center distance of a circuit board design data conform to a target via group inspection default data, each of the circuit board design data corresponding to the via groups includes at least one pass layer number code related to a number of layers passed by the differential pair circuit, at least one avoidance area size parameter corresponding to the at least one pass layer number code, respectively, and at least one via center distance corresponding to the at least one pass layer number code, each of the via group inspection default data includes an ideal area size parameter, and an ideal via center distance, wherein the step (C) includes the sub-steps of:
(C-1) obtaining at least one target via group inspection default data corresponding to the at least one target circuit board design data, respectively, from the via group inspection default data; and
(C-2) for each target circuit board design data, comparing whether at least one avoidance area size parameter of the target circuit board design data is identical to an ideal avoidance area size parameter of the target through-hole inspection default data, and comparing whether at least one through-hole center distance of the target circuit board design data is identical to an ideal through-hole center distance of the target through-hole inspection default data, to generate a through-hole group inspection result information.
4. The method according to claim 3, wherein in the substep (C-2), if the at least one avoidance area size parameter is identical to the ideal avoidance area size parameter and the at least one through hole center distance is identical to the ideal through hole center distance, the through hole group inspection result information indicates a pass; and if one of the at least one avoidance area size parameter is inconsistent with the ideal avoidance area size parameter or one of the at least one through hole center distances is inconsistent with the ideal through hole center distance, the through hole group inspection result information indicates an error.
5. The method of claim 1, wherein the computer device stores a through-hole group inspection rule, each circuit board set data includes at least one pass layer number code related to the number of layers passed by the differential pair line, a plurality of all layer number codes related to all layer numbers of the printed circuit board, and a plurality of headroom region layer number codes, each of the all layer number codes corresponds to a board layer type, the through-hole group inspection rule is a layer number code of all layer numbers of a circuit board design data, and the layer number codes of the board layer type are inspected by the corresponding plurality of through-hole groups in addition to at least one pass layer number code of the circuit board design data, wherein the step (C) includes the following sub-steps:
(C-1) for each target circuit board design data, subtracting the at least one pass layer number code from the layer number codes of the target circuit board design data to obtain a plurality of candidate inspection layer number codes, and screening a plurality of inspection layer number codes corresponding to the inspection layer types of the through hole group inspection layer types from the candidate inspection layer numbers; and
(C-2) for each target circuit board design data, determining whether the inspection layer number codes are included in the layer number codes of the plurality of headroom areas of the target circuit board design data to generate a via group inspection result information.
6. The method according to claim 5, wherein in the sub-step (C-2), if the inspection layer number codes are included in the layer number codes of the headroom regions, the through-hole group inspection result information indicates pass, and if the inspection layer number codes are not included in the layer number codes of the headroom regions, the through-hole group inspection result information indicates error.
7. The method of claim 1, wherein the computer device further stores a plurality of default data for checking via groups corresponding to the via groups, the computer device stores a first via group checking rule and a second via group checking rule, each circuit board set includes at least one pass layer number code corresponding to the number of pass layers of the differential pair circuit, a plurality of all layer number codes corresponding to all layer numbers of the printed circuit board, and a plurality of clear zone place layer numbers, each layer number code corresponds to a layer type, the first via group checking rule is a default data for checking whether at least one avoidance zone size parameter and at least one via center distance of a circuit board design data meet a target via group, each circuit board design data corresponding to the via groups includes at least one pass layer number code corresponding to the number of pass layers of the differential pair circuit, at least one region size parameter corresponding to the at least one pass layer number code, and at least one ideal layer number code corresponding to the at least one pass layer number of pass layer number, each bypass zone comprises a plurality of bypass zone size parameters, and at least one bypass zone size parameter corresponds to the ideal zone type of the circuit board design data, and the first via group includes a plurality of bypass zone size parameters:
(C-1) obtaining at least one target via group inspection default data corresponding to the at least one target circuit board design data, respectively, from the via group inspection default data;
(C-2) for each target circuit board design data, generating a first via group inspection result information corresponding to the target circuit board design data according to the target circuit board design data, a target via inspection default data corresponding to the target circuit board design data, and the first via group inspection rule; and
(C-3) checking default data for each target via, generating second via group check result information corresponding to the target circuit board design data according to the target circuit board design data and the second via group check rule.
8. The method of claim 1, wherein each circuit board setup data packet includes at least one pass-through layer code related to the number of layers passed by the differential pair circuit, a plurality of all layer codes related to all layers of the printed circuit board, and a plurality of headroom layer codes, each all layer code corresponding to a board layer type, the at least one pass-through layer code having a start point layer code related to a check start point layer preset by the differential pair circuit, the connector pin check rule being a plurality of all layer codes of a circuit board design data, a start point layer code adjacent to the circuit board design data and a target all layer code conforming to a connector pin check board layer type being included in the plurality of headroom layer codes of the circuit board design data, wherein step (D) comprises the sub-steps of:
(D-1) for each target circuit board design data, obtaining an inspection layer number code adjacent to the starting point layer number code and corresponding to the connector pin inspection board layer type according to the starting point layer number code of the target circuit board design data; and
(D-2) for each target circuit board design data, determining whether the inspection layer number code is included in the layer number code of the plurality of headroom areas of the target circuit board design data to generate the connector pin inspection result information.
9. The method according to claim 8, wherein in the sub-step (D-2), if the inspection layer number codes are included in the layer number codes of the headroom areas, the connector pin inspection result information indicates that the inspection layer number codes pass, and if the inspection layer number codes are not included in the layer number codes of the headroom areas, the connector pin inspection result information indicates that the inspection layer number codes are wrong.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310080554.6A CN118446171A (en) | 2023-02-03 | 2023-02-03 | Automatic inspection method for through hole and connector pin of printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310080554.6A CN118446171A (en) | 2023-02-03 | 2023-02-03 | Automatic inspection method for through hole and connector pin of printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118446171A true CN118446171A (en) | 2024-08-06 |
Family
ID=92307751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310080554.6A Pending CN118446171A (en) | 2023-02-03 | 2023-02-03 | Automatic inspection method for through hole and connector pin of printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118446171A (en) |
-
2023
- 2023-02-03 CN CN202310080554.6A patent/CN118446171A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7583513B2 (en) | Apparatus for providing an integrated printed circuit board registration coupon | |
| JP2022513109A (en) | PCB design layout circuit open short circuit inspection method, detection system and electronic device | |
| CN111278227A (en) | A method for PCB Layout layout and wiring of SMT32 system motherboard | |
| CN103870619A (en) | Wiring checking system and method | |
| CN113887163A (en) | Methods of Inserting Redundant Vias | |
| US7533005B2 (en) | System and method for checking a reference plane of a signal trace in a PCB | |
| CN118446171A (en) | Automatic inspection method for through hole and connector pin of printed circuit board | |
| CN100455161C (en) | A printed circuit board design method and printed circuit board | |
| CN107908873B (en) | A method and device for inspecting a high-speed line across a reference plane | |
| US7519936B2 (en) | Unallocatable space depicting system and method for a component on a printed circuit board | |
| US10470308B1 (en) | Printed circuit board assembly and electronic device using the same | |
| CN105975698B (en) | A layout method of differential vias and PCB | |
| TWI830565B (en) | Automatic inspection method for through hole vias and connector pins of pcb | |
| CN114254583B (en) | Method, device, equipment and storage medium for checking pin connection of device | |
| CN116546750A (en) | Automatic copper drawing method for PCB | |
| CN101303703B (en) | System and method for forming threading through hole | |
| CN109600919B (en) | Genesis-based PCB (printed Circuit Board) lamination design method and device and readable storage medium | |
| CN111225507A (en) | Method for solving problem of stub affecting signal transmission and PCB adopting same | |
| CN114050428A (en) | Signal acquisition device and system | |
| CN112739044A (en) | Method for manufacturing anti-welding test line through automatic script | |
| US20140054066A1 (en) | Circuit layout method and associated printed circuit board | |
| CN114708210B (en) | Cross-segmentation detection method for photo-drawn file | |
| KR102179446B1 (en) | Apparatus and method for inspecting circuit boards | |
| CN114004193B (en) | Identification method and related device for tin-plating risk of PCB | |
| US20230385516A1 (en) | Method and apparatus for checking signal line |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |