TW202335198A - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a substrate structure, a chip and a reinforcing layer. The substrate structure includes a core layer, a patterned circuit layer disposed on the core layer and a solder resist layer. The solder resist layer is disposed on the patterned circuit layer and exposes at least a part of the patterned circuit layer. The chip is disposed on a chip disposing region of the substrate structure and electrically connected the patterned circuit layer. The reinforcing layer is disposed on the solder resist layer, extended through the solder resist layer and stops at the core layer. The reinforcing layer covers a peripheral region of the chip disposing region. The molding compound at least encapsulates the chip, at least a part of the substrate structure and the reinforcing layer.

Description

Semiconductor packaging structure and manufacturing method thereof

The present disclosure relates to a semiconductor packaging structure and a manufacturing method of the semiconductor packaging structure.

Integrated circuits are usually formed on a substrate, such as a semiconductor wafer. After the wafer is singulated, conductive terminals need to be used to conduct signals to an external carrier (such as a substrate) for subsequent use of end products. Commonly used conductive terminal connection methods mostly use bonding bumps (bonding bumps) or metal wires (wire bonding) as the electrical conduction medium. However, since the chip and the external carrier (such as the substrate) are made of different materials and have different coefficients of thermal expansion (CTE), the package may become more fragile due to a mismatch in the coefficient of thermal expansion, causing the external carrier (such as the substrate) to break. Problems such as line and/or membrane delamination.

The present disclosure provides a semiconductor packaging structure and a manufacturing method of the semiconductor packaging structure, which can improve the structural strength of the semiconductor packaging, thereby reducing problems such as disconnection and delamination in high-stress areas in the semiconductor packaging structure.

A semiconductor packaging structure disclosed in the present disclosure includes a substrate structure, a chip and a strengthening layer. The substrate structure includes a core layer, a patterned circuit layer disposed on the core layer, and a solder resist layer, wherein the solder resist layer is disposed on the patterned circuit layer and exposes at least part of the patterned circuit layer. The chip is arranged on the chip setting area of the substrate structure and is electrically connected to the patterned circuit layer. The reinforcement layer is disposed on the solder mask layer and extends through the solder mask layer and against the core layer. The reinforcement layer covers the peripheral area of the chip setting area. The encapsulant covers at least the chip, at least part of the substrate structure and the strengthening layer.

The manufacturing method of a semiconductor packaging structure of the present disclosure includes the following steps: providing a substrate structure having a chip setting area, wherein the substrate structure includes a core layer, a patterned circuit layer provided on the core layer, and a patterned circuit layer provided on the core layer. A solder mask layer on the patterned circuit layer, wherein the solder mask layer includes a plurality of through holes located in a peripheral area of the chip setting area; forming a patterned photoresist layer on the solder mask layer, wherein the pattern The patterned photoresist layer exposes at least the plurality of through holes and the peripheral area; using the patterned photoresist layer as a mask, an electroplating process is performed to form a reinforcement layer, wherein the reinforcement layer fills the plurality of through holes and covers the peripheral area; and removing the patterned photoresist layer and exposing the strengthening layer; placing a chip on a chip setting area of the substrate structure, wherein the chip is electrically connected to the patterned circuit layer, and a chip of the chip is The edge portion at least partially overlaps the reinforcement layer in the front projection direction; forming a sealant to cover the chip, the patterned circuit layer and at least part of the substrate structure.

Based on the above, the semiconductor package structure of the present disclosure has a strengthening layer formed on the solder mask layer covering at least the peripheral area of the chip setting area to strengthen the structural strength of the peripheral area of the chip setting area, thereby reducing the thermal expansion coefficient mismatch. The adverse effects caused by thermal stress, such as cracking of the chip, disconnection of the circuit layer on the substrate structure below the chip, or delamination of the substrate structure, etc. Therefore, the semiconductor packaging structure of the present disclosure can effectively improve the semiconductor packaging structure. production yield and product reliability.

The aforementioned technical contents, features and effects of the present disclosure will be clearly presented in the following detailed description of each embodiment with reference to the drawings. Directional terms mentioned in the following embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only for reference to the directions in the attached drawings. Accordingly, the directional terms used are illustrative and not limiting of the disclosure. Furthermore, in the following embodiments, the same or similar elements will be given the same or similar numbers.

1 to 6 are schematic cross-sectional views of a manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure. In some embodiments, the manufacturing process of the semiconductor packaging structure may include the following steps. Referring to FIG. 1 , a substrate structure 110 as shown in FIG. 1 is provided. The substrate structure 110 has a chip setting area R1 for placing a chip (such as the chip 120 shown in FIG. 6 ) on the chip setting area R1. In one embodiment, the substrate structure 110 includes a core layer 112 , a patterned circuit layer 114 disposed on the core layer 112 , and a solder resist layer 116 disposed on the patterned circuit layer 114 . In this embodiment, the chip can be disposed on the substrate structure 110 through wire bonding, for example. Accordingly, the patterned circuit layer 114 further includes a plurality of pad portions (also called wire bonding pads) 1141, which can surround It is arranged around the chip setting area R1 and is electrically connected to other circuit contacts.

Referring to FIG. 1 , in some embodiments, the solder mask layer 116 may cover at least a portion of the patterned circuit layer 114 and expose at least a portion of the pad portion 1141 . In this embodiment, the pad portion 1141 is exposed by a plurality of openings 1164 defined by the solder mask 116 for subsequent electrical connection. Specifically, the patterned circuit layer 114 may include a plurality of pad portions 1141 and a plurality of circuit portions 1142 electrically connected to the plurality of pad portions 1141, wherein the solder mask layer 116 covers the circuit portions 1142 and exposes at least part of the connections. Pad 1141. In some embodiments, the solder mask 116 may further include a plurality of through holes 1163 located in the peripheral area of the chip setting region R1. In this embodiment, the through holes 1163 respectively extend through the solder mask layer 116 and stop on the core layer 112 . Moreover, the solder resist layer 116 is insulated from each other between the through hole 1163 and the patterned circuit layer 114 . In this embodiment, the plurality of openings 1164 and the plurality of through holes 1163 in the solder mask layer 116 for exposing the pad portion 1141 can be formed in the same patterning process. Here, it is worth noting that the other surface of the substrate 110 has a plurality of pads that can be electrically connected to the outside. Appropriate external terminals can be connected according to actual needs. In this disclosure, the external terminals are, for example, solder balls. (I will not go into details about its subsequent application here).

Next, referring to FIG. 2 , a patterned photoresist layer 170 is formed on the solder mask 116 , where the patterned photoresist layer 170 includes a plurality of photoresist openings 172 that expose at least a plurality of through holes 1163 . Specifically, a photoresist layer can be formed on the structure in Figure 1 by spin on coating, and then patterned through processes such as exposure and development to form Patterned photoresist layer 170 as shown in FIG. 2 . Next, the patterned photoresist layer 170 is used as a mask to form a penetration portion 132 in the reinforcement layer (such as the reinforcement layer 130 shown in FIG. 4 ). In this embodiment, the material of the penetration portion 132 includes copper, aluminum, and tin. , silver or its alloy and other metal materials, and are formed in the photoresist opening 172 and the through hole 1163 through, for example, an electroplating process to fill the photoresist opening 172 and the through hole 1163 . In this embodiment, the through portion 132 can be formed through two electroplating processes. For example, after the through holes 1163 of the solder mask layer 116 are formed, a first electroplating process can be performed to fill the through holes 1163, and then, after the photoresist openings 172 of the patterned photoresist layer 170 are formed, A second electroplating process is performed to continue filling the photoresist opening 172 . Of course, in other embodiments, the through portion 132 can also be directly filled with the photoresist opening 172 and the through hole 1163 in one electroplating process after the patterned photoresist layer 170 is formed. The present disclosure is not limited to this.

Next, please refer to FIGS. 3 and 4 . As shown in FIG. 3 , a portion of the patterned photoresist layer 170 covering the peripheral area of the solder mask layer 116 (for example, the peripheral area P1 shown in FIG. 7 ) is removed, so that the patterned photoresist layer 170 is removed. Layer 170 exposes the peripheral area. For example, an electroplating process is performed to form a strengthening layer 130 covering the peripheral area and connecting the through portion 132 . In this embodiment, the strengthening layer 130 includes the through portion 132 that fills the through hole 1163 and covers the peripheral area in the chip setting region R1 of the solder mask layer 116 . In alternative embodiments, the strengthening layer 130 can also be electroplated once in the step of FIG. 3 to form the strengthening layer 130 including the through portion 132 , and the present disclosure is not limited thereto. It should be noted that the fabrication flow charts of Figures 1 to 6 are cross-sectional views taken along the peripheral area surrounding the wafer setting area R1 (such as the peripheral area P1 shown in Figure 7). Therefore, the reinforcement in Figure 4 The layer 130 is shown as extending to cover the entire wafer setting area R1, but in fact, the strengthening layer 130 may only cover the peripheral area of the wafer setting area R1 as shown in FIG. 7 . Next, referring to FIG. 5 , the patterned photoresist layer 170 is removed and the reinforcement layer 130 and the pad portion 1141 are exposed. The patterned photoresist layer 170 is removed by, for example, using an organic solvent to remove the patterned photoresist layer 170 .

FIG. 7 is a schematic top view of a semiconductor packaging structure according to an embodiment of the present disclosure. It should be noted that in the top views of the present disclosure (eg, FIGS. 7 to 10 ), at least some components of the semiconductor package structure are shown in a perspective manner to clearly show the configuration relationship of each component. Please refer to FIGS. 6 and 7 . Next, the chip 120 is placed on the chip placement area R1 of the substrate structure 110 . The chip 120 is electrically connected to the patterned circuit layer 114 , and the edge portion of the chip 120 (corresponding to the peripheral area P1 ) at least partially overlaps with the reinforcement layer 130 in the orthographic projection direction. In other words, when viewed from the direction of the top view, the edge portion of the wafer 120 (corresponding to the peripheral area P1 ) at least partially overlaps the reinforcement layer 130 . In this embodiment, the chip 120 is bonded to the substrate structure 110 through wire bonding, for example. For example, the chip 120 may have a plurality of input/output pads 121 , which may be arranged at each edge of the chip 120 , for example. The input/output pads 121 can be electrically connected to the pad portion 1141 of the substrate structure 110 through a plurality of bonding wires 160 , so that the chip 120 can be electrically connected to the patterned circuit layer 114 . Next, an encapsulant 150 is formed to cover the chip 120 , the patterned circuit layer 114 and at least part of the substrate structure 110 .

Generally speaking, when manufacturing a semiconductor packaging structure, thermal stress will be generated in the semiconductor packaging structure due to the mismatch in the coefficient of thermal expansion (CTE) between different component materials, and the die edge of the wafer will cause thermal stress. ) has the most severe impact. This thermal stress can easily lead to chip cracking, disconnection or delamination of the underlying circuit layer. In view of this, in this embodiment, a strengthening layer 130 covering the peripheral area P1 of the chip setting area R1 is formed on the solder mask layer 116 to strengthen the structural strength of the peripheral area of the chip setting area R1, thereby reducing the thermal stress. future impact, and can improve the production yield and reliability of semiconductor packaging structures.

In some embodiments, the structural rigidity of the reinforcement layer 130 may be approximately greater than the structural rigidity of the solder mask layer 116 to enhance the protection of the underlying patterned circuit layer 114 . In this embodiment, the material of the strengthening layer 130 may include copper, aluminum or other suitable metal materials, and is formed through electroplating. In other embodiments, the material of the strengthening layer 130 may further include ceramics, silicon nitride or other suitable materials, and may be formed by deposition or other suitable methods, but the present disclosure is not limited thereto. In some embodiments, the reinforcement layer 130 overlaps at least the line portion 1142 located below the peripheral area P1 in the orthographic projection direction. In other words, when viewed from the direction of the top view, the reinforcement layer 130 at least partially overlaps the line portion 1142 located below the peripheral area P1. Furthermore, the reinforcement layer 130 is electrically insulated from the patterned circuit layer 114 .

In some embodiments, as shown in FIG. 7 , in addition to covering the peripheral area P1 of the wafer setting area R1 , the strengthening layer 130 can also extend along the same plane in a direction outside the wafer setting area R1 to further strengthen the periphery of the wafer 120 Structural strength of the area. That is to say, in the front projection direction, in addition to overlapping the peripheral area P1 of the wafer setting area R1, the strengthening layer 130 may also overlap with the peripheral area surrounding the periphery of the wafer setting area R1. In this embodiment, the strengthening layer 130 may include a plurality of mutually separated strengthening patterns as shown in FIG. 7 , which are respectively disposed on multiple sides of the peripheral area P1 of the wafer setting area R1, and the through portion 132 (indicated by a dotted line) ) are respectively provided at the opposite ends of each strengthening pattern to penetrate the solder mask layer 116 . Furthermore, the reinforcement layer 130 does not overlap with the corners of the wafer 120 in the orthographic projection direction.

8 to 10 are schematic top views of a semiconductor packaging structure according to different embodiments of the present disclosure. It must be noted here that the semiconductor packaging structures 100a, 100b, and 100c of this embodiment are similar to the semiconductor packaging structure 100 of the previous embodiment. Therefore, this embodiment uses the component numbers and part of the content of the previous embodiment, and the same numbers are used. to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be repeated in this embodiment. The following will describe the differences between the semiconductor packaging structures 100a, 100b, and 100c of this embodiment and the semiconductor packaging structure 100 of the previous embodiment.

Please refer to FIG. 8 . In this embodiment, the chip 120 is bonded to the substrate structure 110 through flip-chip bonding. Specifically, the chip 120 is disposed with its active surface facing down (face down). The upper surface of the substrate structure 110 is connected to the substrate structure 110 through a plurality of conductive bumps 122 . In this embodiment, the pad portion 1141 in the patterned circuit layer 114 is located in the central area of the chip setting area R1 to connect with the conductive bumps 122 on the chip 120. The circuit portion 1142 is connected to the pad portion 1141 and can extend to The area outside the wafer setting area R1. Under this configuration, the reinforcement layer 130 may have a plurality of mutually separated reinforcement patterns similar to the configuration of the previous embodiment, so as to be respectively disposed on multiple sides of the peripheral area P1 of the chip setting area R1, and the through portion 132 (to (indicated by dotted lines) are respectively arranged at the opposite ends of each strengthening pattern. Furthermore, the reinforcement layer 130 overlaps at least the line portion 1142 located below the peripheral area P1 in the orthographic projection direction. In other words, when viewed from the direction of the top view, the reinforcement layer 130 at least partially overlaps the line portion 1142 located below the peripheral area P1. In this embodiment, the strengthening layer 130 does not overlap with multiple corners of the wafer 120 in the orthographic projection direction.

Please refer to FIG. 9 . In this embodiment, the strengthening layer 130 b is a ring-shaped structure surrounding the peripheral area P1 . That is to say, the strengthening layer 130 b can completely surround the peripheral area of the wafer setting area R1 . Specifically, in the orthographic projection direction, the reinforcement layer 130b not only overlaps with multiple sides of the wafer 120 but also overlaps with multiple corners of the wafer 120 . In this embodiment, the penetration portion 132 can be configured to penetrate the opposite ends of each side of the chip setting region R1 of the solder mask layer 116 to avoid the main wiring area of the wiring portion 1142 of the patterned wiring layer 114 . In some embodiments, in addition to covering the peripheral area of the wafer setting area R1, the strengthening layer 130b can also extend along the same plane in a direction outside the wafer setting area R1 to further strengthen the structural strength of the peripheral area of the wafer 120. That is to say, in the front projection direction, in addition to overlapping the peripheral area of the wafer setting area R1, the strengthening layer 130b may also partially overlap with the peripheral area surrounding the periphery of the wafer setting area R1.

Please refer to FIG. 10 . In this embodiment, the strengthening layer 130 c can completely cover the chip setting region R1 of the solder resist layer 116 . That is to say, in the orthographic projection direction, the wafer 120 can be completely located within the arrangement range of the reinforcement layer 130c. In this embodiment, the penetration portion 132c can be configured to penetrate each corner of the chip setting area R1 of the solder mask layer 116 to avoid the main wiring area of the wiring portion 1142 of the patterned wiring layer 114 . In some embodiments, in addition to completely covering the wafer setting area R1, the strengthening layer 130c can also extend along the same plane in a direction outside the wafer setting area R1 to further strengthen the structural strength of the periphery of the wafer 120. That is to say, in the front projection direction, in addition to overlapping the wafer setting area R1, the strengthening layer 130c may also partially overlap the peripheral area surrounding the periphery of the wafer setting area R1.

In summary, the semiconductor package structure of the present disclosure has a strengthening layer formed on the solder mask layer covering at least the peripheral area of the chip setting area to strengthen the structural strength of the peripheral area of the chip setting area, thereby reducing the thermal expansion coefficient. Thermal stress caused by mismatch has adverse effects, such as chip cracking, circuit layer disconnection under the chip, or delamination of the substrate structure. Therefore, the semiconductor packaging structure disclosed in the present invention can effectively improve the production of semiconductor packaging structures. Yield and product reliability.

100, 100a, 100b, 100c: packaging structure 110:Substrate structure 112:Core layer 114: Patterned circuit layer 1141: Pad part 1142: Line Department 116: Solder mask 1163:Through hole 1164:Open your mouth 120:Chip 122: Conductive bumps 130, 130b, 130c: Reinforcement layer 132, 132c: penetration part 150:Sealing gel 160:Welding wire 170:Patterned photoresist layer 172: Photoresist opening R1: Chip setting area P1: Peripheral area

1 to 6 are schematic cross-sectional views of a manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure. FIG. 7 is a schematic top view of a semiconductor packaging structure according to an embodiment of the present disclosure. 8 to 10 are schematic top views of a semiconductor packaging structure according to different embodiments of the present disclosure.

100:Package structure

110:Substrate structure

112:Core layer

114: Patterned circuit layer

1141: Pad part

1142: Line Department

116: Solder mask

1163:Through hole

1164:Open your mouth

120:Chip

130: Reinforcement layer

132:Penetration Department

150:Sealing gel

160:Welding wire

R1: Chip setting area

Claims (10)

A semiconductor packaging structure including: A substrate structure, including a core layer, a patterned circuit layer disposed on the core layer, and a solder mask layer, wherein the solder resist layer is disposed on the patterned circuit layer and exposes at least part of the patterned circuit layer; A chip is disposed on a chip setting area of the substrate structure and is electrically connected to the patterned circuit layer; A reinforcement layer is provided on the solder mask layer and extends through the solder mask layer and against the core layer. The reinforcement layer covers a peripheral area of the chip setting area; and A sealant covers at least the wafer, at least part of the substrate structure and the reinforcement layer. The semiconductor packaging structure of claim 1, wherein the strengthening layer overlaps at least an edge of the wafer in the orthographic projection direction. The semiconductor packaging structure of claim 1, wherein the structural rigidity of the strengthening layer is substantially greater than the structural rigidity of the solder mask layer. The semiconductor packaging structure of claim 1, wherein the material of the reinforcement layer includes copper, aluminum, ceramics or silicon nitride. The semiconductor packaging structure of claim 1, wherein the patterned circuit layer includes a plurality of pad portions and a plurality of circuit portions electrically connected to the plurality of pad portions, and the solder mask layer covers the plurality of circuit portions and expose the plurality of pad portions. The semiconductor packaging structure of claim 1, wherein the reinforcement layer overlaps at least the plurality of circuit portions located below the peripheral region in an orthographic projection direction. The semiconductor packaging structure of claim 1, wherein the reinforcement layer includes a plurality of mutually separated reinforcement patterns, respectively disposed on multiple sides of the peripheral region. The semiconductor packaging structure of claim 1, wherein the reinforcement layer is a ring-shaped structure surrounding the peripheral area. The semiconductor packaging structure of claim 1, wherein the reinforcement layer completely covers the chip setting area. A method for manufacturing a semiconductor packaging structure, including: A substrate structure having a chip setting area is provided, wherein the substrate structure includes a core layer, a patterned circuit layer disposed on the core layer, and a solder resist layer disposed on the patterned circuit layer, wherein the resist layer The solder layer includes a plurality of through holes located in a peripheral area of the chip setting area; Forming a patterned photoresist layer on the solder mask layer, wherein the patterned photoresist layer exposes at least the plurality of through holes and the peripheral area; Using the patterned photoresist layer as a mask, electroplating forms a reinforcement layer, wherein the reinforcement layer fills the plurality of through holes and covers the peripheral area; Remove the patterned photoresist layer and expose the reinforcement layer; place a chip on a chip setting area of the substrate structure, wherein the chip is electrically connected to the patterned circuit layer, and an edge portion of the chip is on the front At least partially overlaps the reinforcement layer in the projection direction; and A sealant is formed to cover the chip, the patterned circuit layer and at least part of the substrate structure.

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