CN106816388A - Semiconductor packaging structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor packaging structure and a manufacturing method thereof. Its production method includes the following steps. Package substrate provided. The packaging substrate includes a dielectric layer, a first metal layer and a second metal layer. The second metal layer is patterned to form a circuit layer. A solder resist layer is formed on the circuit layer and partially covers the circuit layer. Arrange the carrier board on the circuit layer and solder mask layer. The dielectric layer and the first metal layer are removed to expose the circuit layer. A portion of the circuit layer between the first contact point and the second contact point is removed to expose the trench on the solder mask layer. The chip is electrically connected to the circuit layer. Form encapsulating colloid on the circuit layer and solder mask layer, and cover the chip. Remove the carrier board. The semiconductor packaging structure produced by the manufacturing method of the semiconductor packaging structure of the present invention does not have a core layer, so the overall thickness of the semiconductor packaging structure can be reduced, thus meeting the development needs of miniaturization.

Description

Semiconductor package structure and manufacturing method thereof

technical field

The invention relates to a packaging structure and a manufacturing method thereof, in particular to a semiconductor packaging structure and a manufacturing method thereof.

Background technique

In the semiconductor industry, the production of integrated circuits (ICs) can be mainly divided into three stages: design of integrated circuits, fabrication of integrated circuits, and packaging of integrated circuits. After the integrated circuits of the wafer are fabricated, the active surface of the wafer is provided with a plurality of die pads. Finally, the bare chips obtained by dicing the wafer can be electrically connected to the carrier through the chip pads. Generally speaking, the carrier can be a lead frame or a package substrate, and the chip can be connected to the carrier by wire bonding or flip chip bonding to achieve The chip pads of the chip are electrically connected to the contacts of the carrier, thereby forming a chip package.

The overall thickness of the chip package is, for example, the sum of the thickness of the encapsulant, the thickness of the carrier and the height of the external terminals. In order to meet the development requirement of miniaturization of the chip package, it is common practice to reduce the thickness of the carrier. However, the reduction of the thickness of the carrier is limited and will affect its structural strength. Therefore, a coreless carrier (such as a substrate) has been developed.

Contents of the invention

The invention provides a semiconductor packaging structure, the carrier does not have a core layer, so the overall thickness can be reduced.

The invention provides a method for manufacturing a semiconductor package structure, and the semiconductor package structure produced by the method can have a thinner thickness.

The invention provides a method for manufacturing a semiconductor packaging structure, which includes the following steps. Package substrates are provided. The packaging substrate includes a dielectric layer, a first metal layer connected to the dielectric layer, and a second metal layer connected to the first metal layer, wherein the first metal layer is located between the dielectric layer and the second metal layer. The second metal layer is patterned to form a circuit layer, wherein the circuit layer has a first contact and a second contact. A solder resist layer is formed on the circuit layer, and the solder resist layer partially covers the circuit layer. Configure the carrier board on the circuit layer and the solder mask layer. The dielectric layer and the first metal layer are removed to expose the circuit layer. A portion of the circuit layer between the first contact and the second contact is removed to expose the trench on the solder resist layer. The chip is electrically connected to the circuit layer through the first contact and the second contact. Forming encapsulation gel on the circuit layer and the solder resist layer, and making the encapsulation gel coat the chip. Remove the carrier board.

The invention proposes a semiconductor package structure, which includes a circuit layer, a solder resist layer, a chip, a package compound and a plurality of external terminals. The line layer has a first contact and a second contact. The solder resist layer partially covers the circuit layer, wherein the solder resist layer exposes the first contact and the second contact, and has a trench between the first contact and the second contact. The chip is configured on the circuit layer and the solder resist layer, and is electrically connected to the circuit layer through the first contact and the second contact. Chips span the top of the trench. The encapsulant is disposed on the circuit layer and the solder resist layer, and covers the chip. These external terminals are respectively arranged on the circuit layer exposed by the solder resist layer.

Based on the above, since the semiconductor package structure produced by the manufacturing method of the semiconductor package structure of the present invention does not have a core layer, the overall thickness of the semiconductor package structure can be reduced, thereby meeting the development requirements of miniaturization.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A to 1L are schematic cross-sectional views of the manufacturing process of a semiconductor package structure according to an embodiment of the present invention;

FIG. 1M is a schematic cross-sectional view of the semiconductor package structure in FIG. 1L where external terminals are formed;

2A to 2F are schematic cross-sectional views of the fabrication process of a semiconductor package structure according to another embodiment of the present invention;

FIG. 2G is a schematic cross-sectional view of the semiconductor package structure with external terminals formed in FIG. 2F .

Reference signs:

10: Line structure

100, 100A: Semiconductor package structure

110: package substrate

111: dielectric layer

112: first metal layer

113: second metal layer

114: Line layer

114a: first contact

114b: second contact

120: solder mask

121: surface

122: Depression

123: Ditch

130, 131: solder protection layer

140: carrier board

150: chips

151: Active surface

152: solder ball

153: back surface

160: encapsulation colloid

170: External terminal

180: Conductive column

190: welding wire

detailed description

1A to 1L are schematic cross-sectional views of the manufacturing process of a semiconductor package structure according to an embodiment of the present invention. First, please refer to FIG. 1A , a packaging substrate 110 is provided. The packaging substrate 110 includes a dielectric layer 111 , a first metal layer 112 formed on the dielectric layer 111 (or called the first metal layer 112 connected to the dielectric layer 111 ) and a second metal layer formed on the first metal layer 112 113 (or called the second metal layer 113 connected to the first metal layer 112 ), wherein the first metal layer 112 is located between the dielectric layer 111 and the second metal layer 113 . In this embodiment, the number of the first metal layer 112 and the number of the second metal layer 113 are two respectively. The aforementioned two first metal layers 112 are respectively located on opposite sides of the dielectric layer 111 , and each second metal layer 113 is correspondingly formed on the first metal layer 112 . The material of the dielectric layer 111 can be silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon nitride carbide or silicon oxycarbide, or FR-4 (epoxy resin glass fiber) substrate, PI (polyimide resin ) substrate or a substrate composed of other similar materials. The material of the first metal layer 112 and the second metal layer 113 can be copper, aluminum, gold, silver, nickel or an alloy of the aforementioned metals. As shown in FIG. 1A , the thickness of the first metal layer 112 is, for example, smaller than the thickness of the second metal layer 113 .

Next, please refer to FIG. 1B , for example, the second metal layer 113 is patterned by exposure and development to form the wiring layer 114 . In this embodiment, the circuit layer 114 still covers the first metal layer 112 and has a first contact 114 a and a second contact 114 b. In other embodiments, the circuit layer may expose part of the first metal layer, which is not limited by the present invention. Next, please refer to FIG. 1C , for example, a solder resist material is formed on the circuit layer 114 by coating, printing or jet printing. Next, the solder resist material is patterned, for example by exposure and development, to form the solder resist layer 120 , so that the solder resist layer 120 partially covers the circuit layer 114 and exposes the first contact 114 a and the second contact 114 b.

In order to prevent oxidation or sulfuration of the first contact 114a and the second contact 114b exposed to the solder resist layer 120, a solder protection layer 130 is further formed on the first contact 114a and the second contact 114b, as shown in FIG. 1D . Generally speaking, the solder protection layer 130 can be an organic solder protection film (OSP), or be made of a metal material that is not easily oxidized, for example, a nickel/gold layer is formed on the first contact 114a and the second contact 114b by electroplating. . On the other hand, the wiring layer 114 , the solder resist layer 120 and the solder protection layer 130 can constitute the wiring structure 10 , wherein each wiring structure 10 is connected to the corresponding first metal layer 112 . Next, referring to FIG. 1E , the carrier board 140 is respectively disposed on each circuit structure 10 . Specifically, each carrier board 140 is disposed on the corresponding circuit layer 114 and the solder resist layer 120 , and abuts against the corresponding solder resist layer 120 without contacting the corresponding circuit layer 114 . The carrier 140 is, for example, a hard substrate or a flexible substrate, and can be bonded to the solder resist layer 120 through a release film. During subsequent packaging steps, the carrier 140 can be used as a temporary auxiliary support structure for supporting the corresponding circuit structure 10 .

Please continue to refer to FIG. 1D and FIG. 1E , the number of wiring structures 10 is, for example, two, wherein the two wiring structures 10 are respectively located on opposite sides of the dielectric layer 111 , and each wiring structure 10 will be in contact with the corresponding carrier board 140 Cooperate. Next, please refer to FIG. 1F , remove the dielectric layer 111 and the first metal layer 112 (or separate each circuit structure 10 from the corresponding first metal layer 112 ). At this time, the portion of the wiring layer 114 that was originally connected to the first metal layer 112 will be exposed to the outside. The encapsulation process of one of the circuit structures 10 will be described later. Next, please refer to FIG. 1G , for example, remove part of the circuit layer 114 covering the solder resist layer 120 by exposure and development, and make the circuit layer 114 slightly lower than the surface of the solder resist layer 120 not covered by the carrier 140 121 to define a plurality of depressions 122 .

Referring to FIG. 1H , for example, the circuit layer 114 in the recess 122 between the first contact 114 a and the second contact 114 b is removed by exposure and development, so as to expose the trench 123 of the solder resist layer 120 . After that, referring to FIG. 1I , a solder protection layer 131 is formed in each recess 122 to cover the circuit layer 114 exposed to the solder resist layer 120 , so as to prevent the circuit layer 114 from being oxidized or sulfurized. Next, please refer to FIG. 1J , the chip 150 is electrically connected to the circuit layer 114 through the first contact 114 a and the second contact 114 b. In this embodiment, the active surface 151 of the chip 150 and the surface 121 of the solder resist layer 120 face each other, so that the chip 150 is flip-chip bonded to the first contact 114a and the second contact 114b, and the chip 150 spans above the trench 123 . Generally, before flip-chip bonding the chip 150 to the first contact 114a and the second contact 114b, the bumps on the chip 150 are coated with flux. Next, the bumps coated with flux are abutted against the first contact 114a and the second contact 114b. Afterwards, the bumps are reflowed, and the solder protection layer 131 is removed by flux, so that the solder balls 152 formed by the reflowed bumps are firmly bonded to the first contact 114a and the second contact 114b. Since the first contact 114a and the second contact 114b are separated by the ditch 123, when the bump is reflowed, the ditch 123 can collect excess solder, thereby preventing the molten solder from overflowing and forming a solder bridge. bridge) to avoid short circuits.

Next, referring to FIG. 1K , an encapsulant 160 is formed on the surface 121 of the solder resist layer 120 , and the encapsulant 160 covers the chip 150 and the solder balls 152 . On the other hand, the encapsulant 160 covers the first contact 114 a , the second contact 114 b and the solder protection layer 131 of the circuit layer 114 , and fills the trench 123 . Afterwards, referring to FIG. 1L , the carrier board 140 is removed to expose the solder protection layer 130 , wherein the chip 150 and the solder protection layer 130 are respectively located on opposite sides of the circuit layer 114 . So far, the fabrication of the semiconductor package structure 100 has been roughly completed. Since the semiconductor package structure 100 does not have a core layer, the overall thickness of the semiconductor package structure 100 can be reduced to meet the development requirements of miniaturization.

FIG. 1M is a schematic cross-sectional view of the semiconductor package structure with external terminals formed in FIG. 1L . Please refer to FIG. 1M, after the semiconductor package structure 100 as shown in FIG. 1L is produced, a ball planting step can be further performed to form a plurality of external terminals 170 on the circuit layer 114 exposed by the solder resist layer 120 (ie, the first circuit layer 114 ). The first contact 114 a and the second contact 114 b are not covered by the encapsulant 160 ). Generally, before performing the ball planting step, flux is firstly coated on the solder protection layer 130 . Next, solder balls are implanted on the flux. Afterwards, the solder balls are reflowed, and the solder protection layer 130 is removed by flux, so that the external terminals 170 formed by the reflowed solder balls can be firmly bonded to the circuit layer 114 exposed by the solder resist layer 120 (that is, the first contact). 114a and the second contact 114b are not covered by the encapsulant 160). In this embodiment, the external terminal 170 is in the form of a ball grid array (BGA), but the invention is not limited thereto. In other embodiments, the external terminals may be in the form of a land grid array (LGA) or a pin grid array (PGA).

It is worth mentioning that in this embodiment, an organic solder protection film is used as the solder protection layer 130 for illustration, and the present invention is not limited thereto. In other embodiments, the solder protection layer may be a nickel/gold layer, and flux may be used to remove impurities adhering to the nickel/gold layer when solder balls are reflowed.

Other embodiments are listed below for illustration. It must be noted here that the following embodiments use the component numbers and partial content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2A to 2F are schematic cross-sectional views of the manufacturing process of a semiconductor package structure according to another embodiment of the present invention. It should be noted that some manufacturing steps of the semiconductor package structure 100A (shown in FIG. 2F ) of this embodiment are substantially the same or similar to those shown in FIGS. 1A to 1F , and will not be repeated here. First, please refer to FIG. 2A , after separating each circuit structure 10 from the corresponding first metal layer 112 (as shown in FIG. 1F ), at least one conductive column 180 (schematically showing two ) on the circuit layer 114. The conductive pillars 180 are located on one side of the first contact 114a or the second contact 114b. In this embodiment, the first contact 114 a and the second contact 114 b are located between the conductive pillars 180 , for example. In other embodiments, the number of conductive pillars may be greater than two, and surround the first contact and the second contact.

Next, please refer to FIG. 2B , for example, by exposing and developing to remove part of the circuit layer 114 covering the solder resist layer 120, and make the circuit layer 114 slightly lower than the surface of the solder resist layer 120 not covered by the carrier 140. 121 to define a plurality of depressions 122 . Next, referring to FIG. 2C , a solder protection layer 131 is formed in each recess 122 to cover the circuit layer 114 exposed to the solder resist layer 120 , so as to prevent the circuit layer 114 from being oxidized or vulcanized. At the same time, the solder protection layer 131 is also formed on the conductive pillar 180 to prevent the conductive pillar 180 from being oxidized or vulcanized. In this embodiment, the circuit layer 114 in the trench 123 between the first contact 114a and the second contact 114b is not removed. In other words, there will be a part of the circuit layer 114 located in the trench 123 .

Next, referring to FIG. 2D , the chip 150 is electrically connected to the circuit layer 114 through the first contact 114 a and the second contact 114 b. In this embodiment, the active surface 151 of the chip 150 faces away from the surface 121 of the solder resist layer 120 . In other words, the chip 150 is disposed on the solder resist layer 120 and straddles above the trench 123 to be electrically connected to the first contact 114 a and the second contact 114 b by, for example, wire bonding. Specifically, the bonding wire 190 is bonded to the active surface 151 of the chip 150 and the first contact 114 a, and bonded to the active surface 151 of the chip 150 and the second contact 114 b to electrically connect the chip 150 to the circuit layer 114 . Generally, before the bonding wire 190 is bonded to the first contact 114a and the second contact 114b, dilute acid or plasma is used to remove part of the solder resist layer 131 to expose the first contact 114a and the second contact 114b. .

It is worth mentioning that in this embodiment, an organic solder protection film is used as the solder protection layer 131 for illustration, and the present invention is not limited thereto. In other embodiments, the solder resist layer may be a nickel/gold layer, and dilute acid or plasma may be used to remove impurities adhering to the nickel/gold layer. In other words, depending on the type of the solder resist layer, the aforementioned cleaning step using dilute acid or plasma is used to selectively remove the organic solder resist layer or impurities attached to the nickel/gold layer.

Referring to FIG. 2E , an encapsulant 160 is formed on the surface 121 of the solder resist layer 120 , and the encapsulant 160 covers the chip 150 and the bonding wire 190 . On the other hand, the encapsulant 160 covers the first contact 114 a and the second contact 114 b of the circuit layer 114 , and the conductive pillar 180 covered by the solder retention layer 131 is exposed to the encapsulant 160 . Afterwards, referring to FIG. 2F , the carrier 140 is removed to expose the solder resist layer 130 , wherein the chip 150 and the solder resist layer 130 are respectively located on opposite sides of the circuit layer 114 . So far, the fabrication of the semiconductor package structure 100A has been roughly completed. Since the semiconductor package structure 100A does not have a core layer, the overall thickness of the semiconductor package structure 100A can be reduced, thereby meeting the development requirement of miniaturization. On the other hand, the conductive pillars 180 exposed from the encapsulant 160 can be used to connect other chips, other semiconductor packaging structures or electronic components. As shown in FIG. 2E , the height of the conductive pillar 180 is, for example, smaller than the thickness of the encapsulant 160 . In other embodiments, the height of the conductive pillars may be greater than or equal to the thickness of the encapsulant.

For example, the semiconductor package structure 100A can be stacked with another semiconductor package structure, wherein the other semiconductor package structure is similar to the semiconductor package structure 100A, and is electrically connected to the conductive column 180 of the semiconductor package structure 100A through the conductive column. At this time, the height of the conductive pillars of the another semiconductor package junction is, for example, greater than the thickness of the encapsulant, so as to facilitate the cooperation of the conductive pillars 180 of the semiconductor package structure 100A.

FIG. 2G is a schematic cross-sectional view of the semiconductor package structure with external terminals formed in FIG. 2F . Please refer to FIG. 2G, after the semiconductor package structure 100A of FIG. 2F is produced, a ball planting step can be further performed to form a plurality of external terminals 170 on the circuit layer 114 exposed by the solder resist layer 120 (ie, the first contact 114a and the side of the second contact 114b not covered by the encapsulant 160). Generally, before performing the ball planting step, flux is firstly coated on the solder protection layer 130 . Next, solder balls are planted on the solder protection layer 130 . Afterwards, the solder balls are reflowed, and the solder protection layer 130 is removed by flux, so that the external terminals 170 formed by the reflowed solder balls can be firmly bonded to the circuit layer 114 exposed by the solder resist layer 120 (that is, the first contact). 114a and the second contact 114b are not covered by the encapsulant 160). In this embodiment, the external terminal 170 is in the form of a ball grid array (BGA), but the invention is not limited thereto. In other embodiments, the external terminals may be in the form of a land grid array (LGA) or a pin grid array (PGA).

To sum up, since the semiconductor package structure manufactured by the semiconductor package structure manufacturing method of the present invention does not have a core layer, the overall thickness of the semiconductor package structure can be reduced, thereby meeting the development requirements of miniaturization. In one embodiment, part of the circuit layer between the first contact and the second contact is removed to expose the trench of the solder resist layer. According to this, during the flip-chip bonding, the molten solder on the first contact and the second contact overflows and overlaps to form a solder bridge, so as to avoid short circuit. In another embodiment, the wiring layer around the first contact and the second contact may be formed with conductive pillars, and the aforementioned conductive pillars may be used to connect other chips, other semiconductor package structures or electronic components. On the other hand, the semiconductor package structures also provided with the conductive pillars can be stacked opposite to each other and electrically connected to each other through the conductive pillars.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be determined by the appended claims.

Claims (11)

1. a kind of preparation method of semiconductor package, it is characterised in that including：

Package substrate is provided, the package substrate includes dielectric layer, connects the first metal of the dielectric layer The second metal layer of layer and the connection the first metal layer, wherein the first metal layer is located at being given an account of Between electric layer and the second metal layer；

The second metal layer is patterned, to form line layer, wherein the line layer has the first contact With the second contact；

Solder mask is formed on the line layer, and makes line layer described in the solder mask local complexity；

Configuration support plate is on the line layer with the solder mask；

The dielectric layer and the first metal layer are removed, to expose the line layer；

The part line layer being located between first contact and second contact is removed, to expose The irrigation canals and ditches gone out on the solder mask；

Chip is set to be electrically connected at the line layer with second contact by first contact；

Packing colloid is formed on the line layer with the solder mask, and makes the packing colloid cladding institute State chip；And

Remove the support plate.

2. the preparation method of semiconductor package according to claim 1, it is characterised in that institute Chip chip bonding is stated in first contact and second contact, to be electrically connected at the circuit Layer.

3. the preparation method of semiconductor package according to claim 1, it is characterised in that also Including：

Before the chip and the line layer is electrically connected with, an at least conductive pole is formed in the circuit On layer, wherein the conductive pole is located at the side of first contact or second contact, and expose Outside the packing colloid.

4. the preparation method of semiconductor package according to claim 3, it is characterised in that also Including：

The part line layer is removed, and forms guarantor's layer on the line layer with the conductive pole.

5. the preparation method of semiconductor package according to claim 1, it is characterised in that institute State chip routing and be engaged in first contact and second contact, to be electrically connected at the circuit Layer.

6. the preparation method of semiconductor package according to claim 1, it is characterised in that also Including：

The support plate is being configured before on the line layer with the solder mask, is being formed and is protected layer in described On line layer.

7. the preparation method of semiconductor package according to claim 1, it is characterised in that also Including：

Before the chip and the line layer is electrically connected with, the part line layer is removed, and formed Layer is protected on the line layer.

8. the preparation method of semiconductor package according to claim 1, it is characterised in that institute It is respectively two that the first metal layer is stated with the quantity of the second metal layer, the two the first metal layers difference Positioned at the opposite sides of the dielectric layer, each second metal layer connects corresponding first metal Layer.

9. the preparation method of semiconductor package according to claim 1, it is characterised in that also Including：

After the support plate is removed, multiple outside terminals are formed described in exposed by the solder mask On line layer.

10. a kind of semiconductor package, it is characterised in that including：

Line layer, with the first contact and the second contact；

Solder mask, line layer described in local complexity, wherein the solder mask expose first contact with Second contact, and with the irrigation canals and ditches between first contact and second contact；

Chip, is configured on the line layer and the solder mask, and by first contact with it is described Second contact is electrically connected at the line layer, wherein the chip crosses over the top of the irrigation canals and ditches；

Packing colloid, is configured on the line layer and the solder mask, and coat the chip；And

Multiple outside terminals, are respectively arranged on the line layer exposed by the solder mask.

11. semiconductor packages according to claim 10, it is characterised in that also include：

An at least conductive pole, is configured on the line layer, wherein the conductive pole connects positioned at described first The side of point or second contact, and outside the packing colloid.