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TW202326985A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW202326985A
TW202326985A TW110147934A TW110147934A TW202326985A TW 202326985 A TW202326985 A TW 202326985A TW 110147934 A TW110147934 A TW 110147934A TW 110147934 A TW110147934 A TW 110147934A TW 202326985 A TW202326985 A TW 202326985A
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TW
Taiwan
Prior art keywords
layer
conductive elements
packaging
wiring structure
circuit structure
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TW110147934A
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English (en)
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TWI819440B (zh
Inventor
柯仲禹
黃柏凱
陳亮斌
Original Assignee
矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW110147934A priority Critical patent/TWI819440B/zh
Priority to CN202111623673.9A priority patent/CN116314102A/zh
Priority to US17/674,457 priority patent/US12113004B2/en
Publication of TW202326985A publication Critical patent/TW202326985A/zh
Application granted granted Critical
Publication of TWI819440B publication Critical patent/TWI819440B/zh

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Abstract

一種電子封裝件，係將包含線路結構、電子元件、複數第一導電元件及第一封裝層之第一封裝模組以及包含佈線結構、複數第二導電元件及第二封裝層之第二封裝模組相堆疊，以令該第二封裝層設於該第一封裝層上，使該佈線結構疊合於該線路結構上，且各該第二導電元件對應結合各該第一導電元件，俾藉由將該線路結構與該佈線結構同時分開製作，以縮短製程時間，且能分別控制該線路結構與該佈線結構上之應力分布。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種可減少應力之電子封裝件及其製法。
為了確保電子產品和通信設備的持續小型化和多功能性，半導體封裝需朝尺寸微小化發展，以利於多引腳之連接，並具備高功能性。例如，於先進製程封裝中，常用的封裝型式如2.5D封裝製程、扇出(Fan-Out)佈線配合封裝體堆疊(Package on Package)元件之製程(簡稱FO-POP)等，其中，FO-POP相對於2.5D封裝製程係具有低成本及材料供應商多等優勢。
圖1A至圖1B係習知FO-POP之半導體封裝件1之製法之剖面示意圖。
如圖1A所示，於一具有扇出(Fan-Out)型線路重佈層(redistribution layer，簡稱RDL)100之線路結構10上設置至少一半導體晶片11及複數導電柱13。
如圖1B所示，形成一包覆層15於該線路結構10上，以令該包覆層15包覆該半導體晶片11與該些導電柱13，使該半導體晶片11埋設於該包覆層15中。接著，藉由扇出(Fan-Out)規格之RDL製程形成一佈線結構12於該包覆層15 上，且令該佈線結構12之線路重佈層120電性連接該些導電柱13，使該半導體晶片11藉由該線路結構10之線路重佈層100與該導電柱13電性連接該佈線結構12之線路重佈層120。
然而，前述半導體封裝件1中，由於進行扇出製程所需時間較長，故先後製作該線路結構10與該佈線結構12將加長製作時間，導致製作成本增加。
此外，若該半導體封裝件1需配置多層線路重佈層100,120時，於該線路結構10上製作該佈線結構12，係容易發生應力分布不均之情況，導致部分線路重佈層100,120因無法承受應力集中而斷裂。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：線路結構；電子元件，係設於該線路結構上並電性連接該線路結構；複數第一導電元件，係設於該線路結構上並電性連接該線路結構；第一封裝層，係設於該線路結構上以包覆該電子元件及該複數第一導電元件；以及封裝模組，係結合於該第一封裝層上，其中，該封裝模組係包含佈線結構、設於該佈線結構上並電性連接該佈線結構之複數第二導電元件及一設於該佈線結構上以包覆該複數第二導電元件之第二封裝層，以令該封裝模組以其第二封裝層設於該第一封裝層上，使該佈線結構疊合於該線路結構上，且各該第二導電元件對應結合各該第一導電元件，使該複數第二導電元件電性連接該複數第一導電元件。
本發明亦提供一種電子封裝件之製法，係包括：於一線路結構上配置電子元件及複數第一導電元件，且該線路結構係電性連接該電子元件及該 複數第一導電元件；形成第一封裝層於該線路結構上，以令該第一封裝層包覆該電子元件及該複數第一導電元件，以形成第一封裝模組；提供一該第二封裝模組，其包含佈線結構、設於該佈線結構上之複數第二導電元件及一設於該佈線結構上以包覆該複數第二導電元件之第二封裝層；以及將該第二封裝模組以其第二封裝層設於該第一封裝模組之第一封裝層上，使該佈線結構疊合於該線路結構上，且各該第二導電元件對應結合各該第一導電元件，以令該複數第二導電元件電性連接該複數第一導電元件。
前述之電子封裝件及其製法中，該第一封裝層之熱膨脹係數不同於該第二封裝層之熱膨脹係數。
前述之電子封裝件及其製法中，該第一封裝層上形成有結合層，以令該第二封裝層透過該結合層設於該第一封裝層上。例如，該結合層包覆該複數第一導電元件及該複數第二導電元件之間的對接處。
前述之電子封裝件及其製法中，該複數第一導電元件與該複數第二導電元件之端部係分別外露出該第一封裝層及該第二封裝層。
由上可知，本發明之電子封裝件及其製法中，主要藉由將該線路結構與該佈線結構同時分開製作，以縮短製程時間，故相較於習知技術，本發明之製法能有效降低製作成本。
再者，本發明由於該線路結構與該佈線結構分開製作，使該佈線結構並非於該線路結構上製作，故相較於習知技術，若該電子封裝件需配置多層線路重佈層時，可分別控制該線路結構與該佈線結構上之應力分布，因而能有效減少應力，以避免該線路層與該佈線層因無法承受應力集中而斷裂之問題。
1:半導體封裝件
10,20:線路結構
100,120:線路重佈層
11:半導體晶片
12,22:佈線結構
13:導電柱
15:包覆層
2:電子封裝件
2a:第一封裝模組
2b:第二封裝模組
20a:第一側
20b:第二側
200:介電層
201:線路層
21:電子元件
21a:作用面
21b:非作用面
210:電極墊
211:導電凸塊
212:底膠
220:絕緣層
221:佈線層
23:第一導電元件
230:凸出部
24:結合層
25:第一封裝層
25a:表面
26:第二導電元件
26b:端部
27:第二封裝層
9:承載件
90:離型層
圖1A至圖1B係為習知半導體封裝件之製法之剖視示意圖。
圖2A至圖2E係為本發明之電子封裝件之製法之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2E係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，於一承載件9上形成一線路結構20，該線路結構20係具有相對之第一側20a與第二側20b，以令該線路結構20以其第二側20b結合該承載件9。
於本實施例中，該線路結構20係如具有核心層與線路層之封裝基板(substrate)或無核心層(coreless)之基板結構，其包含至少一介電層200及結合該介電層200之線路層201。例如，以線路重佈層(redistribution layer，簡稱RDL)之製作方式形成無核心層(coreless)基板結構，其中，形成該線路層201之材質係 為銅，且形成該介電層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該線路結構20亦可為其它可供承載如晶片等電子元件之載板，如矽中介板(interposer)，並不限於上述。
再者，該承載件9例如為半導體材質(如矽或玻璃)之板體，其上形成有一離型層90，使該線路結構20結合於該離型層90上。
如圖2B所示，設置至少一電子元件21於該線路結構20之第一側20a上，且形成複數第一導電元件23於該線路結構20之第一側20a之線路層201上。
於本實施例中，該電子元件21係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容或電感。例如，該電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，且該作用面21a具有複數電極墊210，使該電子元件21以其電極墊210藉由覆晶方式(透過如圖所示之複數導電凸塊211)電性連接該線路層201，再以底膠212包覆該些導電凸塊211；或者，該電子元件21亦可藉由複數銲線(圖略)以打線方式電性連接該線路層201；亦或，該電子元件21可直接接觸該線路層201。然而，有關該電子元件21電性連接線路層201之方式不限於上述。
再者，該第一導電元件23係為如銲錫球之塊體，其以如植球(ball placement)製程將該複數第一導電元件23結合(如熔接)於該線路層201上，使該複數第一導電元件23電性連接該線路層201。
如圖2C所示，形成一第一封裝層25於該線路結構20之第一側20a上，以令該第一封裝層25包覆該電子元件21與該複數第一導電元件23。接著，形成一結合層24於該第一封裝層25上，以於該承載件9上形成一第一封裝模組2a。
於本實施例中，該第一封裝層25係為絕緣材，如聚醯亞胺PI)、乾膜(dry film)、環氧樹脂(epoxy)環氧樹脂之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該線路結構20之第一側20a上。
再者，可藉由整平製程，如蝕刻方式，移除該第一封裝層25之部分材質，以令該第一封裝層25之上側之表面25a齊平該電子元件21之非作用面21b，並使該些第一導電元件23凸出及外露於該第一封裝層25之表面25a，而形成有凸出部230，故該結合層24係接觸覆蓋該電子元件21之非作用面21b且包覆該些第一導電元件23之凸出部230。
又，該結合層24係為黏著材，如膠膜，其不同於該第一封裝層25之材質。
如圖2D所示，於進行圖2A至圖2C所示之製程時，同步進行其它製程，即於一佈線結構22上形成複數第二導電元件26，再於該佈線結構22上形成一第二封裝層27，以包覆該些第二導電元件26，並使該複數第二導電元件26之端部26b外露出該第二封裝層27，俾形成一第二封裝模組2b。
於本實施例中，該佈線結構22係如具有核心層與線路層之封裝基板(substrate)或無核心層(coreless)之基板結構，其包含至少一絕緣層220及結合該絕緣層220之佈線層221。例如，以線路重佈層(redistribution layer，簡稱RDL)之製作方式形成無核心層(coreless)基板結構，其中，形成該佈線層221之材質係為銅，且形成該絕緣層220之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該佈線結構22亦可為其它可供承載如晶片等電子元件之載板，如矽中介板(interposer)，並不限於上述。
再者，該第二導電元件26係電性連接該佈線結構22，且該第二導電元件26係為如銅柱之金屬柱或其它材質之柱體。
又，該第二封裝層27係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該佈線結構22上。應可理解地，形成該第二封裝層27之材質可相同或相異於該第一封裝層25之材質，例如，該第一封裝層25之熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)與第二封裝層27之熱膨脹係數不相同。
如圖2E所示，將該第二封裝模組2b以其第二封裝層27結合至該第一封裝模組2a之結合層24上，使該佈線結構22疊合於該線路結構20上，且各該第二導電元件26對應結合各該第一導電元件23，使該複數第二導電元件26電性連接該複數第一導電元件23。之後，移除該承載件9與離型層90，以外露出該線路結構20之第二側20b，進而製得電子封裝件2。
於本實施例中，該複數第二導電元件26可插入該結合層24中以接觸該複數第一導電元件23，以令該結合層24包覆該複數第一導電元件23及該複數第二導電元件26之間的對接處。
另外，於後續製程中，可於該線路結構20之第二側20b進行植球製程以形成複數銲球(圖略)，供接置一電路板(圖略)。
因此，本發明之製法，主要藉由將該線路結構20與該佈線結構22同時分開製作，以縮短製程時間，故相較於習知技術，本發明之製法能有效降低製作成本。
再者，由於該線路結構20與該佈線結構22分開製作，使該佈線結構22並非於該線路結構20上製作，故若該電子封裝件2需配置多層線路重佈層時，可分別控制該線路結構20與該佈線結構22上之應力分布，因而能有效減少應力，以避免該線路層201與該佈線層221因無法承受應力集中而斷裂之問題。
另一方面，亦可藉由該第一封裝層25之熱膨脹係數不同於該第二封裝層27之熱膨脹係數，以分散應力，故當該第二封裝層27結合至該結合層24上後，能有效分散該佈線結構22與該線路結構20之應力，以減少應力，因而能避免該線路層201與該佈線層221因無法承受應力集中而斷裂之問題。
本發明亦提供一種電子封裝件2，係包括：一線路結構20、至少一電子元件21、複數第一導電元件23、一第一封裝層25以及一第二封裝模組2b。
所述之電子元件21係設於該線路結構20上並電性連接該線路結構20。
所述之複數第一導電元件23係設於該線路結構20上並電性連接該線路結構20。
所述之第一封裝層25係設於該線路結構20上以包覆該電子元件21及該複數第一導電元件23。
所述之第二封裝模組2b係結合於該第一封裝層25上，其中，該第二封裝模組2b係包含一佈線結構22、設於該佈線結構22上並電性連接該佈線結構22之複數第二導電元件26、及一設於該佈線結構22上以包覆該複數第二導電元件26之第二封裝層27，以令該第二封裝模組2b以其第二封裝層27設於該第一封裝層27上，使該佈線結構22疊合於該線路結構20上，且各該第二導電元件26對應結合各該第一導電元件23，使該第二導電元件26電性連接該第一導電元件23。
於一實施例中，該第一封裝層25之熱膨脹係數不同於該第二封裝層27之熱膨脹係數。
於一實施例中，該第一封裝層25上形成有一結合層24，以令該第二封裝層27結合該結合層24。例如，該結合層24包覆該第一導電元件23及第二導電元件26之間的對接處。
於一實施例中，該第一與第二導電元件23,26之至少一者係為銲錫球或金屬柱。
綜上所述，本發明之電子封裝件及其製法，係藉由將該線路結構與該佈線結構同時分開製作，以縮短製程時間，且能分別控制該線路結構與該佈線結構上之應力分布，故本發明不僅能降低製作成本，且能避免線路斷裂之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:第一封裝模組
2b:第二封裝模組
20:線路結構
20a:第一側
20b:第二側
21:電子元件
22:佈線結構
23:第一導電元件
24:結合層
25:第一封裝層
26:第二導電元件
27:第二封裝層

Claims (10)

  1. 一種電子封裝件，係包括：
    線路結構；
    電子元件，係設於該線路結構上並電性連接該線路結構；
    複數第一導電元件，係設於該線路結構上並電性連接該線路結構；
    第一封裝層，係設於該線路結構上以包覆該電子元件及該複數第一導電元件；以及
    封裝模組，係結合於該第一封裝層上，其中，該封裝模組係包含佈線結構、設於該佈線結構上並電性連接該佈線結構之複數第二導電元件及一設於該佈線結構上以包覆該複數第二導電元件之第二封裝層，以令該封裝模組以其第二封裝層設於該第一封裝層上，使該佈線結構疊合於該線路結構上，且各該第二導電元件對應結合並電性連接各該第一導電元件。
  2. 如請求項1所述之電子封裝件，其中，該第一封裝層之熱膨脹係數不同於該第二封裝層之熱膨脹係數。
  3. 如請求項1所述之電子封裝件，其中，該第一封裝層上形成有結合層，以令該第二封裝層透過該結合層設於該第一封裝層上。
  4. 如請求項3所述之電子封裝件，其中，該結合層包覆該複數第一導電元件及該複數第二導電元件之間的對接處。
  5. 如請求項1所述之電子封裝件，其中，該複數第一導電元件與該複數第二導電元件之端部係分別外露出該第一封裝層及該第二封裝層。
  6. 一種電子封裝件之製法，係包括：
    於一線路結構上配置電子元件及複數第一導電元件，且該線路結構係電性連接該電子元件及該複數第一導電元件；
    形成第一封裝層於該線路結構上，以令該第一封裝層包覆該電子元件及該複數第一導電元件，以形成第一封裝模組；
    提供一該第二封裝模組，其包含佈線結構、設於該佈線結構上之複數第二導電元件及一設於該佈線結構上以包覆該複數第二導電元件之第二封裝層；以及
    將該第二封裝模組以其第二封裝層設於該第一封裝模組之第一封裝層上，使該佈線結構疊合於該線路結構上，且各該第二導電元件對應結合並電性連接各該第一導電元件。
  7. 如請求項6所述之電子封裝件之製法，其中，該第一封裝層之熱膨脹係數不同於該第二封裝層之熱膨脹係數。
  8. 如請求項6所述之電子封裝件之製法，其中，該第一封裝層上形成有結合層，以令該第二封裝層透過該結合層設於該第一封裝層上。
  9. 如請求項8所述之電子封裝件之製法，其中，該結合層包覆該複數第一導電元件及該複數第二導電元件之間的對接處。
  10. 如請求項6所述之電子封裝件之製法，其中，該複數第一導電元件與該複數第二導電元件之端部係分別外露出該第一封裝層及該第二封裝層。
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