TW202312121A - Display panel and pixel circuit thereof - Google Patents

Abstract

The present invention discloses a pixel circuit and a display panel. The pixel circuit includes: a driving unit, an emitting element and an emitting control circuit serial connected between a voltage source and a reference voltage source; a first driving block, coupled to a control terminal of the driving unit and a vertical signal line, configured to output a control signal according to a PAM signal and a PWM signal, and configured to receive a reference voltage from the vertical signal line during an emitting period, and receive the PWM signal during a data writing period; and a second driving block, connected to the vertical signal line, and configured to output the reference voltage to the first driving block via the vertical signal line during the emitting period. A frame is compose of the emitting period and the data writing period.

Description

Display panel and its pixel circuit

The invention relates to a display panel and a pixel circuit thereof.

The resolution of display devices is increasing day by day. An increase in resolution means an increase in scan lines. For high-resolution display devices, there are still some practical problems in the progressive scanning driving method. For example, current division affects optical effects, signal voltage conversion loading and other issues. Therefore, it is necessary to improve the high-resolution display device and its driving method.

One aspect of the present invention discloses a pixel circuit, comprising: a driving unit, a light-emitting element and a light-emitting control circuit connected in series between a power supply voltage and a reference power supply; a first driving block coupled to the A control terminal and a vertical signal line of the drive unit are used to output a control signal to the drive unit according to a pulse width modulation signal and an amplitude modulation signal, and to receive a reference from the vertical signal line at a light emitting time voltage, receiving the pulse width modulation signal from the vertical signal line at a data writing time; and a second driving block, connected to the vertical signal line, for outputting the reference through the vertical signal line at the light emitting time voltage to the first drive block. The data writing time and the lighting time constitute a frame.

Another aspect of the present invention discloses a display panel including a plurality of pixel circuits. The pixel circuits are configured as complex groups. Each pixel circuit includes a driving unit, a light emitting element and a light emitting control circuit connected in series between a power supply voltage and a reference power supply; a first driving block, coupled to a control terminal of the driving unit and a The vertical signal line is used to output a control signal to the drive unit according to a pulse width modulation signal and an amplitude modulation signal, and to receive a reference voltage from the vertical signal line at a light emitting time, and to receive a reference voltage at a data writing time receiving the pulse width modulation signal from the vertical signal line; and a second driving block connected to the vertical signal line for outputting the reference voltage to the first driving block through the vertical signal line at the light emitting time . The data writing time and the lighting time constitute a frame. The signal timings used by these pixel circuits are determined according to the group they belong to.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

Please refer to FIG. 1 , which is a block diagram of a pixel unit according to an embodiment of the present invention. The pixel unit 100 includes a driving unit 120 , a light emitting controller 130 , a light emitting element LED, a first driving block 150 and a second driving block 160 .

The driving unit 120 includes a driving transistor TD. The driving transistor TD has a control terminal for receiving a control signal CS, wherein the control signal CS may include a pulse width control signal and an amplitude control signal. The driving transistor TD generates a driving signal according to the control signal CS to drive the light emitting element LED to emit light. In this embodiment, the light emitting element LED may be any form of light emitting diode.

The circuits 130-1, 130-2 in the lighting controller 130 are coupled in series with the driving transistor TD and the light emitting element LED. The driving transistor TD is coupled between the circuits 130-1, 130-2. In this embodiment, the circuits 130-1 and 130-2 include transistors T1 and T2 respectively, and are coupled between the driving transistor TD, the power supply voltage VDD and the light emitting element LED. The control terminals of the transistors T1 and T2 receive a first light emission control signal EM1 and a second light emission control signal EM2 respectively, and are turned on or off according to the first light emission control signal EM1 and the second light emission control signal EM2 respectively. It should be noted that in an alternative embodiment, the circuits 130-1 and 130-2 in the lighting controller 130 can be implemented alternatively, and it is not necessary to configure the circuits 130-1 and 130-2 at the same time.

The first driving block 150 is used for generating the control signal CS according to the pulse width modulation signal D_PWM and the amplitude modulation signal D_PAM. The first driving block 150 is coupled to a vertical signal line VL. During a data writing period of a frame, the first driving block 150 receives the pulse width modulation signal D_PWM through the vertical signal line VL; during an emitting period of a frame, The first driving block 150 receives a reference voltage PPO through the vertical signal line VL.

The second driving block 160 is coupled to the first driving block through vertical signal lines. During the light emitting time, the second driving block 160 outputs the reference voltage PPO.

In one embodiment, the light emitting controller 130 controls the light emitting element LED to emit light intermittently at least twice during the light emitting time.

Please refer to FIG. 2 , which is a block diagram of a display panel according to an embodiment of the present invention. The display panel 200 includes a plurality of pixel circuits P11 -Pxy, a plurality of horizontal signal lines HL1 -HLx, a plurality of vertical signal lines VL1 -VLy and a control chip 210 . The pixel circuits P11 ˜ Pxy can be realized by using the pixel circuit 100 . The pixel circuits P11 ˜ Pxy are configured as x rows and y columns, where x and y are positive integers. Each row of pixel circuits is coupled to the control chip 210 through a corresponding horizontal signal line. The pixel circuits of each column are coupled to the control chip 210 through corresponding vertical signal lines. The pixel circuits are further divided into at least two groups, and this embodiment takes two groups as an example. The pixel circuits of the first group and the second group respectively include multiple rows of pixel circuits, wherein the pixel circuit row belonging to the first group is called the first pixel circuit row, and the pixel circuit row belonging to the second group is called the second pixel circuit row. Two-pixel circuit row. In one embodiment, the first pixel circuit row and the second pixel circuit row are arranged alternately. For example, pixel circuits of odd rows are assigned to the first group, and pixel circuits of even rows are assigned to the second group. The first group of pixel circuits operates at a first timing, and the second group of pixel circuits operates at a second timing, wherein there is a time difference between the start of the first timing and the start of the second timing.

The details of the present invention will be described below with the circuit diagram of the pixel circuit according to an embodiment of the present invention shown in FIG. 3 .

The pixel circuit 300 includes a driving transistor TD, transistors T1-T8, light emitting elements LED and capacitors C1 and C2. The pixel circuit 300 belongs to the pixel circuit in the nth row and the mth column of the display panel 200 , where n is a positive integer not greater than x, and m is a positive integer not greater than y. In this embodiment, the transistors TD, T1-T8 are all PMOS.

The first end of the transistor T1 receives the power voltage VDD. The control terminal of the transistor T1 receives the first light emission control signal EM1[n]. The first terminal of the driving transistor TD is coupled to the second terminal of the transistor T1. The first terminal of the transistor T2 is coupled to the second terminal of the driving transistor TD. The control terminal of the transistor T2 receives the second light emission control signal EM2[n]. A first terminal of the light emitting element LED is coupled to a second terminal of the transistor T2. The second end of the light emitting element LED receives the reference power VSS. The first end of the transistor T3 is coupled to the first end of the driving transistor TD. The control terminal of the transistor T3 receives a first gate driving signal G1 [n]. The second end of the transistor T3 receives the amplitude modulation signal D_PAM[m]. The first terminal of the transistor T4 is coupled to the control terminal of the driving transistor TD. The control terminal of the transistor T4 receives the first gate driving signal G1 [n]. The first end of the transistor T5 is coupled to the first end of the transistor T4. The control terminal of the transistor T5 is coupled to the control terminal of the transistor T4. The second end of the transistor T5 is connected to the corresponding vertical signal line VLm. The first terminal of the transistor T6 is coupled to the second terminal of the driving transistor TD. The second end of the transistor T6 is connected to the first end of the transistor T4. The control terminal of the transistor T6 receives a second gate driving signal G2 [n]. The first end of the transistor T7 is coupled to the second end of the transistor T6. The second end of the transistor T7 receives a reset voltage RES. The control terminal of the transistor T7 receives a reset control signal RES[n]. The first end of the transistor T8 is connected to the corresponding vertical signal line VLm. The second end of the transistor T8 receives the reference voltage PPO. The signal received by the control terminal of the transistor T8 depends on the group to which the pixel circuit 300 belongs. When the pixel circuit 300 belongs to the first group, the signal is the first switching signal IF1; when the pixel circuit 300 belongs to the second group , the signal is the second switching signal IF2. The first switching signal IF1 and the second switching signal IF2 are configured so that the data writing time and light emitting time corresponding to the first group of pixel circuits are between the data writing time and light emitting time corresponding to the second group of pixel circuits with this time difference. The first terminal of the capacitor C1 receives the power voltage VDD. The second end of the capacitor C2 is coupled to the first end of the transistor T4. A first terminal of the capacitor C2 is coupled to a second terminal of the transistor T4. The second terminal of the capacitor C2 receives the time-dependent control signal SWEEP[n].

In this embodiment, the lighting controller includes transistors T1 and T2. The first driving block includes transistors T1-T7 and capacitors C1 and C2. The second driving block includes a transistor T8.

The first gate drive signal G1[n], the second gate drive signal G2[n], the first light emission control signal EM1[n], the second light emission control signal EM2[n], the reset signal RES[n], The time control signal SWEEP[n] is a signal corresponding to the pixel circuit of the nth row, which can be generated by a gate drive circuit array (gate on array, GOA), wherein the GOA circuit can be integrated in the control chip or partially integrated in the control chip And additional settings. The first switching signal IF1 and the second switching signal IF2 can be generated by the control chip. The pulse width modulation signal D_PWM[m] and the amplitude modulation signal D_PAM[m] are data corresponding to the pixel circuit in the mth column, and can be generated by the control chip. In one embodiment, the mth vertical signal line can be coupled to the control chip through a multiplexing circuit MXm. The multiplexing circuit MXm selectively outputs the reference voltage PPO and the pulse width modulation signal D_PWM according to the first switching signal IF1 (or the second switching signal IF2, depending on whether n is odd or even) and the multiplexing control signal MXCS. In an embodiment, the multiplexing circuit MXm may include transistors T9 and T10. The first end of the transistor T9 receives the reference voltage PPO. The second end of the transistor T9 is connected to the vertical signal line VLm. The control terminal of the transistor T9 receives the first switching signal IF1 (or the second switching signal IF2 ). The first end of the transistor T10 receives the pulse width modulation signal D_PWM[m]. The second end of the transistor T10 is connected to the vertical signal line VLm. The transistor T10 receives the multiplexing control signal MXCS.

Specifically, during the data writing time period, the first switching signal IF1 and the second switching signal IF2 cause the transistors T8 and T9 to be turned off, and the multiplexing control signal MXCS causes the transistor T10 to be turned on; during the light-emitting time period, the first switching signal IF1 and the second switching signal IF2 turn on the transistors T8 and T9 , and the multiplexing control signal MXCS turns off the transistor T10 .

Please refer to FIG. 4 , which is a schematic diagram of the operation and signal timing of the display panel. 400 is a schematic diagram of the operation of the first group of pixel circuits, and 410 is a schematic diagram of signal timing used by the first group of pixel circuits. In 400, the horizontal axis is time, and the vertical axis is the number of the first pixel circuit row, for example, 1, 3, 5, . . . from bottom to top. A frame FR1 is divided into a data writing time t1 and a light emitting time t2. At the data writing time t1, the first switching signal IF1 maintains a high level, and writes new pixel data according to the PWM signal and the amplitude modulation signal after clearing the old pixel data in the pixel circuit. At the light-emitting time t2, the first switching signal IF1 is at a low level, and the first pixel circuit intermittently emits light row by row. In this embodiment, the intermittent lighting interval is a quarter of the length of the frame FR1, that is, (t1+t2)/4. 420 is a schematic diagram of the operation of the second group of pixel circuits, and 430 is a schematic diagram of the first group of pixel circuits Schematic diagram of the signal timing used. In 420, the horizontal axis is time, and the vertical axis is the number of the second pixel circuit row, for example, 2, 4, 6, . . . from bottom to top. Similarly, a frame FR2 is divided into a data writing time t1 and a light emitting time t2. At the data writing time t1, the second switching signal IF2 maintains a high level, and writes new pixel data according to the PWM signal and the amplitude modulation signal after clearing the old pixel data in the pixel circuit. At the lighting time t2, the second switching signal IF2 is at a low level, and the second pixel circuit intermittently emits light row by row. In this embodiment, the interval of the intermittent light emission is a quarter of the length of the frame FR2, that is, (t1+t2)/4. It should be noted that there is a time difference t3 between the start time of the frame FR2 and the start time of the frame FR1. In this embodiment, the lengths of the frames FR1 and FR2 are the same, t1+t2, and the time difference t3 is half of the lengths of the frames FR1/FR2, ie t3=(t1+t2)/2.

In detail, each group of pixel circuits adopts sequential scanning to emit light, and multiple groups of pixel circuits adopt interlaced light emission. By overlapping 400 and 420 , it can be seen that the first group and the second group of pixel circuits are equivalent to emitting light four times in one frame. And the four times of lighting evenly divide the time of one frame. If the length of a frame is 16.6ms, the update rate of 60Hz can be achieved. That is to say, the desired update rate can be determined by properly configuring the number of groups of pixel circuits and the number of times each group of pixel circuits emits light within a frame time. For example, the pixel circuits can be divided into three groups, and each group of pixel circuits emits light three times during the light-emitting time, which is equivalent to uniformly emitting nine times in one frame time.

Please refer to FIG. 5 , which shows a circuit diagram of a pixel circuit according to another embodiment of the present invention. The pixel circuit 500 includes a driving transistor TD, transistors T1-T15, light-emitting elements LED and capacitors C1-C3.

The first end of the transistor T1 is coupled to the first end of the driving transistor TD. The first terminal of the transistor T2 is coupled to the second terminal of the driving transistor TD. The control terminal of the transistor T2 receives the light emission control signal EM_PAM[n]. A first terminal of the light emitting element LED is coupled to a second terminal of the transistor T2. The second end of the light emitting element LED receives the reference power VSS. The transistor T3 receives the amplitude modulation signal D_PAM[m]. The second end of the transistor T3 is coupled to the second end of the transistor T1. The control terminal of the transistor T3 receives the gate driving signal G2[n]. The first end of the transistor T4 is coupled to the second end of the transistor T3. The control terminal of the transistor T4 receives the light emission control signal EM_PWM[n]. The second end of the transistor T4 is coupled to the power voltage VDD. The first end of the transistor T5 is coupled to the second end of the transistor T4. The control terminal of the transistor T5 is coupled to the control terminal of the transistor T4. The first end of the transistor T6 is coupled to the second end of the transistor T5. The control terminal of the transistor T6 receives the setting signal VST[n]. The second end of the transistor T6 receives the reference voltage PPO. The first end of the transistor T7 is coupled to the second end of the transistor T5. The second end of the transistor T7 is coupled to the second end of the transistor T6. The control terminal of the transistor T7 receives the gate drive signal GATE[n]. The first end of the transistor T8 is coupled to the first end of the transistor T1. The second terminal of the transistor T8 is coupled to the control terminal of the transistor T1. The control terminal of the transistor T8 is coupled to the control terminal of the transistor T3. The first end of the transistor T9 is coupled to the second end of the transistor T8. The control terminal of the transistor T9 receives the signal VST[n]. The second terminal of the transistor T9 is coupled to the control terminal of the transistor T9. The first terminal of the transistor T10 is coupled to the control terminal of the driving transistor TD. \The control terminal of the transistor T10 receives the light emission control signal EM_PWM[n]. A first terminal of the transistor T11 is coupled to a second terminal of the transistor T10 . The control terminal of the transistor T11 receives the setting signal SET[n]. The second end of the transistor T11 receives the setting voltage VSET. The first end of the transistor T12 is coupled to the first end of the transistor T11. The control terminal of the transistor T12 is coupled to the control terminal of the transistor T7. A first terminal of the transistor T13 is coupled to a second terminal of the transistor T12. The second terminal and the control terminal of the transistor T13 are coupled to the second terminal of the transistor T9. A first terminal of the transistor T14 is coupled to a first terminal of the transistor T12. The second end of the transistor T14 is connected to the vertical signal line VLm, and receives the pulse width modulation signal D_PWM[m] through the vertical signal line VLm at the data writing time. The control terminal of the transistor T14 is coupled to the second terminal of the transistor T12. The first end of the transistor T15 is connected to the vertical signal line VLm. The second end of the transistor T15 receives the reference voltage PPO. The control terminal of the transistor T15 receives the switching signal IF. A first terminal of the capacitor C1 is coupled to a second terminal of the transistor T12. The second end of the capacitor C1 receives the time control signal SWEEP[n]. The first end of the capacitor C2 is coupled to the control end of the transistor T1. The second end of the capacitor C2 is coupled to the second end of the transistor T5. The first end of the capacitor C3 is coupled to the first end of the transistor T10. The second end of the capacitor C3 is coupled to the second end of the transistor T11.

In this embodiment, the transistor T1 is also configured as a transistor for driving the light emitting element LED. The control terminal of the driving transistor TD receives the pulse width control signal generated according to the pulse width modulation signal D_PWM[m]. The control terminal of the transistor T1 receives the amplitude control signal generated according to the amplitude modulation signal D_PAM[m]. That is to say, in this embodiment, the driving unit includes the driving transistor TD and the transistor T1, and the first driving block includes a circuit for generating a pulse width control signal and outputting it to the control terminal of the driving transistor TD and for A circuit that generates an amplitude control signal and outputs it to the control terminal of transistor T1. The second driving block is the transistor T15.

It should be noted that the 8T2C (eight transistors and two capacitors) architecture in Figure 3 and the 16T3C (sixteen transistors and three capacitors) architecture in Figure 5 are just examples, and any applicable PWM/PAM drive circuit architecture can be applied in the present invention.

The advantage of the present invention is that the vertical signal line and the second driving block will provide a stable reference voltage PPO to the first driving block (PAM/PWM driving circuit) during the lighting time without drawing from the power supply voltage. This method can avoid visual flickering caused by unstable brightness caused by current shunting when emitting light.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100, 300, 500: pixel circuit 200: display panel 120: drive unit 130: Lighting control circuit 130-1, 130-2: circuit TD: drive transistor T1~T15: Transistor C1~C3: capacitance 150: The first drive block 160: Second drive block VL, VL1~VLy: vertical signal lines HL1~HLx: horizontal signal lines 210: control chip PPO: reference voltage CS: control signal D_PWM: pulse width modulation signal

FIG. 1 is a block diagram of a pixel circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of a display panel according to an embodiment of the invention. FIG. 3 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. FIG. 4 is a schematic diagram illustrating the operation and signal timing of the display panel according to an embodiment of the present invention. FIG. 5 is a circuit diagram of a pixel circuit according to another embodiment of the present invention.

100:Pixel circuit

130: Lighting control circuit

130-1, 130-2: circuit

TD: drive transistor

T1, T2: Transistor

150: The first drive block

160: Second drive block

VL: vertical signal line

PPO: reference voltage

CS: control signal

D_PWM: pulse width modulation signal

Claims (12)

A pixel circuit, comprising: A drive unit, a light-emitting element and a light-emitting control circuit are connected in series between a power supply voltage and a reference power supply; A first drive block, coupled to a control terminal of the drive unit and a vertical signal line, is used to output a control signal to the drive unit according to a pulse width modulation signal and an amplitude modulation signal, and in a receiving a reference voltage from the vertical signal line during a light emitting time, and receiving the pulse width modulation signal from the vertical signal line during a data writing time; and a second driving block, connected to the vertical signal line, for outputting the reference voltage to the first driving block through the vertical signal line during the light emitting time, The data writing time and the light emitting time constitute a frame. The pixel circuit as described in claim 1, wherein the second driving block selectively outputs the reference voltage according to a switching signal, and a timing of the switching signal depends on the plurality of groups that the pixel circuit belongs to a display panel Groups in the pixel circuit. The pixel circuit as described in claim 2, wherein the second driving block includes a transistor, a first end of the transistor is connected to the vertical signal line, a control end of the transistor receives the switching signal, the A second terminal of the transistor receives the reference voltage. The pixel circuit according to claim 1, wherein the first driving block, the driving unit and the light emission control circuit are configured to cause the light emitting element to emit light intermittently more than twice during the light emitting time. The pixel circuit according to Claim 4, wherein the number of intermittent light emission is twice, and the interval between two light emission is a quarter of a frame time. A display panel, comprising: A plurality of pixel circuits, the pixel circuits are configured as a complex array, each of the pixel circuits includes: A drive unit, a light-emitting element and a light-emitting control circuit are connected in series between a power supply voltage and a reference power supply; A first drive block, coupled to a control terminal of the drive unit and a vertical signal line, is used to output a control signal to the drive unit according to a pulse width modulation signal and an amplitude modulation signal, and in a receiving a reference voltage from the vertical signal line during a light emitting time, and receiving the pulse width modulation signal from the vertical signal line during a data writing time; and a second driving block, connected to the vertical signal line, for outputting the reference voltage to the first driving block through the vertical signal line during the light emitting time, The data writing time and the lighting time constitute a frame, and the signal timings used by the pixel circuits are determined according to the groups they belong to. The display panel as claimed in claim 6, wherein the second driving block selectively outputs the reference voltage according to a switching signal, and a timing of the switching signal depends on the group to which the pixel circuit belongs. The display panel as described in claim 7, wherein the second driving block includes a transistor, a first end of the transistor is connected to the vertical signal line, a control end of the transistor receives the switching signal, and the transistor A second terminal of the crystal receives the reference voltage. The display panel according to claim 6, wherein the first driving block, the driving unit and the light emission control circuit are configured to cause the light emitting element to emit light intermittently more than twice during the light emitting time. The pixel circuit according to Claim 9, wherein the number of intermittent light emission is twice, and the interval between two light emission is a quarter of a frame time. The pixel circuit as described in claim 10, wherein the pixel circuits are configured as a first group and a second group, and the signal timing used by the pixel circuits of the first group is the same as that of the second group There is a time difference between the signal timings used by the pixel circuit, and the time difference is half a frame. The pixel circuit as claimed in claim 6, wherein the pixel circuits in each group of pixel circuits emit light row by row during the lighting time.

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