CN1983365B - Drive circuit for electroluminescence display screen - Google Patents

Abstract

Provided is a source driver circuit for an EL display panel having reduced variation in output current. The source driver circuit includes a number of cell transistors 634, each of which constitutes a single cell. The 0th bit is composed of one unit transistor 634, the first bit is composed of two unit transistors 634, the second bit is composed of four unit transistors 634, the third bit is composed of eight unit transistors 634, and the fourth bit is composed of eight unit transistors 634. A bit is made up of 16 unit transistors 634 , and a fifth bit is made up of 32 unit transistors 634 . Each unit transistor 634 together with the transistor 633a forms a current mirror circuit. Adjusting the current Ib flowing through the transistor 633a can change the current flowing through the unit transistors 634 . An accurate source driver IC with little variation is provided by configuring the output current circuit with unit transistors and adjusting the reference current so that the output current of the unit transistors can be adjusted.

Description

Driving circuit for electroluminescence display

This application is submitted by the applicant on March 5, 2003, and the application number is "03815105.7 (PCT/JP03/02535)", and the invention name is "drive circuit for electroluminescent display screen". Divisional application. the

technical field

The present invention relates not only to a driving circuit (IC) for a display screen, but also to a light-emitting display screen such as an EL display screen using organic or inorganic electroluminescence (EL) elements. In addition, it also relates to an information display device and similar devices using the EL display screen, a driving method for the EL display screen, and a driving circuit for the EL display screen. the

Background technique

Generally, an active matrix display device displays images by arranging a large number of pixels in a matrix, and controlling the light intensity of each pixel according to a video signal. For example, if a liquid crystal is used as an electrochemical substrate, the transmittance to each pixel changes according to the voltage written in the pixel, and an organic electroluminescent (EL) material is used as an electrochemical substrate. In a source matrix display device, the emission brightness varies according to the current written to the pixel. the

In an LCD, each pixel acts as a light barrier, and an image is displayed when the backlight is blocked and revealed by the pixels, the light barriers. Organic EL displays are of the self-luminous type, in which each pixel has elements that emit light. Therefore, the organic EL display has advantages of being more viewable than a liquid crystal display, requiring no backlight, having a high response speed, and the like. the

The brightness of each light-emitting element (pixel) in an organic EL display is controlled by the amount of current. That is to say, the great difference between an organic EL display and a liquid crystal display is that the light-emitting elements are driven or controlled by electric current. the

The structure of an organic EL display is either a simple matrix type or an active matrix type, and although the former type has a simple and inexpensive structure, it is difficult to realize a large-scale high-resolution display of the former type. While the latter type can realize a large high-resolution display screen, it is technically a difficult method to control, and it is more expensive. Currently, active matrix type display screens are being vigorously developed. In an active matrix display, the current flowing through the light-emitting elements arranged in each pixel is controlled by the thin film transistor (transistor) installed in the pixel. the

Such an active matrix type organic EL display panel is disclosed in Japanese Laid-Open Patent No. 8-234683. An equivalent circuit for one pixel of the display screen is shown in FIG. 62 . The pixel 16 is composed of an EL element 15 as a light emitting element, a first transistor 11a, a second transistor 11b, and a storage capacitor 19. The EL element 15 is an organic electroluminescence (EL) element. According to this specification, the transistor 11 a that supplies (controls) current to the EL element 15 is called a driver transistor 11 . A transistor functioning as a switch, such as the transistor 11b shown in FIG. 62, is referred to as a switching transistor 11. the

In many cases, the organic EL element 15 can be called an OLED (Organic Light Emitting Diode) because of its rectifying action. In FIG. 62 or the like, the symbol of a diode is used as the EL element 15 . the

Incidentally, the EL element 15 according to this specification is not limited to OLEDs. It can be of any type as long as its luminous intensity is controlled by the amount of current flowing through the element 15 . Examples include inorganic EL elements, white light-emitting diodes composed of semiconductors, typical light-emitting diodes, and light-emitting transistors. The EL element 15 does not necessarily require a rectification action. Diodes are also available. The EL element 15 according to this specification may be any of the above elements. the

In the example of Fig. 62, the source terminal (S) of the P-channel transistor 11a is indicated by vdd (power supply potential), and the cathode of the EL element 15 is connected to the ground potential (VK). On the other hand, the anode is connected to the drain terminal (D) of the transistor 11b. In addition, the gate terminal of the P-channel transistor 11a is connected to the gate signal line 17a, the source terminal is connected to the source signal line 18, and the drain terminal is connected to the storage capacitor 19 such as the gate terminal of the P-channel transistor 11b (G ). the

To drive the pixels 16, a video signal representing luminance information is first applied to the source signal line 18 with the gate signal line 17a selected. Then, the transistor 11a is turned on, the storage capacitor 19 is charged or discharged, and the gate potential of the transistor 11b matches the potential of the video signal. When the gate signal line 17a is not selected, the transistor 11a is turned off, and the transistor 11b is electrically disconnected from the source signal line 18 . However, the gate potential of the transistor 11a is stably maintained by the storage capacitor (capacitor) 19. the

The current passed through transistor 11a to EL 15 is dependent on the gate-source voltage Vgs of transistor 11a, and the EL element 15 continues to emit light at an intensity commensurate with the amount of current supplied through transistor 11a. the

Since liquid crystal displays are not self-luminous devices, they have the problem of not being able to display images without a backlight. Also, there has been a problem of making the display panel thicker in order to provide the backlight with a certain thickness. In addition, in order to display colors on the LCD screen, color filters must be used. Therefore, there has always been a problem of low utilization of light. Also, there is a problem of a narrow color reproduction range. the

Organic EL displays are made from arrays of low-temperature polysilicon transistors. However, since an organic EL element emits light with an electric current, there has always been a problem that variations in transistor characteristics will cause display unevenness. the

Using pixel current programming can reduce display unevenness. For current programming, a current driven driver circuit is required. However, with a current-driven driver circuit, changes will also occur in the transistor elements making up the current output stage. This in turn causes variation in the gradation output current from the output terminal, making it impossible to display images normally. the

Contents of the invention

For this purpose, a driving circuit for an EL display panel (EL display device) according to the present invention includes outputting cell current and a plurality of transistors for generating the output current by changing the number of transistors. Also, the drive circuit is characterized by constituting a multi-stage current mirror circuit. Populations of transistors that pass signals through voltages are densely formed. In addition, signals are passed through currents between groups of transistors such as current mirror current groups. In addition, a reference current is generated by a plurality of transistors. the

The first inventive item of the present invention is a driver circuit suitable for an EL display panel. include:

A reference current generating device that generates a reference current;

A first current source, which is powered by a reference current from a reference current generating device, and outputs a first current, which is equivalent to a reference current to a plurality of second current sources;

a second current source powered by the first current output from the first current source and outputs a second current corresponding to the first current to a plurality of third current sources, and

a third current source, which is powered by the second current output from the second current source, and outputs a third current, which is equivalent to the second current to a plurality of fourth current sources,

Characterization among the four current sources is represented by selecting an appropriate number of cell current sources based on the input image data. the

The second invention item of the present invention is a kind of driver circuit for EL display screen, comprises:

a plurality of current generator circuits each having unit transistors equal in number to a power of 2,

a switching circuit connected to the relevant current generator circuit;

internal wiring to the outputs; and

The control circuit, which turns on and off the switch circuit according to the input data,

Therein, one end of each switching circuit is connected to the current generator circuit and the other end is connected to the internal wiring. the

The third invention of the present invention is a driver circuit for the EL display screen according to the second invention of the present invention, wherein:

The channel width W of the cell transistor is from 2 to 9 μm, including these two dimensions, and

The size (WL) of the transistor is 4 μm ² or larger.

The fourth invention of the present invention is a driver circuit for an EL display screen according to the second invention of the present invention, wherein;

the ratio of the cell transistor channel length L to the channel width W is 2 or more, and

The supply voltage used is between 2.5V and 9V inclusive. the

The fifth invention of the present invention is a driver circuit for an EL display, comprising:

A first output current circuit composed of a plurality of unit transistors passing the first unit current;

a second output current circuit consisting of a plurality of cell transistors passing the second cell current; and

an output stage which produces an output obtained by summing the output current of the first output current circuit and the output current of the second output current circuit,

Wherein the first unit current is less than the second unit current,

The first output current circuit operates in a low stratum region and a high stratum region according to strata, and

The second output current circuit operates in a high hierarchy region according to the hierarchy, and the output current of the first output current circuit does not change a current value in the high hierarchy region when the second output current circuit operates. the

The sixth invention of the present invention is a driver circuit for an EL display, comprising:

a programmable current generator circuit having a plurality of unit transistors corresponding to the output terminals;

First transistors that generate a first reference current that limits the current flowing through the cell transistors;

a gate connection connected to the plurality of first transistor gate terminals, and

The second and third transistors, whose gate terminals are connected to the gate connection, and together with the first transistors constitute a current mirror circuit,

Wherein the second reference current is provided to the second and third transistors. the

The seventh invention of the present invention is a driver circuit for an EL display screen according to the sixth invention of the present invention, comprising:

a programmable current generator circuit having a plurality of unit transistors corresponding to the output terminals;

a plurality of first transistors which together with the unit transistors form a current mirror circuit, and

second transistors that generate reference currents flowing through these first transistors,

Wherein, the reference current generated by the second transistor is divided by a plurality of first transistors. the

The eighth invention of the present invention is a driver circuit for an EL display panel according to the sixth or seventh invention of the present invention, wherein, in a driver IC chip including the driver circuit, a third transistor is used for setting the first reference In an area of the current supply wiring, the two wirings that are electrically connected to the reference current supply wiring set in this area are placed on the outermost,

The ninth invention of the present invention is an EL display device, comprising:

A first substrate on which the driver transistors are arranged in a matrix, and which includes a display area made up of EL elements formed corresponding to the driver transistors;

A source driver IC that applies programmed current or voltage to the driver transistors;

a first wiring formed on a first substrate located below the source driver IC;

a second wiring electrically connected to the first wiring and formed between the source driver IC and the display area; and

A cathode connection branches off from the second connection and applies an anode voltage to pixels in the display area. the

A tenth invention of the present invention is the EL display device according to the ninth invention of the present invention, wherein the first wiring has a function of shielding light. the

The eleventh invention of the present invention is an EL display device, comprising:

a display area in which pixels with EL elements are formed in a matrix;

a driver transistor, which supplies the light emission current to the EL element, and

source driver circuit, which supplies programmed current to the driver transistor,

Wherein, the driver transistors are P-channel transistors, and

In the source driver circuit, the transistors that generate the programmed current are N-channel transistors. the

The twelfth invention of the present invention is an EL display device comprising

A display area in which EL elements, driver transistors supplying light emission current to the EL elements, a first switching element forming a path between the driver transistors and the elements, and between the driver transistors and source signal lines the second switching elements forming the vias are formed in a matrix;

a first gate driver circuit that performs on/off control of the first switching element; and

a second gate driver circuit that performs on/off control of the second switching element;

a source driver circuit that applies video signals to the transistor elements; and

source driver circuit, which provides programmed current for the driver transistors,

where the driver transistor is a P-channel transistor, and

The transistors that generate the programming current in the source driver circuit are N-channel transistors. the

The thirteenth invention of the present invention is a display device, comprising:

Several EL elements;

A number of P-channel driver transistors, which provide the light emission current for the EL element;

a number of switching transistors formed between the EL elements and the driver transistors;

source driver circuit. It provides programmed current; and

gate driver circuit. They keep the switching transistors off for two horizontal scanning periods or longer in one frame period. the

Brief description of the drawings

Fig. 1 is in the display screen according to the present invention, the block diagram of pixel;

Fig. 2 is in the display screen according to the present invention, the block diagram of pixel;

Figure 3 is an explanatory diagram illustrating the operation of a display screen according to the present invention;

Figure 4 is an explanatory diagram illustrating the operation of a display screen according to the present invention;

5 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

Fig. 6 is a block diagram according to the display device of the present invention;

Figure 7 is an explanatory diagram illustrating a method of making a display screen according to the present invention;

Figure 8 is a block diagram of a display device according to the present invention;

Figure 9 is a block diagram of a display device according to the present invention;

Fig. 10 is a sectional view according to the display screen of the present invention;

Fig. 11 is the sectional view of display screen according to the present invention;

Figure 12 is an explanatory diagram illustrating a display screen according to the present invention;

13 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

14 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

15 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

16 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

17 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

18 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

19 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

20 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

21 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

22 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

23 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

24 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

25 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

26 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

27 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

28 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

29 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

30 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

31 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

32 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

33 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

Figure 34 is a block diagram of a display device according to the present invention;

35 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

36 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

Figure 37 is a block diagram of a display device according to the present invention;

Figure 38 is a block diagram of a display device according to the present invention;

39 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

Figure 40 is a block diagram of a display device according to the present invention;

Figure 41 is a block diagram of a display device according to the present invention;

Figure 42 is a block diagram of a pixel in a display screen according to the present invention;

Figure 43 is a block diagram of a pixel in a display screen according to the present invention;

44 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

45 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

46 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

Figure 47 is a block diagram of a pixel in a display screen according to the present invention;

Figure 48 is a block diagram of a display device according to the present invention;

FIG. 49 is an explanatory diagram illustrating a drive circuit according to the present invention;

Figure 50 is a block diagram of a pixel in a display screen according to the present invention;

Figure 51 is a diagram of a pixel in a display screen according to the present invention;

52 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

53 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

Figure 54 is a block diagram of a pixel in a display screen according to the present invention;

55 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

56 is an explanatory diagram illustrating a driving method of a display device according to the present invention;

Figure 57 is an explanatory diagram illustrating a handset according to the present invention;

Figure 58 is an explanatory diagram illustrating a viewfinder according to the present invention;

Figure 58 is an explanatory diagram illustrating a video camera according to the present invention;

FIG. 60 is an explanatory diagram illustrating a digital camera according to the present invention;

FIG. 61 is an explanatory diagram illustrating a TV (monitor) according to the present invention;

Figure 62 is a block diagram of a pixel in a conventional display screen;

Figure 63 is a functional block diagram of a drive circuit according to the present invention;

Figure 64 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 65 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 66 is an explanatory diagram illustrating a multi-stage current mirror circuit based on a voltage transfer type;

Fig. 67 is an explanatory diagram illustrating a multi-stage current mirror circuit based on a current passing type;

FIG. 68 is an explanatory diagram illustrating a driver circuit according to another example of the present invention;

FIG. 69 is an explanatory diagram illustrating a driver circuit according to another example of the present invention;

FIG. 70 is an explanatory diagram illustrating a driver circuit according to another example of the present invention;

FIG. 71 is an explanatory diagram illustrating a driver circuit according to another example of the present invention;

Figure 72 is an explanatory diagram illustrating a conventional driver circuit;

Figure 73 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 74 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 75 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 76 is an explanatory diagram illustrating a driver circuit according to the present invention;

FIG. 77 is an explanatory diagram illustrating a control method of a driver circuit according to the present invention;

Figure 78 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 79 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 80 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 81 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 82 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 83 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 84 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 85 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 86 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 87 is an explanatory diagram illustrating a driver circuit according to the present invention;

FIG. 88 is an explanatory diagram illustrating a driving method according to the present invention;

Figure 89 is an explanatory diagram illustrating a driver circuit according to the present invention;

FIG. 90 is an explanatory diagram illustrating a driving method according to the present invention;

Figure 91 is a block diagram of an EL display device according to the present invention;

Figure 92 is a block diagram of an EL display device according to the present invention;

Figure 93 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 94 is an explanatory diagram illustrating a driver circuit according to the present invention;

Figure 95 is a block diagram of an EL display device according to the present invention;

Figure 96 is a block diagram of an EL display device according to the present invention;

Figure 97 is a block diagram of an EL display device according to the present invention;

Figure 98 is a block diagram of an EL display device according to the present invention;

Figure 99 is a block diagram of an EL display device according to the present invention;

Figure 100 is a cross-sectional view of an EL display device according to the present invention;

Figure 101 is a cross-sectional view of an EL display device according to the present invention;

Figure 102 is a block diagram of an EL display device according to the present invention;

Figure 103 is a block diagram of an EL display device according to the present invention;

Figure 104 is a block diagram of an EL display device according to the present invention;

Figure 105 is a block diagram of an EL display device according to the present invention;

Figure 106 is a block diagram of an EL display device according to the present invention;

Figure 107 is a block diagram of an EL display device according to the present invention;

Figure 108 is a block diagram of an EL display device according to the present invention;

Figure 109 is a block diagram of an EL display device according to the present invention;

FIG. 110 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 111 is a block diagram of a gate driver circuit according to the present invention;

Figure 112 is a timing diagram of the gate driver circuit shown in Figure 111;

Figure 113 is a block diagram of a portion of a gate driver circuit according to the present invention;

Figure 114 is a timing diagram of the gate driver circuit shown in Figure 113;

FIG. 115 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 116 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

Fig. 117 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 118 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 119 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 120 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 121 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 122 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 123 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 124 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 125 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 126 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 127 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 128 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 129 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 130 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 131 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 132 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 133 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 134 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 135 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 136 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 137 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 138 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 139 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 140 is an explanatory diagram illustrating a display screen according to the present invention;

Figure 141 is an explanatory diagram illustrating a display screen according to the present invention;

Figure 142 is an explanatory diagram illustrating a display screen according to the present invention;

Figure 143 is an explanatory diagram illustrating a display screen according to the present invention;

Figure 144 is a block diagram of a pixel in a display screen according to the present invention;

Figure 145 is a block diagram of a pixel in a display screen according to the present invention;

FIG. 146 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 147 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 148 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 149 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 150 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 151 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 152 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 153 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 154 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 155 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 156 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 157 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 158 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 159 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 160 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 161 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 162 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 163 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 164 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 165 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 166 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 167 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 168 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 169 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 170 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 171 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 172 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 173 is an explanatory diagram illustrating a source driver IC according to the present invention;

FIG. 174 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 175 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

Fig. 176 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 177 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 178 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 179 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 180 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 181 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 182 is an explanatory diagram illustrating an EL display device according to the present invention;

FIG. 183 is an explanatory diagram illustrating an EL display device according to the present invention;

FIG. 184 is an explanatory diagram illustrating an EL display device according to the present invention;

FIG. 185 is an explanatory diagram illustrating an EL display device according to the present invention;

FIG. 186 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 187 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 188 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 189 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 190 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

Fig. 191 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 192 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 193 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 194 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 195 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 196 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 197 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

FIG. 198 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

Figure 199 is an explanatory diagram illustrating a driving circuit of an EL display device according to the present invention;

FIG. 200 is an explanatory diagram illustrating a driving method of an EL display device according to the present invention;

Figure 201 is an explanatory diagram illustrating an EL display device according to the present invention;

Figure 202 is an explanatory diagram illustrating an EL display device according to the present invention;

FIG. 203 is an explanatory diagram illustrating an EL display device according to the present invention;

Figure 204 is an explanatory diagram illustrating an EL display device according to the present invention;

FIG. 205 is an explanatory diagram illustrating an EL display device according to the present invention;

Figure 206 is an explanatory diagram illustrating an EL display device according to the present invention;

FIG. 207 is an explanatory diagram illustrating an EL display device according to the present invention;

FIG. 208 is an explanatory diagram illustrating an EL display device according to the present invention;

Figure 209 is an explanatory diagram illustrating an EL display device according to the present invention;

Figure 210 is an explanatory diagram illustrating an EL display device according to the present invention;

Figure 211 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 212 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 213 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 214 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 215 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 216 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 217 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 218 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 219 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 220 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 221 is an explanatory diagram illustrating a display device according to the present invention;

Figure 222 is an explanatory diagram illustrating a display device according to the present invention;

Figure 223 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 224 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 225 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 226 is an explanatory diagram illustrating a source driver IC according to the present invention;

Figure 227 is an explanatory diagram illustrating a display device according to the present invention;

Figure 228 is an explanatory diagram illustrating a display device according to the present invention;

(Description of code name) 

11 transistors (thin film transistors)

12 gate driver IC (circuit)

14 source driver IC (circuit)

15EL (element) (light-emitting element)

16 pixels

17 grid signal line

18 source signal line

19 storage capacitor (additional capacitor, additional capacitance)

50 display screen

51 write pixels (rows)

52 non-display pixels (non-display area, non-illumination area)

53 display pixels (display area, lighting area)

61 shift registers

62 Inverter

63 output buffers

71 array board (display)

72 laser irradiation range (laser spot)

73 positioning mark

74 glass substrate (array plate)

81 control IC (circuit)

82 power supply IC (circuit)

83 printing plates

84 flexible board

85 sealing cover

86 cathode wiring

87 anode wiring (Vdd)

88 data signal lines

89 gate control signal line

101 slope (rib)

102 interlayer insulation film

104 contact connector

105 pixel electrodes

106 cathode electrodes

107 desiccant

108λ/4 pieces

109 polarizers

111 thin packaging film

281 invalid pixels (rows)

341 output stage circuit

3710R ("or") circuit

401 lighting control line

471 reverse bias line

472 grid potential control line

561 electronic regulator circuit

SD (source-drain) short-circuit circuit of 562 transistor

571 antenna

572 key

573 shell

574 display

581 exit pupil

582 magnifying lens

583 convex lens

591 support points (central points)

592 imaging lens

593 storage part

594 switch

601 subject

602 Photography part

603 shutter switch

611 installation frame

612 bracket

613 frame

614 fixed parts

631 current source

632 current source

633 current source

641 switch (on/off device)

634 current source (single unit)

643 internal wiring

651 regulator (current regulator)

681 transistor group

691 resistor (current limiting device, a device that generates a predetermined current)

692 decoder circuit

693 level shifter circuit

701 counter (counting device)

702 or not

703 with

704 current output circuit

711 trimmer capacitor circuit

721D/A Inverter

722 Operational Amplifier

731 analog switch (on/off device)

732 Inverter

761 output base (output signal terminal)

771 reference current source

772 current control circuit

781 temperature detection circuit

782 temperature control circuit

931 series current connection line

932 reference current signal line

941i current input terminal

941o current output terminal

951 basic anode wire (anode voltage wire)

952 anode wiring

953 connection end

961 connection anode line

962 common anode wire

971 contact holes

991 basic cathode line

992 input signal line

1001 connecting resin (conductive resin, anisotropic conductive resin) 

1011 light absorbing film

1012 resin ball

1013 sealing resin

1021 circuit forming section

1051 grid voltage line

1091 power circuit (IC)

1092 power IC control signal

1093 gate driver circuit control signal

1111 unit gate output circuit

1241 regulating transistor

1251 cutting position

1252 public end

1341 invalid transistor

1351 transistor (single unit transistor)

1352 sub-transistor

1401 switch circuit (analog switch)

1491 flash memory (setting storage device)

1501 laser device

1502 laser

1503 Resistor Array (Adjusting Resistors)

1521 switch (on/off device)

1531 steady state transistor

1541 NAND circuit

1601 capacitor

1611 static switch (on/off control device, reference current on/off device)

1671 protection diode

1731 coincidence circuit (level detection circuit)

1741 output switch circuit

1742 two-way switch

1821 anode connection circuit

2011 coil (transformer)

2012 control circuit

2013 diode

2014 Capacitor

2021 switch

2022 temperature sensor

2041 level shifter circuit

2042 gate driver control signal

2061 bonding layer (connection layer, thermal conductivity layer, and bonding layer)

2062 chassis (metal chassis)

2063 convex part and concave part

2071 small hole

2211 control electrode

2212 video signal circuit

2213 electron emission height

2214 holding circuit

2215 open/disconnect control circuit

2221 select signal line

2222 open/disconnect signal line

2281 sealing resin

Detailed ways

Some parts of the drawings herein are omitted and/or enlarged/reduced for ease of understanding and/or description. For example, in the cross-sectional view of the display screen shown in FIG. 11, the thin packaging film 111 and the like are shown as being quite thick. On the other hand, in FIG. 10, the package cover 85 is shown as being thin. Some parts are omitted. For example, although the display screen according to the present invention requires a phase film like a circular polarizer to prevent reflection, such a phase film is omitted in the drawings herein. This also applies to the following figures. In addition, the same or similar forms, materials, functional elements, or operations are indicated by the same symbols or letters. the

Incidentally, the description made with reference to the drawings and the like can be combined with other examples and the like even if not specifically noted. For example, a touch screen or the like may be attached to the display screen in FIG. 8 to provide the information display device shown in FIGS. 19 and 59 to 61. Also, a magnifying lens 1582 may be installed to constitute a viewfinder (see FIG. 58) for a video camera or the like (see FIG. 159, etc.). Also, the driving methods described with reference to FIGS. 4, 15, 18, 21, 23, etc. can be applied to any display device or display screen according to the present invention. the

Also, the thin film transistors are mentioned herein as the driver transistor 11 and the switching transistor 11, which is not limitative. It can be replaced by thin film diode (TFD) or ring diode (ring diode). Also, the present invention is not limited to thin film elements, and transistors formed on silicon wafers can also be used. In this case, the substrate 71 may be made of a silicon wafer. Needless to say, FET (Field Effect Transistor), MOS-FET (Metal-Oxide-Semiconductor FET), MOS transistor, or bipolar transistor may also be used. Essentially, they are thin film transistors. It goes without saying that variable resistors, thyristors, ring diodes, photodiodes, phototransistors, or PLZT elements can also be used in the invention. That is to say, the transistor 11, the gate driver circuit 12, and the source driver circuit 14 according to the present invention may use any of the above elements. the

An EL panel according to the present invention will be described below with reference to the accompanying drawings. As shown in Figure 10, the organic EL display screen comprises glass substrate (array plate) 71, the transparent electrode 105 that forms as pixel electrode, at least one organic functional layer (EL layer) 15, and a metal electrode (reflection film) (Cathode) 106, which are stacked one layer on top of the other, where the organic functional layers include an electron transport layer, a light emission layer, a positive hole transport layer, and the like. When a positive voltage is applied to the anode, that is, the transparent electrode (pixel electrode) 105, and a negative voltage is applied to the cathode, that is, the metal electrode (reflective electrode) 106, that is, when a direct current is applied between the transparent electrode 105 and the metal electrode 106, When an electric current is supplied, the organic functional layer (EL layer) 15 emits light. the

Preferably, the metal electrode 106 is made of a metal with a small work function, such as lithium, silver, aluminum, magnesium, indium, copper, or alloys thereof. In particular, for example, an AL-Li alloy is preferably selected. The transparent electrode 105 can be made of a conductive material with a large work function, such as ITO, or gold. If gold is used as the electrode material, the electrodes become translucent. Incidentally, IZ0 or other materials may be used instead of IT0. This also applies to the other pixel electrodes 105 . the

Incidentally, a desiccant 107 is placed in the space between the sealing cover 85 and the array plate 71 . This is because the organic EL thin film 15 is susceptible to intrusion of moisture. The desiccant 107 absorbs moisture penetrating into the sealing layer, thereby preventing the deterioration of the organic EL film 15 . the

Although in FIG. 10, the sealing cap 85 is used for sealing, it can be sealed with a film 111 (this may be a film, ie, a thin packaging film), as shown in FIG. The encapsulation film (thin encapsulation film) 111 may be, for example, an electrolytic capacitor film on which DLC (diamond-like carbon) is vapor-deposited. This film exhibits extremely low moisture penetration (high moisture resistance) properties. It is used as a thin encapsulation film 111 . Also, it goes without saying that DLC (diamond-like carbon) may be directly vapor-deposited on the surface of the metal electrode 106 . In addition, a thin packaging film can be formed by laminating a thin resin film and a metal film. the

Ideally, the film thickness of the film should be such that n·d is equal to or smaller than the main emission wavelength λ of the EL element 15 (where n is the refractive index of the film, or if two or more films are laminated, It is the sum of the refractive index (calculate the n d of each film); d is the thickness of the i film, or if two or more films are stacked, d is the sum of the thickness of two or more films. By satisfying this condition , compared with when a glass substrate is used as a seal, it is possible to more than double the efficiency of light extracted from the EL element 15. In addition, alloys, mixtures or laminates of aluminum and silver can also be used.

The technique of sealing using the thin packaging film 111 instead of the sealing cap 85 described above is called thin film packaging. In the case of "underside extraction (see Fig. 10; light is extracted in the direction of the arrow in Fig. 10)", the light is extracted from the side of the plate 71, and thin-film encapsulation involves forming an EL film, and then forming a cathode that will be formed on the EL film. role of aluminum electrodes. Then, a resin layer as a buffer layer is formed on this aluminum layer. Organic materials that can be used for the buffer layer are polypropylene or epoxy. Suitable film thicknesses are from 1 [mu]m to 10 [mu]m (both dimensions inclusive), more preferably film thicknesses are from 2 [mu]m to 6 [mu]m (both dimensions inclusive). The encapsulation film 74 is formed on the buffer film. In the absence of a buffer film, the structure of the EL thin film would be deformed by stress, resulting in streaky defects. As described above, the thin encapsulation film 111 can be made of, for example, an electrolytic capacitor of DLC (diamond-like carbon) or a laminated structure (by alternately vapor-depositing thin dielectric films and aluminum films). the

In the case of "top side extraction" (see Figure 11; the light is extracted in the direction of the arrow in Figure 11)", the light is extracted from the side of the EL layer 15, and the thin film packaging includes forming the EL film 15, and then forming the EL film 15 on the EL film. Ag-Mg film with a thickness of 20 angstroms (including this size) to 300 angstroms to act as a cathode (anode). A transparent electrode such as ITO is formed on the film to reduce resistance. Then formed on the electrode film The resin layer is used as a buffer layer. A thin encapsulation film 111 is formed on this buffer layer.

Half of the light generated by the organic EL layer 15 is reflected by the metal electrode 106 and emitted through the array plate 71 . However, the metal electrodes 106 reflect external light, causing glare that reduces the contrast of the display screen. To cope with this, a λ/4 phase plate 108 and a polarizing plate (polarizing film) 109 are placed on the array plate 71 . Usually, these are called circular polarizing plates (circular polarizing plates). the

Incidentally, if the pixel is a reflective electrode, the light generated by the organic EL layer 15 is reflected upward. Therefore, it goes without saying that the phase plate 108 and the polarizing plate 109 are placed on the light emitting side. Reflective pixels can be obtained by making pixel electrodes out of aluminum, chrome, silver, or the like. Also, it is possible to increase an interface with the organic EL layer 15 by being provided with protrusions (or protrusions and depressions) on the surface of the pixel electrode 105, thereby increasing the area for emitting light, resulting in improved light emission. efficiency. Incidentally, the reflective film functioning as the cathode 106 (anode 105) is formed as a transparent electrode. If the reflection could be reduced to 30% or less, the circular polarizer would not be needed. This is because glare is greatly reduced. Light interference is also reduced. the

Preferably, an LDD (Low Doped Drain) structure is used for the transistor 11 . Taking an organic EL element (various known abbreviations include OEL, PEL, PLED, OLED) 15 as an example, the EL element will be described herein, but this is not limitative, and an inorganic EL element can also be used. the

An active matrix type organic EL display screen must satisfy two conditions: the ability to select a specific pixel and give necessary display information, and the ability to flow current through the EL element throughout a frame period. the

To satisfy these two conditions, in the conventional organic EL pixel structure shown in FIG. film) 15 to provide the current. the

To display a gradation using this structure, a voltage corresponding to the gradation must be applied to the gate of the driver transistor 11a. Therefore, changes in the on-current of the driver transistor 11a appear directly on the display screen. the

If the transistor is monocrystalline, the on-current of the transistor is extremely uniform. However, in the case of low-temperature multi-transistors formed on inexpensive glass substrates by low-temperature polysilicon technology at temperatures not exceeding 450°C, its threshold value varies in the range of ±0.2V to 0.5V. The turn-on current flowing through the driver transistor 11a changes accordingly, resulting in irregular display. This irregularity is caused not only by variations in threshold voltage but also by the mobility of the transistor and the thickness of the gate insulating film. The characteristics also vary due to degradation of the transistor 11 . the

This phenomenon is not limited to low-temperature polysilicon technology, but also occurs in transistors formed on semiconductor thin films grown in solid phase (CGS) by high-temperature polysilicon technology with a process temperature of 450 (Celsius) or higher. In addition, this phenomenon can occur in organic transistors and amorphous silicon transistors. the

As described below, the present invention provides a structure or scheme adaptable to the above techniques. The description given in this paper is mainly for transistors produced by low temperature polysilicon technology. the

In the method of displaying gradations by applying voltages as shown in FIG. 62, it is necessary to strictly control device characteristics in order to obtain uniform display. However, current low-temperature polysilicon polysilicon transistors and the like cannot satisfy a specification which requires variations to be kept within a predetermined range. the

Each pixel structure in the EL display panel according to the present invention includes at least four transistors 11 and -EL elements, as specifically shown in FIG. 1 . The pixel electrodes are configured to overlap the source signal lines. Specifically, the pixel electrode 105 is formed on a planarized polypropylene film which is an insulating film formed on the source signal line 18 for insulation. A structure in which the pixel electrode overlaps at least part of the source signal line 18 is called a high aperture (HA) structure. This reduces unwanted light interference and enables normal light emission. the

When the gate signal is output to the gate signal line (first scanning line) 17a and the gate signal line 17a is activated (on voltage is applied), the current to flow through the EL element 15 passes from the source driver circuit 14 through the EL element 15 The driver transistor 11a and switching transistor 11c are passed. And, due to the detriggering of the gate signal line 17a (applying an off voltage to it), the transistor 11b is turned on, causing a short circuit between the gate and the drain of the transistor 11a, and the gate voltage (or drain voltage) of the transistor 11a is stored in a capacitor (storage capacitance, additional capacitance) 19 connected between the gate and drain of the transistor 11a (see FIG. 3(a)). the

Preferably, capacitor (storage capacitance) 19 should be from 0.2pF to 2pF (both quantities included). More preferably, the capacitor (storage capacitance) should be from 0.4pF to 1.2pF (both quantities included). The capacitance of the capacitor 19 is determined taking the pixel size into consideration. If the capacity required for a single pixel is Cs (pF), and the area occupied by the pixel (rather than the aperture ratio) is Sp (μm ² ), then the condition 500/Sp≤Cs≤20000/S should be satisfied p, more preferably 1000/Sp≤Cs≤10000/Sp. Since the gate capacitance of the transistor is small, Q mentioned here is only the capacitance of the storage capacitance (capacitor) 19 .

The gate signal line 17a is deactivated (off voltage is applied), the gate signal line 17b is activated, and the current path is switched to include the first transistor 11a, the transistor 11d connected to the EL element 15, and the EL element 15 to convert the stored The current is passed to the path of the EL element 15 (see FIG. 3(b)). the

In this circuit, a single pixel contains four transistors 11 . The gate of transistor 11a is connected to the source of transistor 11b. The gates of the transistors 11b and 11c are connected to the gate signal line 17a. The drain of transistor 11b is connected to the source of transistor 11c and the source of transistor 11d. The drain of the transistor 11 c is connected to the source signal line 18 . The gate of the transistor 11 d is connected to the gate signal line 17 b , and the drain of the transistor 11 d is connected to the anode electrode of the EL element 15 . the

Incidentally, all transistors in Fig. 1 are P-channel transistors. Compared to N-channel transistors, P-channel transistors have more or less lower mobility and are preferred because they are more stable against voltage and degradation. However, the EL element according to the present invention is not limited to P-channel transistors, but the present invention can use only N-channel transistors. Also, the present invention can use both N-channel and P-channel transistors. the

Optimally, P-channel transistors should be used not only for the built-in gate driver 12 but also for all transistors 11 constituting a pixel. With an array made of only P-channel transistors, it is possible to reduce masks to five, resulting in low cost and high yield. the

To facilitate the understanding of the present invention, the structure of the EL element according to the present invention will be described below with reference to FIG. 3 . Two time scales are used to control the EL element according to the invention. The first time stamp is the moment when the required current value is stored. Turning on the transistor 11b and the transistor 11c with this timing forms an equivalent circuit shown in FIG. 3(a). A predetermined current Iw is applied from the signal line. This connects the gate and drain of transistor 11a, allowing current I to flow through transistor 11a and transistor 11c. Therefore, the gate-to-source voltage of transistor 11a enables I1 to flow. the

The second time scale is the time when the transistor 11b and the transistor 11c are turned off, and the transistor 11d is turned on. At this point, the equivalent circuit shown in Figure 3(b) can be obtained. The source-gate voltage of transistor 11a remains constant. In this case, since the transistor 11a always operates in the saturation region, the current Iw remains constant. the

The result of this operation is shown in Figure 5. Specifically, reference numeral 51a in FIG. 5(a) denotes a pixel (row) on the display screen 50 (image pixel row) programmed with a current at a certain point in time. The pixel row 51a is non-illuminated (non-display pixel (row)), as shown in FIG. 5(b). The other pixels (rows) are display pixels (rows) 53 (current flows through the EL elements 15 other than the pixels 53 in the display area 53, causing the EL elements 15 to emit light). the

In the pixel structure of FIG. 1, the programmed current Iw flows through the source signal line 18 during the current programming as shown in FIG. 3(a). The current Iw flows through the transistor 11a, and in the capacitor 19 a voltage is set (programmed) to maintain the current Iw. At this time, the transistor 11d is open (off). the

During the period when current flows through the EL element 15, the transistors 11c and 11b are turned off, and the transistor 11d is turned on as shown in FIG. 3(b). Specifically, a shutdown voltage (Vgh) is applied to the gate signal line 17a, turning off the transistors 11b and 11c. On the other hand, the turn-on voltage (Vg1) is applied to the gate signal line 17b to turn on the transistor 11d. the

The timing diagram is shown in Figure 4. The indices (for example, (1)) in parentheses in Fig. 4 indicate the number of rows of pixels. Specifically, the gate signal line 17a(1) represents the gate signal line 17a in the pixel row (1). Also, in the top row of FIG. 4, *H (where "*" is an arbitrary symbol or numeral and indicates the number of horizontal scanning lines) indicates a horizontal scanning period. Specifically, 1H is the first transverse scanning period. Incidentally, the items (1H number, 1-H period, order of pixel row numbers, etc.) described above are for convenience of explanation and not for limitation. the

As can be seen from FIG. 4, in each selected pixel row (assuming that the selection period is 1H), when the turn-on voltage is applied to the gate signal line 17a, the turn-off voltage is applied to the gate signal line 17b. During this period, no current flows through the EL element 15 (non-illumination). In a non-selected pixel row, an OFF voltage is applied to the gate signal line 17a and an ON voltage is applied to the gate signal line 17b, and during this period, current flows through the EL element 15 (illumination). the

Incidentally, the gate of the transistor 11b and the gate of the transistor 11c are connected to the same gate signal line 17a. However, the gate of the transistor 11b and the gate of the transistor 11c may be connected to different gate signal lines 17 (see FIG. 32 ). Thus, a pixel will have three gate signal lines (two in the configuration of Fig. 1). By independently controlling the on/off timing of the gate of the transistor 11b and the on-off timing of the gate of the transistor 11c, it is possible to further reduce variations in the current value of the EL element 15 due to variations in the transistor 11a. the

By sharing the gate signal line 17a and the gate signal line 17b, and using different conductivity types (N-channel and P-channel) for the transistors 11c and 11d, it is possible to simplify the driving circuit and improve the aperture ratio of the pixel. the

With this structure, the writing path from the signal line is turned off by the operation timing according to the present invention. That is, when a predetermined current is stored, if the current path is branched, an accurate current value is not stored in the capacitance (capacitor) between the source (S) and gate (G) of the transistor 11a. By using transistors 11c and 11d of different conductivity types, and controlling their thresholds, it is possible to ensure that transistor 11d is turned on when transistor 11c is turned off when the scan line is switched. the

In that case, however, care must be taken in processing since the threshold of the transistor must be accurately controlled. The above circuit can be implemented with at least four transistors, but for accurate timing control or to reduce reflection effects (described later), even if more than four transistors including transistor 11e are connected in series, the principle of operation is the same of. By adding the transistor 11e, it is possible to more accurately deliver the programming current to the EL element 15 through the transistor 11c. the

Incidentally, the pixel structures according to the present invention are not limited to those shown in Figs. 1 and 2 . For example, the pixels may be constructed as shown in FIG. 140 . Unlike the structure in FIG. 1 , diagram 140 lacks transistor 11d. Instead, a changeover switch 1401 is formed or provided. The switch 11d in FIG. 1 functions to turn on and off (pass and cut off) the current delivered to the EL element 15 from the driver transistor 11a. Also as described in the subsequent examples, the control function of turning on and off of the transistor 11d forms an important part of the present invention. In the structure in Fig. 140, the on/off function is obtained without using the transistor 11d. the

In FIG. 140, one terminal a of the changeover switch 1401 is connected to the anode voltage Vdd. Incidentally, the voltage applied to the terminal a is not limited to the anode voltage Vdd. It may be any voltage capable of shutting off the current flowing through the EL element 15 . the

Connect terminal b of changeover switch 1401 to the cathode voltage (indicated as ground in Figure 140). Incidentally, the voltage applied to the terminal b is not limited to the cathode voltage. It may be any voltage that turns on the current flowing through the EL element 15. the

The terminal C of the changeover switch 1401 is connected to the cathode terminal of the EL element 15 . Incidentally, the changeover switch 1401 may be of any type as long as it has the ability to turn on and off the flow through the EL element 15 . Therefore, its installation position is not limited to the position shown in Fig. 140, but the switch can be installed anywhere on the path where the current is delivered to the EL element 15. Also, the switch is not limited in its functionality as long as it can switch the current flowing through the EL element 15 on and off. In short, the present invention can have any pixel structure as long as switching means capable of turning on and off the current flowing through the EL element 15 is installed on the current path of the EL element 15. the

Also, the term "off" does not mean a state where no current flows, but means a state in which the current flowing through the EL element 15 is reduced to a current lower than that of the normal state. The terms mentioned above also apply to other configurations of the present invention. the

Since transfer switch 1401 can be easily implemented by a combination of P-channel and N-channel transistors, it needs no explanation. For example, it can be realized by a circuit of two analog switches. Of course, the changeover switch 1401 can be made of only P-channel or N-channel transistors because it only turns off the current flowing through the EL element 15 . the

The Vdd voltage is applied to the cathode terminal of the EL element 15 when the changeover switch 1401 is connected to the terminal a. Therefore, current does not flow through the EL element 15 irrespective of the voltage state of the voltage held by the gate terminal G of the driver transistor 11a. Therefore, this EL element 15 is non-illuminating. the

The voltage GND is applied to the cathode terminal of the EL element 15 when the changeover switch 1401 is connected to the terminal b. Accordingly, current flows through the EL element 15 according to the voltage state held by the gate terminal G of the driver transistor 11a. Therefore, the EL element 15 is illuminated. the

Therefore, in the pixel structure shown in FIG. 140, the switching transistor 11d is not formed between the driving transistor 11a and the EL element 15. However, it is possible to control the illumination of the EL element 15 by controlling the changeover switch 1401 . the

In the pixel structure shown in FIGS. 1, 2, etc., a pixel includes a driver transistor 11a. However, the present invention is not limited to this case, and a pixel may include two or more driver transistors 11a. An example is shown in FIG. 144, in which a pixel is shown comprising two driver transistors 11a1 and 11a2, the gate terminals of which are connected to a common capacitor 19. By using multiple driver transistors 11a, it is possible to reduce variations in the programming current. The other parts of the structure are the same as those shown in Fig. 1 and the like, and therefore, its description is omitted. the

In FIGS. 1 and 2 , the current output through the driver transistor 11 a flows through the EL element 15 and is turned on and off by the switching transistor 11 d formed between the driver transistor 11 a and the EL element 15 . However, the present invention is not limited to this case. For example, another structure diagram is shown in FIG. 145 . the

In the example shown in FIG. 145, the current delivered to the EL element 15 is controlled by the driver transistor 11a. The current flowing through the EL element 15 is turned on and off by the transistor 11 d provided between the Vdd terminal and the EL element 15 . Therefore, according to the present invention, the transistor 11d can be provided anywhere as long as it can control the current flowing through the EL element 15. the

The variation in the characteristics of the transistor 11a is related to the size of the transistor. In order to reduce variations in characteristics, it is preferable that the channel length of the first transistor 11a is from 5 μm to 100 μm both dimensions inclusive. More preferably, the height is from 10 [mu]m to 50 [mu]m (both dimensions included). This is likely because a long channel length L increases the grain boundaries contained in the channel, lowering the electric field intensity, thereby suppressing the kink effect. the

Therefore, according to the present invention, the circuit device for controlling the current flowing through the EL element 15 is constructed, formed, that is, arranged on the path along which the current flows into the EL element 15, and the current leaves the EL element along the path (that is, for the EL element 15). 15 current path). the

Incidentally, the structure for controlling the path along which the current flows into the EL element 15 is not limited to the pixel structure in the current-programming mode shown in FIG. 1, 140 or the like. For example, the pixel structure in the voltage programming mode shown in Fig. 141 can also be used. In FIG. 141, the arrangement of the transistor 11d between the EL element 15 and the driver transistor 11a makes it possible to control the current flowing through the EL element 15. Of course, the switch circuit 1401 can be arranged as shown in FIG. 140 . the

Moreover, even in the case where the current is mirrored, by forming or disposing a type of current programming of the transistor 11g as a switching element between the driver transistor 11b and the EL element 15, it is possible to turn on and off (control) the flow through EL element 15 current. Of course, the transistor 11g can be replaced by the changeover switch 1401 in FIG. 140 . the

Incidentally, although the switching transistors 11d and 11c in FIG. 142 are connected to a single gate signal line 17a, the switching transistor 11c can be controlled by the gate signal line 17a1 and the switching transistor 11d can be controlled by the gate signal line 17a2, As shown in Figure 143. The structure in Fig. 143 makes the control of the pixel 16 more versatile. the

As shown in FIG. 42(a), the transistors 11b and 11c may be N-channel transistors. Also, as shown in FIG. 42(b), the transistors 11c and 11d may be P-channel transistors. the

It is an object of the invention to propose a circuit structure in which variations in transistor characteristics do not affect the display. For this, four or more transistors are required. When using transistor characteristics to determine circuit constants, it is difficult to determine appropriate circuit constants if the characteristics of the four transistors are identical. Both the threshold of transistor characteristics and the mobility of the transistor vary depending on whether the channel direction is lateral or vertical with respect to the longitudinal axis of laser irradiation. Incidentally, in both cases the variation is greater in the above case. However, the mobility and average threshold vary between the transverse and longitudinal directions. Therefore, it is ideal that all transistors in a pixel have the same channel direction. the

And, if the capacitance value of the storage capacitor 19 is Cs (pF), the off-current value of the second transistor 11b is Ioff (pA). It is better to satisfy the following equation:

3<Cs/I _off <24

Even better is to satisfy the following equation:

6<Cs/I _off <18

By setting the off current of the transistor 11b to 5pA or less, it is possible to reduce the variation in the current flowing through the EL to 2% or less. This is because the charge stored between the gate and source (across the capacitor) cannot maintain a force field without an applied voltage as the leakage current increases. Therefore, the larger the storage capacity of the capacitor 19, the larger the allowable off current amount. By satisfying the above equation, it is possible to reduce the fluctuation in current value between adjacent pixels to 2% or less. the

And, it is preferable that the transistors forming the active matrix are P-channel polysilicon thin film transistors, and the transistor 11b is a double-gate or multi-gate transistor, and the transistor 11b needs an on/off ratio as high as possible. It acts as a source-drain switch. By adopting a double-gate or multi-gate structure for the transistor 11b, it is possible to obtain a high on/off ratio. the

The semiconductor thin film constituting the transistor 11 in the pixel 16 is generally formed by laser annealing in low temperature polysilicon technology. Variations in laser annealing conditions result in variations in transistor 11 characteristics. However, if the characteristics of the transistor 11 are uniform in the pixel 16, it is possible to drive the pixel by current programming as shown in FIG. 1 so that a predetermined current will flow through the EL element 15. This is an advantage that voltage programming lacks. Preferably, the laser used is an excimer laser. the

Incidentally, the formation of the semiconductor thin film according to the present invention is not limited to the laser annealing method. The invention can also employ thermal annealing and a method involving solid state growth (CGS). In addition, the present invention is not limited to low-temperature polysilicon technology, and high-temperature polysilicon technology can also be used. the

To deal with this problem, the present invention moves the laser spot (laser irradiation range) 72 in a direction parallel to the source signal line 18, as shown in FIG. 7 . Also, the laser spot 72 is moved in such a way as to be aligned with a row of pixels. Of course, the number of rows of pixels is not limited to one row. For example, laser light can be emitted as a single pixel 16 by regarding RGB (red-green-blue) (in this example, three columns of pixels) as in FIG. 72 . Also, laser light can be directed to two or more pixels at the same time. It goes without saying that the moving laser irradiation ranges may overlap (it is common for the moving laser irradiation ranges to overlap).

Pixels constructed in such a way that three RGB pixels form a square shape. Therefore, each of R, G, B pixels has a rectangular shape. Thus, by annealing the rectangular laser spot 72, it is possible to eliminate variations in the characteristics of the transistor 11 within each pixel. Also, the characteristics (mobility, Vt, S value, etc.) of the transistors 11 connected to the same source signal line 18 can be made uniform (that is, although the transistors 11 connected to adjacent source signal lines 18 can be made uniform in characteristics different, but the characteristics of the transistors 11 connected to the same source signal line can be made almost equal). the

In the configuration shown in FIG. 7, three screens are placed lengthwise within the length of the laser spot 72. As shown in FIG. The annealing device emitting the laser spot 72 recognizes the positioning marks 73a and 73b on the glass substrate 74 (automatic positioning based on pattern recognition) and moves the laser spot 72 . The positioning marks 73 are recognized by pattern recognition means. An annealing device (not shown) recognizes the positioning mark 73 and determines the position of the pixel column (making the laser irradiation area 72 parallel to the source signal line 18). It emits laser spot 72 in such a way that it overlaps with the position of each pixel column for continuous annealing. the

Preferably, the laser annealing method described with reference to FIG. 7 (which includes emitting a linear laser spot parallel to the source signal line 18) is especially used for current programming of organic EL displays. This is because the transistors 11 placed in the direction parallel to the source signal line have the same characteristics (the characteristics of the pixel transistors in the vicinity of the vertical direction are quite similar to each other). This reduces the variation in the voltage level of the source signal line when the pixel is driven by current, thus reducing the chance of insufficient write current. the

For example, in a display with a white screen, since almost the same current flows through the transistor 11a in adjacent pixels, the current output from the source driver IC 14 does not vary significantly in magnitude. If the transistors 11a in FIG. 1 have the same characteristics, and the currents for current programming of the pixels in the pixel column have the same value, the potential of the source signal line 18 is constant during the current programming. Therefore, potential fluctuation does not occur on the source signal line 18 . If the transistors 11a connected to the same source signal line 18 have almost the same characteristics, there should be no significant potential fluctuation on the source signal line 18. This is also true for other current-programmable pixel structures, such as the one shown in Figure 38 (thus, the choice of fabrication shown in Figure 7 is preferred). the

A method that involves simultaneous programming of two or more pixel rows, and which is described with reference to FIGS. regular image). In the case of FIG. 27 and the like, since a plurality of pixel rows are simultaneously selected, if the transistors in adjacent pixel rows are identical, irregularities in the characteristics of transistors arranged in the length direction can be caused by Absorbed by the pole driver circuit 14. the

Incidentally, although it is illustrated in FIG. 7 that the IC chip is stacked on the source driver circuit 14, this is not restrictive. And obviously, the source driver circuit 14 can be formed by the same process as the pixel 16. the

In particular, the invention ensures that the voltage threshold Vth2 of the driver transistor 11b does not drop below the voltage threshold Vth1 of the corresponding driver transistor 11a in the pixel. For example, the gate length L2 of the transistor 11b is made longer than the gate length L1 of the transistor 11a, so that even when the process parameters of these thin film transistors vary, Vth2 will not drop below Vth1. This makes it possible to suppress minute current leakage. the

Incidentally, some of the items mentioned above also apply to the pixel structure of the current reflection shown in FIG. 38 . The pixel in FIG. 38 is composed of the following elements, a driver transistor 11a through which a signal current flows, a driver transistor 11b which controls a driving current flowing through a light-emitting element such as an EL element 15, and a control gate signal line 17a1, connected to Or disconnect the transistor 11c of the pixel circuit and the data line "data", and the switching transistor 11d of the gate and drain of the transistor 11a is shorted by controlling the gate signal line 17a2 during writing, and after the voltage is applied, the transistor 11a is maintained Capacitance C19 for gate-source voltage, EL element 15 serving as a light emitting element, and the like. the

In FIG. 38, transistors 11c and 11d are N-channel transistors, and the other transistors are P-channel transistors, but this is only exemplary and not restrictive. One end of the capacitor Cs is connected to the gate of the transistor 11a, and the other end is connected to Vdd (power supply potential), but it may be connected to any fixed potential instead of Vdd. The cathode (negative electrode) of the EL element 15 is connected to ground potential. the

Next, the EL display panel of the present invention, ie, the EL display device, will be described. Fig. 6 is an explanatory diagram mainly explaining the circuit of the EL display device. The pixels 16 are arranged, ie formed in a matrix. Each pixel 16 is connected to a source driver circuit 14 which outputs a current for current programming of the pixel. In the output stage of the source driver circuit 14 is a current mirror circuit (described later) corresponding to the bit count of the video signal. For example, if 64 levels are used, 63 current mirror circuits are formed on the relevant source signal lines, so that when an appropriate number of current mirror circuits is selected, the required current is applied to the source signal line 18 (see Fig. 64). the

Incidentally, the minimum output current of a current mirror circuit is from 10nA to 50nA (both quantities included). Preferably, the minimum output current of the current mirror circuit should be from 15nA to 35nA (both inclusive) to fix the accuracy of the transistors making up the current mirror circuit in the source driver IC. the

In addition, a precharge or discharge circuit is included to forcibly charge or discharge the source signal line 18 . Preferably, the voltage (current) output value of the precharge or discharge circuit forcibly charging or discharging the source signal line 18 can be set for R, G, and B individually. This is because the threshold value of the EL element 15 is differentiated among R, G and B (for the precharge circuit, refer to FIGS. 70 and 173 and its explanation). the

It is known that the organic element EL has a strong temperature dependence (temperature characteristic). In order to adjust the change in emission brightness caused by temperature characteristics, the output current is changed by adding a non-linear element such as a thermistor, that is, a positive temperature coefficient thermistor, to the current reflection circuit to adjust (change) the reference current in an analog manner. And use a thermistor or similar element to adjust for changes due to temperature characteristics. the

According to the present invention, the source driver 14 is made of a semiconductor silicon chip, and is connected to one end of the source signal line 18 on the substrate 71 through chip-on-glass (COG) technology. The source driver 14 is not only mounted by COG technology. It is also possible to mount the source driver circuit 14 and connect it to the signal lines of the display screen by chip-on-film (COF) technology. As for the driver IC, it can be made of three chips by building the power supply IC82 separately. the

The panel is tested before the source driver IC 14 is mounted. The test is performed by applying a constant current to the source signal line 18. The constant current is applied by attaching lead wires 2271 to pads 1522 formed at the terminals of source signal lines 18 and forming test pads 2272 at their terminals, as illustrated in FIG. 227 . the

By forming the solder joints 2272, it is possible to perform testing without using the solder joints 1522. the

After the source driver IC 14 is mounted on the substrate 71, its periphery is sealed with a sealing resin 2281 as illustrated in FIG. 228 . the

On the other hand, the gate driving circuit 12 is formed by low temperature polysilicon technology. That is, it is formed in the same process as the transistors in the pixels. This is because the gate driver 12 has a simpler internal structure and lower operating frequency than the source driver circuit 14 . Therefore, it can be easily formed even by low-temperature polysilicon technology, and the panel width can be reduced. Of course, it is possible to construct the gate driver circuit 12 with silicon chips and mount it on the substrate 71 using COG technology. Also, not only switching elements such as gate drivers but also switching elements such as pixel transistors may be formed by high temperature polysilicon technology or may be formed of organic materials (organic transistors). the

The gate driver 12 includes a shift register circuit 61a for the gate signal line 17a and a shift register circuit 61b for the gate signal line 17b. These shift register circuits 61 are controlled by positive phase and negative phase clock pulse signals (CLK×P and CLK×N) and a start pulse (STx) (see FIG. 6 ). In addition, it is preferable to add an enable (ENABL) signal that controls output and non-output from the gate signal line and an up and down (UPDWN) signal that switches the shift direction up and down. Also, it is preferable to install an output terminal to ensure that the start pulse is shifted and output by the shift register. Incidentally, the shift timing of the shift register is controlled by a control signal from the control IC 81 (see FIGS. 8 and 208). Furthermore, the gate driver circuit 12 includes a level shift circuit for shifting the level of external data. the

Since the shift register circuits 61 have small buffer capacitances, they cannot directly drive the gate signal line 17. Therefore, at least two or more inverter circuits 62 are formed between each shift register circuit 61 and the output gate 63 of the drive gate signal line 17 (see FIG. 204 ). the

The same applies to the cases where the source driver 14 is formed on the substrate 71 by polysilicon technology such as low temperature polysilicon technology. A plurality of inverter circuits are formed between analog switch gates such as transfer gates, which drive the source signal lines 18 , and the shift registers of the source driver circuit 14 . The following items (shift register output and output stage for driving signal lines (inverter circuit provided between output stages such as output gates or transfer gates)) are for the gate driver circuit and the source driver circuit shared. the

For example, although the output from the source driver 14 is directly connected to the source signal line 18, as shown in FIG. The inverter output is connected to an analog switch gate such as a transfer gate. the

The inverter circuit 62 is composed of P-channel MOS transistors and N-channel MOS transistors. As described earlier, the output of the shift register circuit 61 of the gate driver circuit 12 is connected to multiple stages of the inverter circuit 62 , and the final output is connected to the output gate 63 . Incidentally, the inverter circuit 62 may be composed of P-channel MOS transistors alone. In that case, however, the circuit can be constructed as nothing more than a gate circuit rather than an inverter. the

FIG. 8 is a block diagram of signals and voltages supplied to a display device according to the present invention, that is, a block diagram of a display device. Signals (power supply wiring, data wiring, etc.) are supplied from the control IC 81 to the source driver circuit 14 a through the flexible substrate 84 . the

In FIG. 8 , the control signal for the gate driver 12 is generated by the control IC, level-shifted by the source driver 14 , and supplied to the gate driver 12 . Since the driving voltage of the source driver 14 is 4 to 8 (V), the control signal output from the control IC 81 with an amplitude of 3.3 (V) can be converted into a control signal with an amplitude of 5 (V) that can be received by the gate driver 12 . V) signal. the

In FIG. 8 and its ilk, the device marked by reference numeral 14 has been described as a source driver, but instead of being just a driver, it may contain power supply circuits, buffer circuits (including circuits such as shift registers), data conversion circuit, register circuit, instruction decoder, shift circuit, address conversion circuit, image storage, etc. Obviously, the three-sided unconstrained structure or other structures, drive systems, etc. described with reference to FIG. 9 and the like are also applicable to the structures described with reference to FIG. 8 and the like. the

When the display screen is used for an information display device such as a mobile phone, it is preferable to install (form) a source driver IC (circuit) 14 and a gate driver IC (circuit) 12 on one side of the display screen, as shown in FIG. (By the way, this structure in which driver ICs (circuits) are mounted on one side of the display is called a three-sided unconstrained structure (arrangement). Conventionally, the gate driver IC 12 is mounted on one side of the display area X side, and the source driver IC14 is mounted on the Y side). Such a design can easily center the center line of the display screen 50 on the display device and mount the driver ICs. With this three-sided unconstrained structure, the gate driver circuit can be made by high temperature polysilicon technology, low temperature polysilicon technology or similar technology (i.e., at least one of the source driver circuit 14 and the gate driver circuit 12 can be made by polysilicon technology. formed directly on the substrate 71). the

Incidentally, this three-sided unconstrained structure includes not only a structure in which ICs are directly arranged, that is, formed on the gate portion of the substrate 71, but also a structure in which the source driver IC (circuit) 14 and the gate driver IC (circuit) 14 are mounted. ) 12 thin film (TCP, TAB or other technology) is pasted on one side (or almost one side) of the substrate 71. That is, the three-sided unconstrained structure includes structures and arrangements without ICs on two sides and similar configurations. the

If the gate driver circuit 12 is arranged beside the source driver circuit 14, as shown in FIG. 9, the gate signal line 17 must be formed along the C side. the

Incidentally, bold solid lines and the like in FIG. 9 indicate gate signal lines 17 formed in parallel. Therefore, as many gate signal lines 17 as scanning signal lines are formed in parallel in part b (bottom of the screen), and a single gate signal line 17 is formed in part a (top of the screen). the

The gap between the gate signal lines 17 formed on the C side is from 5 μm to 12 μm inclusive. If it is smaller than 5 µm, the parasitic capacitance will cause noise on the adjacent gate signal line. It has been experimentally proven that parasitic capacitance has a significant effect when the gap is 7 μm or less. Also, when the gap is smaller than 5 µm, bouncing noise and other image noise appear concentratedly on the display screen. In particular, the generation of noise is different between the right and left sides of the screen, and it is difficult to reduce jumping noise and other image noise. When the gap exceeds 12 μm, the screen width D of the display becomes too large to be practical. the

In order to reduce image noise, a grounding pattern (a conductive pattern that has been fixed at a constant voltage or generally set at a stable potential) can be arranged below or above the gate signal line 17 . Alternatively, a separate shielding plate (shielding metal foil: a conductive pattern that has been fixed on a constant voltage or generally set on a stable potential) can be set on the gate signal line 17

The gate signal line 17 on the C side in FIG. 9 may be formed of an ITO electrode. However, in order to reduce resistance, they are preferably formed by laminating ITO and thin metal films. It is also preferable to form them with metal thin films. When using ITO lamination, a titanium film is formed on the ITO, and a thin aluminum film or an aluminum-molybdenum alloy film is formed on it. Alternatively, chromium is formed on ITO. For metallic films, thin aluminum or chrome films are used. This also applies to other examples of the invention. the

Incidentally, although the arrangement of the gate signal lines 17 on one side of the display area has been described with reference to FIG. 9 and the like, this is not restrictive and they may be arranged on both sides. For example, the gate signal line 17a may be provided (formed) on the right side of the display screen 50, and the gate signal line 17b may be provided (formed) on the left side thereof. This also applies to other examples. the

Also, the source driver IC 14 and the gate driver IC 12 may be integrated on a single chip. Therefore, only one IC chip needs to be mounted on the display screen. This also reduces production costs. Also, this makes it possible to simultaneously generate various voltages for a single-chip driver IC. the

Incidentally, although it has been described that the source driver IC 14 and the gate driver IC 12 are made of silicon or other semiconductor chips and mounted on the display panel, this is not restrictive. Obviously, they can be formed directly on the display screen 82 using low temperature polysilicon technology or high temperature polysilicon technology. the

Although it has been described that the pixels are the three primary colors of R, G and B, this is not restrictive. They may be three colors of cyan, yellow, and magenta. They are available in two colors B and yellow. Of course, they can be monochromatic. Alternatively, they can be six colors of R, G, B, cyan, yellow and magenta. These are natural colors that provide an expanded range of color reproduction and can provide a good display. Therefore, the EL display device according to the present invention is not limited to those that provide color display using the three primary colors of R, G, and B. the

Mainly, three methods are applicable for colorizing an organic EL display. One of them is the color conversion method. It only needs to form a blue single layer as the light emitting layer. The remaining greens and reds required for full-color display can be produced from blue by color conversion. Therefore, this method has the advantage that it is no longer necessary to color R, G, and B colors separately, and to prepare organic EL materials for R, G, and B colors. Unlike the polychromatic coloring method, the color conversion method does not reduce productivity. Any of the three methods can be applied to the EL display panel of the present invention. the

Also, white light emitting pixels may be formed in addition to the three primary colors. A white light-emitting pixel can be built (formed or constructed) by stacking R, G, and B light-emitting structures. A set of pixels is composed of pixels for the three primary colors RGB and a white light emitting pixel 16W. Forming a white light-emitting pixel makes it easy to express the highest luminance of white, thus making it possible to realize bright image display. the

Even when a set of pixels for the three primary colors RGB is used, it is preferable to change the pixel electrode area for different colors. Of course, if the luminous efficiencies of different colors and the color purity can be well balanced, equal areas can be used. However, if one or more colors are poorly balanced, it may be preferable to adjust the pixel electrode (light emitting area). The electrode area for each color can be determined based on current density. That is, when the white balance is adjusted within the color temperature range of 7000K (Kelvin) to 12000K both inclusive, the difference between the current densities of different colors should be within ±30%. More preferably, this difference should be within ±15%. For example, if the current density is around 100A/M ² , all three primaries should have a current density of 70A/M ² to 130A/M ² (both inclusive). More preferably, all three primary colors should have a current density of 85 A/M ² to 115 A/M ² (both current densities included).

The EL element 15 is a self-luminous element. When light from this self-luminous element enters a transistor serving as a switching element, a photoconductive phenomenon occurs. The photoconductive phenomenon is a phenomenon in which leakage (off leakage) increases due to photoexcitation when a switching element such as a transistor is turned off. the

To deal with this problem, the present invention forms a light-shielding film under the gate driver 12 (in some cases, the source driver 14) and under the pixel transistor 11. The light-shielding film is made of a metal thin film such as chromium, and has a thickness of from 50 nm to 150 nm (both dimensions included). A thin film will provide poor light-shielding effect, while a thick film will cause irregularities, making it difficult to pattern the transistor 11A1 in the upper layer. the

In the case of the driver circuit 12 and its ilk, it is necessary to reduce penetration of light not only from the top side but also from the bottom side. This is because the photoconductive phenomenon will cause malfunction. If the cathode electrode is made of a metal thin film, the present invention also forms the cathode electrode on the surface of the driver 12 and the like, and utilizes it as a light-shielding film. the

However, if the cathode electrode is formed on the driver 12, the electric field from the cathode electrode may cause the driver to malfunction, or place the cathode electrode and the driver circuit in electrical contact. To deal with this problem, the present invention forms at least one organic EL film, preferably two or more layers, on the driver circuit 12 simultaneously with the formation of the organic EL film on the pixel electrodes. the

If a short circuit occurs between the terminals of one or more transistors 11, or between a transistor 11 and a signal line in a pixel, the EL element 15 may become a bright spot that constantly keeps emitting light. This bright spot is visually apparent and must be turned into a black spot (broken). Pixels 16 corresponding to bright spots are detected and capacitor 19 is irradiated with laser light to cause a short across the capacitor. As a result, the capacitor 19 can no longer hold charge, and therefore, the transistor 11a can be stopped from passing current. It is desirable to remove that portion of the cathode film to be irradiated with laser light in order to prevent a short circuit between the terminal electrode of capacitor 19 and the cathode film caused by laser light irradiation. the

A crack in transistor 11 of pixel 16 will affect source driver IC 14 and its ilk. For example, if a source-drain (SD) short circuit 562 occurs in the driver transistor 11a in FIG. 56, the Vdd voltage of the panel is applied to the source driver IC14. Therefore, it is preferable to keep the power supply voltage of the source driver IC 14 equal to or higher than the power supply voltage Vdd of the panel. Preferably, the reference voltage used by the source driver IC 14 can be adjusted with an electronic regulator 561 (see FIG. 148). the

If the SD short circuit 562 occurs in the transistor 11a, an excessive current flows through the EL element 15. In other words, the EL element 15 keeps emitting light constantly (becomes a bright spot). This bright spot is obvious as a defect. For example, if a source-drain (SD) short circuit occurs in transistor 11a in FIG. 56, current flows constantly from the Vdd voltage to EL element 15 (when transistor 11d is turned on) and is connected to the gate (G) terminal of transistor 11a. The magnitude of the voltage is irrelevant. Therefore, a bright spot is formed as a result. the

On the other hand, if the SD short occurs in the transistor 11 a, and if the transistor 11 c is turned on, the Vdd voltage is applied to the source signal line 18 and to the source driver 14 . If the power supply voltage of the source driver 14 is not greater than Vdd, it may exceed the voltage resistance and cause the source driver 14 to be damaged. Therefore, a power supply voltage of the source driver 14 equal to or higher than the Vdd voltage (the higher voltage of the panel) is preferable. the

An SD short of transistor 11a may exceed a point defect and cause breakage of the source driver circuit of the panel. Also, the bright spot is obvious, which causes the screen to be defective. Therefore, it is necessary to convert bright spots into dark spots by cutting the wiring connecting between the transistor 11 and the EL element 15 . Preferably, optical means such as a laser are used to sever the wire. the

A driving method of the present invention will be described below. As shown in Figure 1, when the row is still selected, gate signal line 17a conducts (since transistor 11 in Figure 1 is a P-ditch transistor, so when it is in a low state, gate signal line 17a conducts ), and when the row is left unselected, the gate signal line 17b is turned on. the

In the source signal line 18, a parasitic capacitance exists. This parasitic capacitance is caused by the capacitance at the junction of the source signal line 18 and the gate signal line 17, the channel capacitance of the transistors 11b and 11c, and the like. the

The time t required to change the current value of the source signal line 18 is given by t=C·V/I, where C is the stray capacitance, V is the voltage of the source signal line, and I is the voltage flowing through the source signal line 18. Pole signal line current. Therefore, if the current value can be increased by 10 times, the time required to change the current value can be reduced by almost 10 times. This also means that even if the parasitic capacitance of the source signal line 18 is increased by 10 times, the current can be changed to a predetermined value. Therefore, it is useful to apply a predetermined current value to increase the current value during the short horizontal scanning period. the

When the input current is increased by 10 times, the output current is also increased by 10 times, resulting in a 10 times increase in the brightness of the EL. Therefore, to obtain a predetermined luminance, by reducing the conduction time of the transistor 17d in FIG. 1 by 10 times compared with the conventional conduction time, the light emission time is reduced by 10 times. Incidentally, the 10-fold increase/decrease cited as an example is for ease of understanding and is not meant to be restrictive. the

Therefore, in order to fully charge and discharge the parasitic capacitance of the source signal line 18, and programmatically send a predetermined current value to the transistor 11a of the pixel 16, it is necessary to output a relatively large current from the source driver 14. . However, when such a large current flows through the source signal line 18, its current value is programmed into the pixel, and a current larger than the predetermined current flows through the EL element 15. For example, if a 10 times larger current is programmed, it goes without saying that a 10 times larger current flows through the EL element 15, and the EL element 15 emits 10 times brighter light. To obtain a predetermined emission luminance, the time during which the current flows through the EL element 15 can be reduced by a factor of 10. In this way, the parasitic capacitance can be sufficiently charged/discharged from the source signal line 18, and a predetermined emission luminance can be obtained. the

Incidentally, although it has been described, a 10 times larger current is written into the pixel transistor 11a (more precisely, the terminal voltage of the capacitor 19 is set), and the conduction time of the EL element 15 is reduced to 1 /10, but this is only exemplary. In some cases, a 10 times larger current value can be written into the pixel transistor 11a, and the conduction time of the EL element 15 can be reduced to 1/5. On the other hand, a 10 times larger current value can be written to the pixel transistor 11a, and the conduction time of the EL element 15 can be halved. the

The present invention is characterized in that the current written into the pixel is set at a value different from a predetermined value, and the current flows through the EL element 15 intermittently. For ease of explanation, it has been described herein that an N-times larger current is written into the pixel transistor 11, and the conduction time of the EL element 15 is reduced to 1/N. However, this is not restrictive. Obviously, N1 times larger current is written into the pixel transistor 11, and the conduction time of the EL element 15 can be reduced to 1/N2 (N1 and N2 are different from each other). the

In white screen display, the average luminance over one field (frame) period of the display screen 50 is BO. This driving method is current (voltage) programmed in such a way that the brightness B1 of each pixel 16 is higher than the average brightness B0, and the non-display area 53 appears during at least one field (frame) period. Therefore, in the driving method according to the present invention, the average luminance over one field (frame) period is lower than B1. the

Incidentally, the non-display area 52 and the display area 53 are not necessarily equally spaced. For example, they may appear randomly (as long as the display time or non-display time forms a predetermined value (constant ratio) viewed as a whole). Also, the display time can be changed between R, G and B. the

That is, the display period or non-display period of R, G and B can be adjusted (set) in such a way that an optimum white balance can be obtained. the

For convenience of explaining the driving method according to the present invention, it is assumed that "1/N" means reducing 1F (one field or one frame) to 1/N. However, it goes without saying that it takes time (usually, one horizontal scanning period (1H)) to select a pixel row and to program a current value and errors may occur depending on scanning conditions). the

For example, by programming the pixel 16, the EL element 15 can be illuminated for 1/5 of a period at a larger current of N=10 times. The EL element 15 emits 10/5=2 times brighter light. It is also possible to program an N=2 times larger current into the pixel 16 and illuminate the EL element 15 for 1/4 period. The EL element 15 emits 2/4 = 0.5 times brighter light. In summary, the present invention controls to obtain a display different from a constant display (1/1, ie non-intermittent display) by using a current different from N=1 times the current for the current flow. Also, the drive system turns off the current supplied to the EL element 15 at least once during one frame (or one field) period. Also, the drive system achieves at least intermittent display by programming the pixels 16 with a current greater than a predetermined value. the

One problem with organic (inorganic) EL displays is that they use a display method that is substantially different from that of CRT (cathode ray tube) or other displays that use an electron gun to present an image with a set of display lines. That is, the EL display maintains the current (voltage) written into the pixels for a period of 1F (one field or one frame). So one problem is that it shows moving picture will result in blurred edges. the

According to the present invention, the current flows through the EL element 15 only for a period of 1F/N, but the current does not pass during the rest of the time (1F(N-1)/N). Let's consider a situation where the system is implemented and a point on the screen is observed. Under this display condition, image data display and black display (unirradiated) are repeated every 1F. That is, image data is intermittently displayed in a momentary sense. When moving picture data is intermittently displayed, good display conditions are obtained without edge blurring. In short, the video display can be obtained close to the CRT video display. the

The driving method according to the present invention realizes the display of gaps. However, this intermittent display can be obtained by simply turning transistor 11d on and off during the 1-H period. Therefore, the main clock pulse of the circuit is not different from the conventional circuit, and therefore, the power consumption on the circuit is not increased. A liquid crystal display requires an image memory in order to obtain intermittent display. According to the present invention, image numbers are held in each pixel 16 . Therefore, the present invention does not require an image memory for intermittent display. the

The present invention controls the current flowing through the EL element 15 simply by turning on and off the switching transistor 11d, the transistor 11e, and the like. That is, even if the current Iw flowing through the EL element 15 is cut off, the image data is held because it is in the capacitor 19. Therefore, when the transistor is turned on next time, the current flowing through the EL element 15 has the same value as the current flowing through the EL element 15 last time. Even if black interpolation (such as intermittent display of black display) is to be obtained, the present invention does not require a master clock pulse of the speed-up circuit. Also, it does not need to extend the time axis, therefore, no image memory is required. In addition, the EL element 15 responds quickly, and only a short time is required from application of current to light emission. Therefore, the present invention is suitable for movie display, and can solve the problems associated with conventional data-retaining displays (LCD, EL, etc.) in displaying moving pictures by employing intermittent display. the

Also, in a large display device, if an increased wiring length of the source signal line 18 results in increased parasitic capacitance in the source signal line 18, this can be solved by increasing the N value. When the value of the programming current applied to the source signal line 18 is increased by N times, the conduction period of the gate signal line 17b (transistor 11d) can be set to 1F/N. This makes it possible to apply the present invention to televisions, monitors, and other large display devices. the

The output stage of the source driver circuit 14 is constituted by a constant current circuit 704 (see FIG. 70). Unlike the source driver circuit of an LCD panel, this constant current circuit eliminates the need to change the buffer size of the output stage according to the size of the panel. the

Referring to the accompanying drawings, the driving method according to the present invention will be described in more detail below. The parasitic capacitance of the source signal line 18 is generated by the coupling capacitance with the adjacent source signal line 18, the buffer output capacitance of the source driver IC (circuit) 14, the cross capacitance between the source signal line 18 and the gate signal line 17, and the like. This parasitic capacitance is usually 10pF or greater. In the case of voltage driving, since the voltage is applied from the source driver IC 14 to the source signal line 18 with low impedance, more or less large parasitic capacitances do not interfere with the driving. the

However, in the case of current driving, especially for image display at the black level, the pixel capacitor 19 needs to be programmed with a weak current of 20 nA or less. Therefore, if a parasitic capacitance greater than a predetermined value is generated, this parasitic capacitance cannot be charged and discharged during the time when a pixel row is programmed (usually within 1H, but not limited to 1H, because two rows of pixels may are programmed simultaneously). If this parasitic capacitance cannot be charged and discharged within a period of 1H, sufficient current cannot be written in the pixel, resulting in poor resolution. the

In the pixel structure of FIG. 1, during the current programming period, the program control circuit Iw flows through the source signal line 18, as shown in FIG. 3(a). The current Iw flows through the transistor 11a, and the voltage is set (programmed) in the capacitor 19 in such a way that it maintains the current Iw. At this time, the transistor 11d is open (off). the

During the period when current flows through the EL element 15, the transistors 11c and 11b are turned off, and the transistor 11d is turned on, as shown in FIG. 3(b). Specifically, an off voltage (Vgh) is applied to the gate signal line 17a, turning off the transistors 11b and 11c. On the other hand, an ON voltage (Vg1) is applied to the gate signal line 17b to turn on the transistor 11d. the

Assuming that the current I1 is N times (a predetermined value) the current that should normally flow, the current flowing through the EL element 15 in FIG. 3(b) is also Iw. Therefore, the light emitted from the EL element 15 is N times brighter than the light emitted by the predetermined value. In other words, as shown in FIG. 12, the larger the magnification ratio N is, the higher the display luminance B of the pixel 16 is. Therefore, the magnification N and the brightness of the pixel 16 are proportional to each other. the

If transistor 11d is kept on for 1/N period during which it is normally kept on (about 1F) and kept off during the remaining (N-1)/N period, the average brightness over 1F is equal to the predetermined brightness. This display condition is closely similar to that of a CRT scanning a screen with an electron gun. The difference is 1/N illumination of the entire screen (the entire screen is taken as 1 here) (in a CRT, what is illuminated is - a pixel row - more precisely, a pixel). the

According to the present invention, 1F/N of the image display area 53 is shifted from the top to the bottom of the screen 50, as shown in FIG. 13(b). According to the present invention, the current flowing through the EL element 15 is only 1F/N of the period, but during the remaining period (1F(N-1)/N), the current does not flow. Therefore, pixels are displayed intermittently. However, due to the residual image, the entire screen appears to be displayed uniformly to the human eye. the

Incidentally, as shown in FIG. 13, the writing pixel row 51a is unilluminated 52a. However, this is only true for the pixel structures of Figures 1, 2, etc. In the current mirrored pixel structure shown in FIG. 38 etc., the writing pixel row 51a may be illuminated. However, for ease of explanation, the pixel structure in FIG. 1 will be mainly cited for description herein. A driving method involving driving a pixel with a gap programmed therein with a predetermined driving current Iw greater than that shown in FIGS. 13, 16, etc. is called N-fold pulse driving. the

In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed at regular intervals (intermittently) in a temporal sense. A liquid crystal display (different from the EL display of the present invention) that holds data in pixels for 1F time cannot keep up with changes in image data during movie display, resulting in blurred pictures (edges of images are blurred). Since the present invention displays images intermittently, it can obtain good display conditions of images without blurred edges. Overall, the video display is close to that achievable with a CRT. the

Incidentally, in order to drive the pixel 16 shown in FIG. 13, it is necessary to be able to individually control the current programming period of the pixel 16 (in the structure shown in FIG. 1, the turn-on voltage Vg1 is applied to the gate during this period. signal line 17a), and the time when the EL element 15 is under on/off control (in the pixel structure shown in FIG. ). Therefore, the gate signal line 17a and the gate signal line 17b must be separated. the

For example, only when a single gate signal line 17 is laid from the gate driver circuit 12 to the pixel 16, the driving method according to the present invention cannot be implemented with a structure in which the logic applied to the gate signal line 17 (Vgh or Vg1) is supplied to the transistor 11b, and the logic applied to the gate signal line 17 is converted by an inverter (Vgh or Vg1) and supplied to the transistor 11d. Therefore, the present invention requires the gate driver circuit 12a that operates the gate signal line 17a and the gate driver circuit 12b that operates the gate signal line 17b. the

In addition, according to the driving method of the present invention, even with the pixel structure shown in FIG. 1, a non-illuminated display is provided during a period other than the current programming period (1H). the

A timing diagram of the driving method shown in FIG. 13 is illustrated in FIG. 14 . Regarding the pixel structure and the like in the present invention, unless otherwise specified, it is the one shown in Fig. 1. As can be seen from FIG. 14, in each selected pixel row, (the selection period is denoted as 1H), when the turn-on voltage Vg1 is applied to the gate signal line 17a (see FIG. 14(a)) , the off voltage (Vgh) is applied to the gate signal line 17b (see FIG. 14(b)). During this period, current does not flow through the EL element 15 (unlit mode). In the non-selected pixel row, the turn-on voltage (Vg1) is applied to the gate signal line 17b, and the turn-off voltage (Vgj) is applied to the gate signal line 17a. During this period, current flows through the EL element 15 (lighting mode). In this lighting mode, the EL element 15 is lit with a brightness (N·B) N times the predetermined brightness, and the lighting period is 1F/N. Therefore, the average display brightness of the display screen on 1F is given by (N·B)*(1/N)=B (predetermined brightness). the

FIG. 15 shows an example in which the operation shown in FIG. 14 is applied to each pixel row. This figure shows the voltage waveform applied to the gate signal line 17. The waveform of the disconnect voltage is represented by Vgh (high level), while the waveform of the turn-on voltage is represented by Vg1 (low level). Subscripts such as (1) and (2) indicate the number of selected pixel rows. the

In FIG. 15, gate signal line 17a(1) is selected (Vg1 voltage) and programming current flows through source signal line 18 in the direction from transistor 11a to source driver circuit 14 in the selected pixel row. This programmed current is greater than N times of the predetermined value (for ease of explanation, suppose N=10. Of course, because the predetermined value is the data current for displaying images, it is not a fixed value unless it is displayed on a white screen. ). Therefore, capacitor 19 is programmed so that a 10 times larger current will flow through transistor 11a. When the pixel row (1) is selected, in the pixel structure shown in FIG. the

After 1H, gate signal line 17a(2) is selected (Vg1 voltage) and programming current flows through source signal line 18 in the direction from transistor 11a in the selected pixel row to source driver circuit 14. The programmed current is greater than N times the predetermined value (for ease of explanation, assume N=10). Therefore, capacitor 19 is programmed so that a 10 times larger current will flow through transistor 11a. When the pixel row (2) is selected, in the pixel structure shown in FIG. However, since the OFF voltage (Vgh) is applied to the gate signal line 17a(1) of the pixel row (1) and the ON voltage (Vg1) is applied to the gate signal line 17b(1), the EL element 15 lights up. . the

After the next 1H, the gate signal line 17a(3) is selected, the off voltage (Vgh) is applied to the gate signal line 17b(3), and the current does not flow through the EL element 15 in the pixel row (3). However, since the OFF voltage (Vgh) is applied to the gate signal lines 17a (1) and (2) in the pixel rows (1) and (2), the ON voltage (Vg1) is applied to the gate signal line 17b. (1) and (2), so, the EL element 15 is illuminated. the

After the above operation, the image is displayed synchronously with the synchronous signal of 1H. However, with the driving method in FIG. 15, a 10 times larger current flows through the EL element 15. Therefore, the display screen 50 is 10 times brighter. Of course, it is obvious that in this state, the programmed current can be reduced to 1/10 for a predetermined brightness display. However, a 10 times smaller current will result in insufficient write current due to parasitic capacitance. Therefore, the basic concept of the present invention is to use larger current programming, insert the non-display area 52, and thereby obtain a predetermined brightness. the

Incidentally, the driving method according to the present invention causes a current larger than a predetermined current to flow through the EL element 15, and sufficiently charges and discharges the parasitic capacitance of the source signal line 18. That is to say, N times larger current does not need to flow through the EL element 15 . For example, it is conceivable to form a current path parallel to the EL element 15 (form a dummy EL element and employ a shielding film to prevent the dummy EL element from emitting light) and distribute the current between the EL element 15 and the dummy element. For example, when the signal current is 0.2 μA, the programmed current is set to 2.2 μA, and the 2.2 μA current flows through the transistor 11 a. Then, for example, a signal current of 0.2 µA can flow through the EL element 15, and 2 µA can flow through the inactive EL element. That is, the dummy pixel row 281 in Fig. 27 remains continuously selected. Incidentally, this dummy pixel is either prevented from emitting light or even if it emits light, it cannot be observed by a masking film or the like. the

With the above structure, by increasing the current flowing through the source signal line 18 by N times, it is possible to cause an N times larger current to flow through the driver transistor 11a, and a sufficiently smaller current than the N times larger current to flow through the EL element. 15. As shown in FIG. 5, this method enables the entire display screen 50 to be used as the image display area 53 without the non-display area 52. the

FIG. 13( a ) shows writing to the display screen 50 . In Fig. 13a, reference numeral 51a denotes a writing pixel row. A programming current is supplied from the source driver IC 14 to the source signal line 18 . In Fig. 13 and its ilk, there is a row of pixels to which current is written during 1H, but this is not restrictive. This period can be 0.5H or 2H. Also, although it has been described that the programming current is written into the source signal line 18, the present invention is not limited to current programming. The present invention can also adopt voltage programming (FIG. 62, etc.), and this programming writes the voltage into the source signal line 18. the

In FIG. 13(a), when the gate signal line 17a is selected, the current to flow through the source signal line 18 is programmed to the transistor 11a. At this time, an off voltage is applied to the gate signal line 17b, and current does not flow through the EL element 15. This is because when transistor 11d is on across EL element 15, a capacitive component of EL element 15 is visible from source signal line 18, and this capacitance prevents sufficient current from being programmed to capacitor 19. Therefore, taking the structure shown in FIG. 1 as an example, the pixel row to which current is written is the non-illuminated area 52, as shown in FIG. 13(b). the

Assuming N times larger current is used for programming (as above, assuming N=10), the screen becomes 10 times brighter. Therefore, 90% of the display screen 50 can be constituted by the non-illuminated area 52 . Therefore, for example, if the number of horizontal scan lines in the screen display area is 220 (S=200) according to QCIF, 22 horizontal scan lines can form the display area 53, and 220-22=198 horizontal scan lines can form the non-display area 52 . In general, if the horizontal scanning line (number of pixel rows) is represented by S, then the S/N of the whole area constitutes the display area 53, which is illuminated brightly by N times, and then the display area 53 is displayed in the vertical direction of the screen. is scanned. Therefore, S(N−1)/N of the entire area is the non-illuminated area 52 . The non-illuminated area 52 exhibits a black display (is unilluminated). In addition, the non-illuminated area 52 is produced by turning off the transistor 11d. Incidentally, although it has been stated that the display area 53 is illuminated N times brighter, of course, the value of N is adjusted by brightness adjustment and gray scale adjustment. the

In the above example, if a 10 times larger current is programmed, the screen becomes 10 times brighter, and 90% of the display screen 50 can be made up of the non-illuminated area 52 . However, this does not necessarily mean that R, G and B pixels constitute the non-illuminated area 52 in the same proportion. For example, 1/8 of R pixels, 1/6 of G pixels, and 1/10 of B pixels can constitute non-illuminated areas 52 with different colors determined by different ratios. It is also possible to have the non-illuminated area 52 (or the illuminated area 3) adjusted between R, G and B individually. For this reason, separate gate signal lines 17b must be provided for R, G and B. However, allowing R, G, and B to be adjusted individually makes it possible to adjust the white balance, making it easy to adjust the color balance for each gradation (see FIG. 41). the

As shown in Fig. 13 (b), all pixel rows comprising writing pixel row 51a form non-illuminating area 52, and S/N (1F/N in time sense) above writing pixel row 51a ) area constitutes the display area 53 (when writing scanning is done from the top to the bottom of the screen). These regions change position as the screen is scanned from bottom to top). Regarding the display condition of the screen, a strip of the display area 53 is shifted from the top to the bottom of the screen. the

In FIG. 13, the display area 53 is shifted from the top to the bottom of the screen. At low frame rates, the movement of the display area 53 can be seen by the naked eye. It is often easily seen especially when the user closes his/her eyes up and down or moves his/her head up and down. the

To deal with this problem, the display area 53 can be divided into a plurality of sections as shown in FIG. 16 . If the total area of the divided display area is S(N-1)/N, the luminance is equal to that in FIG. 13 . Incidentally, there is no need to divide the display area 53 equally. Also, there is no need to equally divide the non-display area 52 . the

Dividing the display area 53 can reduce screen flickering. Therefore, a flicker-free good image display can be obtained. Incidentally, the display area 53 can be divided more finely, however, the finer the display area 53 is divided, the worse the movie display performance becomes. the

Fig. 17 shows the voltage waveform of the gate signal line 17 and the emission luminance of the EL element. As can be seen from FIG. 17, the period (1F/N) when the gate signal line 17b is set to Vg1 is divided into a plurality of sections (K sections). That is, the 1F/(K·N) period in which the gate signal line 17b is set to Vg1 is repeated K times. This reduces flicker and enables image display at low frame rates. Preferably, the number of divisions is variable. For example, when a user presses a brightness adjustment switch or turns a brightness adjustment knob, the K value may be changed in response. Also, the user can be allowed to adjust the brightness. Alternatively, the K value can be changed manually or automatically according to the image or data to be displayed. the

Incidentally, although it has been described with reference to FIG. 17 and the like, the period (1F/N) during which the gate signal line 17b is set to Vg1 is divided into a plurality of sections (K sections), and The 1F/(K·N) period in which the line 17b is set to Vg1 is repeated K times, but this is not restrictive. Period 1F(K-N) may be repeated L (L≠K) times. In other words, the present invention displays the display screen 50 by controlling the period (time) during which current flows through the EL element 15 . Therefore, the concept of repeating this 1F/K·N period L (L≠K) times is included in the technical concept of the present invention. Also, by changing the value of L, the brightness of the display screen 50 can be changed by digital calculation. For example, there is a 50% change in brightness (contrast) between L=2 and L=3. Also, when the image display area 53 is divided, the period when the gate signal line 17b is set to Vg1 need not be equally divided. the

In the above example, when the current delivered to the EL element 15 is switched on and off, the display screen 50 is turned on and off (luminous and non-luminous). That is, with the charges held in the capacitor 19, approximately equal currents flow through the transistor 11a multiple times. The present invention is not limited to this case. For example, by charging and discharging capacitor 19, display screen 50 (illuminated and non-illuminated) can be switched on and off. the

FIG. 18 shows voltage waveforms applied to the gate signal line 17 to obtain the image display conditions shown in FIG. FIG. 18 differs from that of FIG. 15 in the operation of the gate signal line 17b. The gate signal line 17b is turned on and off (Vg1 and Vgh) as many times as the number of divisions of the screen. In other respects, FIG. 18 is the same as FIG. 15, and therefore, description thereof will be omitted. the

Since black display on the EL display device corresponds to total non-illumination, contrast is not lowered unlike the case of intermittent display on the liquid crystal display. Also, with the structure in FIG. 1, intermittent display can be obtained by simply turning on and off the transistor 11d. With the structures in Figs. 38 and 51, intermittent display can be obtained by simply turning on and off the transistor element 11e. This is because the image data is stored in the capacitor 19 (the number of layers is infinite because analog values are used). That is, image data is held in each pixel 16 for a period of 1F. Whether or not to pass current corresponding to stored image data to the EL element 15 is controlled by controlling the transistors 11d and 11e. the

Therefore, the driving method described above is not limited to the current driving type, and can also be applied to the voltage driving type. That is, in a structure in which the current flowing through the EL element 15 is stored in each pixel, intermittent driving is performed by turning on and off the current path between the driver transistor 11 and the EL element 15. the

It is important to maintain the terminal voltage of the capacitor 19 . This is because flicker occurs when the brightness of the screen changes and the frame rate drops if the terminal voltage of the capacitor 19 changes (charges/discharges) during one field (one frame) period. The current flowing through the EL element 15 from the transistor 11a must be higher than 65%. More specifically, if the current written into the pixel 16 and passed through the EL element 15 is taken as 100%, then the current flowing through the EL element 15 just written into the pixel 16 in the next frame (field) must not drop. to less than 65%. the

With the pixel structure shown in FIG. 1, there is no difference in the number of transistors 11 in a single pixel between when intermittent display is established and when intermittent display is not established. That is to say, let the pixel structure remain as it is, and by eliminating the parasitic capacitance effect of the source signal line 18, normal current programming can be obtained. In addition, the video display obtained is close to that of a CRT. the

Also, since the operating clock pulse of the gate driver circuit 12 is significantly slower than the operating clock pulse of the source driver circuit 14, there is no need to step up the main clock pulse of the circuit. In addition, the value of N can be easily changed. the

Incidentally, the image display direction (image writing direction) may be from top to bottom of the screen in the first field (frame), and may be from bottom to top of the screen in the second field (frame). That is, the upward direction and the downward direction may be alternately repeated. the

Alternatively, it is possible to adopt the downward direction in the first field (frame), turn the whole screen to black display (non-display) once, and adopt the upward direction in the second field (frame). It may also turn the entire screen to a black display (non-display) once. the

Incidentally, although top-to-bottom and bottom-to-top writing directions are employed in the above driving method, this is not restrictive. It is also possible to fix the writing method on the screen as a top-to-bottom direction or a bottom-to-top direction, and to move the non-display area 52 from top to bottom in the first field and from bottom to top in the second field. Alternatively, it is possible to divide one frame into three fields and designate the first field to R, the second field to G, and the third field to B so that the three fields constitute a single frame. It is also possible to sequentially display R, G, and B by switching between them every horizontal scanning period (1H) (see FIGS. 175 to 180 and their descriptions). The above-mentioned items are also applicable to other examples of the present invention. the

The non-display area 52 need not be entirely non-illuminated. Weak light emission or dim image display is not a problem in practical use. It should be regarded as an area having a lower display brightness than the image display area 53 . Also, the non-display area 52 may be an area where one or two colors of R, G, and B are not displayed. Also, it can be an area of one or two colors displayed between R, G, and B at low brightness. the

Basically, if the brightness of the display area 53 is maintained at a predetermined value, the larger the display area 53 is, the brighter the display screen 50 is. For example, when the brightness of the image display area 53 is 100 (nt), if the percentage of the display screen 50 caused by the display area 53 changes from 10% to 20%, then the brightness of the screen is doubled, therefore, by changing the display area 53 in the proportion of the entire screen 50, it is possible to change the display brightness of the screen. The brightness of the screen 50 is proportional to the ratio of the display area 53 to the screen 50 . the

The size of the display area 53 can be freely specified by controlling the data pulse ( ST2 ) sent to the shift register circuit 61 . Also, switching between the display conditions shown in FIG. 16 and the display conditions shown in FIG. 13 is possible by changing the input timing and cycle of the data pulses. Increasing the number of data pulses in a 1F period makes the screen 50 brighter, while decreasing it makes the screen 50 dimmer. Also, continuous application of data pulses results in the display conditions shown in FIG. 13, while intermittent application of data pulses results in the display conditions shown in FIG. the

FIG. 19( a ) shows the brightness adjustment scheme used when the display area 53 is continuous as in FIG. 13 . The display brightness of the screen 50 in Fig. 19 (a1) is the brightest, the display brightness of the screen 50 in Fig. 19 (a2) is the second brightest, and the display brightness of the screen 50 in Fig. 19 (a3) Brightness is the dimmest. Figure 19a is most suitable for movie display. the

The change from Fig. 19(a1) to Fig. 19(a3) (or vice versa) can be easily obtained by controlling the shift register circuit 61 of the gate driver circuit 12 as described above and the like. In this case, there is no need to change the Vdd voltage in FIG. 1 . That is, the brightness of the screen 50 can be changed without changing the power supply voltage. And in the process of changing from FIG. 19( a1 ) to FIG. 19( a3 ), the gradation characteristics of the screen do not change at all. Therefore, irrespective of the brightness of the screen 50, the contrast and gradation characteristics of the display screen are preserved. This is a remarkable feature of the present invention. the

In conventional screen brightness adjustment, the low brightness of the screen 50 results in poor gradation performance. That is to say, even though 64 gradations can be displayed in a high-brightness display, less than half of the gradations can be displayed in a low-brightness display in most cases. In contrast, according to the driving method of the present invention, 64 levels of gradation up to the highest level can be displayed regardless of the display brightness of the screen. the

FIG. 19( b ) shows the brightness adjustment scheme used when the display area 53 is dispersed as in FIG. 16 . In Fig. 19 (b1), the display brightness of the screen 50 is the brightest, in Fig. 19 (b2), the display brightness of the screen 50 is the second brightest, and in Fig. 19 (b3), the display brightness of the screen 50 is the brightest. Brightness is the dimmest. The change from FIG. 19( b1 ) to FIG. 19( b3 ) (or vice versa) can be easily obtained by controlling the shift register 61 such as the gate driver circuit 12 as described above. By dispersing the display areas 53, as shown in Fig. 19(b), it is possible to eliminate flickering even at a low frame rate. the

To eliminate flicker at even lower frame rates, the display area 53 can be dispersed more finely, as shown in Figure 19(c), however, this will degrade the performance of the movie display. Therefore, the driving method in FIG. 19(a) is suitable for moving screens. The driving method in FIG. 19(c) is suitable for reducing power consumption by displaying a still picture. Switching from FIG. 19(a) to FIG. 19(c) can be easily done by controlling the shift register circuit 61. the

Mainly, N=2 times, N=4 times etc. are used in the above example. However, the present invention is not limited to multiples of integers. Nor is it limited to a value equal to or greater than N=2. For example, less than half of screen 50 may be non-display area 52 at a certain point in time. If the EL element 15 is illuminated up to 4/5 of 1F using a current Iw5/4 of a predetermined value for power supply for programming, a predetermined luminance can be obtained. the

The present invention is not limited to the above. For example, a predetermined value of current Iw10/4 may be supplied to the program to illuminate the EL element for 4/5 of 1F. In this case, the EL element is illuminated with twice the predetermined brightness. Alternatively, the predetermined value of the current Iw5/4 may be supplied up to 2/5 of 1F programmed to illuminate the EL element. On this occasion, the EL element is illuminated at 1/2 the predetermined brightness. Also, the predetermined value of the current Iw5/4 can be programmed to illuminate the EL element up to 1/1 of 1F. On this occasion, the EL element is illuminated with 5/4 of the predetermined brightness. the

Therefore, the present invention controls the brightness of the display screen by controlling the magnitude of the programmed current and the lighting period 1F. Also, by illuminating the EL element for a period shorter than the 1F period, the present invention can insert the non-display area 52 and thereby improve film display performance. The present invention can display a bright screen by continuously illuminating the period of the EL element 1F. the

If the pixel size is Amm ² , and the predetermined brightness of the white screen is B(nt), then the preferred programming current I(μA) (the programming current output from the source drive circuit 14), that is, the current written into the pixel satisfies :

(A×B)/20≤I≤(A×B) 

This provides good light emission efficiency and solves the shortage of writing current. the

More preferably, the programmable current I (μA) is included in the following range:

(A×B)/10≤I≤(A×B) 

FIG. 20 is an explanatory diagram illustrating another example of increasing the current flowing through the source signal line 18 . This method selects multiple rows of pixel rows at the same time, and uses the total current flowing through the multiple rows of pixel rows to charge and discharge the parasitic capacitance of the source signal line 18 and its similar capacitance, thereby greatly reducing the load of the writing current. shortage. Since multiple pixel rows are selected simultaneously, the driving current per pixel can be reduced. Therefore, it is possible to reduce the current flowing through the EL element 15 . For ease of explanation, it is assumed that N=10 (the current flowing through the source signal line 18 is increased by 10 times). the

According to the present invention described with reference to FIG. 20, M rows of pixel rows are simultaneously selected. A current N times larger than a predetermined current from the source driver IC 14 is applied to the source signal line 18. A current greater than N/M times the current flowing through the EL element 15 is programmed to each pixel. As an example, in order to illuminate the EL element 15 with a predetermined emission luminance, a current is passed through the EL element 15 for a duration of M/N of one frame (one field) (M/N is for ease of explanation. , is not meant to be limited. As described earlier, it can be freely specified according to the brightness of the screen 50). This makes it possible to sufficiently charge and discharge the parasitic capacitance of the source signal line 18, resulting in sufficient resolution at the predetermined emission luminance. the

Current is passed through the EL element 15 only for M/N frame (field) periods, but current is not passed during the remaining period (1F(N−1)M/N). In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed at intervals (gaps) in the sense of time. This achieves good display conditions without image edge blurring. Furthermore, since the source signal line 18 is driven by an N-times high current, it is not affected by parasitic capacitance. Therefore, the method is applicable to high-resolution display screens. the

FIG. 21 is an explanatory diagram illustrating waveforms for implementing the driving method shown in FIG. 20 . the

The waveform of the off voltage is indicated by Vgh (H level), and the waveform of the on voltage is indicated by Vg1 (L level). Subscripts such as (1), (2), and (3) indicate the number of pixel rows. Incidentally, in the case of a QCIF screen, the number of lines is 220, and in the case of a VGA display, it is 480. the

In FIG. 21, the gate signal line 17a(1) is selected (voltage Vg1) and the programming current flows through the source signal line in the direction from the transistor 11a in the selected pixel row to the source driver circuit 14. 18. For ease of explanation, it is assumed here that the written pixel row 51a is the (1)th pixel row. the

The programmed current flowing through the source signal line 18 is N times greater than the predetermined value (for ease of explanation, assuming N=10. Of course, because the predetermined value is a data current, it is used for displaying images, unless it is displayed on a white screen. It is not a fixed value). Also assume that five pixel rows are selected simultaneously (M=5). So ideally a pixel's capacitor 19 is programmed so that twice as much (N/M=10/5=2) current will flow through the transistor 11a. the

When writing the pixel row is the (1) pixel row, gate signal line 17a (1), (2), (3), (4) and (5) are selected, as shown in Figure 21, That is, the switching transistors 11b and 11c in the pixel rows (1), (2), (3), (4) and (5) are turned on. In addition, the gate signal line 17b and the gate signal line 17a have a phase difference of 180°. Therefore, the switching transistors 11d in the pixel rows (1), (2), (3), (4) and (5) are turned off, and current does not flow through the EL elements 15 in the corresponding pixel rows. . That is, the EL element 15 is in the non-illumination mode 52 . the

Ideally, the transistors 11a in the five pixels each supply a current of Iw×2 to the source signal line 18 (i.e., a current of Iw×2×N=Iw×2×5=Iw×10 flows through the source signal line 18) Line 18. Therefore, if Iw of a predetermined voltage flows when not driven by the N-fold pulse according to the present invention, a current 10 times larger than Iw flows through the source signal line 18). the

By the above operation (driving method), the capacitor 19 of each pixel 16 is programmed with a twice as large current. For ease of understanding, it is assumed that the transistors 11a have the same characteristics (Vt and S values). the

Since five pixel rows are simultaneously selected (M=5), five driver transistors 11a are active. That is, 10/5=2 times larger current flows through the transistor 11a of each pixel. The total programmed current of the five transistors 11 a flows through the source signal line 18 . For example, if the conventional writing current to the writing pixel row 51 a is Iw, a current of Iw×10 flows through the source signal line 18 . The writing pixel row 51b in which image data is written slightly later than the writing pixel row (1) is an auxiliary pixel row for increasing the amount of current passed to the source signal line 18. However, there is no problem because the normal image signal is written into the writing pixel row 51b later. the

Therefore, in a period of 1H, the four pixel rows 51b provide the same display as the pixel rows 51a. Therefore, at least the selected write pixel row 51a and pixel row 51b to increase the current is in the non-display mode 52 . However, in a current mirrored pixel configuration, such as that shown in Figure 38, or in a voltage programmed pixel configuration, the pixel rows may be display mode. the

After 1H, the gate signal line 17a(1) becomes unselected, and the turn-on voltage (Vg1) is applied to the gate signal line 17b. Simultaneously, the gate signal line 17a (6) is selected (voltage Vgl), and the programming current flows through the source in the direction from the transistor 11a in the selected pixel row (6) to the source driver circuit 14. Signal line 18. Through this operation, normal image data is stored in the pixel row (1). the

After the next 1H, the gate signal line 17a(2) becomes unselected, and the turn-on voltage (Vg1) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (7) is selected (voltage Vg1), and the programming current flows through the source signal line in the direction from the transistor 11a in the selected pixel row (7) to the source driver circuit 14 18. By this operation, normal image data is stored in the pixel row (2). Through the above operations, the entire screen is redrawn as if its shifted pixel rows were scanned row by row. the

With the driving method in FIG. 20, since each pixel is programmed with a twice as large current, ideally, the emission luminance of the EL element 15 of each pixel is twice as high. Therefore, the brightness of the display screen is twice higher than the predetermined value. To make this luminance equal to the predetermined luminance, an area including the written pixel row 51, which is as large as half of the display screen 50, can be diverted into the non-display area 52, as illustrated in FIG. the

As shown in Figure 13, when a display area 53 moves from the top to the bottom of the screen, as shown in Figure 20, if a low frame rate is used, the movement of the display area 53 is recognized by the naked eye. Especially when the user closes his/her eyes up and down or moves his/her head up and down. the

To deal with this problem, the display area 53 can be divided into multiple parts, as illustrated in FIG. 22 . If the total area of the divided non-display area 52 is S(N-1)/N, the luminance is equal to that of the undivided display area. the

FIG. 23 shows voltage waveforms applied to the gate signal line 17. As shown in FIG. FIG. 21 differs from FIG. 23 mainly in the operation of the gate signal line 17b. The number of on and off (Vg1 and Vgh) of the gate signal line 17b is as many as the number of screen divisions. FIG. 23 is otherwise the same as FIG. 21, and thus description thereof will be omitted. the

As described above, dividing the display area 53 reduces flickering of the screen. Therefore, good image display without flicker can be obtained. Incidentally, the display area 53 can be divided more finely. The finer the display area 53 is divided, the less flicker occurs. Since the EL element 15 is highly sensitive, even if it is turned on and off at intervals shorter than 5 µsec, the display brightness is not lowered. the

With the driving method according to the present invention, the EL element 15 can be turned on and off by turning on and off the signal applied to the gate signal line 17b. Therefore, according to the driving method of the present invention, control can be accomplished using a low frequency on the order of KHz (kilohertz). Also, it does not require an image memory or the like in order to insert a black screen (insert into the non-display area 52). Therefore, the driving circuit or method according to the present invention can be realized at low cost. the

Fig. 24 shows the case where two pixel rows are selected at the same time. It has been found that the method of simultaneously selecting two rows of pixels provides a practical level of uniform display on display screens formed by low temperature polysilicon technology. It is possible that this is because the driver transistors 11a in adjacent pixels have very similar characteristics. In laser annealing, good results are obtained when the laser stripes are irradiated parallel to the source signal line 18 . the

This is because that portion of the semiconductor thin film that is simultaneously annealed has uniform characteristics. That is, the semiconductor thin film is uniformly produced within the irradiation range of the laser stripe, and the Vt and mobility of the transistor using the semiconductor thin film are almost uniform. Therefore, if the emission of laser light that makes stripes is moved in parallel with the source signal line 18, the pixels along the source signal line 18 (a pixel column, that is, pixels arranged vertically on the screen) have almost equal characteristics. Therefore, if a plurality of pixel rows are current programmed to be turned on at the same time, the current obtained by dividing the number of pixels selected by the programming current is almost uniformly programmed to the pixels. This makes it possible to program the current close to the target value and obtain a uniform display. Therefore, the direction of laser emission and the driving method described with reference to FIG. 24 and its ilk have superimposed effects. the

As mentioned above, if the direction of laser emission is made to be approximately consistent with the direction of the source signal line 18 (see FIG. 7), the characteristics of the vertically arranged pixel transistors 11a become almost the same, so that they can carry out normal current flow. Program control becomes possible (even if the characteristics of horizontally arranged pixel transistors 11a are not uniform). The above operation is performed in synchronization with 1H (one horizontal scanning period) by shifting the selected pixel rows one by one or by shifting the selected pixel rows by two or more rows at a time. the

Incidentally, as described with reference to FIG. 8 , the direction of laser emission does not always need to be parallel to the direction of the source signal line 18 . This is because the pixel transistors 11a placed along one source signal line 18 can be made to have almost equal characteristics even if the laser light is emitted at some angle to the source signal line 18. Therefore, aligning laser emission parallel to the source signal line 18 means bringing the pixels vertically adjacent to any pixel into the range of laser irradiation along the source signal line 18 . In addition, the source signal line 18 generally constitutes a connection for carrying a programmed current or voltage used as a video signal. the

Incidentally, in the examples of the present invention, the shift is performed every 1H for the written pixel row, but this is not restrictive. Pixel rows can be shifted every 2H (two pixel rows at a time). Also, more than two rows of pixels can be shifted simultaneously. Also the rows of pixels can be shifted at desired time intervals or every second pixel can be shifted. the

The shift interval can vary depending on the position on the screen. For example, the shift gap can be reduced in the middle of the screen and increased at the top and bottom of the screen. For example, a row of pixels may be shifted at intervals of 200 sec in the middle of screen 50 and at intervals of 100 sec at the top and bottom of screen 50 . Thus, the emission brightness is increased in the middle of the screen 50, while the emission brightness is decreased near the periphery (at the top and bottom of the screen 50). Needless to say, the shift intervals are smoothly changed between the top, middle, and bottom of the screen 50 to avoid brightness contours. the

Incidentally, the reference voltage of the source driver circuit 14 can be changed according to the scanning position on the screen 50 (see FIG. 146 etc.). For example, a reference current of 10 μA is used for the middle of the screen 50 and a reference current of 5 μA is used for the top of the screen 50 . the

Changing the reference current corresponding to the position in the screen 50 increases the emission brightness in the middle of the screen 50 and decreases the emission brightness near the periphery (at the top and bottom of the screen 50). Needless to say, between the top middle, and the bottom of the screen 50, the reference current is smoothly changed to avoid brightness contours. the

And, it is obvious that an image can be displayed by combining the driving method of changing the pixel row shift interval with the position on the screen and the driving method of changing the reference voltage with the position on the screen 50 . the

The shift interval can be changed on a frame-by-frame basis. Also, it is not strictly necessary to select consecutive rows of pixels. For example, selected pixel rows may be interlaced. the

Specifically, a driving method involves selecting the first and third pixel rows during the first horizontal scanning period, selecting the second and fourth pixel rows during the second horizontal scanning period, and selecting the second and fourth pixel rows during the third horizontal scanning period. The third and fifth pixel rows are selected in the scan cycle, and the fourth and sixth pixel rows are selected in the fourth scan cycle. Of course, a driving method involving selecting the first, third and fifth pixel rows in the first horizontal scanning period also belongs to the technical item of the present invention. Also, one of every few pixel rows can be selected. the

Incidentally, the combination of laser emission direction and multi-row pixel row selection is not limited to the pixel structures in Figs. 1, 2, and 32, but it is also applicable to current Other current-driven pixel structures mirror the pixel structure. Also, it can be applied to the voltage-driven pixel structures in Figs. 43, 51, 54, 62, etc. This is because current programming can be correctly accomplished using the voltage applied to the same source signal line 18 as long as the transistors in the upper and lower portions of the pixel have the same characteristics. the

In Fig. 24, when writing in the pixel row is the (1) pixel row, gate signal lines 17a (1) and (2) are selected (referring to Fig. 25), and this is in the pixel row (1) ) and (2) the switching transistor 11b and the transistor 11c are turned on. Therefore, at least the switching transistors 11d in the pixel rows (1) and (2) are off, and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL element 15 is in the non-illumination mode 52 . Incidentally, in FIG. 24, the display area 53 is divided into five sections to reduce flicker. the

Ideally, transistors 11a in two pixel rows each deliver current Iw×5 to source signal line 18 (when N=10. Since K=2, current is Iw×K×5=Iw×10 flows via the source signal line 18). The capacitor 19 of each pixel 16 is then programmed with a five times larger current. the

Since two pixel rows are simultaneously selected (K=2), two driver transistors 11a operate. That is, 10/2=5 times larger current flows through the transistor 11a of each pixel. The total programmed current of the two transistors 11 a flows through the source signal line 18 . the

For example, if the current written to the writing pixel row 51a is Id, a current of Iw×10 flows through the source signal line 18 . Since the correct image data is written to the writing pixel row 51b later, there is no problem. During the period of 1H, the pixel row 51b provides the same display as the pixel row 51a. Therefore, at least the writing pixel row 51a and the pixel row 51b selected to increase the current are in the non-display mode 52 . the

After the next 1H, the gate signal line 17a(1) becomes unselected, and the turn-on voltage (Vg1) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (3) is selected (voltage Vg1), and the programming current flows through the source signal line 18 along the direction from the transistor 11a of the selected pixel row (3) to the source driver circuit 14 . Through this operation, the correct image data is stored in the pixel row (1). the

After the next 1H, the gate signal line 17a (2) becomes unselected, and the turn-on voltage (Vg1) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (4) is selected (voltage Vg1), and the programming current flows through the source signal line 18 along the direction from the transistor 11a of the selected pixel row (4) to the source driver circuit 14 . With this operation, the correct image data is stored in the pixel row (2), and the entire screen is redrawn as if it were scanned by shifting the pixel row by row through the above operation (of course, two rows One or more pixel rows can be shifted at the same time, for example, in the case of pseudo-interlaced scanning, two pixel rows will be shifted at the same time, and, from the point of view of image display, the same images can be written in two or more pixel rows). the

As in the case of FIG. 16, with the driving method in FIG. 24, since each pixel is programmed with a 5 times larger current (voltage), ideally, the emission luminance of the EL element 15 is 5 times higher. Therefore, the brightness of the display area 53 is five times higher than the predetermined value. In order to make this luminance equal to a predetermined luminance, including writing to the pixel row 51, an area which is 1/5 of the display screen 50 can be turned into a non-display area 52. the

As shown in Figure 27, two rows of writing pixel lines 51 (51a and 51b) are sequentially selected from the upper side to the lower side of the screen 50 (see also Figure 26, in Figure 26 pixels 16a and 16b are selected ). However, at the bottom of the screen, although the writing pixel row 51a exists as shown in FIG. 27(b), 51b does not exist, that is, only one pixel row is selected. Therefore, all the current supplied to the source signal line 18 is written in the writing pixel row 51a. Therefore, a current twice as large as usual is written to the writing pixel row 51a. the

To deal with this problem, the present invention forms (sets) a dummy pixel row 281 at the bottom of the screen 50, as shown in FIG. 27(b). Therefore, after the pixel row at the bottom of the screen 50 is selected, the last pixel row of the screen 50 and the dummy pixel row 281 are selected. Therefore, in Fig. 27(b), a specified current is written to the writing pixel row. the

Incidentally, although the dummy pixel row 281 is illustrated as being adjacent to the upper end or the bottom of the display screen 50, it may be formed at a position apart from the display screen 50, but not restrictively. In addition, the dummy pixel row 281 need not contain switching transistors 11d or EL elements 15, such as those shown in FIG. This reduces the size of the dummy pixel row 281 . the

Fig. 28 shows the mechanism of how the state shown in Fig. 27(b) occurs. As can be seen from FIG. 28, after the pixel 16c at the bottom of the screen 50 is selected, the last pixel row (dummy pixel row) 281 of the screen 50 is selected. The dummy pixel row 281 is arranged outside the screen 50. As shown in FIG. That is, the dummy pixel row (dummy pixel) 281 is not illuminated, is not illuminated, or is hidden even if illuminated. For example, the contact hole between the pixel electrode 105 and the transistor 11 is eliminated, and no EL film or the like is formed on the dummy pixel row 281 . Also, an insulating film may be formed on the pixel electrode 105 of the dummy pixel row 271 . the

Although it has been described with reference to FIG. 27 that dummy pixels (rows) 281 are provided (formed or disposed) at the bottom of the screen 50, this is not limitative. For example, when the screen is scanned from bottom to top (reverse scanning), as shown in FIG. 29(a), dummy pixel rows 281 should also be formed at the top of the screen 50, as shown in FIG. 29(b). That is, dummy pixel rows 281 are formed (set) at both the top and bottom of the screen 50 . This structure is also suitable for reverse scanning of the screen. In the above example, two rows of pixels are selected simultaneously. the

The present invention is not limited to these cases. For example, five pixel rows can be selected simultaneously (see Fig. 23). When 5 pixel rows are selected at the same time, 4 invalid pixel rows 281 should be formed, that is, the number of invalid pixel rows 281 is equal to the simultaneously selected pixel rows minus 1. However, this is only true if the selected pixel rows are shifted one by one. When two or more pixel rows are shifted each time, (M-1)×L invalid pixel rows should be formed, where M is the number of selected pixels, and L is shifted each time the number of pixel rows. the

According to the structure of the dummy pixel row, that is, the driving of the dummy pixel row, one or more dummy pixel rows are used. Of course, it is preferable to use a combination of row driving of invalid pixels and N times pulse driving. the

In the driving method in which two or more pixel rows are selected at a time, the larger the number of pixel rows simultaneously selected, the more difficult it becomes to absorb variations in the characteristics of the transistor 11a. However, as the number M of simultaneously selected pixel rows decreases, the current programmed to a pixel increases, resulting in a larger current flowing through the EL element 15, which in turn makes the EL element prone to deterioration. the

Figure 30 shows how to solve this problem. The basic concept behind Fig. 30 is to adopt the method of simultaneously selecting multiple rows of pixel rows during 1/2H (1/2 of the horizontal scanning period), as described with reference to Figs. The method of selecting one pixel row in 2H (1/2 of the horizontal scanning period) is as described with reference to FIGS. 5 and 13 . This combination makes it possible to absorb variations in the characteristics of the transistor 11a, and to obtain a high speed and a uniform surface. Incidentally, although a period of 1/2H is used for ease of understanding, this is not limiting. The first period may be 1/4H and the second period may be 3/4H. the

Referring to FIG. 30, for easy understanding, it is assumed that 5 pixel rows are simultaneously selected in the first period, and one pixel row is selected in the second period. First, as shown in 30(a1), in the first period (the first 1/2H), 5 pixel rows are simultaneously selected. This operation has already been described with reference to FIG. 22, and therefore, its description will be omitted. As an example, assume that the current flowing through the source signal line 18 is as large as 25 times the predetermined value, so the transistor 11a in the pixel 16 (in the pixel structure in FIG. 1 ) uses a 5 times larger current (25/5 pixel rows = 5) is programmed. Since the current is 25 times larger, the parasitic capacitance generated in the source signal line 18 and the like is charged and discharged in an extremely short time. Therefore, the potential of the source signal line 18 reaches the target potential in a short period of time, and the terminal voltage of the capacitor 19 of each pixel 16 is programmed to pass a 25 times larger current. This 25 times larger current is applied in the first 1/2H (1/2 of the horizontal scan). the

Of course, since the same image data is written to 5 writing pixel rows, the transistors 11d in these 5 writing pixel rows are turned off in order not to display the image. Therefore, the display conditions are as shown in Fig. 30(a2). the

During the next 1/2H, a pixel is selected for current (voltage) programming. This condition is shown in Fig. 30(b1). Current (voltage) programming is performed so that a 5 times larger current flows through the writing pixel row 51a as in the first period. By reducing the variation in the terminal voltage of the programming capacitor 19, equal currents are passed in Fig. 30(a1) and Fig. 30(b1) to reach the target current more quickly. the

Specifically, in FIG. 30( a1 ), the current is passed through a plurality of pixels and rapidly approaches an approximate target value. During this first phase, since the plurality of transistors 11a are programmed, variations in the transistors cause errors equal to the intended values. In this second stage, only one pixel row for which data will be written and stored is selected, and full programming is accomplished by varying the current value from an approximate target value to a predetermined target value. the

Incidentally, the scanning from the top of the screen to the bottom non-illuminated area 52 and the scanning of the writing pixel row 51a from the top to the bottom of the screen are performed in the same manner as in FIG. 13 and its ilk. Therefore, A description thereof will be omitted. the

FIG. 31 shows driving waveforms for implementing the driving method shown in FIG. 30 . As can be seen from FIG. 31, 1H (one horizontal scanning period) consists of two states. The ISEL signal is used to toggle between these two states. The ISEL signal is illustrated graphically in Figure 31. the

First, the ISEL signal will be described. The driver circuit 14 for performing the operation shown in FIG. 30 includes a current output circuit A and a current output circuit B. Each current output circuit includes a D/A circuit for converting 8-bit level data from data to analog, an operational amplifier, and the like. In the example of FIG. 30, the current output circuit A is configured to output 25 times larger current. On the other hand, the current output circuit B is configured to output 5 times larger current, and the outputs from the current output circuit A and the current output circuit B are controlled by the ISEL signal by the switch circuit formed in the current output section, and applied to source signal line 18. Such a current output circuit is provided on each source signal line 18 . the

When the ISEL signal is low, the current output circuit A that outputs 25 times the larger current is selected, and the current from the source signal line 18 is absorbed by the source driver IC14 (more precisely, the current is absorbed by the source driver IC14. Formed current output circuit A sinks). The current magnification (such as 25 times or 5 times) from the current output circuit can be easily adjusted by using multiple resistors and an analog switch. the

As shown in Figure 30, when writing the pixel row is the (1)th pixel row (see 1H column in Figure 30) gate signal line 17a (1), (2), (3), (4) , and (5) are selected (in the case of the structure shown in Figure 1). That is, the switching transistor 11b and the transistor 11c in the pixel rows (1), (2), (3), (4), and (5) are turned on. Also, since ISLE is low, the current output circuit A which outputs a current 25 times larger is selected and connected to the source signal line 18 . And, an off voltage (Vgh) is applied to the gate signal line 17b. Therefore, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are turned off, and current does not flow through the EL element 15 in the corresponding pixel rows. . That is, the EL element 15 is in the non-illumination mode 52 . the

Ideally, each of the transistors 11a in the five pixels delivers a current Iw×2 to the source signal line 18, respectively. The capacitor 19 of each pixel 16 is then programmed with a five times larger current. For ease of understanding, it is assumed here that each transistor has equal characteristics (Vt and S values). the

Since 5 pixel rows are simultaneously selected (K=5), five driver transistors 11a operate. That is, 25/5=5 times larger current flows through the transistor 11a per pixel. The total programmed current of the five transistors 11 a flows through the source signal line 18 . For example, if the current written to the writing pixel row 51a by the conventional driving method is Iw, a current of Iw×25 flows through the source signal line 18 . The writing pixel row 51b to which image data is written slightly later than the writing pixel row (1) is an auxiliary pixel writing row for increasing the amount of current delivered to the source signal line 18. However, since the correct image data is written to the writing pixel row 51b later, there is no problem. the

Therefore, the pixel row 51b provides the same display as the pixel row 51a in a period of 1H. Therefore, at least the writing pixel row 51a and the pixel row 51b selected to increase the current are in the non-display mode 52 . the

In the next 1/2H period (1/2 of the horizontal scanning period), only the writing pixel row 51a is selected. That is, only the (1)th row of pixels is selected. It can be seen from FIG. 31 that the turn-on voltage (Vg1) is applied only to the gate signal line 17a(1), and the turn-off voltage (Vgh) is applied to the gate signal line 17(a)(2), (3 ), (4), and (5). Therefore, the transistor 11a in the pixel row (1) is in operation (supplying current to the source signal line 18), but the switches in the pixel row (2), (3), (4), and (5) The transistor 11b and the transistor 11c are off. That is, they are not selected. the

In addition, since ISEL is at high level, the current output circuit B which outputs a current five times larger is selected, and the current output circuit B is connected to the source signal line 18 . And, an off voltage (Vgh) is applied to the gate signal line 17b, which is in the same state as the first 1/2H period. Therefore, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are turned off, and the current does not flow through the EL elements 15 in the corresponding pixel rows. . That is, the EL element 15 is in the non-illumination mode 52 . the

Therefore, each transistor 11 a in the pixel row ( 1 ) delivers a current of Iw×5 to the source signal line 18 . Capacitor 19 in pixel row (1) is then programmed with a 5 times larger current. the

In the next horizontal scanning period, the written pixel row is shifted by one row. That is, the write pixel row (2) becomes the current write pixel row. In the first 1/2H period, when the write-in pixel row is the (2)th pixel row, the gate signal lines 17a (2), (3), (4), (5) and (6) are selected Certainly. That is, the switching transistor 11b and the transistor 11c in the pixel rows (2), (3), (4), (5) and (6) are turned on. In addition, since ISEL is at low level, the current output circuit A which outputs 25 times larger current is selected and connected to the source signal line 18 . And, an off voltage (Vgh) is applied to the gate signal line 17b. the

Therefore, the switching transistors 11d in the pixel rows (2), (3), (4), (5) and (6) are turned off, and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL element 15 is in the non-illumination mode 52 . On the other hand, since the voltage Vg1 is applied to the gate signal line 17(1) of the pixel row(1), the transistor 11d is turned on, and the EL element 15 in the pixel row(1) is illuminated. the

Since 5 pixel rows are simultaneously selected (K=5), 5 driver transistors 11a operate. That is, 25/5=5 times larger current flows through the transistor 11a of each pixel. The total programmed current of the five transistors 11 a flows through the source signal line 18 . the

In the next 1/2H period (1/2 of the horizontal scanning period), only the writing pixel row 51a is selected. That is, only the (2)th pixel row is selected. It can be seen from FIG. 31 that the turn-on voltage (Vg1) is applied only to the gate signal line 17a (2), and the turn-off voltage (Vgh) is applied to the gate signal line 17a (3), (4), ( 5) and (6). the

Therefore, the transistors 11a in the pixel rows (1) and (2) are in operation (the pixel row (1) supplies current to the EL element 15, and the pixel row (2) supplies current to the source signal line 18), But switching transistor 11b and transistor 11c in pixel rows (3), (4), (5) and (6) are off. That is, they are not selected. the

In addition, since ISEL is at high level, the current output circuit B which outputs a five times larger current is selected, and the current output circuit B is connected to the source signal line 18 . And, the off voltage (Vgh) is applied to the gate signal line 17b, which is in the same state as in the first 1/2H period. Therefore, the switching transistors 11d in the pixel rows (2), (3), (4), (5) and (6) are turned off, and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL element 15 is in the non-illumination mode 52 . the

Therefore, each transistor 11a delivers a current of Iw×5 to the source signal line 18 in the pixel row (1). The capacitor 19 in each pixel row (1) is then programmed with a 5 times larger current. The entire screen is drawn when the above operations are performed sequentially. the

The driving method described with reference to FIG. 30 selects G pixel rows (G is 2 or larger) in the first period and performs programming in such a way that N times larger current flows through each pixel row. In the second period, the drive method selects B rows of pixels (B is less than G, but not less than 1) and is programmed in such a way that N times larger current flows through the pixels. the

Another solution is also available. It selects G pixel rows (G is 2 or greater) in the first cycle and implements programming in such a way that the total current in all pixel rows will be N times larger. In the second cycle, this scheme selects B rows of pixels (B is less than G, but not less than 1), and implements programming in such a way that the total current in each pixel row that can be selected (if one row The pixel row is selected, then the current in this row of pixel row) will be a larger current of N times. For example, in Fig. 30(a1), 5 pixel rows are selected simultaneously, and a twice larger current flows through the transistor 11a in each pixel. Therefore, a larger current of 5×2=10 times flows through the source signal line 18 . In the second cycle, in Fig. 30(b1), one row of pixels is selected. A 10 times larger current flows through the transistor 11a in this pixel. the

Incidentally, in FIG. 31, although a plurality of pixel rows are simultaneously selected in a period of 1/2H, and a single pixel row is selected in a period of 1/2H, this is not restrictive. In the period of 1/4H, multiple rows of pixel rows may be selected simultaneously, and in the period of 3/4H, a single row of pixel rows may be selected. Also, the sum of the period during which a plurality of pixel rows are selected and the period during which a single pixel row is selected is not limited to 1H. For example, the total period may be 2H or 1.5H. the

In FIG. 30, after simultaneously selecting 5 pixel rows in the first 1/2H, it is also possible to simultaneously select two pixel rows in the second period. This also enables an acceptable image display to be obtained practically. the

In Fig. 30, pixel rows are selected in two stages—5 pixel rows are simultaneously selected in the first 1/2H period, and a single row of pixel rows is selected in the second 1/2H period, but This is not restrictive. For example, it may also select 5 pixel rows at the same time in the first stage, select two of the 5 pixel rows in the second stage, and finally select one pixel row in the third stage . In general, image data can be written to rows of pixels in two or more stages. the

In the above examples, pixel rows are selected row by row and current programmed, or two or more pixel rows are selected at a time and current programmed. However, the present invention is not limited to this case. It is also possible to use a combination of two methods based on image data: a method of selecting pixel rows one by one and current programming them, and a method of selecting two or more pixel rows at a time and current programming them . the

Figure 186 combines the driving system for selecting pixel rows row by row with the driving method for selecting pixel rows row by row. the

In the case of selecting a plurality of pixel rows at a time, for ease of understanding, it is assumed that two pixel rows are simultaneously selected, as illustrated in Fig. 186(a2). Therefore, one dummy pixel row 281 is formed on each of the top and bottom of the screen. the

A drive system that selects rows of pixels on a row-by-row basis eliminates the need to use dummy pixel rows. the

Incidentally, for ease of understanding, it is assumed that the source driver IC 14 outputs equal currents in FIG. 186(a1) (one pixel row is selected) and FIG. 186(a2) (two pixel rows are selected). the

Therefore, the driving system shown in FIG. 186(a2) that selects pixel rows two at a time provides half the brightness of the screen compared to the driving system that selects pixel rows one by one as shown in FIG. 186(a1). the

To provide equal screen brightness, the duty factor in Figure 186(a2) can be doubled (e.g. if the duty factor in Figure 186(a1) is 1/2, then it can be seen that The duty factor of is set to 1/1=1/2×2). the

Also, the magnitude of the reference current input to the source driver IC 14 can be changed by twice as much. Alternatively, the programmed current can be doubled. the

Fig. 186(a1) shows a typical driving method according to the present invention. If the input video signal is a non-interlaced (progressive) signal, the drive system in 186(a1) is used. If the input video signal is an interlaced signal, the drive system in Fig. 186(a2) is used. And if the video signal has low picture resolution. Then adopt the drive system in Figure 186 (a2), it is also possible to use the drive method in Figure 186 (a2) for the moving picture, and use the drive method in Figure 186 (a1) for the still picture, can be supplied to the gate by controlling The driving method in FIG. 186( a1 ) and the driving method in FIG. 186( a2 ) are easily switched by a start pulse of a pole driver current 12. the

Compared with the driving system of Fig. 186(a1) that selects pixel rows row by row, as shown in Fig. 186(a2), the problem of the driving system that selects two pixel rows at a time is to provide half the brightness of the screen. To provide equal screen brightness, the duty factor in Figure 186(a2) can be doubled (for example, if the duty factor in Figure 186(a1) is 1/2, then the duty factor in Figure 186(a2) The duty factor can be set to 1/1=1/2×2). That is, the ratio of the non-display area 52 and the display area 53 in FIG. 186(b) can be changed. the

The ratio of the non-display area 52 and the display area 53 in FIG. 186( b ) can be easily changed by controlling the start pulse supplied to the gate driver circuit 12 . That is, the driving mode in FIG. 186(b) can be changed according to the display modes in FIGS. 186(a1) and 186(a2). the

Now, the interlace drive according to the present invention will be described in more detail below. Fig. 187 shows the structure of a display panel performing interlaced driving according to the present invention. In FIG. 187, the gate signal lines 17a of odd-numbered pixel rows are connected to the gate driver circuit 12a1. The gate signal lines 17a of even-numbered pixel rows are connected to the gate driver circuit 12a2. On the other hand, the gate signal lines 17b of odd-numbered pixel rows are connected to the gate drive circuit 12b1. The gate signal lines 17b of even-numbered pixel rows are connected to the gate driver 1262. the

Accordingly, image data in odd-numbered pixel rows are sequentially rewritten by the operation (control) of the gate driver circuit 12a1. In odd-numbered pixel rows, illumination and non-illumination of the EL elements are controlled by the operation (control) of the gate driver circuit 12b1. And by the operation (control) of the gate driver circuit 12a2, the image data in the even-numbered pixel rows are sequentially rewritten. Illumination and non-illumination of the EL elements are controlled by operation (control) of the gate driver circuit 1262 in even-numbered pixel rows. the

Fig. 188(a) shows the state of working in the first field of the display screen. Fig. 188(b) shows the state of operation in the second field of the display screen. In FIG. 188 , the oblique shaded line marking the gate driver circuit 12 indicates that the gate driver circuit 12 does not participate in the data scanning operation. Specifically, in the first field of FIG. 188(a), the gate driver circuit 12a1 is working for the writing control of the programming current, and the gate driver circuit 1262 is working for the lighting control of the EL element 15. . In the second field of FIG. 188(b), the gate driver circuit 12a2 is operating for programming current writing control, and the gate driver circuit 12b1 is operating for EL element 15 lighting control. The above operations are repeated within this frame. the

Fig. 189 shows the image display condition in the first field. Figure 189(a) illustrates writing to pixel rows (positions of odd-numbered pixel rows programmed with current (voltage)). The positions of the written pixel rows are sequentially shifted: FIG. 189 (a1)→(a2)→(a3). In the first field, the odd-numbered pixel rows are sequentially overwritten (the image data in the even-numbered pixel rows remains unchanged). Fig. 189(b) illustrates the display condition of odd-numbered pixel rows. Incidentally, Fig. 189(b) illustrates only odd-numbered pixel rows, and even-numbered pixel rows are illustrated in Fig. 189(c). As can be seen from Fig. 189(b), the EL elements 15 of the pixels in odd-numbered pixel rows are non-illuminated. On the other hand, even-numbered pixel rows are scanned in the display area 53 and the non-display area 52, as shown in Fig. 189(c) (N times pulse driving). the

Figure 190 shows the state of image display in the second field. Figure 190(a) illustrates writing to a pixel row (position of odd-numbered pixel row programmed with current voltage). The positions of the written pixel rows are sequentially shifted: Figure 190 (a1)→(a2)→(a3). In the second field, the even-numbered pixel rows are sequentially overwritten (the image data in the odd-numbered pixel rows remain unchanged). Fig. 190(b) illustrates the display condition of odd-numbered pixel rows. Incidentally, Fig. 190(b) illustrates only pixel rows marked with odd-numbered pixel rows, and even-numbered pixel rows are illustrated in Fig. 190(c). As can be seen from Fig. 190(b), the EL elements 15 of the pixels in the even-numbered pixel rows are non-illuminated. On the other hand, odd-numbered pixel rows are scanned in both the display area 53 and the non-display area 52, as shown in Fig. 190(c) (N times pulse driving). the

It can be seen that on an EL display screen, interlaced driving can be easily realized. And, N times pulse driving eliminates the shortage of writing current and blurred moving picture. In addition, current (voltage) programming and illumination of the EL element 15 can be easily controlled, and circuits can be easily implemented. the

Incidentally, the driving method according to the present invention is not limited to those shown in Figs. 189 and 190 . For example, the driving method shown in FIG. 191 is also available, and in FIGS. 189 and 190, programmed odd-numbered pixel rows or even-numbered pixel rows belong to the non-display area 52 (non-luminous or black shown), the example in FIG. 191 involves synchronizing the gate driver circuits 12b1 and 1262 that control the illumination of the EL element 15. However, it goes without saying that the write pixel row 51 programmed by current (voltage) belongs to the non-display area (in the case of the current reflective pixel structure of FIG. 38, this need not be done). In FIG. 191, since the illumination control is common to odd-numbered pixel rows and even-numbered pixels, there is no need to provide two gate driver circuits: 12b1 and 1262. The gate driver circuit 12b alone can perform lighting control. the

In the driving method in Fig. 191, illumination control is used for both odd-numbered pixel rows and even-numbered pixel rows. However, the present invention is not limited to these cases. Fig. 192 shows an example of lighting control varying between odd-numbered and even-numbered pixel rows. In FIG. 192, the illumination pattern of odd-numbered pixel rows (display area 53 and non-display area 52), and the illumination pattern of even-numbered pixel rows have opposite patterns. Therefore, the display area 53 and the non-display area 52 have the same size. However, this is not restrictive. the

In the above example, the driving method uses one current (voltage) at a time to program the rows of pixels. However, the driving method according to the present invention is not limited to these cases. Needless to say, two pixel rows (multiple pixel rows) can be programmed with current (voltage) at the same time, as shown in FIG. 193 . Also, in Figures 190 and 189, it is not strictly necessary to place all odd-numbered pixel rows or even-numbered pixel rows in the non-illumination mode. the

According to the N-fold pulse driving method of the present invention, the same waveform is used for the gate signal lines 17b of different pixel rows, and the current is applied by shifting the pixel rows at intervals of 1H. The adoption of such scanning makes it possible to sequentially shift the illuminated pixel rows with the light emission duration of the EL element 15 fixed at 1F/N. It is easy to shift the pixel rows in this way while using the same waveform for the gate signal lines 17b of the pixel rows. This can be done by simply controlling the data ST1 and ST2 supplied to the shift register circuits 61a and 61b in FIG. For example, if Vgh is output to the gate signal line 17b when the input ST1 is low and Vg1 is output to the gate signal line 17b when the input ST1 is high, ST2 applied to the shift register circuit 17b can be It is set low for 1F/N cycles and set high for the rest of the cycles. Then the input ST2 can be shifted in synchronization with 1H by the clock pulse CLK2. the

Incidentally, the EL element 15 must be turned on and off at intervals of 0.5 msec or longer. Short intervals will cause insufficient black display due to persistence of vision, resulting in blurred images and making it appear as if the resolution has been reduced. This also represents the display status of the data save display. However, increasing the on/off interval to 100msec will cause flickering. Therefore, the ON/OFF interval of the EL element must be not shorter than 0.5msec and not longer than 100msec, more preferably, the ON/OFF interval should be from 2msec to 30msec (including both times). More preferably, the on/off interval should be from 3msec to 20msec (both inclusive). the

Also as above, the undivided black screen 152 results in a good movie display, but makes the flickering of the screen more noticeable. So dividing this black insert into many parts is ideal. However, too many partitions will blur the motion picture. The number of partitions should be from 1 to 8 (inclusive). Preferably it should be from 1 to 5 inclusive. the

Incidentally, it is preferable that the number of divisions of the black screen can be changed between still pictures and moving pictures. When N=4, 75% is occupied by a black screen, and 25% is occupied by an image display. When the number of divisions is 1, a black display occupying 75% is scanned vertically, and when the number of divisions is 3, 3 blocks are scanned. Here each block consists of a 25% black screen and a 25% percentage display. The number of partitions is increased for still pictures and decreased for moving pictures. This switching can be done either automatically based on the input image (detection of moving pictures) or manually by the user. Alternatively, the conversion can be done based on input content such as video on a display device. the

For example, for a wall display or an input screen on a mobile phone, the number of partitions should be 10 or more (in extreme cases the display can be switched on and off every -H). When displaying moving pictures in NTSC format, the division number shall be from 1 to 5 inclusive. Preferably, the number of partitions is variable in three or more levels; eg, 0, 2, 4, 8 partitions, etc. the

Preferably, the ratio of the black screen to the entire display screen should be from 0.2 to 0.9 (by N, then from 1.2 to 9) when the area of the entire plane is taken as 1, including these two ratios. Preferably, the ratio should be from 0.5 to 0.6 (or from 1.25 to 6 by N), inclusive of both ratios. If the ratio is 0.2 or less, the video display does not improve much. When the ratio is 0.9 or larger, the display portion becomes bright, and its vertical movement becomes easily recognized by the naked eye. the

And, preferably, the number of frames per second is from 10 to 100 (10 Hz to 100 Hz), both inclusive. More preferably, from 12 to 65 (12Hz to 65Hz), both numbers included. When the number of frames is small, flickering of the screen becomes conspicuous, and when the number of frames is too large, writing from the source driver circuit 14 and the like is difficult, resulting in deterioration of resolution. the

The present invention enables the brightness of the image to be varied by controlling the gate signal line 17 . However, it goes without saying that the brightness of an image can be changed by changing the current (voltage) applied to the source signal line 18. Obviously, the above two methods (FIGS. 33 and 35 and their counterparts) can be used in combination: the method of controlling the gate signal line 17 and the method of changing the current (voltage) applied to the source signal line 18. the

Needless to say, the above items apply not only to the pixel structure for voltage programming in FIGS. 43, 51, 54 and their ilk, but also to the pixel structure for current programming in FIG. 38. This can be accomplished by on/off control of transistor 11d in FIG. 38, transistor 11d in FIG. 43, and transistor 11e in FIG. In this way, by turning on and off the connection passing the current to the EL element 15, the N-fold pulse driving according to the present invention can be easily realized. the

And, at any time of a period of 1F (not limited to 1F, any unit time is fine), the gate signal line 17b can be set to Vg1 for a period of 1F/N. This is because predetermined luminance is obtained by turning off the EL element 15 for a predetermined period in the slave unit time. However, it is preferable to set the gate signal 17b to Vg1 and illuminate the EL element 15 immediately after the current programming period (1H). This will reduce the effect of the hysteresis characteristic of capacitor 19 in FIG. 1 . the

And, preferably, the number of screen partitions is made variable. For example, when a user presses a brightness adjustment switch or turns a brightness adjustment knob, the K value may be changed accordingly. Alternatively, the K value may be changed manually or automatically depending on the image or data to be displayed. the

In this way, a mechanism for changing the K value (the number of divisions of the image display section 53) can be easily realized, which can be changed simply by making the time of changing ST (when ST low level is set during 1F) adjustable to get. the

Incidentally, although it has been described with reference to FIG. 16 and the like, the period (1F/N) during which the gate signal line 17b is set to Vg1 is divided into a plurality of sections (K sections), and The period 1F(K·N) during which the pole signal line 17b is set to Vg1 is repeated K times, but this is not restrictive. Period 1F(K·N) may be repeated L (L≠K) times. In other words, the present invention displays the display screen 50 by controlling the period (time) during which current flows through the EL element 15 . Therefore, the concept of repeating the 1F/(K·N) period L(L≠K) times is included in the technical concept of the present invention, and, changing the value of L, the brightness of the display screen 50 can be digitally changed. For example, there is a 50% change in brightness (contrast) between L=2 and L=3. The controls described here also apply to other examples of the invention (of course it applies to examples described later in this text). These are also included in N-fold pulse driving according to the present invention. the

The above examples relate to disposing (forming) the transistor 11d serving as a switching element between the EL element 15 and the driver transistor 11a and turning on and off the screen 50 by controlling the transistor 11d. This driving method eliminates the shortage of write current under black display conditions during current programming, thereby obtaining normal resolution or black display. That is, in current programming, it is important to obtain a normal black display. The driving method described in the next step achieves normal black display by resetting the driver transistor 11a. This example will be described below with reference to FIG. 32 . the

The pixel structure in Fig. 32 is basically the same as that shown in Fig. 1, adopts the pixel structure in Fig. 32, the program control current Iw flows through the EL element 15, illuminates the EL element 15, and by program control, the driver transistor 11a The ability to pass current is maintained. The drive system shown in Figure 32 takes advantage of this ability to pass current, resetting (turning off) transistor 11a. Hereinafter, this drive system is called reset drive. the

To implement reset driving with the pixel structure shown in FIG. 1, the transistors 11b and 11c must be able to be turned on and off independently of each other. Specifically, as illustrated in FIG. 32, it is necessary to be able to independently control the gate signal line 17a (gate signal line WR) for the on/off control of the transistor 11b and the on/off control for the transistor 11c. The gate signal line 17c (gate signal line EL). The gate signal lines 17a and 17c can be controlled using two independent shift registers 61 illustrated in FIG. 6 . the

Preferably, the driving voltage should be varied between the gate signal line 17a of the driving transistor 11b and the gate signal line 17b of the driving transistor 11d (when the pixel structure of FIG. 1 is used). The amplitude of the gate signal line 17a (difference between turn-on and turn-off voltages) should be smaller than that of the gate signal line 17b. the

Too much amplitude of the gate signal line 17 will increase the penetration voltage between the gate signal line 17 and the pixel 16, resulting in an insufficient black level. The amplitude of the gate signal line 17a can be controlled by controlling the time when the potential of the source signal line 18 is not applied to (or applied (during selection period)) to the pixel 16. Since the change in potential of the source signal line 18 is small, the amplitude of the gate signal line 17a can be made small. the

On the other hand, the gate signal line 17b is used for on/off control of the EL. Therefore, its magnitude becomes large. For this, the output voltage is varied between the shift register circuits 61a and 61b. If the pixel is made of P-channel transistors, approximately equal Vgh (off voltage) is used for the shift register circuits 61a and 61b, so that the Vg1 (turn-on voltage) of the shift register 61a is higher than that of the shift register circuit 61b. Vg1 (turn-on voltage) is low. the

Reset driving will be described below with reference to FIG. 33 . FIG. 33 is a diagram illustrating the principle of reset driving. First, as illustrated in FIG. 33( a ), the transistors 11c and 11d are off, and the transistor 11b is on. As a result, the drain (D) terminal and gate (G) terminal of the drive transistor 11a are short-circuited, allowing the current Ib to flow. Typically, transistor 11a has been programmed with current in the previous field (frame). In this state, when the transistor 11d is turned off and the transistor 11b is turned on, the drive current Ib flows through the gate (G) terminal of the transistor 11a. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, resetting the transistor 11a (to a state where no current flows). the

The reset mode (in which no current flows) of the transistor 11a is equivalent to a state. In this state a compensation voltage is maintained in the voltage compensation cancellation mode described with reference to FIG. 51 and its ilk. That is, in the state of FIG. 33(a), the compensation voltage is held between the terminals of the capacitor 19, and the compensation voltage varies with the characteristics of the transistor 11a. Therefore, in Fig. 33(a), the state where the transistor 11a passes no current is retained in the capacitor 19 of each pixel (i.e., the transistor 11a passes a black display current close to zero). the

Incidentally, before the operation of FIG. 33(a), it is preferable to turn off the transistors 11b and 11c, turn on the transistor 11d, and flow the current through the driver transistor 11a. Preferably, this should be done in the least amount of time possible. Otherwise, there is a fear that a current will flow through the EL element 15, illuminating the EL element 15, thereby lowering the display contrast. Preferably, the operating time here is from 0.1% to 10% of 1H (one horizontal scanning period). Including these two data, more preferably, from 0.2% to 2%, ie from 0.2 μsec to 5 μsec, (including these two data). Also, this operation (which should be completed before the operation in Fig. 33(a)) can be performed on all the pixels 16 of the screen at once. This operation lowers the voltage at the drain (D) terminal of the driver transistor 11a, making it possible for the current Ib to flow smoothly in the state of FIG. 33(a). Incidentally, the above items are also applicable to other resets according to the present invention. the

When the operation time of FIG. 33(a) becomes longer, a larger current Ib flows, lowering the terminal voltage of the capacitor 19. Therefore, the operation time of Fig. 33(a) should be fixed. It has been pointed out experimentally and analytically that it is preferable to operate from 1H to 5H (both times inclusive) in Fig. 33(a). the

Preferably, this period should vary between R, G and B pixels. This is because the EL material varies between different colors and the boosted voltage varies between different EL materials. Optimum periods for EL materials should be specified for R, G, and B pixels, respectively. Although it has been stated that this period should be from 1H to 5H (including these two data) in the example, it is obvious that this period may be 5H or more in the case of a driving system that mainly involves black insertion (writing of a black screen). long. Incidentally, the longer the period, the better the black display condition of the pixel. the

The state shown in FIG. 33(b) occurs after the state in FIG. 33(a), during the period of 1H to 5H (including these two data), FIG. 33(b) shows that the transistors 11c and 11b are turned on, And the state in which the transistor 11d is turned off, which is a state in which current programming is being performed, as described earlier. Specifically, the program control current Iw is output (or absorbed) from the source driver circuit 14 and flows through the driver transistor 11a, and the potential of the gate (G) terminal of the drive transistor 11a is set so that the program control current Iw flows (this set The potential is stored in capacitor 19). the

If the programming current Iw is zero ampere, the transistor 11a remains in the state in FIG. 33(a), in which the transistor 11a does not flow current, thus obtaining a normal black display. And when the current programming for white display shown in 33(b) is performed, even if there is a change in the characteristics of the driving transistor in the pixel, the current programming is started from the compensation voltage for complete black display. Therefore, the time required to achieve the target current value becomes uniform according to the hierarchy. This eliminates gradation errors due to variations in characteristics of the transistor 11a, making it possible to obtain normal image display. the

After programming in FIG. 33(b), transistors 11b and 11c are sequentially turned off, and transistor 11d is turned on to deliver programming current Iw (=Ie) from driver transistor 11a to EL element 15, thereby illuminating EL element 15. The situation shown in FIG. 33(c) has already been described with reference to FIG. 1 and its counterparts, and thus a detailed description thereof will be omitted. the

The drive system (reset drive) described with reference to FIG. 33 consists of cutting off the connection of the driver transistor 11a to the EL element 15 (so that there is no current) and short-circuiting between the drain (D) terminal and the gate (G) terminal of the driver transistor. (or between the source (S) terminal and the gate (G) terminal, or in general, between the two ends of the driver transistor including the gate (G) terminal) and in the first operation The second operating composition of the transistor is then programmed with the current (voltage). At least the second operation is performed after the first operation. Incidentally, for reset driving, the transistors 11b and 11c must be independently controllable as shown in FIG. 32 . the

In image display mode (if a transient change can be observed), the pixel row to be current programmed is reset (black display mode) and after 1H is current programmed (also black display because transistor 11d is off) middle). Next, current is supplied to the EL element 15 and the pixel row is illuminated with a predetermined brightness (with a programmed current). That is, the row of pixels displayed in black moves from the top to the bottom of the screen, and it should appear as if the image was rewritten where the row of pixels bypassed. the

Incidentally, although it has been described that the current programming is completed 1H after a reset, this period may be approximately 5H or shorter. This is because it takes a considerable amount of time for the reset to be done in Fig. 33(a). If this period is like 5H, 5 pixel rows will display black (including 6 pixel rows that are current programmed pixel rows). the

Also, the number of pixel rows to be reset at one time is not limited to one, but two or more pixel rows can be reset at one time. It is also possible to reset and scan two or more pixel rows at a time by overlapping some of them, for example, if 4 pixel rows are reset at a time, the pixels are reset during the first horizontal scan (1 cell) Rows (1), (2), (3) and (4), reset pixels during the second horizontal scan Rows (3), (4), (5) and (6), reset during the third horizontal scan Pixel rows (5), (6), (7) and (8), pixel rows (7), (8), (9) and (10) are reset during the fourth horizontal scan. Incidentally, the driving operations in 33(b) and 33(c) are of course carried out in synchronization with the driving operation in Fig. 33(a). the

Needless to say, the driving operations of Figs. 33(b) and 33(c) can be performed simultaneously after resetting all the pixels in the screen, or during scanning. And, obviously, the pixel row can be reset (at the interval of one or more pixel rows) under the interlaced driving mode (scanning at the interval of one or more pixel rows), and the pixel row Randomly resettable, the reset drive according to the present invention involves manipulating rows of pixels (i.e., controlling the vertical orientation of the screen). However, the concept of reset driving is not limited to controlling the indication of pixel row direction. For example, it is obvious that reset driving can be performed in the direction of pixel columns. the

Incidentally, if the reset drive in Fig. 33 is combined with the N-fold pulse drive according to the present invention or with the interlace drive, better image display can be obtained. In particular, the structure in Figure 22 can easily realize intermittent N/K times pulse driving (this driving method provides two or more illuminated areas on the screen, and the transistor can be turned on or off by controlling the gate signal line 17b 11d: and this was described earlier), therefore, normal image display without flickering can be obtained. the

Needless to say, a more excellent image display can be obtained by combining the reverse bias driving method, the precharge driving method, the penetration voltage driving method, or the like described later. Therefore, it is apparent that reset driving can be accomplished in combination with other examples according to the present invention. the

Fig. 34 is a block diagram of a display device implementing re-driving. The gate driver circuit 12a controls the gate signal line 17a and the gate signal line 17b in FIG. 32 . The transistor 11b is turned on and off by application of an on/off voltage to the gate signal line 17a. And, the transistor 11d is turned on and off by application of an on/off voltage to the gate signal line 17b. The gate driver circuit 12b controls the gate signal line 17c in FIG. 32 . The transistor 11c is turned on and off by application of an on/off voltage to the gate signal line 17c. the

Therefore, the gate signal line 17a is controlled by the gate driver circuit 12a. The gate signal line 17c is controlled by the gate driver circuit 12b, which not only makes it possible to freely specify the time for turning on the transistor 11c and using the current program to control the driver transistor 11a, but also makes it possible to freely specify the time for turning on the transistor 11b and resetting the driver transistor 11a. time becomes possible. The other parts of the structure are the same as or similar to those described earlier, so description thereof is omitted. the

Fig. 35 is a timing diagram of reset drive. When an ON voltage is applied to the gate signal line 17a to turn on the transistor 11b and reset the driver transistor 11a, an OFF voltage is applied to the gate signal line 17b to keep the transistor 11d off. This establishes the state shown in Fig. 32(a). The current Ib flows during this period. the

Although in the timing chart shown in FIG. 35, the reset time is 2H (when the on-voltage is applied to the gate signal line 17a and the transistor 11b is turned on), this is not restrictive. Reset time can be longer than 2H. If the reset can be done very quickly, the reset time may be less than 1H. the

Using the DATA(ST) pulse period input into the gate driver circuit 12, the duration of the reset period can be easily changed. For example, if DATA input into the ST terminal is set to a high level for a period of 2H, the reset period output to each gate signal line 17a is 2H. Similarly, if the DATA input into the ST terminal is set to a high level for a period of 5H, the reset period output to each gate signal line 17a is 5H. the

After the reset period of 1H, an ON voltage is applied to the gate signal line 17c(1) of the pixel row (1). When the transistor 11c is turned on, the programming current Iw applied to the source signal line 18 is written into the driver transistor 11a through the transistor 11c. the

After current programming, a cut-off voltage is applied to the gate signal line 17c of the pixel row (1), the transistor 11c is turned off, and the pixel is disconnected from the source signal line. Simultaneously, the cut-off voltage is also applied to the gate signal line 17a, and the driver transistor 11a leaves the reset mode (by the way, the term "current-programmed mode" is more suitable for this period than the term "reset"). On the other hand, an ON voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and the current programmed to the driver transistor 11a flows through the EL element 15. What has been said about pixel row (1) applies analogously to pixel row (2) and subsequent pixel rows. And, their operations are clear at a glance from FIG. 35 . Therefore, descriptions of (2) and subsequent pixel rows are omitted. the

In FIG. 35, the reset period is 1H. FIG. 36 shows an example where the reset period is 5H. The duration of the reset period can be easily changed by using the DATA (ST) pulse period input to the gate driver circuit 12 . FIG. 36 shows an example in which DATA input to the ST1 terminal of the gate driver circuit 12a is set to a high level for a period of 5H, and a reset period output to each gate signal line 17a is 5H. The longer the reset period, the more completely the reset is done, resulting in a normally black display. However, the display brightness is reduced accordingly. the

In FIG. 36, the reset period has been 5H. Also, the reset mode is continuous. However, the reset pattern need not necessarily be continuous. For example, a signal output from each gate signal line 17a may be turned on and off every -H. Such on/off operation can be easily obtained by operating a start circuit (not shown) formed in the output stage of the shift register or controlling the DATA (ST) pulse input to the gate driver circuit 12 . the

In the circuit configuration shown in FIG. 34, the gate driver circuit 12a requires at least two shift register circuits (one for the gate signal line 17a and the other for the gate signal line 17b). This suggests a problem of increasing the circuit range of the gate driver circuit 12a. FIG. 37 shows an example in which the gate driver circuit 12a has only one shift register. The timing diagram of the output signal resulting from the operation of the circuit in Fig. 37 is shown in Fig. 35 . Note that the gate signal lines 17 from the gate driver circuits 12a and 12b are indicated by different symbols between FIGS. 35 and 37 . the

As can be seen from the fact that an OR (OR) circuit 371 is included in FIG. 37, the output of each gate signal line 17a is ORed (ORed) with the output from the previous stage to the shift register circuit 61a. That is, the gate signal line 17a outputs a turn-on voltage, and the period is 2H. On the other hand, the gate signal line 17c outputs the output of the shift register circuit 61a as it is. Therefore, the turn-on voltage is added, and the period is 1H.

For example, if the shift register circuit 61a outputs a high-level signal second, then a turn-on voltage is output to the gate signal line 17c of the pixel 16(1), and the pixel is now in the state of current (voltage) programming . At the same time, the turn-on voltage is also output to the gate signal line 17a of the pixel 16(2), turning on the transistor 11b of the pixel 16(2), and resetting the driver transistor 11a of the pixel 16(2). the

Similarly, if the shift register circuit 61a outputs a high-level signal third, a turn-on voltage is output to the gate signal line 17c of the pixel 16(2), and the pixel is now in the state of current (voltage) programming middle. Simultaneously, the turn-on voltage is also output to the gate signal line 17a of the pixel 16(3), turns on the transistor 11b of the pixel 16(3), and resets the driver transistor 11a of the pixel 16(3). Therefore, the gate signal line 17a outputs an ON voltage for a period of 2H, and the gate signal line 17c receives an ON voltage for a period of 1H. the

In programmed mode, since transistors 11b and 11c are turned on simultaneously (Fig. 33(b)), if transistor 11c is turned off before transistor 11b during transition to unprogrammed mode (Fig. 33(c)), what happens in Fig. 33(b ) in reset mode. To prevent this, transistor 11c must be turned off after transistor 11b. For this reason, it is necessary to apply the turn-on voltage to the gate signal line 17a earlier than to the gate signal line 17c. the

The above examples relate to the pixel structure in Fig. 32 (basically, in Fig. 1). However, the present invention is not limited to these cases. For example, a current mirror pixel structure such as that shown in FIG. 38 is also applicable. Incidentally, in FIG. 38, by turning on and off the transistor 11e, the N-fold pulse driving explained in FIGS. 13, 15, etc. can be realized. FIG. 39 is an explanatory diagram illustrating an example using the structure of a current-reflecting pixel shown in FIG. 38. FIG. Reset driving in the current-reflecting pixel structure will be described below with reference to FIG. 39 . the

As shown in FIG. 39(a), the transistors 11c and 11e are turned off, and the transistor 11d is turned on. Then, the drain (D) terminal and the gate (G) terminal of the current-programmed transistor 11b are short-circuited, and the current Ib flows between them, as shown in the figure. Usually, transistor 11b has been controlled by current in the previous field (frame), and can flow current (because the gate potential is held in capacitor 19 for a period of 1F, and the image is displayed, so this is very natural. However , the current does not flow during the entire black display period). In this state, since the transistor 11e is turned off and the transistor 11d is turned on, the driver current Ib flows through the gate (G) terminal of the transistor 11a (the gate (G) terminal and the drain (D) terminal are short-circuited). Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, resetting the transistor 11a (to a state where no current flows). Since the drive transistor 11b shares the gate (G) terminal with the current-programmed transistor 11a, the drive transistor 11b is also reset. the

The reset mode of transistors 11a and 11b (in which no current flows) is equivalent to a state in which the compensation voltage is preserved in the voltage compensation cancellation mode described with reference to FIG. 51 and its ilk. That is, in the state of FIG. 39( a), the compensation voltage is held between both ends of the capacitor 19 (the compensation voltage is a start-up voltage at which current starts to flow: when a voltage equal to or greater than the start-up voltage is applied , the current flows through the transistor 11). The compensation voltage varies with the characteristics of the transistors 11a and 11b. Thus, in FIG. 39(a), a state in which transistors 11a and 11b do not flow current is maintained in capacitor 19 of each pixel (transistors 11a and 11b pass near zero black display current, i.e., they have been reset to the starting voltage at which current begins to flow). the

In FIG. 39(a), when the reset period becomes longer, a larger Ib current tends to flow, reducing the terminal voltage of the capacitor 19, as in the case of FIG. 33(a). Therefore, the operation time in Fig. 39(a) should be fixed. It has been pointed out experimentally and analytically that it is preferable that the operation time in Fig. 39(a) is from 1H to 10H (10 horizontal scanning periods) both inclusive. More preferably, it should be from 1H to 5H or from 20μsec to 2msec (including these two times). This also applies to the drive system in FIG. 33 . the

As in the case of FIG. 33(a), if the reset mode in FIG. 39(a) is synchronized with the current-programmed mode in FIG. 39(b), since the reset mode in FIG. 39(a) The period to the current programming mode in Fig. 39(b) is fixed (unchanged), so there is no problem. That is, it is preferable that the period from the reset mode in FIG. 33(a) or FIG. 39(a) to the current programming mode in FIG. 33(b) or FIG. 39(b) should be from 1H to 10H (10 horizontal scanning periods) include these two times. More preferably, it should be from 1H to 5H or 20μsec to 2msec (both times included). If this period is short, the driver transistor 11 is not completely reset. If it is too long, the driver transistor 11 is completely turned off, which means more time is needed for current programming. And, the brightness of the screen 50 is lowered. the

After the state in Fig. 39(a), the state shown in Fig. 39(b) occurs. Fig. 39(b) shows a state where the transistors 11c and 11d are turned on, and the transistor 11e is turned off. This is the state in which current programming is in progress. Specifically, the programming current Iw is output (sinked) from the source driver circuit 14 and flows through the current programming transistor 11a. The gate (G) terminal potential of the driver transistor 11a is set in the capacitor 19 so that the programming current Iw will flow. the

If the programming current Iw is zero (black display), the transistor 11b is kept in a state in which no current flows in FIG. 33(a), and therefore, a correct black display is obtained. Also, when performing current programming for white display in FIG. 39(b), even if there is a characteristic variation of the driver transistor in the pixel, current programming starts from the compensation voltage for complete black display (the compensation voltage is the start-up voltage at At this voltage, the current specified by the characteristics of each driver transistor starts to flow). Therefore, the time required to reach the target current value becomes uniform according to the hierarchy. This eliminates gradation errors due to variations in the characteristics of the transistor 11a or 11b, making it possible to obtain correct image display. the

After the current programming in Fig. 39(b), transistors 11c and 11d are sequentially turned off, and transistor 11e is turned on to deliver the programmed current Iw (=Ie) from the driver transistor 11b to the EL element 15, thereby illuminating the EL element 15 . The cases shown in Fig. 39(c) have already been described, and therefore, detailed description thereof will be omitted. the

The drive system (reset) described with reference to FIGS. 33 and 39 consists of disconnecting the driver transistor 11a or 11b from the EL element 15 (using the transistor 11e or 11d so that no current flows), and at the drain (D) terminal of the driver transistor and the gate (G) terminal (or between the source (S) terminal and the gate (G) terminal, or in general, between the two ends including the gate (G) of the driver transistor Between) a first operation and a second operation of programming the driver transistor with a current (voltage) after the first operation. the

The second operation is done at least after the first operation. Incidentally, in the first operation, the operation of disconnecting the driver transistor 11a or 11b from the EL element 15 is not absolutely required. In the case where the driver transistor 11a or 11b is not disconnected from the EL element 15, the drain (D) terminal and the gate (G) terminal of the drive transistor are short-circuited in the first operation, and in the reset mode, nothing more than some Change can take place. Whether to omit the disconnect should be determined by considering the characteristics of the transistors in the structured array. the

The current-reflecting pixel structure in FIG. 39 provides a drive method that resets the current-programmed transistor 11a, and thus resets the drive transistor 11b. the

With the current-reflecting pixel structure in FIG. 39, it is not always necessary to disconnect the driver transistor 11b from the EL element 15 in the reset mode. Therefore, the following operations are performed: Short circuit between the drain (D) terminal and the gate (G) terminal (or between the source (s) terminal and the gate (G) terminal, or in general, between the two terminals comprising the gate (G) terminal of the current-programmed transistor, or between the two terminals comprising the gate (G) terminal of the driver transistor), and in the first operation Afterwards, the second operation of this current-programmed transistor is programmed with a current (voltage). The second operation is performed at least after the first operation. the

In image display mode (if transient changes are observed), the current-programmed pixel row is reset (black display mode) and, after a predetermined H, current-programmed. The rows of pixels displayed in black move from the top to the bottom of the screen, and it should appear as if the image was rewritten where the row of pixels bypassed. the

Although the above examples have been described mainly in relation to pixel structures for current programming, the reset drive according to the present invention can also be applied to pixel structures for voltage programming. Fig. 43 is an explanatory diagram illustrating a pixel structure (panel structure) for performing reset driving for voltage programming in the pixel structure according to the present invention. the

In the structure shown in FIG. 43, a transistor 11e that resets the driver transistor 11a is formed. When the turn-on voltage is applied to the gate signal line 17e, the transistor 11e is turned on, causing a short circuit between the gate (G) terminal and the drain (D) terminal of the driver transistor 11a. In addition, a transistor 11d for cutting off a current path between the EL element 15 and the driver transistor 11a is formed. In the pixel structure according to the present invention, reset driving for voltage programming will be described below with reference to FIG. 44 . the

As illustrated in FIG. 44( a ), the transistors 11b and 11d are turned off, and the transistor 11e is turned on. The drain (D) terminal and gate (G) terminal of the driver transistor 11a are short-circuited, and the current Ib flows as shown in the figure. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, resetting the transistor 11a (to a state where no current flows). Before resetting the transistor 11a, the transistor 11d is turned on, the transistor 11e is turned off, and a current flows through the transistor 11a in synchronization with the HD synchronization signal as described with reference to FIG. 33 or 39 . Then the operation shown in Fig. 44(a) is completed. the

The reset mode of transistors 11a and 11b (in which no current flows) is equivalent to the compensation voltage being held in a state in the voltage compensation cancellation mode described with reference to FIG. 41 and its ilk. That is, in the state of FIG. 44( a ), the compensation voltage (reset voltage) is held between both terminals of the capacitor 19 . The reset voltage varies with the characteristics of the driver transistor 11a. Therefore, in Fig. 44(a), the state in which the driver transistor 11a does not flow current is maintained in the capacitor 19 of each pixel (the transistor 11a passes a black display current close to zero, that is, it has been reset to the point where the current starts to flow. Starting voltage). the

Incidentally, in the pixel structure used for voltage programming, when the reset period becomes longer, a larger Ib current tends to flow, reducing the terminal voltage of the capacitor 19, such as the pixel used for current programming The same is true for the structure. Therefore, the operation time in Fig. 44(a) should be fixed. Preferably, the operation time should be from 0.2H to 5H (5 horizontal scanning periods) including these two times. More preferably, it should be from 0.5H to 4H or from 2µsec to 400µsec (both times inclusive). the

In addition, the gate signal line 17e should be shared with the gate signal line 17a in the preceding stage. That is, the gate signal line 17e should be short-circuited with the gate signal line 17a in the pixel row in the previous stage. This structure is called a front-stage gate control system. Incidentally, the stage-by-stage gate control system employs the waveform of the gate signal line for one or more H selected pixel rows preceding the pixel row of interest. Therefore, this system is not limited to the preceding pixel rows. For example, the pixel row driver transistor 11a of interest may take the waveform of the gate signal line two pixel rows ahead. the

The level-level gate control system will be described in more detail. Assume that the pixel row of interest is the (N)th pixel row, and its gate signal lines are 17e(N) and 17a(N). The previous pixel row selected 1H ago is assumed to be the (N-1)th pixel row, and its gate signal lines are 17e(N-1) and 17a(N-1). The pixel row selected after the pixel row of interest 1H is assumed to be the (N+1)th pixel row, and its gate signal lines are 17e(N+1) and 17a(N+1). the

In the (N-1)H period, when the turn-on voltage is applied to the gate signal line 17a(N-1) of the (N-1)th row of pixel rows, the turn-on voltage is also applied to the Nth row of pixels. Gate signal lines 17e (N) in a row. This is because the gate signal line 17e(N) and the gate signal line 17a(N-1) of the pixel row are short-circuited in the previous stage. Therefore, the pixel transistor 11b(N-1) is turned on in the (N-1)-th pixel row, and the voltage applied to the source signal line 18 is written into the gate of the driver transistor 11a(N-1) ( G) end. At the same time, the pixel transistor 11e(N) is turned on in the (N)-th pixel row. The gate (G) terminal and the drain (D) terminal of the driver transistor 11a(N) are short-circuited, and the driver transistor 11a(N) is reset. the

In the (N)th H period following the (N-1)th H period, when the turn-on voltage is applied to the gate signal line 17a(N) of the (N)th pixel row, the turn-on voltage is also It is supplied to the gate signal line 17e(N+1) of the (N+1)-th pixel row. Accordingly, the pixel transistor 11b(N) is turned on in the (N)th pixel row, and the voltage applied to the source signal line 18 is written to the gate (G) terminal of the driver transistor 11a(N). Simultaneously, the pixel transistor 11e (N+1) in the (N+1)th pixel row is turned on, and the gate (G) terminal and the drain (D) terminal of the driver transistor 11a (N+1) are short-circuited, And the driver transistor 11a(N+1) is reset. the

Similarly, in the (N+1)th period after the (N)th H period, when the turn-on voltage is added to the gate signal line 17a(N+1) of the (N+1)th pixel row , the turn-on voltage is also applied to the gate signal line 17e(N+2) of the (N+2)-th pixel row. Therefore, the pixel transistor 11b(N+1) in the (N+1)-th pixel row is turned on, and the voltage applied to the source signal line 18 is written into the gate of the driver transistor 11a(N+1) ( G) end. Simultaneously, the pixel transistor 11e (N+2) in the (N+2)th pixel row is turned on, and the gate (G) terminal and the drain (D) terminal of the driver transistor 11a (N+2) are short-circuited , and the driver transistor 11a (N+2) is reset. the

According to the stage-one-stage gate control system of the present invention described above, the driver transistor 11a is reset for a period of 1H, and then, voltage (current) programming is performed. the

As in the case of FIG. 33(a), if the reset mode in FIG. 44(a) is synchronized with the voltage programming mode in FIG. 44(b), then because from the reset mode in FIG. The period of the current programming mode in Fig. 44(b) is fixed (unchanged), so there is no problem. If this period is short, the driver transistor 11 is not fully reset. If it is too long, the driver transistor 11a is completely turned off, which means a lot of time is needed for current programming. Also, the brightness of the screen 12 is reduced. the

After the state of Fig. 44(a), the state shown in Fig. 44(b) occurs. Fig. 44(b) shows that the transistor 11b is turned on, and the transistors 11e and 11d are turned off. This state in Fig. 44(b) is a state in which voltage programming is being performed. Specifically, the programming voltage is output from the source driver circuit 14, and written in the gate (G) terminal of the driver transistor 11a (the potential of the gate (G) terminal of the driver transistor 11a is set in the capacitor 19). Incidentally, in the case of voltage programming, it is not always necessary to turn off the transistor 11d during voltage programming. In addition, if it is not necessary to combine with the N-fold drive shown in Figures 13, 15 or their counterparts or perform intermittent N/K one-fold pulse drive (this drive method provides two or more lighting area, and can be easily realized by turning on and off the transistor 11e), the transistor 11e is not necessarily required. Since this case has been described earlier, its description is omitted. the

When voltage programming is performed for white display using the structure shown in FIG. 43 or the driving method shown in FIG. 44, even if there is a change in the characteristics of the driver transistor in the pixel, the voltage programming starts from the compensation voltage for complete black display ( The compensation voltage is the starting voltage at which the current specified by the characteristics of each driver transistor starts to flow). Therefore, the time required to reach the target current value becomes uniform according to the hierarchy. This eliminates gradation errors due to variations in the characteristics of the transistor 11a, making it possible to obtain correct image display. the

After the current programming of FIG. 44(b), the transistor 11d is turned off, and the transistor 11d is turned on to deliver the programmed current from the driver 11a to the EL element 15, thereby illuminating the EL element 15, as shown in FIG. 44(c). Show. the

As described above, according to the present invention, the voltage-programmed reset drive shown in FIG. 43 is used in the first operation of turning on transistor 11d, turning off transistor 11e, and making current flow through transistor 11a synchronously with the HD synchronization signal; switching transistor 11a from The EL element 15 is disconnected and is between the drain (D) terminal and the gate (G) terminal (or between the source (S) terminal and the gate (G) terminal, or generally , a second operation of shorting between both ends including the gate (G) terminal of the driver transistor; and a third operation of programming the driver transistor 11a with a voltage after the above operation constitutes. the

In the above example, transistor 11d is turned on and off to control the transfer of current to EL element 15 from driver transistor element 11a (in the case of the structure shown in FIG. 1). To turn on and off the transistor 11d, the gate signal line 17b needs to be scanned, and for this, the shift register circuit 61 (gate driver circuit 12) is required. However, the shift register circuit 61 is large-sized, and employing the shift register circuit 61 for the gate signal line 17b makes it impossible to reduce the screen width. The system described with reference to FIG. 40 solves this problem. the

Incidentally, although the pixel structure for current programming illustrated in Fig. 1 and its ilk is mainly described here as an example, the present invention is not limited to these cases, and it is obvious that the present invention Also applicable to other structures for current programming described with reference to FIG. 38 and its ilk (current-reflecting pixel structure). Also, the technical concept of turning on and off elements as blocks is also applicable to the pixel structure for voltage programming in Fig. 41 and its ilk. According to the present invention, since this method makes current flow intermittently through the EL element 15, it can be used in combination with the method of applying a reverse bias voltage (described with reference to FIG. 50 and the like). Therefore, a reset drive can be used in conjunction with other examples according to the invention. the

Fig. 40 shows an example of a block drive system device. For easy understanding, it is assumed that the gate driver circuit 12 is directly formed on the substrate 71 or a silicon chip, and the gate driver IC 12 is mounted on the substrate 71 . The source driver circuit 14 and the source signal line 18 are omitted to avoid complicating the drawing. the

In FIG. 40 , the gate signal line 17 a is connected to the gate driver circuit 12 . On the other hand, the gate signal line 17b is connected to the lighting control line 401 . In FIG. 40 , four gate signal lines 17 b are connected to one lighting control line 401 . the

Incidentally, although four gate signal lines 17b are gathered into one block here, this is not restrictive, and it is obvious that more than four gate signal lines 17b may be gathered into one device. Usually, it is preferable to divide the screen 50 into 5 parts or more. More preferably, the screen 50 should be divided into 10 parts or more. Preferably, the screen should be divided into 20 parts or more. A small number of partitions will increase the flicker. Too many partitions will increase the number of lighting control lines 401 , making it difficult to arrange the lighting control lines 401 . the

Therefore, in the case of a QCIF display, which has 220 vertical scan lines, at least 220/5 = 44 or more lines should be gathered into one block. More preferably, 220/10=11 or more wires should be gathered into one device. However, by grouping the odd-numbered and even-numbered lines in different blocks, even at low frame rates, there is not much flickering, so two blocks are sufficient. the

In the example of FIG. 40 , by applying either the turn-on voltage (Vg1) or the turn-off voltage (Vgh) to the lighting control lines 401a, 401b, 401c, 401d, . . . are turned on and off on a block basis. the

Incidentally, in the example of FIG. 40 , the gate signal line 17 b does not intersect the lighting control line 401 . Therefore, there can be no defect that the gate signal line 17b becomes short-circuited with the lighting control line 401 . Also, since there is no capacitive coupling between the gate signal line 17b and the lighting control line 401, when the gate signal line 17b is viewed from the lighting control line 401, the addition of capacitance is very small. This makes it easy to drive the lighting control line 401 . the

The gate driver circuit 12 is connected to the gate signal line 17a. When a turn-on voltage is applied to the gate signal line 17a, appropriate pixel rows are selected, and the transistors 11b and 11c in the selected pixel rows are turned on. Then, the current (voltage) applied to the source signal line 18 is programmed to the capacitor 19 in these pixels. On the other hand, the gate signal line 17b is connected to the gate (G) terminal of the transistor 11d in the pixel. Therefore, when the turn-on voltage (Vg1) is applied to the lighting control line 401, a current path is formed between the driving transistor 11a and the EL element 15. When a cut-off voltage (Vgh) is applied, the anode terminal of the EL element 15 is opened. the

Preferably, the control timing of the on/off voltage added to the illumination control line 401 and the pixel row selection voltage (Vg1) output to the gate signal line 17a by the gate driver circuit 12 are related to a horizontal scan clock pulse ( 1H) Synchronization. However, this is not restrictive. the

The signal applied to the lighting control line 401 simply turns the current delivered to the EL element 15 on and off. They need not be synchronized with the image data output from the source driver circuit 14. This is because the signal applied to the illumination control line 401 attempts to control the current programmed into the capacitor 19 in the pixel 16. Therefore, they do not always need to be synchronized with the pixel row select signal. Even when they are synchronized, the clock pulses are not limited to 1-H signals but may be 1/2-H or 1/4-H signals. the

Even in the case of the current-reflective pixel structure shown in FIG. 38, if the gate signal line 17b is connected to the illumination control line 401, the transistor 11e can be turned on and off. Therefore, block driving can be realized. the

Incidentally, in FIG. 32, by connecting the gate signal line 17a to the lighting control line 401 and performing reset, it is possible to realize block driving. In other words, block driving according to the present invention is a driving method that simultaneously places a plurality of pixel rows in a non-illumination (black display) mode using one control line. the

In the above example, one selected pixel row is set (formed) per pixel row. The present invention is not limited to these, and one selection gate signal line may be provided (formed) for two or more pixel rows. the

Fig. 41 shows such an example. Incidentally, for ease of understanding, the pixel structure in Fig. 1 is mainly used. In FIG. 41, the gate signal line 17a for pixel row selection simultaneously selects three pixels (16R, 16G, and 16B). The reference character R is to indicate some information about red pixels, the reference character G is to indicate some information about green pixels, and the reference character B is to indicate some information about blue pixels. the

Therefore, when the gate signal line 17a is selected, the pixels 16R, 16G, and 16B are selected and ready to write data. Pixel 16R writes information into capacitor 19R via source signal line 18R, pixel 16G writes information into capacitor 19G via source signal line 18G, and pixel 16B writes information into capacitor 19B via source signal line 18B. the

The transistor 11d of the pixel 16R is connected to the gate signal line 17bR, the transistor 11d of the pixel 16G is connected to the gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to the gate signal line 17bB. Therefore, the EL element 15R of the pixel 16R, the EL element 15G of the pixel 16G, and the EL element 15B of the pixel 16B can be turned on and off individually. The lighting times and lighting periods of the EL element 15R, the EL element 15G, and the EL element 15B can be individually controlled by controlling the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB. the

To realize this operation, in the structure of FIG. 6, it is appropriate to form (arrange) four shift register circuits: a shift register circuit 61 for scanning the gate signal line 17a, a shift register circuit for scanning the gate signal line 17bR 61, the shift register circuit 61 for scanning the gate signal line 17bG, and the shift register circuit 61 for scanning the scanning signal line 17bB. the

Incidentally, although it has been stated that a current N times larger than the predetermined current flows through the source signal line 18 and a current N times larger than the predetermined current flows through the EL element 15 for a period of 1/N, in practice, this cannot be realized. Actually, the signal pulse applied to the gate signal line 17 penetrates into the capacitor 19, making it impossible to set a desired voltage value (current value) on the capacitor 19. Usually, a voltage value (current value) lower than desired is set on the capacitor 19 . For example, even if it is intended to set a 10 times larger current value, only about 5 times larger current value is set on the capacitor 19 . For example, even though N=10 is stipulated, actually N=5 times larger current flows through the EL element. Therefore, this method sets a larger current value of N times to pass a current proportional to or corresponding to N-times through the EL element 15. In other words, this driving method applies a pulse greater than the desired value to the EL element 15. value of current. the

This method performs current (voltage) programming by intermittently flowing a current greater than the desired value through driver transistor 11a (in the example of FIG. 1 ) in order to obtain the desired emission brightness of the EL element (i.e. 15, it will give a brightness greater than desired). the

Incidentally, a compensation circuit using a penetration capacitor 19 is connected to the source driver circuit 14, which will be described later. the

Preferably, in FIG. 1 and its ilk, N-channel transistors are used as the switching transistors 11b and 11c and so on. This will reduce the bleed voltage to capacitor 19 . Also, since the off Leakage of the capacitor 19 is reduced, the method can be applied to a frame rate of 10-Hz or lower. the

Depending on the pixel structure, if the penetration voltage tends to increase the current flowing through the EL element 15, the white peak voltage will increase, increasing perceived contrast in image display. This will provide a good image display. the

Conversely, it is also useful to use P-channel transistors as the switching transistors 11b and 11c in FIG. 1 to cause bleeding to obtain a correct black display. When P-channel transistor 11b is turned off, the voltage goes to a high potential (Vgh), shifting the terminal voltage of capacitor 19 slightly to the side of vdd. Therefore, the voltage at the gate (G) terminal of the transistor 11a rises, resulting in a denser black display, and the current for the first level display can be increased (some base current can be supplied up to level 1) , therefore, the shortage of write current can be alleviated during current programming. the

Another driving method according to the present invention will be described below with reference to the accompanying drawings. Fig. 174 is an explanatory diagram illustrating a display panel driven sequentially according to the present invention, the source driving display circuit 14 outputs their data to the connection terminal 761 by switching between R, G and B. Therefore, the source driver circuit 14 only needs 1/3 as many output terminals as in FIG. 48 . the

The signal output from the source driver circuit 14 to the connection terminal 761 is distributed to 18R, 18G, and 18B through the output conversion circuit 1741 . The output switching circuit 1741 is directly formed on the base plate 71 by polysilicon technology. The output switching circuit 1741 can be formed with a silicon chip and mounted on the base plate 71 by COG technology. Also, the output conversion circuit 1741 can be incorporated into the source driver circuit 14 as a sub-circuit of the source driver circuit 14 . the

The reversing switch 1742 is connected to the R terminal. The output signal from the source driver circuit 14 is applied to the source signal line 18R. If this changeover switch 1742 is connected to the G terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18G. If the changeover switch 1742 is connected to the B terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18B. the

Incidentally, in the structure of FIG. 175, when the reversing switch 1742 is connected to the R terminal, the G terminal and the B terminal of the reversing switch are open. Therefore, the current entering the source signal lines 18G and 18B is 0A, and thus, the pixels 16 connected to the source signal lines 18G and 18B provide black display. the

When the reversing switch 1742 is connected to the G terminal, the R and B terminals of the reversing switch are open. Therefore, the current flowing into the source signal lines 18R and 18B is 0 A, so that the pixels 16 connected to the source signal lines 18R and 18B provide black display. the

In the structure of FIG. 175, when the reversing switch 1742 is connected to the B terminal, the R terminal and the G terminal of the reversing switch are open. Therefore, the current flowing into the source signal lines 18R and 186 is 0A. Thus, the pixels 16 connected to the source signal lines 18R and 18G provide black display. the

Basically, if one frame consists of three fields, R image data is sequentially written to the pixels 16 in the screen 50 in the first field. In the second field, G image data is sequentially written to the pixels 16 in the screen 50 . In the third field, B picture data is sequentially written to the pixels 16 in the screen 50 . the

Therefore, R data→G data→B data→R data... are sequentially written in appropriate fields for continuous driving. the

How to perform N-fold pulse driving by turning on and off the switching transistor 11d as shown in FIG. 1 has been described with reference to FIGS. 5, 13, 16 and the like. Needless to say, this driving method can be combined with continuous driving. Of course, it is obvious that other methods according to the invention can be combined with continuous driving. the

In the above example, it has been described that when the image data is written in the R pixel 16, the black data is written in the G pixel and the B pixel, and when the image data is written in the G pixel 16 When in, black data is just written in R pixel and B pixel, and when image data is written in B pixel 16, then black data is just written in R pixel and G pixel. However, the present invention is not limited to these cases. the

For example, when image data is written in the R pixel 16, the G pixel and the B pixel can hold the image data rewritten in the previous field. This makes the screen 50 brighter. When image data is written into the G pixel 16, the R pixel and the B pixel can hold the image data of the previous field rewritten. When image data is written into the B pixel 16, the G pixel and the R pixel can hold the image data of the previous field rewritten. the

In order to hold image data in pixels other than the color pixels to be rewritten, the gate signal lines 17a can be individually controlled for R, G and B pixels. For example, as illustrated in FIG. 174, the gate signal line 17aR may be designated as a signal line for turning on and off the transistors 11b and 11c of the R pixel, and the gate signal line 17aG may be designated as a signal line for turning on and off the G pixel. As the signal line of the transistors 11b and 11c of the B pixel, the gate signal line 17bB can be designated as the signal line for turning on and off the transistors 11b and 11c of the B pixel. Alternatively, the gate signal line 17b may be designated as a signal line for commonly turning on and off the transistors 11d of the R, G, and B pixels. the

With the above structure, when the source driver circuit 14 outputs R image data, and the changeover switch 1742 is set to the R contact, the ON voltage can be applied to the gate signal line 17aR, and the OFF voltage can be applied to the gate signal line aG and aB. Therefore, R image data can be written to the R pixel 16, while the G pixel 16 and R pixel 16 can retain the image data of the previous field. the

When the source driver circuit 14 outputs G image data in the second field, and the changeover switch 1742 is set to the G contact, the ON voltage can be applied to the gate signal line 17aG, and the OFF voltage can be applied to the gate signal line aR and aB. Therefore, G image data can be written to the G pixel 16, while the R pixel 16 and B pixel 16 can retain the image data of the previous field. the

When the source driver circuit 14 outputs B image data in the third field, and the changeover switch 1742 is set to the B contact, the ON voltage can be applied to the gate signal line 17aB, and the OFF voltage can be applied to the gate signal line aR and aG. Therefore, B picture data can be written to the B pixel 16, while the R pixel 16 and the G pixel 16 can retain the picture data of the previous field. the

In the example shown in FIG. 174, the gate signal line 17a is arranged (formed) in such a manner that the transistors 11b of the R, G, and B pixels 16 can be turned on and off individually. However, the present invention is not limited to these cases. For example, a gate signal line 17a common to R, G, and B pixels 16 may be formed, that is, arranged as illustrated in FIG. 175 . the

Regarding the structure in Fig. 174 and its ilk, it has been described that when the R source signal line is selected by the changeover switch 1742, the G and B source signal lines are opened. However, the open state is an electrically floating state and is not desired. the

Figure 175 shows a structure in which measures are taken to eliminate this floating behavior. One terminal a of the reversing switch 1742 of the output switching circuit 1741 is connected to a voltage Vaa (voltage for black display). The terminal b is connected to the output terminal of the source driver circuit 14 . A reverse switch 1742 is connected to each of the R, G, and B pixels. the

In the state shown in Fig. 175, the reversing switch 1742R is connected to the Vaa terminal. Therefore, the voltage Vaa (voltage for black display) is applied to the source signal line 18R. Reversing switch 1742G is connected to terminal Vaa. Therefore, the voltage Vaa (voltage for black display) is applied to the source signal line 18G. The commutation switch 1742B is connected to the output terminal of the source driver circuit 14 . Therefore, the B picture signal is applied to the source signal line 18B. the

In the above state, the B pixel is rewritten, and the black display voltage is applied to the R pixel and the G pixel. When the reversing switch 1742 is controlled in the above mode, the image composed of pixels 16 is rewritten. Incidentally, the control of the gate signal line 17b is the same as in the above-described examples, and therefore, its detailed description is omitted. the

In the above example, R pixels 16 are rewritten in the first field, G pixels 16 are written in the second field, and B pixels 16 are written in the third field. That is, the color of the rewritten pixel changes every field. The present invention is not limited to these cases. The rewritten pixel color can be changed every horizontal scanning period (1H). For example, one possible driving method involves rewriting R pixels in the first H, G pixels in the second H, and B pixels in the third H, R pixels in the fourth H, etc. wait. Of course, the rewritten pixel color can be changed to one color every two horizontal scanning periods or every 1/3 field. the

Fig. 176 shows an example in which the rewritten pixel color is changed every -H. Incidentally, in Figs. 176 to 178, oblique hatching indicates that the pixel 16 either retains image data from the top field without being rewritten, or is displayed in black. Of course, the black display of pixels and the retention of image data from the top field may be alternately repeated. the

Needless to say, in the driving systems of Figs. 174 to 178, it is also possible to employ the N-fold pulse driving in Fig. 13 or the driving of M-lines at the same time. 174 to 178 show the writing of the pixel 16. FIG. Although the lighting control of the EL element 15 is not described, it is obvious that this example can be used in combination with the examples described earlier or later. the

One frame does not necessarily need to be composed of three fields, and may be composed of two fields or four or more fields. In one example illustrated in this article, a frame consists of two fields, the R and G pixels from the primary colors RGB are rewritten in the first field, and the B pixels are rewritten in the second field . In another example illustrated herein, a frame consists of four fields, R pixels from the primary colors RGB are rewritten in the first field, G pixels are rewritten in the second field, and B pixels are rewritten in the second field. The pixels are rewritten in the third and fourth fields. In these orders, if the luminous efficiencies of the EL elements 15 of R, G, and B are taken into consideration, the white balance can be obtained more efficiently. the

In the above example, R pixels 16 are rewritten in the first field, G pixels 16 are rewritten in the second field, and B pixels 16 are rewritten in the third field. That is, the rewritten pixel color is changed every field. the

According to the example shown in FIG. 176, in the first field, R pixels are rewritten in the first H, G pixels are rewritten in the second H, and B pixels are rewritten in the third H. written, the R pixel is rewritten in the fourth H, and so on. Of course, the color of the rewritten pixels can be changed every two or more horizontal scanning periods or every 1/3 field. the

According to the example shown in Fig. 176, in the first field, in the first H, R pixels are rewritten, in the second H, G pixels are written, and in the third H, B pixels is rewritten, and the R pixel is rewritten in the fourth H. In the second field, in the first H, the G pixel is rewritten, in the second H, the B pixel is rewritten, in the third H, the R pixel is rewritten, and in the In the fourth H, the G pixel is rewritten. In the third field, in the first H, the B pixels are rewritten, in the second H, the R pixels are rewritten, in the third H, the G pixels are rewritten, and in the B pixels in 4H are rewritten. the

Therefore, in each field, it is possible to prevent separation between R, G, and B colors by rewriting R, G, and B pixels arbitrarily or according to certain rules. Also, flickering is reduced. the

In Fig. 177, every H, the colors of a plurality of pixels 16 are written. In Fig. 176, in the first field, in the first H, the rewritten pixel 16 is an R pixel, in the second H, the rewritten pixel 16 is a G pixel, and in the third H In H, the rewritten pixel 16 is a B pixel, and in the fourth H, the rewritten pixel 16 is an R pixel. the

In Fig. 177, each H changes the position of a rewritten pixel of a different color. By assigning R, G and B pixels to different fields (needless to say, this can be done with some regularity), and rewriting them in sequence, it is possible not only to reduce flicker, but also to prevent flicker between R, G and B separation between

Incidentally, even in the example of Fig. 177, the R, G and B pixels should have the same lighting time or lighting intensity in each picture element, which is a group of R, G and B pixels. Rather, this is also done in the examples of Figures 175, 176, and their ilk, to avoid color irregularities. the

As shown in Figure 177, in order to rewrite pixels of different colors in each H (in Figure 177, in the first H of the first field, rewrite three colors - R, G and B ), in Figure 174, the source driver circuit 14 can be configured to output an image signal of any color (or the color determined by some rules) to the terminals, and the reversing switch 1742 can be made into any (or have a certain color) regularity) to the contact points of R, G and B. the

The panel in the example in Fig. 178 has W (white) pixels 16W in addition to the three primary colors RGB. By forming or arranging the pixels 16W, not only a high-brightness display is obtained, but also it is possible to correctly obtain the peak luminance of colors. the

Fig. 178(a) shows an example in which R, G, B, and W pixels 16 are formed in each pixel row. Fig. 178(b) shows an example in which R, G, B, and W pixels are arranged in different pixel rows in this order. the

Needless to say, the driving method in Fig. 178 can be combined with the driving methods in Figs. 176, 177 and so on. And, obviously, N-fold pulse driving, simultaneous M-row driving, etc. can be combined. Those skilled in the art can easily implement these matters based on this specification, and thus, descriptions thereof are omitted. the

Incidentally, for ease of understanding, it is assumed that the display screen according to the present invention has three primary colors RGB, but this is not restrictive. The display screen may have cyan, yellow, and magenta in addition to R, G, and B, or it may have any one of R, G, and B or any two of R, G, and B. kind. the

Also, although it has been stated that the continuous drive system handles R, G, and B in each field, it is obvious that the present invention is not limited to these cases. In addition, in the examples of Figs. 174 to 178, how image data is written into the pixels 16 is illustrated. They do not illustrate (although they are relevant, of course) the method of displaying an image by operating the transistor 11d and passing the current through the EL element 15, unlike in FIG. In the structure shown in FIG. 1, current is passed through the EL element 15 by controlling the transistor 11d. the

Also, the driving methods in FIGS. 176, 177, etc. can sequentially display RGB images (in the case of FIG. 1) by controlling the transistor 11d. For example, in FIG. 179(a), the R display area 53R, the G display area 53G, and the B display area 53B are scanned from the top to the bottom (or from the bottom to the top) of the screen during one frame (one field) period. . The remaining area becomes the non-display area 52 . That is, intermittent driving is performed. the

Fig. 179(b) shows an example in which a plurality of RGB display areas 53 are generated during one field (one frame) period. This driving method mimics the one shown in FIG. 16 . Therefore, it needs no explanation for it. In FIG. 179(b), by dividing the display area 53, it is possible to eliminate flickering even at a lower frame rate. the

Fig. 180(a) shows the case where the R, G, and B display areas 53 have different sizes (needless to say, the size of the display area 53 is proportional to its illumination period). In FIG. 180(a), the R display area 53R and the G display area 53G have the same size. The B display area 53B has a larger size than the G display area 53G. With an organic EL display, B often has lower lighting efficiency. By making the B display area 53B larger than the display areas 53 of the other colors, as shown in FIG. 180(a), it is possible to effectively obtain white balance. the

Fig. 180(b) shows an example in which there are a plurality of B display periods 53B (53B1 and 53B2) during one field (one frame) period. While Fig. 180(a) shows a method of changing the size of a B display area 53B so that the white balance is adjusted correctly, Fig. 180(b) shows a method of displaying a plurality of display areas 53B with the same surface area to obtain Correct white balance method. the

The driving system according to the present invention is not limited to Fig. 180(a), or Fig. 180(b). It is intended to create R, G and B display areas 53 and create intermittent displays to correct blurry moving pictures and insufficient writing to pixels 16. With the driving method shown in FIG. 16, independent display areas 53 for R, G and B are not generated. R, G and B are simultaneously displayed (it should be noted that the W display area 53 appears). Incidentally, it is obvious that Fig. 180(a) and Fig. 180(b) can be combined. For example, it is possible to combine the driving method of display areas 53 of different sizes for R, G, and B in FIG. 180(a) with that for R, G, and B in FIG. 180(b). The driving methods of the display area 53 are combined. the

Incidentally, according to the present invention, the driving method in FIGS. 179 and 180 is not limited to the driving method in FIGS. 174 to 178. Needless to say, with a structure in which the current pairs R, G, and B flowing through the EL element 15 (EL element 15R, EL element 15G, and EL element 15B) are controlled separately, as shown in FIG. and the drive method in 180. It is possible to turn on and off the R pixel 16R by applying an on/off voltage to the gate signal line 17bR. By applying an on/off voltage to the gate signal line 17bG, it is possible to turn on and off the G pixel 16G. By applying an on/off voltage to the gate signal line 17bB, it is possible to turn on and off the B pixel 16B. the

The above driving can be realized by forming or arranging the gate driver circuit 12bR for controlling the gate signal line 17bR, the gate driver circuit 12bG for controlling the gate signal line 17bG, and the gate driver circuit 12bB for controlling the gate signal line 17bB, as shown in FIG. 181 Illustrated. The driving methods in FIGS. 179 and 180 can be realized by driving the gate drivers 12bR, 12bG, and 12bB in FIG. 181 by the method described in FIG. 6 or its equivalent. Of course, it is obvious that the driving method in FIG. 16 and the like can be realized by adopting the structure of the display screen in FIG. 181. the

Also, with the structures shown in FIGS. 174 to 177, it is possible to control the EL element 15R without using the gate signal line 17bR, the gate signal line 17bG for controlling the EL element 15G, and the gate signal line 17bB for controlling the EL element 15B. , the drive method in Figures 179 and 180 can be realized by using the common gate signal line 17b for R, G and B pixels, as long as the black image data can be written differently than its image data can be rewritten into the image Pixel 16 of pixel 16 will do. the

As described with reference to FIGS. 15, 18, 21, etc., a turn-on voltage (Vg1) and a turn-off voltage (Vgh) are applied to the gate signal line 17b (EL side selection signal line) every horizontal scanning period (1H). However, in the case of a constant current, the light irradiation amount of the EL element 15 is proportional to the duration of the current. Therefore, this duration is not limited by 1H. the

Figure 194 shows 1/4 duty ratio drive. The turn-on voltage is applied to the gate signal line 17b (EL side selection signal line) 1H every 4H, and the position to which the turn-on voltage is applied is scanned in synchronization with the horizontal synchronizing signal (HD). Therefore, the unit length of the conduction period is 1H. the

However, the present invention is not limited to these cases. The duration of the conduction period may be less than 1H (1/2H in FIG. 197), as shown in FIG. 197, or may be equal to or less than 1H. In conclusion, the unit length of the conduction period is not limited to 1H, but a unit length different from 1H can be easily produced. The OEV2 circuit formed or provided in the output stage of the gate driver circuit 12b (circuit that controls the gate signal line 17b) can be used for that purpose. the

To introduce the concept of output enable (0EV), the following provisions are made. By performing OEV control, on and off voltages (voltage Vg1 and voltage Vgh) are applied to the pixel 16 from the gate signal lines 17a and 17b within one horizontal scanning period (1H). the

For ease of understanding, it is assumed that in the display screen according to the present invention, the pixel row to be current-programmed is selected by the gate signal line 17a (in the case of FIG. 1). The output from the gate driver circuit 12a controlling the gate signal line 17a is called a WR side selection control line. It is also assumed that the EL element 15 is selected by the gate signal line 17b (in the case of FIG. 1). The output from the gate driver circuit 12b which controls the gate signal line 17b is referred to as an EL side selection signal line. the

The gate driver circuit 12 is fed a start pulse, which is shifted as it sequentially holds data in the shift register. Whether to output the ON voltage (Vg1) or the OFF voltage (Vgh) to the WR side selection signal line is determined based on the held data in the shift register of the gate driver circuit 12a. An OEV1 circuit (not shown) that forcibly cuts off the output is formed or provided in the output stage of the gate driver circuit 12a. When the OEV1 circuit is at low level, the WR side selection signal, which is the output of the gate driver circuit 12a, is output to the gate signal line 17a as it is. The above relationship is logically illustrated in Fig. 224(a) (OR circuit). Incidentally, the turn-on voltage is set at logic level L(0), and the turn-off voltage is set at logic voltage H(1). the

That is, when the driver circuit 12a outputs an off voltage, the off voltage is applied to the gate signal line 17a. When the gate driver circuit 12 outputs the turn-on voltage (logic low), it is ORed with the output of the OEV1 circuit through the OR circuit, and the result is output to the gate signal line 17a. That is, when the OEV1 circuit is high level, the off voltage (Vgh) is output to the gate driver signal line 17a (see an exemplary timing chart in FIG. 224 ). the

Whether to output the ON voltage (Vg1) or the OFF voltage (Vgh) to the gate signal line 17b (E1 side selection signal line) is determined based on the held data in the shift register of the gate driver circuit 12b. An OEV2 circuit (not shown) that forcibly cuts off the output is formed or provided in the output stage of the gate driver circuit 12b. When the OEV2 circuit is at low level, the output of the gate driver circuit 12b is output to the gate signal line 17b as it is. The above relationship is logically illustrated in Figure 116(a). Incidentally, the on-voltage is set at logic level L(0), and the off-voltage is set at logic voltage H(1). the

That is, when the gate driver circuit 12b outputs an off voltage (the EL side selection signal is the off voltage), the off voltage is applied to the signal line 17b. When the gate driver circuit 12 outputs the turn-on voltage (logic low), it is ORed with the circuit of OEV2 through the OR circuit, and the result is output to the gate signal line 17b. That is, when the input signal is at a high level, the OEV2 circuit outputs an off voltage (Vgj) to the gate driver signal line 17b. Therefore, even if the EL side selection signal from the OEV2 circuit is the ON voltage, the OFF voltage is forcibly output to the gate signal line 17b. Incidentally, if the input to the OEV2 circuit is low level, the EL side selection signal is directly output to the gate signal line 17b (see an exemplary timing diagram in FIG. 176). the

Incidentally, the screen brightness is adjusted under the control of OEV2. There are allowable limits to changes in screen brightness. Figure 223 illustrates the functional relationship between allowable variation (%) such as screen brightness (nt). As can be seen from Figure 223, relatively dark images have little allowable variation. Therefore, in adjusting the brightness of the screen 50 under the control of the OEV2 or through the duty factor control, the brightness of the screen 50 should be taken into consideration. When the screen is dark, the allowed variation should be shorter than when it is bright. the

In FIG. 195, the conduction period of the gate signal line 17b (EL side selection signal line) has no unit length of 1H. An ON voltage slightly shorter than 1H is applied to the gate signal line 17b (EL side selection signal line) in the odd-numbered pixel row. An ON voltage for a very short period is applied to the gate signal line 17b (EL side selection signal line) in the even-numbered pixel row. Added to the duration T1 of the on-voltage of the gate signal line 17b (EL side selection signal line) in the odd-numbered pixel row plus the gate signal line 17b (EL side selection signal line) in the even-numbered pixel row. ) duration T2 is designed to be 1H. Figure 195 shows the state of the first field. the

In the second field following the first field, an ON voltage slightly shorter than 1H is applied to the gate signal line 17b (EL side selection signal line) in the even-numbered pixel row. An ON voltage for a very short period is applied to the gate signal line 17b (EL side selection signal line) in the odd-numbered pixel row. Add to the duration T1 of the on-voltage of the grid signal line 17b (EL side selection signal line) in the even-numbered pixel row plus the voltage applied to the gate signal line 17b (EL side selection signal line) in the odd-numbered pixel row. ) The duration T2 of the turn-on voltage is designed to be 1H. the

The sum of the durations of the turn-on voltages applied to the gate signal lines 17b in a plurality of pixel rows can be designed to be constant. Alternatively, the lighting time of the EL elements 15 in each pixel row in each field can be designed to be constant. the

FIG. 196 shows a case where the conduction period of the signal line 17b (EL side selection signal line) is 1.5H. At point A, the rise and fall of the potential of the gate signal line 17b are designed to overlap. The gate signal line 17b (EL side selection signal line) and the source signal line 18 are coupled. Therefore, any change in the waveform of the gate signal line 17 b (EL side selection signal line) permeates to the source signal line 18 . Consequently, any potential variation in the source signal line 18 degrades the accuracy of current (voltage) programming, causing irregularities in the characteristics of the driver transistor 11a to appear in the display. the

Referring to FIG. 196, at point A, the voltage applied to the gate signal line 17B (EL side selection signal line) (1) changes from the turn-on voltage (Vg1) to the turn-off voltage (Vgh). The voltage applied to the gate signal line 17B (EL side selection signal line) (2) changes from the off voltage to the on voltage (Vg1). Therefore, at point A, the signal waveform of the gate signal line 17B (EL side selection signal line) (1) and the signal waveform of the gate signal line 17B (EL side selection signal line) (2) cancel each other out. As a result, even if the gate signal line 17b (EL side selection signal line) and the source signal line 18 are coupled, a change in the gate signal line 17b (EL side selection signal line) does not penetrate to the source signal line 18 . This improves the accuracy of current (voltage) programming, resulting in a uniform image display. the

Incidentally, in the example of FIG. 196, the conduction period is 1.5H. However, the present invention is not limited to these cases. Needless to say, the duration of on-voltage application may be 1H or less, as illustrated in FIG. 198 . the

By adjusting the duration of the ON voltage application to the gate signal line 17B (EL side selection signal line), it is possible to linearly adjust the brightness of the display screen 50 . This is easily done through the control of the OEV2 circuit. Referring to FIG. 199, for example, the display luminance in FIG. 199(b) is lower than that in FIG. 199(a). Also, the display luminance in FIG. 199(c) is lower than that in FIG. 199(b). the

As shown in diagram 200, in a period of 1H, multiple sets of on-voltage and off-voltage can be applied. Figure 200(a) shows an example in which 6 groups are added. Figure 200(b) shows an example in which 3 groups are added. Figure 200(c) shows an example in which 1 group is added. In the graph 200, the display brightness in the graph 200(b) is lower than that in the graph 200(a). In graph 200(c) is lower than in graph 200(b). Therefore, display brightness can be easily adjusted (controlled) by controlling the number of conduction periods. the

One of the problems with the N-fold pulse driving according to the present invention is that a current N times larger than in the conventional case is applied to the EL element 15, although instantaneously. A large current may reduce the operating time of the EL element. To solve this problem, it may be useful to apply a reverse bias voltage Vm to the EL. the

The application of reverse bias means the application of reverse current, therefore, the injected electrons and positive holes are guided to negative and positive holes, respectively. This makes it possible to cancel the formation of space charges in the organic layer and reduce electrochemical degradation, thus extending the lifetime. the

FIG. 45 is a graph showing the reverse bias voltage Vm versus changes in the terminal voltage of the EL element 15. FIG. When a rated current is applied to the EL element 15, a terminal voltage is formed. In FIG. 45, the current density of the current flowing through the EL element 15 is 100 A per square meter. The trends in Figure 45 indicate little difference from those observed when the current density was 50 to 100A. Therefore, it is sufficient to presume that this method can be applied to a wide range of current densities. the

The vertical axis represents the ratio of the terminal voltage of the EL element after 2500 hours to the initial terminal voltage. For example, if the terminal voltages are 8V and 10V respectively, when a current with a current density of 100A per square meter is applied at time 0 (zero), and after 2500 hours, the terminal voltage ratio is 10/8=1.25. the

The horizontal axis represents the ratio of the reverse bias voltage Vm and its application duration H to the rated terminal voltage V0 in a period. For example, if the reverse bias voltage Vm is applied for 1/2 (half) cycle at 60 Hz (60 Hz has no special meaning), then t1 = 0.5. And, when a current having a current density of 100A per square meter is applied at time 0 (zero), if the terminal voltage (nominal terminal voltage) is 8V, and if the reverse bias is 8V, then |reverse bias × t1| /(rated terminal voltage×t2)=|-8(V)×0.5|/(8(V)×0.5)=1.0. the

In FIG. 45, when |reverse bias voltage×t1|/(rated terminal voltage×t2) is 1.0 or more (no change to the initial rated terminal voltage), the terminal voltage ratio stops changing. Therefore, the application of the reverse bias voltage Vm works well. However, when |reverse bias voltage×t1|/(rated terminal voltage×t2) is 1.75 or larger, the ratio of terminal voltage tends to increase. Therefore, the reverse bias voltage Vm and the application duration rate t1 (or t2 or the ratio between t1 and t2) should be determined in such a manner that |reverse bias voltage × t1|/(rated terminal voltage × t2) is equal to or greater than 1.0. Preferably, the reverse bias voltage Vm and the application duration rate t1 should be determined in such a manner that |reverse bias voltage×tl|/(rated terminal voltage×t2) is equal to or less than 1.75. the

However, for bias driving, reverse bias Vm and rated current should be alternately applied. In order to make the average luminance per unit time of samples A and B equal by application of reverse bias voltage, as shown in FIG. 46, it is necessary to instantaneously pass a larger current than when no reverse bias voltage is applied. Therefore, the application of the reverse bias voltage Vm (sample A in FIG. 46 ) also increases the terminal voltage of the EL element 15 . the

However, in FIG. 45, even with a driving method involving application of a reverse bias voltage, this rated terminal voltage V0 should satisfy the average luminance (ie, illuminate the EL element 15). (According to the examples cited herein, such a terminal voltage can be obtained when a current with a current density of 200A/ ^M2 is applied. However, since the duty ratio is 1/2, the average brightness over one cycle is equal to Brightness at a current density of 200A/ ^M2 ).

Generally, in the case of video display, the current applied to (flowing through) each EL element 15 is approximately the white peak current (at the rated terminal voltage, or at a current density of 100 A/ 0.2 of the current flowing under the current of M ² ).

So, for the example in Figure 45, the values on the horizontal axis should be multiplied by 0.2. Therefore, the reverse bias voltage Vm and the application duration rate t1 (or t2 or the ratio between t1 and t2) should be determined in such a way that |reverse bias voltage × t1|/(rated terminal voltage × t2) is equal to 0.2 or larger. Preferably, the reverse bias voltage Vm and the application duration rate t1 should be determined in such a manner that the reverse bias voltage Vm and the application duration application rate t1 should be determined in such a manner that |reverse bias voltage×t1| /(rated terminal voltage×t2) is equal to 0.35 (=1.75×0.2) or less. the

That is, on the horizontal axis in Figure 45 (|reverse bias voltage × t1 |/(nominal terminal voltage × t2), the value of 1.0 should be changed to 0.2. Therefore, displaying video on the display (probably this is normal case, and probably will not often display a white screen), the reverse bias voltage Vm should be applied for a predetermined time t1 in such a manner that |reverse bias voltage×t1|/(rated terminal voltage×t2) is equal to 0.2 or greater. Even if the value of |reverse bias voltage×t1|/(rated terminal voltage×t2) increases, the ratio of terminal voltage will not increase greatly, as shown in Figure 45. Therefore, by considering the white screen display, the upper limit should be set To make |reverse bias voltage×t1|/(rated terminal voltage×t2) equal to 1.75 or less. 

The reverse bias drive according to the present invention will be described with reference to the accompanying drawings. In the pixel structure for reverse bias driving, an N-channel transistor 11g is used, as shown in FIG. 47 . Of course, this could also be a P-channel transistor. the

In FIG. 47, when the voltage applied to the gate potential control line 473 is set higher than the voltage applied to the reverse bias voltage line 471, the transistor 11g (N) is turned on, and the reverse bias voltage Vm is applied to the EL element 15 the anode. the

In the pixel structure in Fig. 47 and its ilk, the gate potential control line 473 can always be operated at a fixed potential. For example, in FIG. 47, when the voltage VK is 0V, the potential of the gate potential control line 473 is set to 0V or higher (preferably, 2V or higher). Incidentally, this potential is represented by Vsh. In this state, when the potential of the reverse bias line 471 is set to the reverse bias voltage Vm (0 V or lower, preferably -5 V or lower than VK), the transistor 11g (N) is turned on, and the reverse bias voltage is supplied to the anode of the EL element 15. When the voltage of the reverse bias line 471 is set higher than the voltage applied to the gate potential control line 473 (that is, the gate (G) terminal voltage of the transistor 11g), the transistor 11g is kept off, and the reverse bias voltage Vm is not to the anode of the EL element 15. Of course, it is obvious that in this state, the reverse bias line 471 can be put into a high-impedance state (such as an open state). the

Also, the gate driver circuit 12c may be formed separately, that is, provided to control the reverse bias line 471, as illustrated in FIG. 48 . The gate driver circuit 12c operates by sequentially shifting as in the case of the gate driver circuit 12a, and the application position of the reverse bias voltage is shifted in synchronization with the shifting operation. the

The driving method described above makes it possible to apply the reverse bias voltage Vm to the EL element 15 by only changing the potential of the reverse bias line 471 by setting the gate (G) terminal of the transistor 11g at a fixed potential. This makes it easy to control the application of the reverse bias voltage Vm. the

When current does not flow through the EL element 15, a reverse bias voltage Vm is applied. This is done by turning on transistor 11g when transistor 11d is off. That is, the reverse of the on/off logic of the transistor 11d is applied to the gate potential control line 473 . For example, in FIG. 47, the gate (G) terminals of the transistors 11d and 11g may be connected to the gate signal line 17b. Since the transistor 11d is a P-channel transistor and the transistor 11g is an N-channel transistor, they are turned on and off in the opposite manner. the

Fig. 49 is a timing diagram of reverse bias driving. In this figure, subscripts such as (1) and (2) indicate the number of pixel rows. It is assumed for ease of explanation that (1) indicates the first pixel row and (2) indicates the second pixel row, but not restrictively. It can also be considered that (1) indicates the N-th pixel row, and (2) side indicates the (N+1)-th pixel row. Except for a few special cases, the above applies to other examples. Although the examples in FIG. 49 and the like are described by referring to the pixel structure in FIG. 1 and the like, this is not restrictive. They are also applicable to, for example, the pixel structures in Figs. 41, 38 and the like. the

When the turn-on voltage (Vg1) is applied to the gate signal line 17a(1) in the first pixel row, the turn-off voltage (Vgh) is applied to the gate signal line 17b(1) in the first pixel row. Therefore, the transistor 11d is turned off, and current does not flow through the EL element 15 . the

Voltage Vs1 (which turns on transistor 11g) is applied to reverse bias line 471(1). Therefore, the transistor 11d is turned on, and the reverse bias voltage is applied to the EL element 15. After the off voltage (Vgh) is applied to the gate signal line 17b, a reverse bias voltage is applied for a predetermined period (1/200 of 1H or longer; or 0.5 μsec). This reverse bias voltage is turned off for a predetermined period (1/200 of 1H or longer; or 0.5 μsec) before the turn-on voltage (Vg1) is applied to the gate signal line 17b. This is done to prevent transistors 11d and 11g from being turned on at the same time. the

In the next 1H (horizontal scanning period), an off voltage (Vgh) is applied to the gate signal line 17a, and the pixel row of the second row is selected. That is, the turn-on voltage is applied to the gate signal line 17b(2). On the other hand, the turn-on voltage (Vg1) is applied to the gate signal line 17b, the transistor 11d is turned on, and the current from the transistor 11a flows through the EL element 15, causing the EL element to emit light. And, applying a cut-off voltage (Vsh) to the reverse bias line 471(1) prevents the reverse bias from being applied to the EL elements 15 in the first row of pixels (1). The voltage Vs1 (reverse bias voltage) is applied to the reverse bias line 471(2) in the second row of pixels. the

When the above operations are repeated sequentially, the image is rewritten on the entire screen. In the above example, reverse bias is applied while the pixel is being programmed. However, the circuit configuration in Fig. 48 is not limited to these cases. Obviously, the reverse bias can be continuously applied to multiple rows of pixels. It is also apparent that reverse bias driving can be combined with block driving (see FIG. 40), N-fold pulse driving, reset driving, or dummy pixel driving. the

The reverse bias is applied not only during graphic display but also for a predetermined period of time after the EL display device is turned off. the

Although the above example has been described with reference to the pixel structure in FIG. 1, it is obvious that the use of reverse bias voltage is also applicable to the pixel structure in FIGS. A pixel structure for current programming is produced. the

Fig. 50 shows the pixel structure of current reflection. The transistor 11d is turned on for 1H (horizontal scanning period, ie, one row of pixels) or more before a given pixel is selected. Preferably, it is turned on at least before 3H: if so, transistor 11d turns on 3H before the selection of the pixel, shorting the gate (G) terminal of transistor 11a, such as the drain (D) terminal, so that transistor 11a is turned off, therefore, the current stops flowing through the transistor 11b, and the EL element 15 is turned off. the

When the EL element 15 is not illuminated, the transistor 11g is turned on, and a reverse bias is applied to the E1 element 15, and when the transistor 11d is turned on, a reverse bias is applied. Therefore, the transistor 11d and the transistor 11g are turned on simultaneously in a logical relationship. the

The voltage Vsg is continuously applied to the gate (G) terminal of the transistor 11g, and when the reverse bias voltage is sufficiently lower than the voltage Vsg applied to the reverse bias line 471, the transistor 11g is turned on. the

Next, when a horizontal scanning period occurs, during which a video signal is applied (written into) the pixel, a turn-on voltage is applied to the gate signal line 17a1, and the transistor 11c is turned on. Therefore, the video signal voltage output from the source driver circuit 14 to the source signal line 18 is applied to the capacitor 19 (the transistor 11d is kept on). the

When the transistor 11d is turned on, the pixel enters a black display mode. The longer the conduction period of the transistor 11d in one field (one frame) period, the larger the proportion of the black display period. Therefore, regardless of the black period, it is necessary to increase the luminance during the display period to obtain a desired average luminance over one field (one frame), ie, during the display period, it is necessary to increase the current flowing through the EL element 15 . This operation is N-fold pulse driving according to the present invention. Thus, an operational characteristic of the present invention is achieved by a combination of N-fold pulse driving and driving involving the establishment of a black display by turning on transistor 11d. Also, a structural (method) characteristic of the present invention includes applying a reverse bias voltage to the EL element 15 when the EL element 15 does not emit light. the

A predetermined current (programmed current (at the voltage held in the capacitor 19)) flows through the EL element 15 again during N-fold pulse driving even after a black display is established once during one field (one frame). However, with the structure in FIG. 50, once the transistor 11d is turned on, it is impossible for a predetermined current (programmed current) to flow through the E1 element 15 since the capacitor 19 is discharged (ie, its charge is reduced). However, this structural feature facilitates circuit operation. the

Incidentally, although the above examples employ pixel structures for current programming, the present invention is not limited to these cases, and is applicable to other current-based pixel structures such as those shown in FIGS. 38 and 50. structure. Also applicable to pixel structures for voltage programming such as those shown in FIGS. 51, 54 and 62. the

Figure 51 typically shows one of the simplest pixels for voltage programming. The transistor 11 b functions as a selection switching element, and the transistor 11 a functions as a driver transistor that applies current to the EL element 15 . This structure includes a transistor (switching element) 11g that applies a reverse bias voltage to the anode of the EL element 15 . the

With the pixel structure in FIG. 51, the current to flow through the EL element 15 is applied to the source signal line 18. Then, when the transistor 11b is selected, it is applied to the gate (D) terminal of the transistor 11a. the

To describe the structure in FIG. 51, basic operations will first be described with reference to FIG. 52. The pixel structure in Fig. 51 is of the cancel voltage compensation type, and operates in four stages: preset operation, reset operation, programming operation, and light emitting operation. the

The preset operation is performed after the horizontal synchronizing signal (HD) is supplied. An ON voltage is applied to the gate signal line 17b to turn on the transistor 11g, and an ON voltage is also applied to the signal line 17a to turn on the transistor 11c. At this time, the voltage Vdd is applied to the source signal line 18 . Therefore, the voltage Vdd is applied to one terminal a of the capacitor 19b. In this state, the driver transistor 11 a is turned on, and a small current flows through the EL element 15 . This current makes the voltage at the drain (D) terminal of the driver transistor 11a larger in absolute value than at least the voltage at the operating point of the driver transistor 11a. the

Next, a reset operation is performed, an off voltage is applied to the signal line 17b, and the transistor 11e is turned off. On the other hand, the transistor 11b is turned on for a period of T1 by applying the turn-on voltage to the gate signal line 17c, and the period of T1 corresponds to the period of reset. The turn-on voltage is continuously applied to the signal line 17a for a period of 1H. Preferably, the period T1 is between 20% and 90% of 1H (both percentages inclusive) or between 20 μsec and 160 μsec (both periods inclusive). Preferably, the capacitance ratio Ca/Cb between the capacitor 19b (Cb) and the capacitor 19a (Ca) is between 1/6 and 2/1 (both ratios inclusive). the

During the reset period, the transistor 11b is turned on, and the gate (G) and drain (D) terminals of the drive transistor 11a are shorted. Therefore, the voltages at the gate (G) and drain (D) terminals of transistor 11a are equalized, putting transistor 11a in compensation mode (reset mode: a mode in which no current flows). In this reset mode, the voltage at the gate (G) terminal of the transistor 11a is close to the start-up voltage at which current starts to flow. The gate voltage for maintaining the reset mode is held at one terminal b of the capacitor 19 . Therefore, the capacitor holds the compensation voltage (reset voltage). the

In the next programming mode, an off voltage is applied to the gate signal line 17c, turning off the transistor 11b. On the other hand, the DATA voltage is applied to the source signal line 18 for a period of Td. Therefore, the sum of the DATA voltage and the compensation voltage (reset voltage) is applied to the gate (G) terminal of the driving transistor 11a. This causes driver transistor 11a to pass a programming current. the

After the programmed period, an off voltage is applied to the gate signal line 17a, turning off the transistor 11c and disconnecting the driver transistor 11a from the source signal line 18. In addition, an off voltage is also applied to the gate signal line 17c, turning off the transistor 11b, which remains off for a period of 1F. On the other hand, on-voltage and off-voltage are periodically applied to the gate signal line 17b as required. Therefore, if combined with N-fold pulse driving in Figs. 13, 15, etc., or with interlaced driving, this method can achieve a more favorable image display. the

With the driving system in 52, in the reset mode, the capacitor 19 holds the voltage (compensation voltage, reset voltage) of the start-up current of the transistor 11a. Therefore, when the reset voltage is being applied to the gate (G) terminal of the driver transistor 11a, the darkest black display is established. However, the coupling between the source signal line 18 and the pixel 16, the crossover voltage to the capacitor 19, or the punch through of the transistor can cause excessive brightness (contrast is lowered) resulting in a whitish screen. Therefore, the driving method described with reference to Fig. 53 cannot obtain a high-contrast display. the

To apply the reverse bias voltage Vm to the EL element 15, the transistor 11a must be turned off. To turn off the transistor 11a, the Vdd terminal and the gate (G) terminal of the transistor 11a must be short-circuited. This structure will be described later with reference to FIG. 53 . the

Alternatively, the Vdd voltage or the voltage that turns off transistor 11a is applied to source signal line 18, turns on transistor 11b, and this voltage is applied to the gate (G) terminal of transistor 11a, this voltage turns off transistor 11a (or makes it barely pass current (almost off: transistor 11a in high impedance state)). Next, the transistor 11q is turned on, and the reverse bias voltage is applied to the element 15. the

Next, reset driving in the pixel structure in Fig. 51 will be described. Fig. 53 shows an example. As shown in FIG. 53, the gate signal line 17a connected to the gate (G) terminal of the transistor 11c in the pixel 16a is connected to the gate (G) terminal of the reset transistor 11b of the pixel 16b in the next stage. Similarly, the gate signal line 17a connected to the gate (G) terminal of the transistor 11c in the pixel 16b is also connected to the gate (G) terminal of the reset transistor 11b in the pixel 16c in the next stage. the

Therefore, when the turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c in the pixel 16a, the pixel 16a enters the voltage programming mode, and the reset transistor 11b of the pixel 16b in the next stage is turned on, And the driver transistor 11a of the pixel 16b is reset. Similarly, when the turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c in the pixel 16b, the pixel 16b enters the current programming mode, and the reset transistor 11b of the pixel 16c is turned on in the next stage , and the driver transistor 11a of the pixel 16c is reset. Therefore, reset driving by the previous-stage gate control system can be easily realized. Also, the number of leads from the gate signal line of each pixel can be reduced. the

A more detailed description will be provided. Assuming that a voltage is applied to the gate signal line 17 as shown in Figure 53(a), specifically, the turn-on voltage is applied to the gate signal line 17a of the pixel 16a, and the turn-off voltage is applied to the gate signal line 17a of another pixel 16. Signal line 17a. Also, an OFF voltage is applied to the gate signal lines 17b of the pixels 16a and 16b, and an ON voltage is applied to the gate signal lines 17b of the pixels 16c and 16d. the

In this state, pixel 16a is in voltage-programmed mode and is non-luminous, pixel 16b is in reset mode and non-luminous, pixel 16c is current-programmed in progress and is non-luminous, and pixel 16d is electrical programming in progress and is illuminated. the

After 1H, the data in the shift register 61 circuit of the control gate driver circuit 12 is shifted by 1 bit to enter the state shown in FIG. 53(b). In Figure 53(b), the pixel 16a is in the current programming mode and is emitting light, the pixel 16b is in the current programming mode and is not emitting light, and the pixel 16c is in the reset mode and is not emitting light , while the pixel 16d is being programmed, it is luminous. the

Therefore, it can be seen that the voltage applied to the gate signal line 17a of each pixel resets the driver transistor 11a of the pixel in the next stage, and voltage programming is performed sequentially in the next horizontal scanning period. the

The pixel structure used for voltage programming in FIG. 43 can also realize front-stage gate control. FIG. 54 shows an example of a method of connecting a front-stage gate control system for the pixel structure in FIG. 43. FIG. the

In FIG. 54, the gate signal line 17a connected to the gate (G) terminal of the transistor 11b in the pixel 16a is connected to the gate (G) terminal of the reset transistor 11e of the pixel 16b in the next stage. Similarly. The gate signal line 17a connected to the gate (G) terminal of the transistor 11b in the pixel 16b is connected to the gate (G) terminal of the reset transistor 11e of the pixel 16c in the next stage. the

Therefore, when the turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b in the pixel 16a, the pixel 16a enters the voltage programming mode, and the reset transistor 11e of the pixel 16b in the next stage is turned on, And the driver transistor 11a of the pixel 16b is reset. Similarly, when the turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b in the pixel 16b, the pixel 16b enters the current programming mode, and the reset transistor 11e of the pixel 16c in the next stage is turned on , and the driver transistor 11a of the pixel 16c is reset. Therefore, reset driving by the previous-stage gate control system can be easily realized. the

A more detailed description will be provided. Suppose, voltage is added to gate signal line 17, as shown in Fig. 55 (a), concretely, turn-on voltage is added to gate signal line 17a of pixel 16a, and cut-off voltage is added to the gate signal of other pixel 16 Line 17a. Assume that all reverse biased transistors 11g are off. the

In this state, pixel 16a is in voltage programming mode, pixel 16b is in reset mode, pixel 16c is current programming, and pixel 16d is current programming. the

After 1H, the data in the shift register 61 circuit of the control gate driver circuit 12 is shifted by 1 bit to enter the state shown in FIG. 55( b ). In FIG. 55(b), pixel 16a is in current programming, pixel 16b is in current programming mode, pixel 16c is in reset mode, and pixel 16d is in programming mode. the

Therefore, it can be seen that the voltage applied to the gate signal line 17a of each pixel to the previous stage resets the driver transistor 11a of the pixel in the next stage to sequentially perform voltage programming in the next horizontal scanning period. the

For a completely black display in current drive, the driver transistor 11 of the pixel is programmed with an O current. That is, the source driver circuit 14 passes no current. When no current is delivered, the parasitic capacitance caused in the source signal line 18 cannot be discharged, and the potential of the source signal line 18 cannot be changed. As a result, the gate potential of the driver transistor also remains unchanged, and the potential in the previous frame (field) (1F) remains accumulated in the capacitor 19 . For example, if the previous frame contained a white display, the white display is preserved even if the current frame contains an all black display. the

To solve this problem, according to the present invention, before the current to be programmed is output to the source-gate signal line 8, a black level voltage is written into the source signal line 18 at the beginning of a horizontal scanning period (1H). For example, if the image data is composed of levels 0 to 7 close to the black level, the black level voltage is only written in a certain period of time at the beginning of a horizontal scanning period to reduce the load of current programming and Compensate for insufficient writes. Incidentally, all black display corresponds to gradation 0, and white display corresponds to gradation 63 (in the case of display of 64), and precharge will be described later. the

The current driving source driver IC (circuit) 14 according to the present invention will be described below. The source driver IC according to the present invention is used to realize the driving method and the driving circuit according to the present invention described earlier. It is used in combination with the driving direction, the driving circuit and the display device according to the present invention. Incidentally, although the source driver circuit will be described as an IC chip, this is not restrictive, but the source driver circuit may be formed on a display panel using low temperature polysilicon technology, or the like. the

First, an example of a conventional current-driven source driver circuit is shown in FIG. 72, which provides the concept required to describe a current-driven source driver IC (source driver circuit) according to the present invention. the

In Fig. 72, reference numeral 721 denotes a D/A inverter. The D/A inverter 721 is fed with an -n-bit data signal and outputs an analog signal according to the input data. The analog signal enters operational amplifier 722, which feeds into N-channel transistor 631a. The current flowing through N-channel transistor 631 a flows to resistor 691 . The terminal voltage of the register R provides a negative input to the operational amplifier 722 . The voltage at the negative terminal is equal to the voltage at the positive terminal of operational amplifier 722 . Therefore, the output voltage of the D/A inverter 721 is equal to the terminal voltage of the register 691 . the

If the resistance value of the resistor 691 is 1MΩ, and the output of the D/A inverter 721 is 1(v), then a current of 1(v)/1MΩ=1(μA) flows through the resistor 691, forming a constant current circuit. Therefore, the analog output of the D/A inverter 721 varies with the value of the data signal, and a predetermined current according to the analog output flows through the resistor 691 to provide the programmed current Iw. the

However, the D/A inverter circuit 721 has a large circuit size. The same is true for operational amplifier 722 . Formation of the D/A inverter 721 and the operational amplifier 722 in a single output circuit results in a huge source driver IC 14, which is practically impossible to fabricate. the

The present invention has been made in consideration of the above features. The source driver 14 according to the present invention has a circuit structure and a layout structure which reduces the size of the current output circuit and minimizes the output current variation between the current output terminals.

FIG. 63 is a block diagram showing a source driver IC (circuit) 14 for current driving according to the present invention. Fig. 63 shows a multi-stage current mirror circuit including three-stage current sources (631, 632, 633). the

In FIG. 63, the current value of the current source 631 in the first stage is copied by the circuit reflection circuit to N current sources 632 in the second stage (where N is an arbitrary integer). The current value of the current source 632 in the second stage is copied to the M current sources 633 in the third stage by the current mirror circuit (where M is any integer). Therefore, this structure causes the current value of the first-stage current source 631 to be copied to N×M third-stage current sources 633 . the

For example, when the source signal line 18 is driven by one driver IC 14, there are 176 outputs (since the total number of 176 outputs is required for the signal lines R, G, and B). It is assumed here that N=16 and M=11. Therefore, 16*11=176, and these 176 outputs can be covered. Thus, by using a multiple of 8 or 16 for N or M, it becomes easier to arrange and design the current source of the driver IC. the

The current-driven source driver IC (circuit) 14 using a multi-stage current mirror circuit according to the present invention can absorb variations in transistor characteristics because it has two-stage current sources 632 in between, instead of using a current mirror circuit to separate the first The current value of the primary current source 631 is directly copied to N×M third-stage current sources 633. the

In particular, the present invention is characterized by disposing the first-stage current mirror circuit (current source 631) and the second-stage current mirror circuit (current source 632) close to each other. If the first-stage current source 631 is connected with the third-stage current source 633 (that is, in the case of a two-stage current mirror circuit), the third-stage current source 633 connected to the first-stage current source is very large in number , making it impossible to place the first-stage current source 631 and the third-stage current source 633 very close to each other. the

According to the source drive circuit 14 of the present invention, the current value of the first-stage current reflection circuit (current source 631) is copied to the second-stage current reflection circuit (current source 632), and the second-stage current reflection circuit (current source 632) The current value of the current is copied to the third-stage current mirror circuit (current source 633). With this structure, the number of second-stage current mirror circuits connected to the first-stage current mirror circuit (current source 631) is very small. Therefore, the first stage current circuit (current source 631) and the second stage current mirror circuit (current source 632) can be placed very close to each other. the

If the transistors making up the current mirror circuit are placed close to each other, the variation in the transistors is naturally reduced. The same is true for changes in current value. The number of third-stage current mirror circuits (current sources 633 ) connected to the second-stage current mirror circuits (current sources 632 ) is also reduced. Therefore, the second stage current mirror circuit (current source 632) and the third stage current mirror circuit (current source 633) can be placed very close to each other. the

That is, the transistors in the current receiving part in the first-stage current mirror circuit (current source 631), the second-stage current mirror circuit (current source 632) and the third-stage current mirror circuit (current source 633) can be integrated placed very close to each other. In this way, the transistors forming the current mirror circuit can be placed very close to each other, reducing variations in the transistors and greatly reducing variations in the current signal from the output. For simplicity, a multi-stage current mirror circuit consisting of three stages has been referenced in the above example. Needless to say, the larger the number of stages, the smaller the current variation in the source driver IC 14 that currently drives the panel. Therefore, the number of stages of the current mirror circuit is not limited to three stages, and may be more than three stages. the

In the present invention, the terms current source 631, 632, 633" and current mirror circuit are used interchangeably. That is, the current source is a basic constituent of the present invention, and the current source embodies it with a current mirror circuit. Therefore , the current source is not limited to the current mirror circuit, it can be a current circuit formed by the combination of the operational amplifier 722, the transistor 631 and the register R, as shown in Figure 72. 

FIG. 64 is a configuration diagram of a more specific source driver IC (circuit) 14 . It illustrates the third current source 633 of the section. This is the output section connected to a source signal line 18 . It is composed of a plurality of current mirror circuits (current source 634 (1 unit)) of the same size as the current mirror structure in the final stage. Their number is bit-weighted according to the data size of the image data.

Incidentally, the transistors constituting the source driver IC (circuit) 14 according to the present invention are not limited to MOS type, but may be of bipolar type. In addition, they are not limited to silicon semiconductors, but can also be gallium arsenide semiconductors. Furthermore, they can also be germanium semiconductors. Or alternatively, form them directly on the substrate using low temperature polysilicon technology, other polysilicon technology, or amorphous silicon technology. the

Figure 48 illustrates an example of the present invention processing 6-bit digital input. 6 bits are the sixth power of 2, so 64 levels of display are provided. This source driver IC 14, when mounted on an array board, provides 64 gradations each of red (R), green (G) and blue (B), meaning 64 x 64 x 64 = approximately 260,000 colors. the

Sixty-four (64) levels need 1 DO-bit unit transistor 634, 2 D1 bit unit transistors 634, 4 D2-bit unit transistors 634, 8 D3-bit unit transistors 634, 16 D4 - bit cell transistor 634, 32 D5-bit cell transistors 634, 63 cell transistors 634 in total. Therefore, the present invention employs as many cell transistors 643 as the number of layers (64 layers in this example) minus one to generate one output. Incidentally, even if 1 unit transistor is divided into multiple subunit transistors, this simply means that 1 unit transistor is divided into several subunit transistors, which is different from the fact that the present invention employs as many unit transistors as the number of layers minus 1 Make no difference. the

In Figure 64. D0 represents the LSB input, while D5 represents the MSB input. When the D0 input terminal is high level (positive logic), the switch 641a is turned on (the switch 481a is an on/off device, and can be formed by a single transistor, or can be an analog circuit composed of a P-ditch transistor and an N-ditch transistor. switch). The current then flows to a current source (single cell) 634 that constitutes a current mirror. This current flows through the internal wiring 643 in IC14. Since the internal wiring 643 is connected to the source signal line 18 through the terminal electrode in the IC 14, the current flowing through the internal wiring 643 supplies the programming current for the pixel 16. the

For example, when the D1 input terminal is at a high level (positive logic), the switch 641b is turned on. The current then flows to the two current sources (single cell) 634 that make up the current mirror. Current flows through internal wiring 643 in IC14. Since the internal wiring 643 is connected to the source signal line 18 through the terminal electrode of the IC 14, the current flowing through the internal wiring 643 supplies the programming current for the pixel 16. the

This also applies to the other switches 641 . When the D2 input terminal is high level (positive logic), the switch 641c is turned on. The current then flows to four current sources (single cell) 634 that make up the current mirror. When the D5 input terminal is at a high level (positive logic), the switch 641f is turned on. The current then flows to 32 (three + two) current sources (single cell) 634 that make up the current mirror. the

Thus, according to the external data (D0 to D5), the current flows to the corresponding current source (single cell). That is, the current flows to 0 to 63 current sources (single unit) according to the data. the

Incidentally, for ease of explanation, it is assumed that there are 63 current sources for the 6-bit structure, but this is not restrictive. In the case of the 8-bit structure, 255 unit transistors 634 can be formed (arranged). For a 4-bit structure, 15 single-element boosters 634 can be formed (set up). The transistor 634 constituting a unit current source has a channel width W and a channel length L. The use of equal transistors makes it possible to build output stages with small variations. the

Additionally, not all current sources 634 need to pass the same current. For example, individual current sources 634 may be weighted. For example, the current output circuit can be composed of a single-unit current source 634 , a double-sized current source 634 , a quadruple-sized current source 634 , and the like. However, if the current sources 643 are weighted, the weighted current sources may not provide the correct ratio, resulting in variations. Therefore, when even using weighting, it is preferable to construct each current source from each transistor corresponding to a single cell current source. the

The cell transistor 634 should be equal to or larger than a certain size. The smaller the transistor size, the greater the variation in the output current. The size of transistor 634 is given by the channel length L times the channel width W. For example, if W=3 μm and L=4 μm, the size of the unit transistor 634 constituting the unit current source is W×L=12 μm ² . It is believed that the grain boundary conditions of the silicon wafers are related to the fact that smaller transistor sizes lead to larger variations. Therefore, when each transistor is formed across a plurality of grain boundaries, the variation in the output current of the transistor is small.

The graph relationship of the variation in transistor size and output current is shown in FIG. 117 . The horizontal axis of the graph in Fig. 117 represents the transistor size (µm ² ). The vertical axis represents the change in output current in percentage relation. Here, the variation (%) of the current is determined using a combination of 63 unit current sources (unit transistors) 634 formed on one wafer. Thus, although the horizontal axis of the graph represents the size of transistors constituting one current source, since there are actually 63 transistors connected in parallel, the total area of transistors is 63 times larger. However, the present invention is based on the size of the cell transistor 634 . Therefore, FIG. 117 shows that the change in output current is 0.5% in 63 unit transistors 634 each having an area of 30 µm ² .

In the case of 64 layers, 100/64=1.5%. Therefore, the variation in output current must be within 1.5%. From Fig. 117, it can be seen that in order to vary within 1.5%, the cell transistor size must be equal to or larger than 2 µm ² (in the case of 64 levels, 63 2 µm ² cell transistors are operating). On the other hand, since larger transistors increase the size of the IC chip, there is a limit to the transistor size and a limit to the width of each output. In this regard, the upper limit to the size of the cell transistor 634 is 300 μm ² . Therefore, in the case of 64 levels, the size of the cell transistor 634 must be from 2 μm ² to 300 μm ² inclusive.

In the case of 128 levels, 100/128=1%. Therefore, the variation in output current must be within 1%. From Fig. 117, it can be seen that the cell transistor size must be equal to or greater than 8 µm ² in order to vary within 1%. Therefore, in the case of 128 levels, the size of the cell transistor 634 must be from 8 μm ² to 300 μm ² inclusive.

In general, if the number of layers is K and the size of the cell transistor 634 is St (μm ² ), the following relationship should be satisfied:

$40\&le;K/\sqrt{S\left(t\right)}$ and St≤300

Even better, the following relations should be satisfied:

$120\&le;K/\sqrt{S\left(t\right)}$ and St≤300

In the example above, 64 levels are represented by 63 transistors. When 127 unit transistors 634 represent 64 levels, the size of the unit transistor 634 is the total size of the two unit transistors 634 . For example, in the case where 64 levels are represented by 127 unit transistors 634, if the size of the unit transistor 484 is 10 μm ² , the size of the unit transistor 484 given in FIG. 117 is 10×2=20. Similarly, in the case where 64 levels are represented by 255 unit transistors 634 , if the size of the unit transistor 484 is 10 μm ² , the size of the unit transistor given in FIG. 117 is 10×4=40.

Not only the size but also the shape of the cell transistor 634 should be considered. This is to reduce the kink effect, which is a phenomenon. In this phenomenon, when the voltage between the source (S) and drain (D) of the unit transistor 634 changes with the gate voltage of the unit transistor 634 kept constant, the current flowing through the unit transistor 634 The current has changed. In the absence of the kink effect (ideal state), even if the voltage applied between the source (S) and drain (D) of the cell transistor 484 is changed, the current flowing through the cell transistor 634 does not change. the

The kink effect occurs when the source signal line 18 changes due to a change in the vt of the driver transistor 11a shown in FIG. 1 and its ilk. The driver circuit 14 passes the programming current through the source signal line 18 so that the programming current will flow through the driver transistor 11a of the pixel. The programming current causes a change in the voltage at the gate terminal of driver transistor 11a. Therefore, a programming current flows through the driver transistor 11a. It can be seen from FIG. 3 that the voltage at the gate terminal of the driver transistor 11a is equal to the potential of the source signal line 18 when the selected pixel 16 is in the programming mode. the

Therefore, the potential of the source signal line 18 changes due to a change in Vt of the driver transistor 11 a in the pixel 16 . The potential of the source signal line 18 is equal to the source-drain voltage of the unit transistor 634 of the driver circuit 14 . That is, a change in Vt of the driver transistor 11a in the pixel 16 causes a change in the source-drain voltage applied to the unit transistor 634. Then, the source-drain voltage causes a change in the output voltage of the cell transistor 634 due to kink. the

Fig. 118 is a graph representing this phenomenon. The vertical axis represents the output current of the unit transistor 634 obtained when a predetermined voltage is applied to the gate terminal. The horizontal axis represents the voltage between the source (S) and drain (D). L in L/W represents the channel length of the unit transistor 634, and w represents the width of the channel. And, L, w represent the size of the unit transistor 634 outputting current for one layer. Therefore, to output current for one layer using a plurality of subunit transistors, w and L should be calculated by replacing the subunit transistors with one equivalent unit transistor 634 . Basically, this calculation should be done by considering the size of this transistor and the output current. the

When L/w is equal to 5/3, even if the source-drain voltage increases, the output current remains almost unchanged. However, when L/w is equal to 1/1, the output current increases roughly proportional to the source-drain voltage. Therefore, the larger the L/W, the better. the

Fig. 172 is a graph showing deviation (variation) from a target value in L/W of a cell transistor. When the L/W ratio of the cell transistor is equal to less than 2, the deviation from the target value is large (the slope of the straight line is large). However, as L/W increases, the deviation from the target value tends to decrease. When the L/w of the cell transistor is equal to more than 2, the deviation from the target value is small. And, when L/w=2 or more, the deviation from the target value is 0.5% or less. Therefore, this value can be used in the source driver circuit 14 to indicate the accuracy of the transistor. the

In view of the above, it is preferable that L/W of the cell transistor is 2 or more. the

However, a large L/W means a long L and thus a large transistor size. the

Therefore, more preferably, L/W is 40 or less. the

In addition, L/w is also related to the number of layers. If the number of layers is small, there is no problem even if there is a change in the output current of the cell transistor 634 due to the kink effect because there is a large difference between layers. However, in the case of a display screen with a large number of layers, since there are small differences between the layers, even a small change in the cell transistor 634 output current will reduce the number of layers due to the kink effect. the

In view of the above situation, the driver circuit 14 according to the present invention is formed to satisfy the following relational expression:

Here K is the number of levels, L is the channel length of the unit transistor 634, and W is the channel width of the unit transistor. This relationship is illustrated graphically in FIG. 119 . The area above the straight line in Fig. 119 is relevant to the present invention. This corresponds to the third-stage current reflection section explained in FIG. 63 . Therefore, the first current source 631 and the second current source 632 are separately formed and arranged densely (close to each other). In addition, the transistors 633a in the current mirror circuits constituting the second current source 632 and the third current source are also densely arranged (close to each other). the

The variation in the cell transistor 634 output current is also related to the voltage resistance of the source driver IC 14 . The voltage resistance of the source driver IC usually means the supply voltage of the IC. For example, a voltage resistance of 5V means the use of a power supply voltage of 5B at the standard voltage. Incidentally, IC voltage resistance translates into maximum operating voltage. Manufacturers of semiconductor ICs have standardized piezoresistive processes, such as a 5V piezoresistive process and a 10V piezoresistive process. the

It is believed that the film properties and film thickness of the gate insulating film of the cell transistor 634 are related to the fact that the IC voltage resistance affects changes in the cell transistor 634 output current. The transistor 634 produced in a process with high IC voltage resistance has a thick gate insulating film. This is intended to avoid dielectric breakdown even at high applied voltages. A thick gate insulating film makes its control difficult and increases variations in its film properties. This situation increases the variation in the transistor. Also, transistors produced in high voltage resistance processes have low mobility. At low mobility, even slight variations in the electrons injected into the gate of a transistor can cause a change in characteristics. This situation increases the variation in the transistors. To reduce variations in the cell transistor 634, it is preferable to adopt an IC process with low IC voltage resistance. the

Figure 170 illustrates the relationship between IC voltage resistance and cell transistor output variation. The rate of change on the vertical axis is based on the change of the cell transistor 634 produced in the 1.8V volts-resistive process, and its change is taken as 1. Graph 170 shows output variations of the unit transistor 634 produced in various IC piezoresistive processes and having a form factor of L/W=12/6 (µm). A plurality of unit transistors 634 were produced in each IC piezoresistive process, and changes in their output currents were measured. The voltage resistance process is composed of 1.8-V voltage resistance, 2.5-V voltage resistance, 3.3-V voltage resistance, 5-V voltage resistance, 8-V voltage resistance, and 10-V voltage resistance, 15-V voltage resistance process . However, for ease of explanation, the variation in transistors formed in different piezoresistive processes is plotted on the graph and connected by straight lines. the

It can be seen from graph 170 that the rate of change (change in cell transistor 634 output current) gradually increases upwards until the IC voltage resistance of 9V. However, when the IC voltage resistance exceeds 10V, the slope of the rate of change becomes larger with respect to the IC voltage resistance. the

In Fig. 170, the allowable limit of the rate of change is 3 for 64- to 256-level displays. The rate of change varies with the area, L/W, etc. of the cell transistor 634 . However, the rate of change with respect to IC voltage resistance is hardly affected by the shape of the cell transistor 634 . The rate of change tends to increase when the IC voltage resistance is above 9 to 10V. the

On the other hand, the potential of the output terminal 64 varies with the programming current in the driver transistor 11a of the pixel 16 in FIG. When the driver transistor 11a of the pixel 16 passes a white screen (maximum white display) current, its gate terminal voltage is represented by Vw. When the driver transistor 11a of the pixel 16 passes a black and white screen (full black display) current, its gate terminal voltage is represented by Vb. The absolute value of Vw-Vb must be 2V or more. When the voltage Vw is applied to the output terminal 761, the internal channel voltage of the cell transistor 634 must be 0.5V or higher. the

Therefore, a voltage of 0.5V to ((Vw-Vb)+0.5)V is applied to terminal 761 (when current programming, the gate terminal voltage of driver transistor 11a of pixel 16 is applied to the output connected to source signal line 18 terminal 761). Since Vw-Vb is equal to 2V, a voltage up to 2V+0.5V=2.5V is applied to the output terminal 761 . Therefore, even if the output voltage (current) of the source driver IC 14 is based on rail-to-rail output, the IC voltage resistance must be 2.5V. The magnitude required by terminal 741 is 2.5V or more. the

It is therefore preferred that the voltage resistance process for the source driver IC 14 be in the range of 2.5V to 10V (both values inclusive). More preferably, the voltage resistance process used for the source driver IC 14 is in the range of 3V to 9V (both values inclusive). the

Incidentally, it has been stated that a voltage resistance process in the range of 2.5V to 10V is used for the source driver IC12. This voltage resistance also applies to instances where the source driver circuit 14 is formed directly on the array board 71 (eg, low temperature polysilicon technology). The operating voltage resistance of the source driver circuit 14 formed directly on the array board 71 can be high, and in some cases exceeds 15V. In such an example, the supply voltage for the driver circuit 14 may be replaced by the IC voltage resistance illustrated in FIG. 170 . Also, the source driver IC 14 may have an IC voltage resistance replaced by a power supply voltage. the

The area of cell transistor 634 correlates to the change in its output current. FIG. 171 is a diagram obtained by changing the transistor width of the unit transistor 634 while keeping the area of the unit transistor 634 constant. In FIG. 170 , the variation of the cell transistor 634 having a channel width of 2 μm is taken as 1. It can be seen from FIG. 171 that the rate of change gradually increases when the W of the cell transistor is from 2 μm to 9 or 10 μm. When W is 10 μm or more, the increase in the rate of change tends to be large. Also, when the channel width w=2 μm or less, the rate of change tends to increase. the

In Fig. 171, the allowable limit of the rate of change is 3 for 64- to 256-gradation display. The rate of change varies with the area of the cell transistor 634 . However, the rate of change of resistance with respect to IC voltage is hardly affected by the area of the unit transistor 634 . the

Therefore, it is preferable that the channel width W of the cell transistor 634 is from 2 μm to 10 μm inclusive. More preferably, the channel width W of the cell transistor 634 is from 2 µm to 9 µm (both dimensions included). the

As illustrated in FIG. 68, the current flowing through the second stage current mirror circuit 632b is copied to the transistor 633a constituting the third stage current mirror circuit. If the current reflection rate is 1, the current flows through the transistor 633b. This current is replicated to the cell transistor 634 in the final stage. the

DO supplied by a unit transistor 634 provides the value of the current flowing through the last-stage current source unit transistor 633 . D1 provided by two unit transistors 634 provides a current value twice as large as that of the last-stage current source. D2 provided by four unit transistors 634 provides a current value four times greater than that of the final current source; and D5 provided by 32 unit transistors 484 provides a current value 32 times greater than that of the final current source. the

Thus, the programming current Iw is output to the source signal line through the switch controlled by the 6-bit image data composed of D0, D1, D2, . . . and D5. Therefore, according to the excitation and de-excitation of the 6[bit image data composed of DO, D1, D2, ... and D5, the last stage current source 633 is 1 times, 2 times, 4 times, ... and/or A current as large as 32 times is added and output to the output line. That is, according to excitation and de-excitation of 6-bit image data composed of DO, D1, D2, ... and D5, a current as large as 0 to 63 times that of the final-stage current source 633 is drawn from the output line output (the current is derived from the source signal line 18). the

Actually, as illustrated in FIG. 146, in the source driver IC 14, the reference currents (IaR, IaG, and IaB) for R, G, and B, respectively, can be adjusted by variable resistors 651 (651R, 651G, and 651B). adjust. By adjusting this reference current Ia, the white balance can be easily adjusted. the

The use of integer multiples of the current value of the last-stage current source 633 makes it possible to control the current value more accurately (reduce output variation between terminals) than conventional methods using ratio distribution based on W/L. the

However, this structure is applicable only when the driver transistor 11a of the pixel 16 is a P-channel transistor, and the current source (single-cell transistor) 634 of the source driver IC 14 is an N-channel transistor. In other cases (for example, when the driver transistor 11a of the pixel 16 is an N-channel transistor), the present invention can adopt a structure in which the programming current Iw is the discharge current. the

Now, a reference current generator circuit will be described in detail. The current output mode that is used for the source driver circuit (IC) 14 of the present invention adopts a reference current, and outputs the programmed current Iw (the source driver of the liquid crystal display adopts the voltage output mode, which is combined with the unit current proportional to the reference current) using a stepped voltage as the signal). Figure 144 shows an example. In Figures 67, 68, 76, etc., a variable resistor 651 is used to generate the reference current. In FIG. 144, the variable resistor 651 in FIG. 68 is replaced by a transistor 631a, and the current flowing through a transistor 1444 forming a current mirror circuit together with the transistor 631a is controlled by an operational amplifier 722 or the like. Transistor 1444 and transistor 631a form a current mirror circuit. If the current reflection factor is 1, the current through transistor 1444 provides the reference current. the

The output voltage of operational amplifier 722 is fed to N-channel transistor 1443 , and the current flowing through this N-channel transistor 1443 flows through external resistor 691 . Incidentally, the resistor 691a is a fixed chip resistor. Basically, resistor 691 is sufficient. The resistor 691b is a resistive element, such as a positive temperature coefficient thermistor, that is, a thermistor, and its value changes with temperature. The resistor 691b is used to compensate the temperature characteristic of the EL element 15. The resistor 691a is inserted, ie set, in parallel or in series with the resistor 691b according to (to compensate for) the temperature characteristic of the EL element 15 . Incidentally, for ease of explanation, the resistor 691a and the resistor 691b will be treated as one resistor 691 below. the

Resistor 691 with an accuracy of 1% or better is readily available. Resistor 691 can be built into source driver IC14 using diffused resistor technology or polysilicon patterning. A chip resistor 691 is installed at the input terminal of 761a. In the case of an EL display panel, in particular, the temperature characteristic of the EL element 15 is different among R, G and B. Therefore, three external resistors 691 are required for R, G and B. the

The voltage across resistor 691 provides a negative input to operational amplifier 722 , and the voltage at the negative terminal has the same magnitude as the voltage at the positive terminal of operational amplifier 722 . Therefore, if the positive input voltage of the operational amplifier 722 is V1 , the current obtained by dividing this voltage by the resistance value 691 flows through the transistor 1444 . This current acts as a reference current. If the resistance value of the resistor 691 is 100K Ω, and the positive terminal input voltage of the operational amplifier 722 is V1=1(V), then a reference current of 10 μA (=1(V)/100K Ω) flows through the resistor 691. Preferably, the reference current is set between 2 μA and 30 μA (both current values are included). More preferably, it is set between 5 μA and 20 μA (both current values included). The small reference current flowing through the start transistor 63 reduces the accuracy of the cell current source 634 . The reference current is too large, increasing the current mirror factor of the switch (in this case, in a downward direction) within the IC, increasing the variation in the current mirror circuit, thus again reducing the accuracy of the cell current source 634 . the

The above structure makes it possible (by size and variation) to form a very accurate reference current, as long as the positive input of op amp 722 and resistor 691 are sufficiently accurate. When fabricating resistor 691 into source driver circuit (IC) 14, it is recommended to trim the incorporated resistor to increase accuracy. the

The reference voltage Vref received from the reference voltage circuit 1441 is applied to the positive terminal of the operational amplifier 722 . As for ICs for the reference voltage circuit 1441 for outputting the reference voltage, various types are available from Maxim and others. Alternatively, the reference voltage Vref may be generated within the source driver circuit 14 (internally generated reference voltage Vref). Preferably, the range of the reference voltage is between 2 (V) and the anode voltage Vdd (V) (including these two voltage values). the

The reference voltage is fed in via connection 761a. Basically, the voltage Vref can be fed into the positive terminal of the operational amplifier 722 . Since the luminous efficiency of the EL element 15 varies among R, G and B, an electronic regulator circuit 561 is provided between the connection terminal 761a and the positive terminal. In other words, the electronic adjuster circuit 561 is intended to adjust the current flowing through the respective EL elements 15 for R, G, and B so as to achieve white balance. Of course, what can be adjusted through the resistor 691 does not need to be adjusted through the electronic regulator circuit 561 . For example, a variable resistor may be used as the resistor 691 . One of the uses of the electronic adjuster circuit 561 is to readjust the white balance when the degradation rate of the EL element 15 varies between R, G and B. The EL element 15 for B is particularly prone to degradation. Therefore, as the EL display screen is used for many years, the EL element 15 for B becomes darker, turning the screen yellowish. If so, use the electronic adjustment circuit for B 561 to adjust the white balance. Of course, brightness correction or white balance correction of the EL element 15 can be performed by connecting the electronic regulator circuit 561 to the temperature sensor 781 (see FIG. 78 and its description). the

The electronic regulator circuit 561 can be built into the IC (circuit) 14 . Alternatively, it is formed directly on the array plate 71 using low temperature polysilicon technology. A plurality of unit resistors (R1, R2, R3, R4, . . . Rn) formed by patterning polysilicon are connected in series. Analog switches (S1, S2, S2, . . . Sn+1) are provided between the unit resistors, the reference voltage Vref is divided, and the resulting voltage is output. the

In FIG. 148 and its ilk, transistor 1443 is illustrated as a bipolar transistor, but this is not limiting. It may be a FET (Field Effect Transistor) or a MOS (Metal-Oxide-Semiconductor) transistor. Needless to say, transistor 1443 need not be built into IC 14, but it can be placed outside this IC. Also, not only the transistor 1443 but also a power generator and other generator circuits can be incorporated into the driver circuit 12. the

In order to obtain a full color display on an EL display, it is necessary to provide a reference current for each of R, G and B. White balance can be adjusted by controlling the ratio of the RGB reference currents. Not only in the case of the present invention but also in the case of current driving, the value of the current passed by the unit current source 634 is determined based on the reference current. Therefore, the current passed by the cell current source 634 can be determined by determining the magnitude of the reference current. Therefore, the white balance in each gradation can be obtained by setting the reference currents for each of R, G and B. The above works because the source driver circuit 14 produces a current output in steps (is current driven). Therefore, the question is how to set the magnitude of the reference current for each of R, G and B. the

The light emission efficiency of the EL element is determined by, or largely depends on, the thickness of the film vapor deposited or applied to the EL element. The thickness of the film is almost constant within each segment. By stepwise controlling the film thickness of the EL element 15, it is possible to determine the relationship between the current flowing through the EL element 15 and the light emission efficiency. That is, the current value for white balance is fixed for each segment. the

For example, if the currents flowing through the EL element 15 for each of R, G, and B are Ir(A), Ig(A), and Ib(A), respectively, the ratio of the reference current for white balance can be obtained, which can be obtained step by step based on knowing. So, for example, white balance can be obtained when Ir:Ig:Ib=1:2:4. With duty cycle driving etc. according to the invention, once the white balance is obtained, it is added to all levels. This is accomplished by optimal synergy between a driving method according to the invention and a source driver circuit according to the invention. the

With the structure shown in FIG. 148, the value of resistor 691 can be varied on a segment-by-segment basis in the circuit generating the RGB reference currents to achieve white balance. However, resistor 691 must be varied on a segment-by-segment basis. the

In FIG. 148, the electronic regulator circuit 561 is controlled from outside the source driver current (IC) 14, and the value of the reference current Ia is changed by operating the switch Sx in the electronic regulator circuit 561. In FIG. 149 , the settings of the electronic regulator circuit 561 may be stored in the flash memory 1491 . The values in the flash memory 1491 can be set independently of each other by the RGB electronic adjuster circuit 561 . The values in the flash memory 1491 are then set, for example, for each segment of the EL display panel, and are read out to set the switches Sx in the electronic regulator circuit 561 when the source driver IC 14 is powered on. the

FIG. 150 is a block diagram in which the electronic regulator circuit 561 in FIG. 149 is constructed as a resistor array circuit 1501. In FIG. 150, reference character Rr designates an external resistor. Of course, Rr can be built into the source driver circuit (IC) 14 . The resistor array 1503 is built into the source driver circuit (IC) 14 . The resistors (R1 to Rn) constituting the resistor array are connected in series, and the resistors (R1 to Rn) are connected through short-circuited metal lines. Cutting the wire at point a or b etc. shown in FIG. 150 changes the current Ir flowing through the resistor array 1503. A change in current Ir causes a change in the voltage applied to the positive terminal of operational amplifier 722, resulting in a change in reference current Ia. The target reference current is generated by monitoring the current through resistor Rr to determine the point on the wire that will be cut. the

To trim resistor array 1503 , laser light 1502 may be emitted from laser device 1501 . the

Incidentally, it has been described with reference to FIG. 148 that the RGB reference current is changed by changing the value of the RGB resistor 691. Also, as has been described with reference to FIG. 149, the RGB reference currents are changed by operating the switches Sx in the electronic adjuster 561 using the values stored in the flash memory 1491. Also, as described with reference to FIG. 150 , the RGb reference current is changed by trimming the resistance value of the resistor array 1503 . However, the present invention is not limited to those cases. the

For example, it goes without saying that the reference current can be changed by changing the RGB reference voltages (VrefR, VrefG, VrefB) in FIGS. 149 and 150 . The RGB reference voltage Vref can be easily generated by an operational amplifier circuit or the like. Also, in FIGS. 148, 149, 150, etc., by using the resistor Rr as a regulator, as a result, it is possible to change the reference voltage applied to the source driver circuit (IC) 14. the

It has been stated that 0 to 63 times the current of the final-stage current source 633 is output, but this is true only when the current reflection factor of the final-stage current source 633 is 1. When the current reflection factor is 2, 0 to 126 times the current of the final stage current source 633 is output, and when the current reflection factor is 0.5, 0 to 31.5 times the current of the final stage current source 633 is output. the

Therefore, the present invention enables the value of the output current to be easily changed by changing the current reflection factor of the last-stage current source 633 or the current sources (631, 632, etc.) of the previous stage. Preferably, the current response factors for R, G, and B are individually changed (different). The current factor of any current source, for example, only for R can be changed (different) from the other color (from the current source circuit for the other color). In particular, EL displays have different luminous efficiencies for different colors (R, G, and B; or cyan, yellow, and magenta). Therefore, by changing the current reflection factor between different colors, it is possible to improve the current reflection factor. the

The current reflection factors of the current sources may be changed (different) from other colors (from current source circuits to other colors) in a non-fixed manner. It can be mutable. The current reflection factor can be made variable by providing a plurality of transistors constituting the current reflection circuit in the current source, and changing the number of transistors through which current flows according to an external signal. This structure makes it possible to obtain the best white balance through adjustment when observing the emission conditions of various colors of the manufactured EL display screen. the

In particular, the present invention is configured to connect current sources (current mirror circuits) in multiple stages. Therefore, changing the current factor between the first stage current source 631 and the second stage current source 632, it is possible to easily change the output current of many outputs using a few connection means (current mirror circuit and its ilk). Needless to say, this makes it easier to change a large number of connections using a smaller number of connection means (current mirror circuits and their like) than by changing the current reflection factor between the second-stage current source 632 and the third-stage current source 633. The output current of the output becomes possible. the

Incidentally, changing the current reflection factor means changing (adjusting) the amplification factor of the current. Therefore, it is not limited to current mirror circuits. For example, it can be realized by an operational amplifier circuit for current output or a D/A circuit for current output. The above items also apply to other examples of the present invention. the

Fig. 65 shows an exemplary circuit diagram of 176 (N x M = 176) outputs of a three-stage current mirror circuit. In FIG. 65, the current source 631 composed of the first-stage current reflection circuit is called the first-generation current source, and the current source 632 composed of the second-stage current reflection circuit is called the second-generation current source. The current source 633 composed of three-stage current mirror circuits is called a third-generation current source. The use of the third-stage current reflection circuit as the last-stage current reflection circuit with integer multiples makes it possible to minimize the variation among the 176 outputs and generate high-precision current output. Of course, it should be remembered that the current sources 531, 632 and 633 must be placed densely. the

Incidentally, dense arrangement means placing the first current source 631 and the second current source 632 (current or voltage output and current or voltage input) within a distance of at least 8 mm. Even better, keep them within 5mm. It has been analytically indicated that, when placed at this density, the current sources can be fitted into silicon chips with little difference in transistor characteristics (Vt and mobility (μ)). Similarly, the second current source 632 and the third current source 633 (current output and current input) must be placed within a distance of at least 8 mm. Even better, keep them within 5mm. It goes without saying that the above items are also applicable to other examples of the present invention. the

The current or voltage output and the current or voltage input mean the following relationship. In the case of voltage-based transfer shown in FIG. 66, the transistor 631 (output) of the I-th current source and the transistor 632a (input) of the (I+1)-th current source are placed close to each other. In the case of current-based transfer shown in FIG. 67, the transistor 631a (output) of the I-th current source and the transistor 632b (input) of the (I+1)-th current source are placed close to each other. the

Incidentally, although one transistor 631 is assumed in Figs. 65, 66, etc., this is not restrictive. For example, it is also possible to form multiple small sub-transistors 631 and connect the source or drain terminals of the sub-transistors to the variable resistor 651 to form a unit transistor. By connecting many small sub-transistors in parallel, it is possible to reduce the variation of the unit transistor. the

Similarly, while one transistor 632a is assumed, this is not limiting. For example, it is also possible to form a plurality of small sub-transistors 632 a and connect the gate terminals of these transistors 632 a to the gate terminal of the transistor 631 . By connecting a plurality of small transistors 632a in parallel, it is possible to reduce variation of the transistor 632a. the

Therefore, according to the present invention, the following structures can be illustrated: a structure in which one transistor 631 is connected to multiple transistors 632a, a structure in which multiple transistors 631 are connected to one transistor 632a, and multiple transistors 631 and multiple transistors 632a connected structure. These examples are described in detail below. the

The above items also apply to the structure of the transistors 633a and 633b in FIG. 68 . Possible structures include a structure connecting one transistor 633a to multiple transistors 633b, a structure connecting multiple transistors 633a to one transistor 633b, and a structure connecting multiple transistors 633a to multiple transistors 633b. By connecting a plurality of small transistors 633 in parallel, it is possible to reduce variations of the transistors 633 . the

The above items also apply to the relationship between transistors 632a and 632b in FIG. 68 . Also, preferably, multiple transistors 633b are used in FIG. 64 . Similarly, it is preferred to use multiple transistors 633 in FIGS. 73 and 74 . the

Although described here as being made of a silicon chip, this means a semiconductor chip. Thus, what is referred to herein as a chip may be a chip on a gallium substrate, or other semiconductor chip formed on a germanium substrate or the like. Therefore, the source driver IC 14 can be formed of any semiconductor substrate. Also, the cell transistor 634 may be a bipolar transistor, a CMOS transistor, a bi-CMOS transistor, or a DMOS transistor. However, in terms of reducing variation in the output of the unit transistor 634, it is preferable to use a CMOS transistor for the unit transistor 634. the

Preferably, the cell transistor 634 is an N-channel transistor. The unit transistor composed of P-channel transistors had an output variation 1.5 times larger than that of the unit transistor composed of N-channel transistors. the

Since the unit transistor 634 of the source driver IC 14 is preferably an N-channel transistor, the programming current of the source driver IC 14 is the current drawn from the pixel 16 . Thus, the driver transistors for pixel 16 are P-channel transistors. The switching transistor 11d in FIG. 1 is also a -ditch transistor. the

Therefore, the structure in which the unit transistor 634 in the output stage of the source driver IC (circuit) 14 is an N-channel transistor and the driver transistor 11a of the pixel 16 is a P-channel transistor is a feature of the present invention. Incidentally, it is better if all the transistors 11 constituting the pixel 16 are as illustrated in FIG. 1, since this can reduce the number of process masks required to produce the pixel 16. the

If a P-channel transistor is used as the transistor 11 of the pixel 16, the programming current flows in the direction from the pixel 16 to the source signal line 18. Therefore, an N-channel transistor should be used for the cell transistor 634 of the source driver circuit (see FIGS. 73, 74, 126 and 129). That is, the source driver circuit 14 should be constructed in such a way that the programming current Iw can be drawn. the

Therefore, if the driver 11a of the pixel 16 (in the case of FIG. 1) is a P-channel transistor, the cell transistor 634 of the source driver circuit 14 must always be an N-channel transistor to ensure that the source driver circuit 14 will draw the programming current Iw . In order to form the source driver circuit 14 on the array board 71, it is necessary to use two kinds of masks, a mask (process) for N-channel transistors and a mask (process) for P-channel transistors. Conceptually, in the display screen (display device) of the present invention, the P-channel transistor is used for the pixel 16 and the gate driver circuit 12, and the N-channel transistor is used as one of the transistors of the source driver's current source. use. the

Therefore, a P-channel transistor is used as the transistor 11 of the pixel 16 and for the gate driver circuit 12 . This makes it possible to reduce the cost of the array board 71 . However, in the source driver 14, the unit transistor 634 must be an N-channel transistor. Therefore, the source driver circuit 14 cannot be formed directly on the board 71 . Therefore, the source driver circuit 14 is fabricated solely from silicon chips and the like, and mounted on the array board 71 . In short, the present invention is constituted by externally mounting the source driver IC 14 (means for outputting programming current as a video signal). the

Incidentally, although it has been stated that the source driver circuit 14 is made of a silicon chip, this is not restrictive. For example, many source driver circuits are simultaneously formed on one glass substrate using low temperature polysilicon technology or the like, diced into chips, and mounted on the board 71 . Incidentally, although it has been described that the source driver circuit is mounted on the board 71, this is not restrictive. Any formation may be adopted as long as the output terminal 681 of the source driver circuit 14 is connected to the source signal line 18 of the board 71 . For example, source driver circuit 14 may be connected to source signal line 18 using TAB techniques. By separately forming the source driver circuit 14 on a silicon chip or the like, it is possible not only to reduce the cost but also to reduce variations in output current and obtain correct image display. the

The structure in which P-channel transistors are used as selection transistors for pixels 16 and for gate driver circuits is not limited to organic EL or other self-luminous devices (panel or display devices). For example, it is also applicable to liquid crystal display devices and FEDs (Field Emission Displays). the

If switching transistors 11b and 11c of pixel 16 are P-channel transistors, pixel 16 becomes selected at Vgh and becomes unselected at Vg1. As described earlier, when the gate signal line 17a is changed from Vg1 (on) to Vgh (off), the voltage penetrates (penetrating voltage). If the driver transistor for pixel 16 is a P-channel transistor, the penetration voltage more narrowly limits the current flowing through transistor 11a in the black display mode. This makes it possible to obtain a correct black display. A problem with the current drive type system is that it is difficult to obtain a black display. the

According to the present invention, since the P-channel transistor is used for the gate driver circuit 12, the turn-on voltage corresponds to Vgh. Therefore, the gate driver circuit 12 is well matched to the pixel 16 built from P-channel transistors. And, in order to improve the black display, it is important that the program control current Iw flows from the anode voltage Vdd to the unit transistor 634 of the source driver circuit 14 through the driver transistor 11a and the source signal line 18, just in FIGS. 1, 2, 32, 140, 142 , 144, and 145 shown in the pixel 16 structure. Therefore, if a P-channel transistor is used for the gate driver circuit 12 and the pixel 16, the source driver circuit 14 is mounted on the substrate, and an N-channel transistor is used as the unit transistor 634 of the source driver circuit 14, good results can be produced. Synergistic effect, in addition, the unit transistor 634 composed of N-channel transistors has a smaller variation in output current than the unit transistor 634 composed of P-channel transistors. The N-channel cell transistor 634 has a variation as large as 1/1.5 to 1/2 of the output current of the P-channel cell transistor 634 when they have the same area (W×L). For this reason, it is preferable that an N-channel transistor is used as the unit transistor 634 of the source driver IC 14 . the

This also applies to Fig. 42(b). 42(b) shows a structure in which the programming current Iw flows from the anode voltage Vdd through the programming transistor 11a and the source signal line 18 to the unit transistor 634 of the source driver circuit 14, not a structure in which In this structure, current flows into the unit transistor 634 of the source driver circuit 14 through the driver transistor 11b. Therefore, when in the case of FIG. 1, if the P-channel transistor is used for the gate driver circuit 12 and the pixel 16, the source driver circuit 14 is mounted on the substrate, and the N-channel transistor is used as a unit of the source driver circuit 14 The transistor 634 can produce a good synergistic effect. the

According to the present invention, the driver transistor 11a of the pixel 16 is a P-channel transistor, and the switching transistors 11b and 11c are P-channel transistors. Also, the cell transistor 634 in the output stage of the source driver IC 14 is an N-channel transistor. In addition, preferably, a P-channel transistor is used for the gate driver circuit 12 . the

Needless to say, a configuration in which P-channel and N-channel transistors are interchanged would also work well. Specifically, the driver transistor 11a of the pixel 16 is an N-channel transistor, and the switching transistors 11b and 11c are N-channel transistors. Also, the unit transistor 634 is a P-channel transistor in the output stage of the source driver IC 14 . Additionally, preferably, N-channel transistors are used for the gate driver circuit 12 . This structure also belongs to the present invention. the

The above items apply not only to an IC including a single unit transistor 634, but also to a source driver IC 14 having another structure such as a source driver circuit whose current output stage includes a plurality of transistors or a current mirror. the

In addition, they are also applicable to the source driver 14 by using low-temperature polysilicon, high-temperature polysilicon, CGS formed by solid-phase growth, or a semiconductor thin film of amorphous silicon. In that case, however, the screen is often quite large. On a large screen, it is difficult to visually perceive the effect of certain changes in the output of the source signal line 18. the

Therefore, in a display screen, where the source driver circuit 14 is formed on a glass substrate or the like substrate together with the pixel transistors, the dense arrangement means that the first current source 631 and the second current source 632 (current input and output) within at least 30mm (inclusive) of each other. More preferably, they are within 20mm (inclusive) of each other. It has been analyzed that there is little difference in the characteristics (Vt and mobility (μ)) of transistors placed in this range. Similarly, place the second current source 632 and the third current source 633 (input and output of current) within at least 30 mm (inclusive) of each other. Even better, they are within 20mm (inclusive) of each other. the

It has been stated that, for ease of understanding and illustration, signals are transmitted between current reflecting circuits by way of voltage. However, with current-based transfer, it is possible to reduce variations in the driver circuit (IC) 14 of a current-driven display. the

Figure 67 shows an example of a structure for delivery based on current. Figure 66 also shows an example of a structure for current based transfer. Figs. 66 and 67 are similar in circuit diagram but different in layout structure, that is, wiring layout. In FIG. 66, reference numeral 631 refers to the N-channel transistor used for the first-stage current source, 632a refers to the N-channel transistor used for the second-stage current source, and 632b refers to the N-channel transistor used for the second-stage current source. current source for the P-channel transistor. the

In FIG. 67, reference numeral 631a designates a first-stage N-channel current source transistor, 632a designates a second-stage N-channel current source transistor, and 632b designates a second-stage P-channel current source transistor. the

In Fig. 66, the gate voltage of the first-stage current source constituted by the variable register 651 (for changing the current) and the N-channel transistor 631 is passed to the gate of the N-channel transistor 632a of the second-stage current source . Therefore, this is a layout structure based on the voltage pass-through type. the

In FIG. 67, the gate voltage of the first-stage current source constituted by the variable register 651 and the N-channel transistor 631a is applied to the gate of the N-channel transistor 632a adjacent to the second-stage current source, and thereby the current The current value through this transistor is passed to the P-channel transistor 632b of the second stage current source. Therefore, this is a current-based pass-through layout structure. the

Incidentally, although this example of the present invention focuses on the relationship between the first current source and the second current source for ease of explanation or understanding, this is not restrictive, and it is obvious that this example applies not only to ( can be applied to) the relationship between the second current source and the third current source, but also to the relationship between other current sources. the

In the layout structure of the voltage-based pass-type current mirror circuit shown in FIG. 66, the N-channel transistor 631 of the first-stage current source and the N-channel transistor 632a of the second-stage current source constituting the current mirror circuit are separated. , (to be precise, or easy to achieve separation), therefore, these two transistors are often different in characteristics. Therefore, the current value of the first-stage current source is not correctly transferred to the second-stage current source and may vary. the

On the contrary, in the layout structure of the current mirror circuit based on the transfer type of current shown in FIG. are placed adjacent to each other (easily placed adjacent to each other). Therefore, there is little difference in characteristics between these two transistors. Therefore, the current value of the first-stage current source is correctly transferred to the second-stage current source with possibly little change. the

In view of the above, from the viewpoint of reducing variations, it is preferable to adopt a current-based transfer type rather than a voltage-based transfer-type layout structure for the circuit structure of the multi-stage current reflection circuit according to the present invention, ( A source driver IC (circuit) 14) of the current-based pass-through type according to the present invention. It goes without saying that the above examples are applicable to other examples of the present invention. the

Incidentally, for reasons of explanation, the transfer from the first stage current source to the second stage current source has been quoted, and this also applies to the transfer from the second stage current to the third stage current source, and from the third stage current to the Four-stage current source delivery, etc. the

FIG. 68 shows a current-based transfer model of the three-stage current mirror circuit (three-stage current source) shown in FIG. 65 (which for this purpose shows a voltage-based transfer type circuit structure). the

In FIG. 68, the reference current is first established through the variable register 651 and the N-channel transistor 631. Incidentally, although it is described that the reference current is adjusted by the variable register 651, actually, the source voltage of the transistor 631 is set and adjusted by an electronic regulator formed (ie, set) in the source driver IC (circuit) 14 . In other words, the reference current is regulated by directly supplying the output current from the current-mode electronic regulator to the source terminal of the transistor 631, wherein the electronic regulator is composed of many unit transistors (single unit) 634 as shown in FIG. 64 ( See Figure 69). the

The gate voltage of the first-stage current source constituted by transistor 631 is applied to the gate of the N-channel transistor 632a of the adjacent second-stage current source, and thus, the current flowing through this transistor is passed to the second-stage current source source P-channel transistor 632b, and the gate voltage of the P-channel transistor 632b of the second stage current source is added to the gate of the N-channel transistor 633a of the adjacent third stage current source, and thus, flows through The current of this transistor is passed to the N-channel transistor 633b of the third stage current source. According to the required bit count, a number of current sources 634 are formed (disposed) at the gate of the N-channel transistor 633b of the third stage current source, as illustrated in FIG. 64 . the

The structure in FIG. 69 is characterized in that the first stage current source 631 of the multistage current mirror circuit is equipped with a current value adjustment element. This structure enables the output current to be controlled by changing the current value of the first-stage current source 631 . the

Variations in transistor Vt (variations in characteristics) are on the order of 100 mV within a wafer. However, the variation in Vt of transistors formed within 100 µ of each other should be 10 mV or less (actually measured value). That is, by making a current mirror circuit having transistors formed close to each other, it is possible to reduce variations in the output current of the current mirror circuit. This reduces variations in output current between terminals of the source driver IC. the

Incidentally, although variations in Vt are described as variations among transistors, variations between transistors are not limited to variations in Vt. However, since variation in Vt is the main cause of variation between transistors, for ease of understanding it is assumed that variation in Vt = variation between transistors. the

FIG. 110 is a graph showing the formation area (mm ² ) of the transistor versus the change in output current of the cell transistor 484 , which is the change in current at the threshold voltage (Vt), according to the measurement results. Black dots indicate changes in output current in evaluation sample transistors (10 to 200 in number) built up on the formed area. In FIG. 110, the output current of the transistor formed on the region A (a formation area of 0.5 mm ² or less) has little change (the output current change is only within the margin of error, meaning that a constant current is generated). On the contrary, in the region C (a formation area of 2.4 mm ² or less), the change in output current tends to rapidly increase with respect to the formation area. In region B (a forming area of 0.5 to 2.4 mm ² ), the change in output current is almost proportional to the forming area.

However, the absolute value of the output current varies from wafer to wafer. However, this problem can be solved by adjusting the reference voltage in the source driver circuit (IC) 14 of the present invention, or setting it to a fixed value. And, it is handled (solved) by cleverly modifying the current mirror circuit. the

The present invention changes (controls) the amount of current flowing through the source signal line 18 by switching the amount of current flowing through the unit transistor 634 using input digital data (D). When the number of layers is 64, or more, since 1/64=0.015, the change in output current should be 1 to 2% in theory. Incidentally, an output variation within 1% is difficult to discern with the naked eye, and an output variation of 0.5% or less is impossible to discern (looks uniform). the

To keep the output current variation within 1%, the formation area of the transistor population (during which the transistor variation should be suppressed) should be kept within 2mm ² , as indicated by the results shown in FIG. 110 . More preferably, output current variation (ie, variation in transistor Vt) should be kept within 0.5%. That is, the formation area of the transistor group 681 can be kept within 1.2 mm ² , as indicated by the results shown in FIG. 110 . Incidentally, the formation area is given by multiplying the length in the longitudinal direction by the length in the transverse direction. For example, a formation area of 1.2mm ² is obtained by 1mm×1.2mm.

Incidentally, the above applies to data of 8-bit (256 levels) or larger. For a smaller number of layers, for example, in the case of 6-bit data (64 layers), the variation in output current is about 2% (no problem with the naked eye as far as image display is concerned). If so, the formation area of the transistor group 681 can be kept within 5 mm ² . This condition need not be satisfied for both transistor populations 681 (transistor populations 681a and 681b are shown in Figure 68). If at least one of these two transistor groups (if there are more than three, one or more transistor groups 681) satisfies this condition, the effect of the present invention can be obtained. Preferably, this condition should be satisfied for the lower level transistor population 681 (681a is higher than 681b). This will reduce image display problems.

In the source driver circuit (IC) 14 of the present invention, at least a plurality of current sources, such as current sources including first generation, second generation and third generation, are connected in multiple stages (of course there may be The second stage of the second-generation current source) and densely placed, as shown in Figure 68. Current-based transfers are made between current sources (between transistor populations 681 ). Specifically, transistors (transistor group 681 ) surrounded by dotted lines in FIG. 68 are densely placed. Transistor groups 681 make voltage-based transfers between each other. The first-generation current source 631 and the second-generation current source 632 a are formed approximately in the center of the source driver IC chip 14 . This makes it possible to relatively shorten the distance between the transistor 632a constituting the second-generation current source placed on the left and right sides of the chip and the transistor 632b constituting the second-generation current source. That is, the high-level transistor group 681a is placed approximately in the center of the IC chip. The lower level transistor groups 681b are then placed on the left and right sides of the IC chip 14. Preferably, the transistors are placed, formed, or created in such a manner that they are on the left and right sides of the IC chip 14 . Preferably, the transistors are placed, formed, or created in such a way that there are approximately equal numbers of lower level transistor groups 681b on the left and right sides of IC chip 14. Incidentally, the above items are not limited to the IC chip 14, but are applicable to the source driver circuit 14 formed directly on the array board 71 using low-temperature polysilicon technology or high-temperature polysilicon technology, and this is true for other items as well. the

According to the present invention, one transistor group 681a is constructed, placed, formed, i.e. fabricated in approximately the center of the IC chip 14, and 8 transistor groups 681b are each formed on the left and right sides of the chip (N=8+8, See Figure 63). It is preferred to arrange the second generation transistor groups 681b in such a way that their number will be equal to those on the left and right sides of the chip, or formed on the left side relative to the center of the chip forming the first generation. That is, the difference between the number of placed second-generation transistor groups 681b and the number of second-generation transistor groups 681b formed or placed on the right side of the chip will be 4 or less. More preferably, the difference between the number of second-generation transistor groups 681b formed or placed on the left side of the chip and the number of second-generation transistor groups 681 formed or placed on the right side of the chip is 1 or less. The above applies similarly to the third generation transistor population (omitted in FIG. 68 ). the

A voltage-based transfer (voltage connection) is made between the first-generation current source 631 and the second-generation current source 632a. Therefore, tends to be affected by variations in the transistor Vt. Therefore, the transistors in transistor group 681a are densely placed. The formation area of the transistor group 681a is kept within 2 mm ² as shown in FIG. 110 . Even better, stay within 1.2mm ² . Of course, if the number of layers is 64 or less, this formation area can be within ^5mm2 .

Data is passed through the current between the transistor group 681a and the second generation transistor 632b, so this current may travel some distance. Regarding this distance (for example, between the output terminal of the transistor group 681a of the higher level and the input terminal of the transistor group 681b of the lower level), the transistor 632a constituting the second current source (second generation) should be combined with the transistor 632a constituting the second current source (second generation) The source (second generation) transistors 632b are placed at least within 10 mm of each other, as described above. Preferably, the transistors should be placed or formed within 8 mm. Even better, they should be placed within 5mm. the

It has been analyzed that the differences in the characteristics (Vt and mobility (μ)) of transistors placed on silicon chips will not have much influence in the case of current transfer based distances within this range . Preferably, the above conditions are fulfilled especially by the lower level transistor population. For example, if transistor group 681a is at the top level, transistor group 681b is below it and transistor group 681c is below them, then the current based transfer between transistor group 681b and transistor group 681c should satisfy the above conditions . Therefore, according to the present invention, it is not always necessary for all transistor populations to satisfy the above conditions. It is sufficient that at least one pair of transistor groups 681 satisfies the above conditions. This is because the lower the level, the more transistor populations 681. the

This similarly applies to the transistor 633a constituting the third (third generation) current source and the transistor 633b constituting the third current source. It goes without saying that almost the same applies to voltage-based transfers. The transistor group 681b is formed so as to be placed in the left-to-right direction of the chip (in the vertical direction, ie, the position facing the output terminal 761). The transistor group 681b is formed so as to be placed in the left-to-right direction of the chip (in the longitudinal direction, ie, the position facing the output terminal 761). According to the present invention, the M number of transistor population 681b is 11 (see FIG. 63). the

A voltage-based transfer (voltage connection) is made between the second-generation current source 632b and the third-generation current source 633a. Accordingly, the transistors in transistor group 681b are densely placed as in the case of transistor group 681a. The formation area of the transistor group 681b should be within 2 mm ² , as shown in FIG. 110 . More preferably, it should be within 1.2mm ² . However, even slight variations in transistor Vt in transistor population 681b tend to appear on the screen. Therefore, it is preferable that the formation area should be the area A (0.5 mm ² or less) in FIG. 110 .

Data is transferred between third generation transistor 633a and transistor 633b (current based transfer), and thus in transistor population 681b, the current may flow some distance. The distance descriptions provided earlier apply here as well. The transistor 633a constituting the third (third generation) current source and the transistor 633b constituting the second (third generation) current source should be placed within at least 8mm of each other. Even better, they should be placed within 5mm of each other. the

FIG. 69 shows a current value adjustment element constituted by an electronic regulator. The electronic regulator includes a resistor 691 (which is formed of polysilicon, controls current, and establishes a reference voltage), a decoding circuit 692, a level shifter circuit 693, and the like. By the way, electronic regulators output current. The transistor 641 functions as an analog switch circuit. the

Incidentally, in the source driver IC (circuit) 14, transistors can be used as current sources. This is because in a current mirror circuit composed of transistors and its counterparts, the transistor acts as a current source. the

The electronic adjuster circuit is formed (ie, set) according to the number of colors used by the EL display screen. For example, if RGB three primary colors are used, it is preferable that three electronic adjusters are formed (ie, provided) corresponding to the colors so that the colors can be adjusted independently. However, if one color is used as a reference (fixed), electronic adjusters should be formed (ie, set) as many as the number of colors minus one. the

FIG. 76 shows a structure in which a resistive element 651 is formed (ie, provided) to independently control the reference voltages of the three primary colors of RGB. Of course, it is obvious that the resistive element 651 can be replaced by an electronic regulator. Basic current sources including first-generation and second-generation current sources such as current source 631 and current source 632 are densely placed in the output current circuit 704 in a region illustrated in FIG. 76 . This dense layout reduces variations in the output from the source signal line 18 . As illustrated in FIG. 76, by placing them in the output current circuit 704 at the center of the source driver IC (circuit) 14, it becomes easy to distribute the currents from the current source 631 and the current source 632 to the source driver IC (Circuit) 14 left and right, resulting in reduced output variation between left and right (it is right to put them in the reference current generator circuit or controller, not the current output circuit. ie, 704 is a non-formed area of the output circuit). the

However, it is not always necessary to place them in the output current circuit 704 at the center. They can be placed on one or both ends of the IC chip. Also, they can be formed or provided in parallel with the output current circuit 704 . the

It is not desirable to form the controller or output current circuit 704 at the center of the IC chip 14 because they are susceptible to the Vt distribution of the cell transistors 634 in the IC chip 14 (wafer's Vt is evenly distributed in the wafer). the

The reason for this will be described with reference to FIG. 120 . If the controller or the output current circuit 704 is formed at the center of the IC chip, it is impossible to form or construct the output current circuit composed of the unit transistors 634 at the center. On the other hand, the pixels 16 are formed in a matrix in the display screen 50 of the display screen. The pixels are gridded at equal intervals. Therefore, as illustrated in FIG. 120, in the center of the IC chip 14, there is no output terminal 761b of the output current circuit. Therefore, unlike those at the center of the EL element 15, the wires are routed from the output terminals 761a and 761c to the center portion of the display screen 50 of the display screen. the

However, there is a possibility that the unit transistors of the output circuits connected to the output terminals 761b and 761c differ in Vt. Even though the cell transistors 634 at the output end have equal gate terminal voltages, their output currents will vary according to the Vt distribution of the cell transistors 634 . Therefore, there may be a ladder of output current in the center of the screen. This step in output current can result in a brightness difference between the right and left sides of the screen center. the

The structure used to solve this problem is shown in Figure 122. Fig. 122(a) shows an exemplary structure in which the output current circuit 704 is placed on the IC chip side. Fig. 122(b) shows an exemplary structure in which output current circuits 704 are placed on both sides of an IC chip. Fig. 122(c) shows an exemplary structure in which the output current circuit 704 is placed on the input side of the IC chip. Therefore, the output terminals are regularly formed in the area not occupied by the output current circuit 704 . the

In the circuit structure of FIG. 68, the transistor 633a and the transistor 633b are connected one by one. In FIG. 67, the transistor 632a and the transistor 632b are integrally connected again one-to-one. the

However, if transistors are connected in a one-to-one relationship with other transistors, any change in the characteristics of the transistor's characteristics (Vt, etc.) will result in a change in the output of the corresponding transistor connected to it. the

An example with a suitable structure to solve this problem is shown in Figure 123. In the structure shown in FIG. 123, each pass transistor group 681b (681b1, 68162, and 681b3) composed of four transistors 633a, each pass transistor group 681c (681c1, 681c2) composed of four transistors 633b , and 681c3), connected to each other. Although it has been described that each transistor group 681b and 681c is composed of four transistors 633, this is not limiting and may be composed of less than four or more than four transistors. That is, the reference current Ib flowing through the transistor 633a is output from the plurality of transistors 633 forming a current mirror circuit together with the transistor 633a, and this output current is received by the plurality of transistors 633b. the

Preferably, the plurality of transistors 633a and the plurality of transistors 633b are approximately equal in size and equal in number. Preferably, the unit transistors 634 (in the case of 64 levels as shown in Figure 124, the number is 63), each only produces an output, and the transistor 633b that forms the current reflection together with the unit transistors 634 is also similar in size equal and equal in number. The above structure makes it possible to accurately set the current reflection rate and reduce variation in output current. the

Preferably, the current flowing through the transistor 633b is equal to or five times greater than the current Ic1 flowing through the transistor 632b. This stabilizes the gate potential of the transistor 633a and suppresses the transition phenomenon caused by the output current. the

Although it has been stated that the pass transistor group 681b1 and the pass transistor group 68162 are placed adjacent to each other and each of them includes four transistors 633a placed immediately after the other, this is not restrictive. For example, transistors 633a of pass transistor group 681b1 and transistors 633a of pass transistor group 68162 may be alternately formed or placed. This will reduce the variation in the output current (programmed current) at each terminal. the

The use of multiple transistors based on current transfer makes it possible to reduce the variation in the output current of the transistor population as a whole and further reduce the variation in the output current of each terminal (programmed current). the

The total formation area of the transistors 633 constituting the transfer transistor group 681 is an important item. Basically, the larger the total formation area of the transistor 633 is, the smaller the variation in output current (programmed current flowing from the source signal line 18) is. That is, the larger the formation area of the transfer transistor group 681 (the total formation area of the transistors 633), the smaller the variation. but. The larger formation area of the transistor 633 increases the area of the chip, which in turn increases the price of the IC chip 14 . the

Incidentally, the formation area of the transfer transistor group 681 is the sum of the formation areas of the transistors 633 constituting the transfer transistor group 681 . The area of a transistor 633 is the product of the channel length L and the channel width W of the transistor 633 . Therefore, if the transistor group 681 is composed of 10 transistors 633, its channel length L is 10 μm, and the channel width W is 5 μm, then the formation area Tm (μm ² ) of the transfer transistor group 681 is 10 μm×5 μm×10= 500 (m ² ).

The formation area of the transfer transistor group 681 should be determined in such a manner as to maintain a certain relationship with the cell transistor 634 . Also, pass transistor population 681a and pass transistor population 681b should maintain a certain relationship. the

Now, the relationship between the formation area of the transistor group 681 and the unit transistor 634 will be given. As also illustrated in FIG. 66, a plurality of unit transistors 634 are connected to each transistor 633b. In the case of 64 layers, 63 unit transistors 634 correspond to one transistor 633b (the structure in FIG. 64). If the channel length L of the unit transistor 633 is 10 μm and the channel width W of the unit transistor 633 is 10 μm, the formation area Ts (μm ² ) of the unit transistor group is 10 μm×10 μm×63=6300 μm ² .

Transistor 633b in FIG. 64 and transistor group 681C in FIG. 123 are relevant here. The formation area Ts of the cell transistor group and the formation area Tm of the transfer transistor group 681c have the following relationship:

1/4≤Tm/Ts≤6

More preferably, the formation area Ts of the unit transistor group and the formation area Tm of the transfer transistor group 681c have the following relationship:

1/2≤Tm/Ts≤4

By satisfying the above relationship, it is possible to reduce variations in the output current (programmed current) at each terminal. the

Also, the formation area Tmm of the transfer transistor group 681b and the formation area Tms of the transfer transistor group 681c have the following relationship

1/2≤Tmm/Tms≤8

More preferably, the formation area Ts of the unit transistor group and the formation area Tm of the transfer transistor group 681c have the following relationship:

1≤Tm/Ts≤4

By satisfying the above relationship, it is possible to reduce variations in the output current (programmed current) at each terminal. the

Assume that the output current from the transistor group 681b1 is Ic1, the output current from the transistor group 681b2 is Ic2, and the output current from the transistor group 681b2 is Ic3. Therefore, the output currents Ic1, Ic2, and Ic3 must be consistent. According to the present invention, since each transistor group 681 is composed of a plurality of transistors 633, even if individual transistors 633 vary, the output current Ic of the transistor group 681 as a whole no change. the

Incidentally, the above example is not limited to the three-stage current mirror connection (multi-stage current mirror connection) shown in FIG. 68 . It goes without saying that it also works with single stage current mirror connections. The example shown in FIG. 123 involves transistor groups 681b (681b1, 681b2, 681b3, ...) each consisting of a plurality of transistors 633a and transistor groups 681c (681c, 681c2, 681c3 ,……)connect. However, the present invention is not limited to these cases. It is also possible to connect a single transistor 633a to transistor groups 681c (681c1, 681c2, 681c3) each consisting of a plurality of transistors 633b, or to connect transistor groups 681b (681c1, 681c2, 681c3) each consisting of a plurality of transistors 633a. . . . ) are connected to a transistor group 633b. the

In FIG. 64, switch 641a corresponds to the zeroth bit, switch 641b corresponds to the first bit, switch 641c corresponds to the second bit, ... and switch 641f corresponds to the fifth bit. The zeroth bit consists of one unit transistor, the first bit consists of two unit transistors, the second bit consists of four unit transistors, ..., and the fifth bit consists of 32 unit transistors. For ease of explanation, it is assumed that the source driver circuit 14 is a 6-bit driver maintaining a 64-level display. the

With the structure of the driver 14 according to the present invention, the first bit outputs twice the programming current to the zeroth bit, the second bit outputs twice the programming current to the first bit, and the third bit outputs two The twice as large programming current is sent to the second bit, the fourth bit outputs twice the programming current to the third bit, and the fifth bit outputs twice the programming current to the fourth bit. In other words, each bit must be able to output twice the programmed current of the lower bit of the next stage. the

In practice, however, it is difficult, if not impossible, to construct such that each terminal will output exactly twice as much programmed current because of variations in the cell transistors 634 making up different bits. An example that solves this problem is shown in Figure 124. the

The structure in FIG. 124 includes adjustment transistors in addition to cell transistors 634 for each single bit. These adjustment transistors 1241 correspond to the fifth bit (switch 641f) and the fourth bit (switch 641e). the

In the example shown in FIG. 124, the adjustment transistor 1241 is placed, formed, or constructed between the fifth bit (unit transistor 634 connected to switch 641f) and the fourth bit (unit transistor 634 connected to switch 641d). ) place. Four adjustment transistors 1241 are placed at the fifth bit and the fourth bit respectively. However, the present invention is not limited to these cases. The number of adjustment transistors 1241 for each bit can be changed. Also, pass transistors 1241 may be attached to all bits (by forming, building, or placing them). The adjustment transistor 1241 is made smaller than the unit transistor 634 . Alternatively, they are designed to generate a smaller output current than the unit transistor 634. Even if the transistor size is fixed, it is possible to change the output current by changing W/L. the

Incidentally, the adjustment transistor 1241 and the unit transistor 634 may be constructed, ie connected, so as to share a gate terminal to which the same gate voltage is applied. Therefore, when the current Ib flows through the transistor 633 , the gate voltage of the unit transistor 634 is established, specifying the current to be output from the unit transistor 634 . At the same time, the output current of the regulating transistor 1241 is also limited. That is, the output current of the adjustment transistor 1241 is proportional to the output current of the unit transistor 634 . This output current can be controlled by means of the current Ib to be passed through the transistor 633 paired with the unit transistor 634 . the

According to the present invention, the size of one unit transistor 634 is made larger than the total size of two or more adjustment transistors. That is, the size of the cell transistor 634 is larger than that of the adjustment transistor 1241 . Alternatively, the total size of two or more adjustment transistors 1241 is made larger than the size of the unit transistor 634 . By controlling the number of adjustment transistors 1241 operating, it is possible to adjust the variation of the output current to each bit in small increments. the

According to another example of the present invention, the output current of one unit transistor 634 is made larger than the output current of two or more adjustment transistors. That is, the output current of the cell transistor 634 is greater than the output current of the regulating transistor 1241 . By controlling the number of adjustment transistors 1241 operating, it is possible to adjust the variation of the output current for each bit in small increments. the

FIG. 125 is an explanatory diagram illustrating a method of adjusting the output current for each bit using the adjustment transistor 1241. the

Figure 125 shows four pass transistors 1241 that have been formed. Incidentally, for ease of explanation, it is assumed that the target output current of the bit used for output current adjustment is Ia, and the actual output current Ib is smaller than the target output current Ia by an amount Ie (Ia=Ib+Ie). And, if Ig is the current flowing when all four adjustment transistors 1241 are working normally, Ig>Ie should always be satisfied even if there are variations of the transistors during production. Therefore, when the four regulating transistors 1241 are working, the output current Ib exceeds the target output current Ia (Ib>Ia). the

In the above condition, the adjustment transistor 1241 is cut off from the common terminal 1251 to obtain the target output current Ia. These pass transistors 1241 are cut by laser cutting. It is suitable to use YAG (yttrium aluminum garnet) laser for laser cutting. Alternatively, a neon-helium laser or a carbon dioxide laser may be used. Also, machining such as sandblasting may also be used. the

In FIG. 125 , transistors 1241 a and 1241 b are severed from common terminal 1252 at two cut locations 1251 . Therefore, the current Ig is halved. In this way, the adjustment transistors 1241 are cut off from the common terminal 1251 one by one until the target output current Ia is obtained. The output current is measured with a microammeter, and when the measured value reaches the target value, the regulating transistor 1241 is stopped and cut off. the

Incidentally, although it has been described with reference to FIG. 125 that the cutting position 1251 is cut with a laser to adjust the output current, this is not restrictive. For example, the laser light can be directly emitted to the adjustment transistors 1241 to output current by destroying them, and it is also possible to install an analog switch at the cutting position 1251, which is turned on and off by an external control signal, and thus changes the connection to the point g The number of adjustment transistors 1241. That is, the present invention forms the regulating transistor 1241 , and obtains the target output voltage by turning on and off the regulating transistor 1241 . Therefore, it goes without saying that other structures can also be used. the

Moreover, it is not strictly necessary to cut at the cutting position 1251, and it is also possible to use another method to open the cutting position in advance and make a connection by depositing a metal film or a film of the same type on the cutting position. the

In addition, although it has been described that the adjustment transistor 1241 is formed in advance, this is not limitative. For example, it is possible to fine-tune part of the unit transistor 634, thereby adjusting the output current of the unit transistor 634, so as to obtain the target output current for each bit . Or alternatively, it is possible to obtain target output currents for different bits by individually adjusting the gate terminal voltage of the cell transistor 634 corresponding to the corresponding bit, for example, by trimming the gate terminal connected to the cell transistor 634 The wiring is done by adding resistance. the

FIG. 166 illustrates a portion of the adjustment transistor 1241 or the cell transistor 634. A plurality of unit transistors 634 (or adjustment transistors 1241 ) are connected by an internal line 1622 . For easy trimming, the pass transistors 1241 have slit cuts at their source terminals (S terminals). By making a cutout at the cut-off point 1661b, it is possible to limit the current flowing between the channels of the adjustment transistor 1241 . This reduces the output current at the current output stage 704. Incidentally, not only the source terminal but also the drain or gate terminal can be formed with a slit. Needless to say, even if the slit is not formed, part of the adjustment transistor 1241 can be cut off, and it is also possible to form a plurality of adjustment transistors 1241 of different shapes. After the measurement of the output current, the adjustment transistor 1241 is fine-tuned, so that the selection will produce the closest transistors at the target output current. the

Incidentally, although the output current in the above example can be adjusted by trimming the unit transistor 634 or the adjustment transistor 1241, the present invention is not limited to these cases. For example, it is possible to form the regulating transistors 1241 in isolated form, connect their source terminals or the like to the output current circuit 704 through the FIB process, and thereby regulate the output current. However, pass transistor 1241 need not be completely isolated. For example, it is possible to form the output current circuit 704 and the adjustment transistor 1241 with their gate and source terminals connected, and to connect the drain terminal of the adjustment transistor 1241 through the FIB process. the

Also, it is possible to construct the gate terminal of the adjustment transistor 1241 isolated from the gate terminal of the unit transistor 634 forming the output current circuit 704, and to form or set the unit transistor 634 and the adjustment transistor with their drain terminals and source terminals connected. 1241. The potential at the gate terminal of the cell transistor 634 is determined by the current Ic, as illustrated in Figure 164 and its ilk. The potential at the gate terminal of this adjustment transistor 1241 can be freely adjusted. By adjusting the potential, it is possible to vary the output current of the regulating transistor 1241 . Therefore, by adjusting the potential at the gate terminal of the adjustment transistor 1241, it is possible to adjust the output current of the output current circuit 704, which is the sum of the output currents from the unit transistor 634 and the adjustment transistor 1241. This method does not require a fine-tuning process or a FIB process. The voltage at the gate terminal of the adjustment transistor 1241 can be adjusted using an electronic regulator or other similar devices. the

Although it has been described that the output current of the adjustment transistor 1241 is adjusted through adjustment of the potential at the gate terminal, this is not restrictive. The output current can be adjusted by adjusting the voltage applied to the source terminal or the drain terminal of the adjustment transistor 1241 . These terminal voltages can also be adjusted using electronic regulators. Also, the voltage applied to the terminals of the regulating transistor 1241 is not limited to a DC voltage. It is also possible to apply a rectangular voltage (pulse voltage or the like) and control the output voltage by duration control. the

To greatly vary the magnitude of the output current, the regulation transistor 1241 can be cut off at the cutoff point 1661a, as illustrated in FIG. 166 . Thus, by trimming all or part of the unit transistor 634 or the adjustment transistor 1241, it is possible to easily adjust the output current. To protect the trimming locations from degradation, it is recommended to seal them after trimming by vapor deposition or coating them with an inorganic or organic material so that they will not be exposed to the air. the

In particular, it is preferable that the output current circuit 704 on both ends of the IC chip 14 is equipped with a trimming function. In the case of a large display screen, multiple source driver ICs 14 must be connected in series. This is because the series connection makes the difference between the output currents of adjacent ICs as noticeable as a boundary. By trimming transistors and the like, as illustrated in Figure 166, it is possible to correct output current variations between adjacent output current circuits. the

Needless to say, the above also applies to other examples of the present invention. the

In the structure of Fig. 123, by having a plurality of transistors 633b receive output currents from a plurality of transistors 633a, the variation in the output current at each end is reduced, and Fig. 126 shows a structure in which supply current to reduce variations in output current at each terminal. Multiple sources provide current Ia. The current Ia1 and the current Ia2 have the same current value, and the transistor generating the current Ia1 and the transistor generating the current Ia2 constitute a current mirror circuit as a pair. the

Therefore, in this structure, a plurality of transistors (current generating means) are formed, arranged, that is, constructed to generate a reference current that specifies the output current of the unit transistor 634 . More preferably, output currents from a plurality of transistors are connected to a current receiving circuit, such as transistors constituting a current mirror circuit, and the output current of the unit transistor 634 is controlled by a gate voltage generated through the plurality of transistors. the

In addition, according to an embodiment of FIG. 126 , the transistor 633b constituting the current reflection circuit is formed on both sides of the unit transistor group 634. However, the present invention is not limited to these cases, and the transistor 632a constituting the current reflection circuit is arranged on both sides of the transistor group 681b. The structures on both sides also belong to the present invention. the

As can be seen from FIG. 126, the transistor group 681b contains a plurality of transistors 633a that output current, and transistors 632a (632a1 and 632a2) are arranged on both sides of the transistor group 681b, and they share the gate terminal of the transistor group 681b, and are connected with the transistor 633a Together, a current mirror circuit is formed. The reference current Ia1 flows through the transistor 632a1, and the reference current Ia2 flows through the transistor 632a2. Therefore, the gate terminal voltage of the transistor 633a (633a1, 633a2, 633a3, 633a4...) is limited by the transistors 632a1 and 632a2, and the output current from the transistor 633a is limited. the

Make the magnitudes of the reference currents Ia1 and Ia2 consistent. This can be accomplished by a constant current circuit such as a current mirror circuit outputting the reference currents Ia1 and Ia2. Even if the reference currents Ia1 and Ia2 deviate from each other more or less, this poses little problem because they correct each other. the

Although in the above example, it has been described that the reference currents Ia1 and Ia2 are roughly made identical, the present invention is not limited to these cases. For example, the reference currents Ia1 and Ia2 may be different from each other. For example, if the current Ia1 is smaller than the current Ia2, the current Ib1 output by the transistor 633a1 can be made smaller than the current Ibn output by the transistor 633an (Ib1<Ibn). The smaller the current Ib1, the smaller the current output by the transistor group 681c1. The larger the current Ibn, the larger the current output by the transistor group 681cn. The transistor group 681 disposed between the transistor group 681c1 and the transistor group 681cn can generate an intermediate magnitude output current. the

Therefore, by making the current Ia1 and the current Ia2 different from each other, it is possible to generate a slope in the output current of the transistor group 681 . The slope of the output current of the transistor group 681 is valid for the series connection of the source driver IC 14 because the adjustment of the IC chip by the two reference currents IA1 and Ia2 makes it possible to adjust the output current of the output current circuit 704 . Therefore, it is possible to make adjustments so as to eliminate the difference between the output currents of adjacent IC chips 14 . the

Even if the current Ia1 and the current Ia2 are made different from each other, if the potentials at the gate terminals of the unit transistors 634 in the transistor group 681 are the same, it is impossible to generate a slope in the output current of the transistor group 681. The reason why a slope occurs in the output current of the transistor group 681 is that the gate terminal voltage is different between the cell transistors through 634, and to change this gate terminal voltage, it is necessary to increase the resistance of the gate connection 1261 in the transistor group 681, specifically That is, the gate wiring 1261 is formed of polysilicon. Also, the resistance value of the gate connection between the transistors 632a1 and 632an should be between 2KΩ and 2MΩ (both inclusive). Thus, by increasing the resistance of the gate connection 1261, it is possible to create a slope in the output current of the transistor group 681c. the

Preferably, the voltage at the gate terminal of the transistor 633a is set at 0.52 to 0.68V (both inclusive), and a silicon IC chip is used. This range reduces variations in the output current of transistor 633a. The above applies similarly to other examples of the invention. the

It goes without saying that the above items are also applicable to other examples of the present invention. the

In the structure shown in FIG. 126, the current mirror circuit includes two or more (multiple) transistors 632a paired with transistors 633a. Since the reference current is supplied from both sides, in the transistor group 681a, the gate terminal voltage of the transistor 633a can be reliably kept constant, and therefore, the variation in the output current generated by the transistor 633a is extremely small. Therefore, there is an extremely small change in the programmed current output to the source signal line 18 or the programmed current drawn from the source signal line 18. the

In FIG. 126, current is transferred not only between the transistor 633a2 and the transistor 63362 but also between the transistor 633a1 and the transistor 633a2. The transistor group 681c1 is therefore also structured to supply current from both sides. Similarly, current is transferred not only between transistor 633a4 and transistor 63364, but also between transistor 633a3 and transistor 63363, and current is transferred not only between transistor 633a6 and transistor 63366, but also between transistor 633a5 and transistor 63365. also transfer current. the

The transistor group 681c constitutes an output stage circuit connected to the associated source signal line 18 . Therefore, by supplying current to the transistor group 681c from both sides, and canceling the voltage drop at the gate terminal of the unit transistor 634, that is, the potential distribution, it is possible to remove variation in output current from the source signal line 18. the

Each transistor group 681c includes a plurality of unit transistors 634 for outputting current. On both sides of the transistor group 681c, there are transistors 633b (633b1 and 63362) which share the gate terminal of the transistor 634 and form a current mirror circuit together with the transistor 634. The reference current Ib1 flows through the transistor 633b1 , and the reference current Ib2 flows through the transistor 63362 . Therefore, the gate terminal voltage of the unit transistor 634 is defined by the transistors 633b1 and 63362, and the current output from the unit transistor 634 is limited. the

Make the amplitudes of the reference currents Ib1 and Ib2 consistent. This can be accomplished by a constant current circuit such as transistor 633a that outputs reference currents Ib1 and Ib2. Even if the reference currents Ib1 and Ib2 deviate from each other more or less, this causes little problem because they correct each other. the

FIG. 127 shows a variation of the example shown in FIG. 126 . In FIG. 127, in addition to the transistor 632a forming the current mirror circuit on both sides of the transistor group 681b, there is a transistor 632 forming the current mirror circuit in the middle of the transistor group 681b. Therefore, compared with the structure shown in FIG. 126, the transistor 633a has a more constant gate terminal voltage and less variation in its output. Needless to say, the above items also apply to the transistor group 681c. the

FIG. 128 shows another variation of the example shown in FIG. 126 . In FIG. 126, the 633a transistors in the transistor group 681b are sequentially connected to the transistor 633b which forms a current mirror circuit together with the transistor group 681c. In the example shown in FIG. 128, the transistors 633a are connected in a different order. the

In FIG. 128, transistor 633a1 performs current based transfer to/from transistor 633b1 which forms a current mirror circuit with transistor group 681c1. Transistor 633a2 performs current based transfer to/from transistor 63363 which together with transistor group 681c2 forms a current mirror circuit. Transistor 633a3 performs current based transfer to/from transistor 63362 which together with transistor group 681c1 forms a current mirror circuit. Transistor 633a4 performs current based transfer to/from transistor 63365 which together with transistor group 681c3 forms a current mirror circuit. Transistor 633a5 performs current based transfer to/from transistor 63364 which together with transistor group 681c2 forms a current mirror circuit. the

With the structure shown in FIG. 126, the distribution of any characteristics of transistors 633a tends to cause groups of transistors 681c that supply current from transistors 633a to form blocks, resulting in variations in output current. Therefore, a blocky border may appear on the EL display. the

As shown in FIG. 128, by rearranging the order of connections with transistors 633 forming a current mirror circuit together with transistor groups 681c, instead of sequentially connecting transistors 633a, even if there is a characteristic distribution of transistors 633a, it is possible to reduce The change in output current caused by the bulk formed by 681c. This prevents blocky borders from appearing on the EL display screen. the

Of course, the transistor 633a and the transistor 633b need not be connected regularly, but may be connected arbitrarily. Also, jump two or more. Instead of jumping one connects transistor 633a to transistor 633b. As shown in Figure 28. the

In the above example, the current mirror circuits are connected in multiple stages as illustrated in FIG. 68 . However, the present invention is not limited to a multi-level circuit structure, and a single-level circuit structure may be used, as illustrated in FIG. 129 . the

Fig. 129 controls, ie regulates, the reference current through the reference current regulating means 651, (it goes without saying that this means is not limited to a variable regulator, and may be an electronic regulator). The unit transistor 634 forms a current mirror circuit together with the transistor 633b, and the reference current Ib defines the magnitude of the output current from the unit transistor 634. the

With the structure shown in FIG. 129, the reference current Ib controls the current of the unit transistors 634 in the transistor group 681c, in other words, the transistor 633b defines the programming current for the unit transistors 634 in the transistor groups 681c1 to 681cn. the

However, there is often a slight difference between the gate terminal voltage of the unit transistor 634 in the transistor group 681c1 and the gate terminal voltage of the unit transistor 634 in the transistor group. It is presumed that this is caused by a voltage drop or the like caused by a current flowing through the gate wiring or the like. Even a small change in voltage will cause a few percent change in output current (programmed current). According to the present invention, in the case of 64 levels, the difference between levels is 1.5% (=100/64). Therefore, variations in output current should be reduced to at least on the order of 1% or less. the

A structure for solving this problem is shown in Fig. 130, in Fig. 130, there are two generator circuits of the reference current Ib. The reference current generator circuit 1 delivers a reference current Ib1, and the reference current generator circuit 2 delivers a reference current Ib2, and the reference current Ib1 and the reference current Ib2 have the same current value. The reference current is controlled, i.e. regulated, by the reference current regulating means 651 (needless to say, this device is not limited to a variable regulator, but could also be an electronic regulator, or alternatively, the reference current can be adjusted by changing a fixed resistor) . Incidentally, the output terminal of the transistor group 681c is connected to the source signal line 18 . The structure used here is a single-stage current mirror circuit. the

However, if the reference current Ib1 and the reference current Ib2 are constructed to be individually adjustable, when the voltages at the point a and at the point b at the common terminal 1253 are different from each other, and in the transistor group 681c1, the unit transistors 634 and When the output currents of the unit transistors 634 are different in the transistor group 681c2, it is possible to adjust the output currents (programmed currents) to be uniform. Also, since the cell transistors on the left and right sides of the IC chip 14 are different in Vt, it is possible to cancel the slope in the output current and correct any generated slope. the

In FIG. 130, although two reference current generator circuits are formed separately, this is not limitative. And they can be constructed from transistors 633a in transistor group 681b shown in FIG. 128 . By adopting the structure in 128 and controlling (adjusting) the current flowing through the transistor 632a constituting the current mirror, it is possible to simultaneously control (adjust) the reference currents Ib1 and Ib2 shown in FIG. 130 . That is, the transistors 633b1 and 63362 are controlled as a transistor group (see FIG. 130(b)). the

With the structure in FIG. 130, it becomes possible to make the voltage at point a and the voltage at point b equal on the common terminal 1253 (gate wiring 1261). This also makes it possible that the output current of the unit transistor 634 in the transistor group 681c1 and the output current of the unit transistor 634 in the transistor group 681c2 become equal, and supply a uniform program current without variation to the source signal line 18 . the

Thus, the structure in Figure 130 contains two reference current sources. FIG. 131 shows a structure in which the gate voltage of the transistor 633b constituting the reference current source is also applied to the center of the common terminal 1253. the

The reference current generator circuit 1 delivers a reference current Ib1, and the reference current generator circuit 2 delivers a reference current Ib2. The reference current generator circuit 3 delivers a reference current Ib3. The reference current Ib1, the reference current Ib2, and the reference current Ib3 have the same current value. These reference currents are controlled, ie regulated, by means of a current regulating device 651 (it goes without saying that this device is not limited to a variable regulator and may be an electronic regulator). the

If the reference current Ib1, the reference current Ib2, and the reference current Ib3 are constructed to be individually adjustable, it is possible to adjust the gate terminal voltages of the transistor 633b1, the transistor 63362, and the transistor 63363. It is possible to adjust the voltage at point a, the voltage at point b, and the voltage at point c on the common terminal 1253 . Therefore, it is possible to correct the output current (programming current) by changing the Vt of the unit transistor 634 in the transistor group 681c, the Vt of the unit transistor 634 in the transistor group 681c2, and the Vt of the unit transistor 634 in the transistor group 681cn. (change in ). the

Although three reference current generator currents are formed individually in FIG. 130, this is not limitative, and four or more reference current generator circuits may be formed. They may be constructed from transistors 633a in transistor group 681b shown in FIG. 128 . By adopting the structure in FIG. 128 and controlling (adjusting) the current flowing through the transistor 632a constituting the current mirror, it is possible to control (adjust) the reference currents Ib1, Ib2 and Ib3 shown in FIG. 130 at the same time. That is, the transistors 633b1, 63362, and 63363 are controlled as a transistor group (see FIG. 131(b)). the

FIG. 130 shows a structure in which the reference current adjusting means 651a is formed or provided for the transistor 633b1, and the reference current adjusting means 651b is formed or provided for the transistor 63362. Fig. 132 shows a structure in which the source terminal is shared by transistors 633b1 and 63362, and a reference current adjusting means 651 is formed or provided. The reference currents Ib1 and Ib2 are controlled (regulated) by the current regulating device 651 to vary. The programmed current output from the cell transistor 634 varies in proportion to the variation in the reference currents Ib1 and Ib2. Transistor 633b1 and transistor 63362 are connected in the same manner as transistor 633b in transistor group 681c shown in FIG. 123 . the

The reference currents Ib1 and Ib2 are controlled, ie regulated, by a reference current regulating device 651 (it goes without saying that this device is not limited to a variable regulator and may be an electronic regulator). The unit transistor 634 forms a current mirror circuit together with the transistor 633b (633b and 63362) in each transistor group 681c. The reference currents Ib1 and Ib2 define the magnitude of the output current from the cell transistor 634 . the

With the structure shown in FIG. 129, the reference current Ib1 is used to mainly adjust the gate terminal voltage at point a to a predetermined value, and the reference current Ib2 is used to mainly adjust the gate terminal voltage at point b to a predetermined value. predetermined value. The reference currents Ib1 and Ib2 are substantially the same current. Transistors 633b1 and 63362 formed close to each other have equal transistor Vt. the

Therefore, the transistor 633b1 and the transistor 63362 share a gate terminal, and the voltage at point a is equal to the voltage at point b. Therefore, voltage is supplied from both sides of the common terminal 1253 so that the voltage at the common terminal 1253 is equalized on the left and right sides of the IC chip. Once the terminal voltages at the common terminal 1253 are uniform, the voltages at the gate terminals of all cell transistors 634 in the transistor group 681c become equal. This eliminates variations in the programmed current output from the unit transistor 634 to the source signal line 18 . the

Thus, the structure in Figure 132 includes two transistors 633b that generate the reference current source. FIG. 133 shows a structure in which the gate voltage of the transistor 63362 constituting the reference current source is also applied to the center of the common terminal 1253. the

Reference current generator circuit 1 delivers reference current Ib1, and reference current generator circuit 2 delivers reference current Ib2. The reference current generator circuit 3 delivers the reference current Ib3, and the reference current Ib1, the reference current Ib2, and the reference current Ib3 have the same current value. These reference currents are controlled, ie regulated, by reference current regulating means 651 (it goes without saying that this means is not limited to variable regulators and may be electronic regulators). the

In FIG. 133, although three reference current generator circuits are formed individually, this is not restrictive, and four or more reference current generator circuits may be formed. the

Incidentally, in the structures of Figs. 126, 127, 128, etc., transistors passing the reference current are provided, that is, formed on both sides of the gate wiring 1261, however, the present invention is not limited to these cases. Needless to say, a constant voltage may be directly applied to the gate wiring 1261 instead of the provided transistor. The above items also apply to other examples of the present invention. the

In the few examples above, current-based or voltage-based delivery is primarily implemented in single-stage structures. However, the present invention is not limited to these. It goes without saying that, for example, as shown in FIG. 146, the present invention is also applicable to the multistage structure shown in FIG. 68. the

In FIG. 147, transistors 631a and 631b are formed, that is, disposed at both ends of a transistor group 681a (on or near the left and right ends of the IC chip). Also, a variable resistor 651 as a reference current adjusting means is formed, ie set. Incidentally, the reference currents Ia1 and Ia2 may be fixed. It goes without saying that the reference currents Ia1 and Ia2 may be equal. the

By adjusting the reference currents Ia1 and Ia2 by the reference current adjusting means 651, it is possible to adjust the output current Ib of the transistors 632 in the transistor group 681a. The current Ib is delivered to the transistor 633a, causing a current to flow through the transistor 633a forming a current mirror circuit in the transistor group 681b, and thereby determining the output current of the cell transistor 634. Other items are the same as those in Fig. 68 and its ilk, so description thereof is omitted. the

Although it has been described that the magnitude of the reference current flowing through the transistors provided on both sides of the chip is adjusted by an electronic regulator or the like, the present invention is not limited to these cases. For example, this can be done by trimming the reference current adjustment resistor Rm, as illustrated in FIG. 165 . That is, by trimming the resistor Rm with the laser light 1502 emitted from the laser device 1501, the resistance value is increased. An increase in the resistance value of the resistor Rm changes the reference current Ia. By fine-tuning Rm1 or Rm2, it is possible to adjust the reference currents Ia1 and Ia2 respectively. the

Preferably, the current generated by the transistors constituting the current mirror circuit is delivered by a plurality of transistors. Transistors formed on the IC chip 14 have variations in characteristics. To suppress variations in transistor characteristics, the size of the transistor can be increased. However, if the size of the transistor is increased, the current reflection rate of the current mirror circuit may deviate. To solve this problem, it is proposed to make current or voltage based transfer with multiple transistors. Even if there are variations in the characteristics of individual transistors, the use of multiple transistors reduces the overall variation. This also improves the accuracy of the current reflection rate. Overall, the area of the IC chip is also reduced. Figure 156 shows an example. Incidentally, the above applies to both current-based or voltage-based multi-stage transfer and current-based or voltage-based single-stage transfer. the

In FIG. 156, a transistor group 681a and a transistor group 681b constitute a current mirror circuit. The transistor group 681a is composed of a plurality of transistors 632b. On the other hand, each of transistor groups 681b is composed of a plurality of transistors 633a. Similarly, each of transistor groups 631c is composed of a plurality of transistors 633c. the

The transistor group 681b1, the transistor group 68162, the transistor group 68163, the transistor group 68164, etc. are composed of the same number of transistors 633a. Also, the total area of transistors 633a is (approximately) equal across transistor groups 681b (here, the total area is the W and L dimensions of transistors 633a multiplied by the number of transistors 633a in each transistor group 681b) . The same applies to transistor population 681c. the

Let Sc denote the total area of transistors 633b in each transistor group 681c (where total area is the W and L dimensions of transistors 633b in each transistor group 681c multiplied by the number of transistors 633b). Also let Sb denote the total area of the transistors 633a in each transistor group 681b (here, the total area is multiplied from the W and L sizes of the transistors 633a in each transistor group 681b by the number of transistors 633a), and let Sa represents the total area of the transistors 632b in each transistor group 681a (here, the total area is the W and L sizes of the transistors 632b in each transistor group 681a multiplied by the number of transistors 632b). Also let Sd denote the total area of the cell transistors 634 per output. the

Preferably, the total area Sc and the total area Sb are approximately equal. And, preferably, the transistors 633a constituting each transistor group 681b and the transistors 633b constituting the transistor group 681c are equal in number. However, considering the layout constraints on the IC chip 14, the transistors 633a constituting each transistor group 681b can be made smaller in number and larger in size than the transistors 433b constituting each transistor group 681c. An example of the above structure is shown in Figure 157. The transistor group 681a is composed of a plurality of transistors 632b. The transistor group 681a and the transistor 633a constitute a current mirror circuit. Transistor 633a generates current Ic. One transistor 633a drives multiple transistors 633b in transistor group 681c (the current Ic from a single transistor 633a is shunted to multiple transistors 633b). In general, the number of transistors 633a corresponds to the number of output circuits. For example, in a QCIF ⁺ panel, there are 176 transistors 633a in each R, G and B circuit.

The relationship between the total area Sd and the total area Sc is related to the output variation. This correspondence is shown in Figure 210. For rate of change and such, see Figure 170. The rate of change when the total area Sd:total area Sc=2:1 (Sc/Sd=1/2) is taken as 1. It can be seen from graph 210 that a small Sc/Sd ratio results in a rapid degradation in the rate of change. Especially when Sc/Sd is 1/2 or less, a poor rate of change is obtained. When Sc/Sd is 1/2 or more, the output variation decreases. This reduction is gradual. When Sc/Sd is about 1/2 or larger, the output variation is within the allowable range. In view of the above, it is preferable to satisfy 1/2≦Sc/Sd. However, a larger Sc means a larger IC chip. Therefore, an upper limit of Sc/Sd=4 should be specified. That is, 1/2≦Sc/Sd≦4 should be satisfied. the

Incidentally, A≥B means that A is equal to or greater than B. A>B means that A is greater than B. A≤B means that A is equal to or smaller than B. A<B means that A is less than B. the

In addition, it is preferable that the total area Sd and the total area Sc are approximately equal. Also, preferably, the number of unit transistors 634 per output is equal to the number of transistors 633b in each transistor group 681c. That is, in the case of 64 layers, there are 63 unit transistors 634 per output. Thus, there are 63 transistors 633b in transistor population 681c. the

And, preferably, the transistor group 681a, the transistor group 681b, and the transistor group 681c are composed of unit transistors 634 whose WL area is within 4 times. More preferably, they consist of cell transistors 484 whose WL area is within 2 times. Even more preferably, they consist of unit transistors 484 of the same size. That is, the current mirror circuit and the output current circuit 704 are composed of transistors of approximately the same size. the

The total area Sa should be larger than the total area Sb. Preferably, the relationship of 200Sb≥Sa≥4 is satisfied. Also, the total area Sa of transistors 663a making up all transistor groups 681b should be approximately equal to Sa. the

Incidentally, as illustrated in FIG. 164, the transistor 632a constituting the current mirror circuit with the transistor group 681b need not be included in the transistor group 681a (see FIG. 156). the

In the structure of Figs. 126, 127, 128, 147 or the like, transistors through which a reference current flows are provided, that is, formed on both sides of the gate wiring 1261. FIG. 158 shows an example of applying this structure (scheme) to the structure in FIG. 157 . In FIG. 158 , transistor groups 681a1 and 681a2 are arranged, that is, formed on both sides of a gate wiring 1261 . The other items are the same as those in Figs. 126, 127, 128, 147, etc., so descriptions thereof are omitted. the

In the structures shown in FIGS. 126, 127, 128, 147, 158, etc., a transistor or group of transistors is provided at each end of the gate connection 1261. Therefore, a total of two transistors or two transistor groups are provided at both ends of the gate wiring 1261. However, the present invention is not limited to these cases. As illustrated in FIG. 159, a transistor or group of transistors may be placed in the center of gate connection 1261 or elsewhere. In FIG. 159 three transistor groups 681a are formed. The present invention is characterized in that a plurality of transistors or transistor groups 681 are formed on the gate wiring 1261 . The use of multiple transistors or groups of transistors makes it possible to lower the impedance of the gate connection 1261, resulting in improved stability. the

In order to further improve the stability, it is preferable to form or place a capacitor 1601 on the gate wiring 1261 as illustrated in FIG. 160 . Alternatively, the capacitor 1601 is formed in the IC chip 14, that is, the source driver circuit 14, or provided as an external capacitor of the IC 14, that is, mounted outside the chip. When the capacitor 1601 is mounted externally, a capacitor connection terminal is provided on one end of the IC chip. the

The above example is configured to flow a reference current, replicate this reference current with a current mirror circuit, and transfer this reference current to the unit transistor 634 in the final stage. When the image display is a black display (completely black screen), since each switch 641 is open, current does not flow through any of the unit transistors 634. Therefore, 0 (A) current flows through the source signal line 18, and no power is consumed. the

However, even during the black screen display period, the reference current still flows. In FIG. 161, the examples include currents Ib and Ic. They become reactive currents. The reference current effectively flows if configured to flow during current programming. Therefore, the flow of the reference current is restricted during the vertical and horizontal blanking periods of the image. And, during the waiting period, the flow of the reference current is restricted. the

To prevent the reference current from flowing, the static switch 1611 can be opened, as shown in FIG. 161 . This static switch is an analog switch. This analog switch is formed in the source driver IC14 which is the source driver circuit. Of course, the static switch 1611 is provided outside the IC 14 and can be controlled. the

When the static switch 1611 is turned off, the reference current Ib stops flowing. Therefore, current does not flow through the transistor 633a in the transistor group 681a1, and the reference current Ic is also reduced to 0A. Therefore, current also does not flow through transistor 633b in transistor group 681c. This improves the efficiency of the power supply. the

Figure 162 is a timing diagram. A blanking signal is generated in synchronization with the horizontal synchronizing signal HD. The period when the blanking signal is high corresponds to the blanking period. When the blanking signal is low, the video signal is applied. The static switch 1611 is turned off (open) when the blanking signal is low, and turned on when the signal is high. the

During the blanking period A when the static switch 1611 is turned off, the reference current does not flow. During the blanking period D when the static switch 1611 is turned on, the reference current flows. the

Incidentally, on/off control of the still switch 1611 can be performed based on image data. For example, when all the image data in the pixel row are black image data (for the period of 1H, the programming current output to all source signal lines 18 is 0), the static switch 1611 is turned off to stop the reference current ( Ic, Ib, etc.) flows. Also, a static switch can be formed or provided for each source signal line, and subjected to ON/OFF control. For example, when the odd-numbered source signal lines 18 are in black display mode (shown by vertical black bars), the corresponding static switches are turned off. the

With the structure shown in FIG. 124, the reference current Ib flows through the transistor 633 during the video period. According to the image signal, the switch 641 is turned on and off, and the current flows through the appropriate unit transistor 634 . During black screen display, all switches 641 are turned on. Even if the switch 641 is turned on, since the reference current Ib flows through the transistor 633, the unit transistor 634 tries to flow current. This lowers the inter-channel voltage (Vsd) of the cell transistor 634 (eliminates the potential difference between the source potential and the drain potential). The potential of the gate connection 1261 of the cell transistor 634 also drops at the same time. When the image is changed from a black screen to a white screen, the switch 641 is turned on, and the voltage Vsd is generated in the unit transistor 634 . There is a parasitic capacitance between the gate wiring 1261 and the internal wiring 634 (source signal line 18). the

A parasitic capacitance between the gate wiring 1261 and the internal wiring 643 (source signal line 18 ) causes potential fluctuations in the gate wiring 1261 together with Vsd in the cell transistor 634 . This potential fluctuation changes the output current of the unit transistor 634 . This variation in output current produces horizontal stripes and the like in the image. Where the image changes from white display to black display or from black display to white display, horizontal stripes appear. the

FIG. 151 illustrates fluctuations in potential in the gate wiring 1261. Connections occur at image change points (where the image changes from white display to black display, from black display to white display, etc.). the

Figure 152 shows one way to solve this problem. A resistor R is formed or set in the selector switch 641 . Specifically, instead of forming a resistor R, the size of the analog switch 641 is changed. Therefore, FIG. 152 is an equivalent circuit diagram of the switch 641 . the

The resistance in the switch 641 is designed to satisfy the following relationship:

R1<R2<R3<R4<R5<R6

D0 is provided by a cell transistor 634 . D1 is provided by 2 unit transistors 634 , and D2 is provided by 4 unit transistors 634 . D3 is provided by 8 cell transistors 634 . D4 is provided by 16 cell transistors 634 . D5 is provided by 32 transistors 634 . Therefore, the current flowing through the switches 641 increases as it goes from DO to D5. The on-resistance of the switches must also be reduced accordingly. On the other hand, connections as illustrated in Figure 151 must also be reduced. The structure shown in Fig. 152 makes it possible to reduce the connection and adjust the on-resistance of the switches. the

The connection of the gate line 1261 in Fig. 151 is caused by the presence of an image which cuts off all cell transistors 634 and the flow of the reference current Ib when all cell transistors 634 are turned off (see Fig. 153 and its similar graph). For the above reasons, the gate wiring 1261 of the cell transistor 643 is prone to potential fluctuations. the

Figure 127 and its ilk, showing structures involving multiple levels of current mirror connections. 129 to 133 show a single-stage structure. The problem of the unstable gate wiring 1261 has been described with reference to FIG. 151 . This instability is affected by the power supply voltage of the source driver IC 14, since this power supply voltage is diverted to the maximum voltage. Graph 211 shows the ratio of fluctuations in the gate wiring potential based on values obtained when the source driver IC 14 is at 1.8V. This fluctuation ratio increases with an increase in the power supply voltage of the source driver IC 14 . The allowable fluctuation rate range is about 3. A higher undulation rate will cause lateral crosstalk. The fluctuation rate relative to the power supply voltage tends to increase when the power supply voltage of the IC is 10 to 12V or higher. Therefore, the power supply voltage of the source driver IC14 should be 12V or less. the

On the other hand, in order to switch the driver transistor 11a from the current for white display to the current for black display, it is necessary to change the potential of the source signal line 18 to a certain extent. The desired amplitude variation range is 2.5V or more. Since the output voltage of the source signal line 18 does not exceed the power supply voltage, it is lower than the power supply voltage. the

Therefore, the power supply voltage of the source driver IC14 should be from 2.5V to 12V (both voltages included). The use of this range makes it possible to keep the fluctuation in the gate wiring 1261 within the specified range, eliminate horizontal crosstalk, and obtain normal image display. the

There is also a problem with the wiring resistance value of the gate wiring 1261 . In FIG. 215, the wiring resistance value (Ω) of the gate wiring 1261 is the wiring resistance value of its entire length from the transistor 633b1 to the transistor 63362, that is, the resistance value of the entire length of the gate wiring. The magnitude of the transient as shown in FIG. 151 also depends on one horizontal scanning period (1H), because the shorter the period of 1H, the greater the influence of the transient. A larger wiring resistance value (Ω) causes the transient phenomenon shown in Figure 151 to occur earlier. This phenomenon poses a problem particularly for the single-stage current reflection connection structures shown in FIGS. the

Fig. 212 is a graph in which the horizontal axis represents the product (R·T) of the wiring resistance value (Ω) of the gate wiring 1261 and the 1-H period T (seconds), and the vertical axis represents the fluctuation rate. This fluctuation rate is taken as 1 when R·T=100. It can be seen from FIG. 212 that when R·T is 5 or less, the fluctuation rate tends to become larger. When R·T is 1000 or more, the fluctuation rate also tends to become larger. Therefore, it is preferable that R·T is from 5 to 100 (both values inclusive). the

Another way to solve this problem is shown in Figure 153. In FIG. 153, a cell transistor 1531 through which a current flows stably is formed, that is, provided. These transistors 1531 are called steady state transistors 1531 . the

The steady state transistor 1531 constantly flows the current Is while the reference current Ib is flowing. Therefore, they do not depend on the magnitude of the programming current Iw. The flow of the current Is reduces the potential fluctuation of the gate wiring 1261 . Preferably, the current Is is as large as 2 to 8 times (both values inclusive) the current flowing through the cell transistor 634 . The steady-state transistor 1531 is constructed of a plurality of transistors having the same WL as the cell transistor 634 . Also, preferably, the steady-state transistor 1531 is formed at the farthest position from the transistor 633 passing the reference current Ib. the

Although forming a plurality of steady state transistors has been described with reference to FIG. 153, the present invention is not limited to these cases. A single steady state transistor 1531 as shown in FIG. 155 can be formed. Also, a plurality of steady state transistors 1531 may be formed at various locations as shown in FIG. 154 . In FIG. 154 , one steady state transistor 1531 a is formed close to transistor 633 , and four steady state transistors 1531 b are formed farthest from transistor 633 . the

In FIG. 154, switch S1 is formed for steady state transistor 1531b. The switch S1 is turned on and off according to the image data (D0 to D5). In the case of black screen image data (including image data close to the black screen (the high-order bit of D is 0), the output of the NOR (or not) circuit 1541 enters a high potential, and the switch S1 is turned on. The current I s2 flows through the steady state transistor 1531. Otherwise, the switch S1 remains open, and the current does not flow through the steady state transistor 1531. This structure can reduce power consumption.

Figure 163 shows a structure including both a steady state transistor 1531 and a static switch 1611. Therefore, it goes without saying that the structures already described herein can be used in combination. the

The dummy transistor group 681c is formed, that is, arranged outside the transistor groups 681c1 and 681cn located at both ends of the chip IC. Preferably, at least two dummy transistor groups 681c are formed on the left and right (outermost) sides of the chip IC. More preferably, 3 to 6 circuits (both numbers included) are formed. In the absence of inactive transistor population 681c, diffusion or etch processes during production of the IC would cause cell transistors 634 in the outer transistor population 681c to differ in Vt from those in the middle of IC chip 14. A difference in Vt will result in a change in the cell transistor 634 output current (programmed current). the

129 to 133 are block diagrams of driver ICs having a single-stage current mirror structure. The single-stage structure will be further described. Figure 215 shows the structure of a single-stage driver circuit. The transistor group 681c in FIG. 215 corresponds to the output stage structure constituted by the unit transistors 634 shown in FIG. 214 (see also FIGS. 129 to 133). the

The transistor 632b and the two transistors 633a constitute a current mirror circuit. The size of the transistor 633a1 and the transistor 633a2 are the same. Therefore, the current Ic flowing through the transistor 633a1 is the same as the current Ic flowing through the transistor 633a2. the

In FIG. 214, a transistor group 681c composed of unit transistors 634 constitutes a current mirror circuit together with a transistor 633b1 and a transistor 63362. There is a change in the output current of transistor population 681c. However, the transistor groups 681 that make up the current mirror circuit in close proximity to each other have their output currents accurately controlled. The transistor 633b1 and the transistor group 681c1 form a current mirror circuit at each close adjacent position. Also, the transistor 63362 and the transistor group 681cn form a current reflection circuit at adjacent positions close to each other. If the current flowing through transistor 633b1 and the current flowing through transistor 63362 are equal, the output current of transistor group 681c1 and the output current of transistor group 681cn are equal. If the current is accurately generated in each IC chip, the output current of the transistor group 681c is equal at both ends of the output stage in any IC chip. Therefore, even if the IC chips are cascaded, the seams between the ICs can be made imperceptible. the

As in the case of FIG. 123, a plurality of transistors 633b may be mounted to form a transistor group 681b1 and a transistor 68162. Multiple transistors 633a may be mounted to form transistor population 681a as in FIG. 123 . the

Although it has been stated that the current of the transistor 632b is regulated by the resistance value R1, this is not limitative. Electronic regulators 1503a and 1503b may be used, as shown in FIG. 218 . In the configuration shown in Figure 218, electronic regulators 1503a and 1503b can be operated independently. Therefore, the value of the current flowing through the transistors 632a1 and 632a2 can be changed. This makes it possible to adjust the slope of the output current in the output stage 681c at the left and right sides of the chip. Incidentally, it is also possible to install only one electronic regulator 1503, as shown in FIG. 219, and use it to control the two operational amplifiers 722. the

The static switch 1611 has been described with reference to FIG. 161. Needless to say, a static switch as shown in FIG. 220 can be similarly arranged or formed. In Figures 153, 154, 155, and 163, it has been described that the steady-state transistor 1531 is formed and arranged, and the steady-state transistor 1531 in Figure 226(b) can be formed and arranged in block A, as shown in Figure 225 illustrated. the

And, it has been described with reference to FIG. 160 that the capacitor 1601 has been connected to the gate wiring 1261 for stability, and it is obvious that the capacitor 1601 which plays a stabilizing role in FIG. In A. the

Also, as described with reference to Fig. 165 and its counterparts, the resistance and the like can be trimmed for adjusting the current. Similarly, it goes without saying that either resistor R1 or R2 can be trimmed, as illustrated in FIG. 225 . the

As already described with reference to FIG. 210, there are some conditions for the region where the transistor group 681 is constructed. However, the conditions in Figure 210 do not apply to the single-stage current mirror structures in Figures 129 to 133 and Figures 215 to 220, in which there are very many cell transistors 634. The output stage of the single-stage driver circuit will be additionally described below. Incidentally, for ease of explanation, FIGS. 216 and 217 will be taken as examples. but. Since the description relates not only to the number and total area of the unit transistors 634 but also to the number and total area of the transistors 633b, it is obvious that this description also applies to other examples. In FIGS. 216 and 217, let Sb represent the total area of transistors 633b in each transistor group 681b (here, the total area is the W and L dimensions of transistors 633b multiplied by the number of transistors 633b in each transistor group 681b). Incidentally, if the transistor group 681b is mounted on the left and right sides of the gate wiring 1261 as in FIGS. 216 and 217, the area is doubled. If there is one transistor, as shown in Fig. 129, then Sb is equal to the area of transistor 633b. If the transistor group 681b is composed of a single transistor 633b, it goes without saying that Sb is equal to the size of one transistor 633b. the

Also let Sc represent the total area of the unit transistors 634 in each transistor group 681c (here, the total area is the W and L sizes of the transistors 634 multiplied by the number of transistors 634 in each transistor group 681c). Assuming that the number of transistor groups 681c is n, in the case of a QCIF ⁺ panel, n is 176 (reference current circuits are formed for each of R, G, and B).

In FIG. 213, the horizontal axis represents Sc×n/Sb, and the vertical axis represents the undulation rate. The fluctuation rate in the worst case is taken as 1. As can be graphically illustrated in Figure 213, the fluctuation ratio becomes worse as Sc×n/Sb increases. A large Sc×n/Sb means that when the number n of output terminals is constant, the total area of unit transistors 634 in transistor group 681c is larger than the total area of transistors 633b in transistor group 681b. If so, the heave rate is unfavorable. the

A small value of Sc×n/Sb means that when the number n of output terminals is constant, the total area of the unit transistors 634 in the transistor group 681c is smaller than the total area of the transistors 633b in the transistor group 681b. If so, the fluctuation rate is small. the

The allowable range of fluctuation corresponds to a value of Sc×n/Sb of 50 or less. When Sc×n/Sb is 50 or less, the fluctuation rate falls within the allowable range, and the potential fluctuation of the gate wiring 1261 is extremely small. This makes it possible to eliminate horizontal crosstalk, keep the output variation within the allowable range, and obtain normal image display. When Sc×n/Sb is 50 or less, it is true that the undulation rate falls within the allowable range. However, reducing Scxn/Sb to 5 or less has little effect. On the contrary, Sb becomes larger, increasing the chip area of IC14. Therefore, it is preferable that Sc×n/Sb to 5 should be from 5 to 50 (both numbers inclusive). the

Also, the layout of the cell transistors 634 in the transistor group 681c has issues that need to be considered. The transistor population 681c should be arranged in order. Any voiding of a cell transistor 634 will cause the characteristics of the cell transistors 634 around it to differ from those of other cell transistors 634. the

FIG. 134 schematically illustrates the arrangement of the unit transistors 634 in the transistor group 681c of the output stage. 63 unit transistors 634 representing 64 levels are arranged in a matrix in order. However, although 64 unit transistors 634 can be arranged in 4 rows×16 columns, the arrangement of 63 unit transistors 634 creates vacancies (shaded areas). This makes the characteristics of the cell transistors 634 a , 634 b , and 634 c around the shaded region different from those of the other cell transistors 634 . the

To solve this problem, the present invention forms or arranges an invalid transistor 1341 in the shaded area. This makes the characteristics of the cell transistors 634a, 634b, and 634c coincide with those of the other cell transistors 634 . That is, by forming the dummy transistors 1341, the present invention arranges the unit transistors 634 in a matrix. And, without any omission, the unit transistors 634 are arranged in a matrix. In addition, the unit transistors 634 are also arranged in axis symmetry. the

Although it has been described that 63 unit transistors 634 are arranged in each transistor group 681c to represent 64 levels, the present invention is not limited to these cases. The unit transistor 634 may further be composed of a plurality of sub-transistors. the

FIG. 135 shows this unit transistor 634 . FIG. 135( b ) shows a one-unit transistor (single unit) 1351 composed of four sub-transistors 1352 . The cell transistor (single cell) 1351 is designed to be equal to the cell transistor 634 in output current. That is, the unit transistor 634 is composed of four sub-transistors 1352 . Incidentally, the present invention is not limited to the structure in which the unit transistor 634 is composed of four sub-transistors 1325 , but is applicable to any structure in which the unit transistor 634 is composed of a plurality of sub-transistors 1352 . However, designing the sub-transistors to be the same size produces the same output current. the

In FIG. 135, the letter S designates the source terminal of the transistor, G designates the gate terminal of the transistor, and D designates the drain terminal of the transistor. In FIG. 135(b), sub-transistors 1352 are arranged in the same direction. In FIG. 135(c), sub-transistors 1352 are arranged in different directions between different rows. In FIG. 135( d ), the sub-transistors 1352 are arranged in different directions along different columns, and are symmetrical with respect to a point. All arrangements in Figures 135(b), 135(c), and 135(d) are regular. the

Variations in the direction in which the cell transistor 634 or sub-transistor 1352 are formed often change their characteristics. For example, in FIG. 135(c), even though equal voltages are applied to the gate terminals of the unit transistor 634a and the sub-transistor 1352b, they both generate different output currents. However, in FIG. 135(c), in the same number, sub-transistors 1352 having different characteristics are formed. This reduces variation in the transistor (cell) as a whole. If the direction of the cell transistor 634 or the sub-transistor 1352 having different formation directions is changed, the differences in characteristic directions will complement each other, resulting in reduced variation in transistors (single cells). Needless to say, the above items also apply to the arrangement in Fig. 135(d). the

Therefore, as illustrated in FIG. 136 and its ilk, by changing the orientation of the cell transistor 634, it is possible to cause the characteristics of the cell transistor 634 formed in the vertical direction and the characteristics of the cell transistor 634 formed in the lateral direction to be different from each other in the transistor group. 681c as a whole complement each other, resulting in reduced variation in transistor population 681c as a whole. the

FIG. 136 shows an example in which cell transistors 634 are oriented differently between different columns within each transistor group 681c. FIG. 137 shows an example in which the cell transistors 634 are oriented differently between different rows within each transistor group 681c. FIG. 138 shows an example in which the cell transistors 634 are oriented differently not only between different columns but also between different rows within each transistor group 681 . Incidentally, these requirements are also observed when forming, ie, disposing, the inactive transistor 1341 . the

The above example involves configuring, ie forming, unit transistors of the same size, ie, the same current output, in the transistor group 681c (see FIG. 139(b)). However, the present invention is not limited to these cases, and the structure illustrated in FIG. 139(a) can also be used as follows. The cell transistor 634a of a single cell is connected (formed) to the 0th bit (switch 641a). The first bit (switch 641b) of the cell transistor 634b of 2-cell is connected (formed). The cell transistor 634c of the 4-cell is connected (formed) to the second bit (switch 641c). The cell transistor 634d of the 8-cell is connected (formed) to the third bit (switch 641d). The cell transistor 634a of the 16-cell is connected (formed) to the fourth bit (not shown). The cell transistor 634a of the 32-cell is connected (formed) to the fifth bit (not shown). Incidentally, for example, a 16-unit unit transistor is a transistor whose output current is equivalent to that output by 16 unit transistors 634 . the

By changing the channel width W proportionally (while keeping the channel length L constant), -n-units (n is an integer) of unit transistors can be easily formed. However, in practice, when the channel width W is doubled, the doubled output current is often not obtained. Therefore, the channel width W is determined experimentally by actually constructing a transistor. According to the invention, however, the channel W is assumed to be proportional even if the channel width W deviates more or less from the ratio. the

The reference current circuit will be described below. The output current circuit 704 is formed (set) for R, G and B one by one. RGB output current circuits 704R, 7046, and 704B are provided in close proximity. Also, the reference current INL in the low current region of FIG. 73 and the reference current INH in the high current region of FIG. 74 are adjusted for each color (R, G and B) (see also FIG. 79). the

Therefore, the output current circuit 704R for R is equipped with a regulator (or electronic regulator for voltage output or current output) 651RL to regulate the reference current INL in the low current region, and a regulator (or electronic regulator for voltage output Or current output electronic regulator) 651RH to regulate the reference current INH in the high current region. Similarly, the output current circuit 704G for G is equipped with a regulator (or electronic regulator for voltage output or current output) 651GL to regulate the reference current INL in the low current region, and a regulator (or electronic regulator for voltage output or current output electronic regulator) 651GH to adjust the reference current INH in the high current region. Also, the output current circuit 704B for B is equipped with a regulator (or an electronic regulator for voltage output or current output) 651BL to adjust the reference current INL in the low current region, and a regulator (or an electronic regulator for voltage output Or current output electronic regulator) 651BH to adjust the reference current INH in the high current region. the

Preferably, the regulator 651 and its ilk should be capable of adapting to temperature changes to compensate for the temperature characteristics of the EL element 5 . Needless to say, if there are two more turning points in the gamma shown in Fig. 79, then three or more electronic adjusters or resistors can be installed to adjust the reference currents for different colors. the

The output stage 761 is formed, that is, provided at the output terminal of the IC chip. They are connected to the source signal line 18 of the display screen. A bump is formed on the output table 761 by plating technique or ball bonding technique. The bumps should be 10 to 40 μm high (both heights included). the

The bump is electrically connected to the source signal line 18 through a conductive bonding layer (not shown). The conductive bonding layer is made of epoxy resin or phenol-based resin mixed with silver (Ag), gold (Au), nickel (Ni), carbon (C), tin dioxide (SnO ₂ ), and similar materials , or made of UV curable resin. A conductive bonding layer is formed on the bumps by transfer or other techniques. Also, the bump and the source signal line 18 are bonded by thermal pressing using ACF resin. Incidentally, the technique for connecting the bump, that is, the output pad 761, to the source signal line 18 is not limited to those described above. Alternatively, a thin-film carrier technology can be used instead of mounting the IC 14 on the array board. Also, a polyimide film and the like can be used to connect the source signal line 18 and the like.

Referring to FIG. 69, the inputted 4-bit current control data (DI) is decoded by a 4-bit decoder circuit 692 (needless to say, if there are 64 components, 6-bit decoding is used. code circuit. For ease of explanation, it is assumed that 4-bit data is used here). The output of the decoder is pushed up from the logic level voltage value to the analog level voltage value by the level shifter circuit 693 and sent to the analog switch 641 . the

The main components of the electronic regulator circuit are a fixed resistor R0 (691a) and 16 unit registers r (691b). The output from the decoder circuit 692 is connected to one of the 16 analog switches 641 and is used to determine the resistance value of the electronic regulator through the output from the decoder circuit 692 . For example, if the output of decoder circuit 692 is 4, the resistance value of the electronic regulator is RO+5r. The resistance value of the electronic regulator acts as a load on the first stage current source 631 and is boosted to the analog supply Avdd. Therefore, a change in the resistance value of the electronic regulator causes a change in the current value of the first stage current source 631 . This in turn causes a change in the current value of the second stage current source 632 , and thus a change in the current value of the third stage current source 633 . The output current of the driver IC is controlled in this way. the

Incidentally, although it has been assumed for the sake of illustration that 4-bit data is used for the current value control, this is not restrictive. Needless to say, the larger the bit count, the larger the number of steps in the current flow. Also, although it has been stated that the multi-stage current mirror has a three-stage structure, it goes without saying that this is not restrictive and any number of stages may be employed. the

In addition, in order to deal with the problem of variation in the emission luminance of the EL element due to temperature variation, it is preferable that the electronic adjustment circuit is equipped with an external resistor 691a whose resistance value varies with temperature. 33 and 35 and their counterparts, external resistors whose resistance value varies with temperature include thermistors, positive temperature coefficient thermistors, and the like. In general, light-emitting elements whose luminance varies with current flowing through themselves have temperature dependence, and their emission luminance varies with temperature even if the same value of current flows through them. By attaching an external resistor 691a whose resistance value varies with temperature to the electronic adjuster, it is possible to change the current value that outputs a constant current with temperature and keep the emission luminance constant even when the temperature changes. the

Preferably, the multi-level current mirror circuit is divided into three systems for red (R), green (G), and blue (B). Generally, organic EL or other current-driven light-emitting elements have different emission characteristics among R, G, and B. Therefore, to obtain the same luminance among R, G, and B, the current flowing through the light emitting element should be adjusted independently for R, G, and B. Also, a current-driven light-emitting element such as that used in an organic EL display panel has different temperature characteristics among R, G, and B. Therefore, characteristics such as auxiliary elements formed or set to compensate for temperature characteristics should also be adjusted individually for R, G and B. the

Since the multi-stage current reflection circuit is divided into three systems for red (R), green (G), and blue (B), the present invention makes adjustments to emission characteristics and temperature characteristics for R, G, and B individually, And thus make it possible to obtain the best white balance. the

As described earlier, in the case of current drive, only a small current is written to the pixel during black display. Therefore, if the source signal line 18 or the like has a parasitic capacitance, current cannot be sufficiently written into the pixel 16 during one horizontal scanning period (1H). Generally, in a current-driven light-emitting element, the current of the black level is as weak as several nA, and therefore, it is difficult to drive the parasitic capacitance (load capacitance of wiring), which is considered to be measured by the signal value of the black level current by several nA. Ten pF. To solve this problem, by applying a precharge voltage before writing the image data into the source signal line 18, the black level current in the pixel transistor 11a (basically, the transistor 11a is turned off) is equal to that of the source signal. It is useful that the potential levels of lines 18 are equal. In order to develop (build up) the precharge voltage, a constant voltage output black level is useful by decoding the higher order bits of the image data. the

FIG. 70 shows an example of a current output type source driver circuit (IC) 14 equipped with a precharge function according to the present invention. Fig. 70 shows the case where the precharge function is installed in the output stage of the 6-bit constant current output circuit. In FIG. 70, the precharge control signal is constructed so that it can decode the case where the higher order 3 bits D3, D4 and D5 in the image data DO to D5 are all zeros by the NOR circuit 702. , taking an AND circuit 703, using the output of the counter circuit 701 having a reset function based on the horizontal synchronizing signal HD from the dot clock pulse CLK, and thereby outputs the black level voltage Vp for a fixed period. In other cases, the output current from the current output stage 704 described with reference to FIG. 68 and the like is supplied to the source signal line 18 (the programming current is drawn from the source signal line 18). When the image signal consists of the 0th to 7th levels close to the black level, at the beginning of the horizontal period, by writing only the voltage corresponding to the black level for a fixed period, the above structure reduces the burden of current driving , and compensate for insufficient writes. Incidentally, it is assumed that the 0th gradation corresponds to a completely black display, and the 63rd gradation corresponds to a completely white display (in the case of a 64-gradation display). the

Preferably, the pre-charged levels should be limited to black display areas. Specifically, precharging is performed by selecting from the written image data in the black area (low brightness area, in the case of current driving, in this area, only a small (weak) write current flows). level (selective precharge) to complete. If precharging is performed over the entire range of gradation, the luminance is reduced in the white display area (the target luminance is not reached). And, in some cases, vertical stripes are shown. the

Preferably, selective precharging is performed on 1/8 of all levels starting from the 0th level (for example, in the case of 64 levels, after precharging the 0th to 7th levels, the image data is written enter). More preferably, selective precharging is performed on 1/16 of all levels starting from the 0th level (for example, in the case of 64 levels, after precharging the 0th to 3rd levels, the image data is written enter). the

A method of performing precharging by detecting only the 0th gradation is also effective in enhancing contrast, particularly in black display, which achieves extremely good black display. The problem is that the screen appears slightly white in tint when the entire screen is showing the first and second levels. Therefore, selective precharging is performed within a predetermined range: 1/8 of all levels starting from level 0. The image display is hardly damaged by extracting only the 0th level for precharging. Therefore, it is the most desirable to take this method as a pre-charging technique. the

Incidentally, it is useful to change the precharge voltage and gradation range among R, G and B because the emission start voltage and the emission luminance of the EL element 15 vary between R, G and B. For example, in the case of R, starting from that 0th level, selectively precharge 1/8 of all levels (for example, in the case of 64 levels, after precharging the 01st to 7th levels, image data is written). In the case of other colors (G and B), selective precharging starts from the 0th level and is performed on 1/16 of all levels (for example, in the case of 64 levels, the precharge for the 0th to the third level After charging, the image data is written). Regarding this precharge voltage, if for R, 7V is written into the source signal line 18, and for the other colors (G and B) 7.5V is written into the source signal line 18. The optimum precharge voltage often varies with the production batches of EL displays. Therefore, preferably, the precharge voltage can be adjusted by an external regulator or the like. Such a regulator circuit can also be easily implemented using an electronic regulator circuit. the

Incidentally, it is preferable that the precharge voltage is not higher than the anode voltage Vdd minus 0.5V and within the range of the anode voltage Vdd minus 2.5V in FIG. 1 . the

Even with the method of precharging only layer 0, it is useful to precharge one or two colors from among R, G, and B. This will cause less damage to the image display. the

It is preferable to provide several modes that can be switched by command, these modes include: the 0th mode that does not precharge, the first mode that only precharges the 0th level, and the 0th to 3rd level The second mode for precharging within the range, the third mode for precharging within the range from 0 to the seventh level, and the fourth mode for precharging over the entire level and so on. These modes can be easily realized by constructing (designing) a logic circuit in the source driver circuit (IC) 14 . the

Fig. 75 is a specific configuration diagram showing a selective precharge circuit. Reference letter PV denotes an input terminal of a precharge voltage. Set separate pre-charge voltages for R, G and B through external input or through electronic regulator circuit. Incidentally, although it has been explained that separate precharge voltages are set for R, G, and B, this is not restrictive. The precharge voltages may be common to R, G and B because they are related to the Vt of the drive transistor 11a of the pixel 16, and Vt is not different between R, G and B. If the W/L ratio etc. of the driver transistor 11a of the pixel 16 is varied among R, G and B (designed differently), it is preferable that the precharge voltage is adjusted to a different design. For example, a larger channel length L of the driver transistor 11a degrades the diode characteristic of the transistor 11a and increases the source-drain (SD) voltage. Therefore, the precharge voltage should be set lower than the power supply potential (Vdd). the

The precharge voltage PV is fed to the analog switch 731 . In order to reduce the on-resistance value, W (channel width) of the analog switch 731 should be 10 μm or more. However, it is set to 100 μm or less because too large a W will also increase the parasitic capacitance. More preferably, the channel width W should be between 15 μm and 60 μm (both dimensions included). The above items also apply to the analog switch 731 in the switch 641b of FIG. 75 and the analog switch 731 in FIG. 73 . the

The switch 641a is controlled by the precharge enable (PEN) signal, the selective precharge (PSL) signal, and the higher order three bits (H5, H4, and H3) of the logic signal in FIG. 74 . The higher order three bits (H5, H4 and H3) of the logic signal are referenced because when they are "0", selective precharging is performed. That is, precharging is selectively performed when the lower three bits are "1" (from the 0th to the seventh hierarchy). the

Incidentally, although selective charging is possible for fixed levels such as only the 0th level or within the range of 0th to 7th levels, it can be automatically performed in any specified low level area (in FIG. 79 , level 0 to level R1 ie level "R1-1"). Specifically, if a low-level area ranging from level 0 to level R1 is specified, selective precharge will automatically be performed within this range, and if a low-level area ranging from level 0 to level R2 is specified, then Selective precharge will automatically be performed within this range. This control system requires a smaller hardware scale than other systems. the

Switch 641a is turned on or off depending on which of the above signals is applied. When the switch 641a is turned on, the precharge voltage PV is applied to the source signal line 18 . Incidentally, during the period in which the precharge voltage PV is applied, it is set by a separately formed counter (not shown). This counter is structured to be set by command. Preferably, the application duration of the precharge voltage is from 1/100 to 1/5 of one horizontal scanning period (1H), both inclusive. For example, if 1H is 100 μsec, the application duration should be from 1 μsec to 20 μsec (from 1/100 to 1/5 of 1H), both times included. More preferably, it should be from 2 μsec to 10 μsec (from 2/100 to 1/10 of 1H), both times included. the

FIG. 173 shows a variation of FIG. 70 or 75 . It shows a precharge circuit which determines whether to perform precharge and controls the precharge based on input image data. For example, the precharge circuit can be set so that precharging occurs when the image data contains only level 0, precharge occurs when the image data contains only levels 0 and 1, or when level 0 occurs Precharging is always performed, and when the first level occurs continuously for a predetermined number of times or when the predetermined number of times is exceeded, precharging is performed. the

Fig. 173 shows an example of a current output type source driver circuit (IC) 14 equipped with a precharge function according to the present invention. Fig. 173 shows the case where the precharge function is incorporated in the output stage of the 6-bit constant current output circuit. In FIG. 173, a coincidence circuit 1731 performs decoding based on the image data DO to D5, and determines whether to perform precharging using inputs in the REN terminal equipped with a reset function based on the horizontal synchronizing signal HD and the dot clock CLK terminal. The coinciding circuit 1731 has a memory and retains the result of precharging with respect to image data for several H or several fields (frames). And, it has the ability to control pre-charging by determining whether to perform pre-charging according to the retained data. For example, coincidence circuit 1731 can be set so that precharging is always performed when level 0 occurs, and precharge occurs when level 1 occurs consecutively for 6H (six horizontal scanning periods) or more. Also, it can be set so that precharging is always performed when the 0th or first hierarchy appears, and precharging is performed when the second hierarchy successively appears for 3F (three frame periods) or more. the

The output from the coincidence circuit 1731 and the output from the counter circuit 701 are logically multiplied by an AND circuit 703, and thus the black level voltage Vp is output for a predetermined period. In other cases, the output current from the current output stage 704 described with reference to FIG. 68 and its ilk is applied to the source signal line 18 (from which the programming current Iw is drawn). Other parts of the structure are the same or similar to those shown in Figs. 70, 75, and the like, and therefore, their descriptions are omitted. Incidentally, although the precharge voltage is applied to point A in FIG. 173, it goes without saying that it can also be applied to point B (see FIG. 75). the

Good results can also be obtained if the application duration of the precharge voltage PV is varied using the image data supplied to the source signal line 18. For example, the application duration may be increased for a 0th gradation corresponding to a full black display, and decreased for a fourth gradation. Also, good results can be obtained if the duration of the application is specified in consideration of the difference between the image data and the image data to be applied after 1H. For example, after writing a current into the source signal line to put the pixel in the white display mode, when writing a current into the source signal line to put the pixel in the black display mode 1H, the precharge time should be increased . This is due to the use of a weak current for the black display. On the contrary, after writing a current into the source signal line to put the pixel in the black display mode, when writing a current into the source signal line to put the white pixel in the black display mode 1H, the precharge should be reduced time or should stop precharging (no precharging). This is because a large current is used for white display. the

It is also useful to change the precharge voltage according to the image data to be applied. This is because a weak current is used for a black display and a large current is used for a white display. Therefore, in the lower hierarchy region (when the P-channel transistor is used as the pixel transistor 11a), the precharge voltage is raised (relative to Vdd), and in the higher hierarchy region (when the P-channel transistor is used When used as the pixel transistor 11a), the precharge voltage is lowered. the

For ease of understanding, description will be made below mainly with reference to FIG. 75 . However, it goes without saying that the items described below are also applicable to the precharge circuits shown in FIGS. 70 and 175 . the

When the start of the program control current (P0 terminal) is "0", the switch 1521 is turned off, so that the IL terminal and the IH terminal are disconnected from the source signal line 18 (the Iout terminal is connected to the source signal line 18). Therefore, the programming current Iw does not flow through the source signal line 18 . the

When the programming current Iw is applied to the source signal line, the terminal P0 is “1”, and the switch 1251 is kept open so that the programming current Iw flows through the source signal line 18 . When no row of pixels is selected in the display area, "0" is added to the P0 terminal to open the switch 1251. The unit transistor 634 constantly draws current from the source signal line 18 according to the input data (D0 to D5). This current flows from the VDD terminal of the selected pixel 16 into the source signal line 18 through the transistor 11a. Thus, there is no path for current to flow from the pixel 16 to the source signal line 18 when no row of pixels is selected. After the time when an arbitrary pixel row is selected until the time when the next pixel row is selected, there occurs a period when no pixel row is selected. Incidentally, during a period in which no pixel (pixel row) is selected and there is no path for current to flow into (flow into) the source signal line 18 is referred to as a total non-selection period. the

In this state, if the IOUT terminal is connected to the source signal line 18, the current flows to the activated unit transistor 634 (actually, the activated transistor is controlled by the switch 641 through data from D0 to D5 terminals). Therefore, the charge in the parasitic capacitance of the source signal line 18 is discharged, rapidly lowering the potential of the source signal line 18 . Then, the source signal line 18 is normally written into the source signal line 18 with the time taken to restore the potential of the source signal line 18 . the

To solve this problem, the present invention adds "0" to the PO terminal to turn off the switch 1521 in FIG. Therefore, no current flows from the source signal line 18 to the unit transistor 634, and therefore, the potential of the source signal line 18 does not change during the total non-selection period. Thus, by controlling the PO terminal during the total non-selection period, and disconnecting the current source from the source signal line 18, it is possible to write the current normally. the

When a white display area (an area with a certain luminance) (white area) and a black display area (an area with a luminance below a predetermined level) (black area) coexist on the screen, and the ratio of the white area to the black area belongs to a certain range, because it is useful to increase the performance of stopping precharging (normal precharging) when vertical stripes appear in this range. On the contrary, precharging can be performed in a range because the images may act as noise when they move. Normal precharging can be easily realized by using an arithmetic circuit to count (calculate) pixel data corresponding to the white area and the black area. the

Since the emission start voltage and emission luminance of the EL element 15 vary among R, G and B, it is also useful to change the precharge voltage among R, G and B. For example, one possible method includes stopping or starting pre-charging of R when the ratio of white areas with a predetermined brightness to black areas with a predetermined brightness is 1 to 20 or more, and when the ratio of white areas with a predetermined brightness to black areas with a predetermined brightness When the black area ratio of the predetermined luminance is 1 to 16 or more, the precharging of G and B is stopped or started. It has been experimentally and analytically pointed out that in an organic EL screen, when the ratio of the white area with a predetermined brightness to the black area with a predetermined brightness is 1 to 100 or more (i.e., the black area is at least one hundred times larger than the white area) ), preferably, the pre-charging should be stopped. More preferably, the precharging should be stopped when the ratio of the white area with the predetermined brightness to the black area with the predetermined brightness is 1 to 200 or more (ie, the black area is at least 200 times larger than the white area). When the driver transistor 11a of the pixel 16 is a P-channel transistor, a voltage close to Vdd should be output from the source driver circuit (IC) 14 as a precharge voltage. (See Figure 1)

However, when the precharge voltage PV is closer to Vdd, a higher voltage is required for the semiconductor used in the source driver circuit (IC) 14 (however, the high voltage resistance is only on the order of 5V to 10V, and more than 5V The high voltage resistance will increase the price of the semiconductor process). Therefore, it is possible to adopt a high-resolution and low-cost process by using a 5V voltage-resistive process. the

If the 5V is not exceeded when the diode characteristics of the driver transistor 11a in the pixel 16 are good and the current when the path is established for the white display, then because this 5V process is also available for the source driver IC 14, there is no question. However, problems occur when the diode characteristics exceed 5V. Especially during precharging, since it is necessary to apply a precharging voltage PV close to the power supply voltage Vdd of the transistor 11a, it is impossible to generate an output from the IC 14. the

Fig. 92 shows a screen structure to solve this problem. In FIG. 92 , a switch circuit 641 is formed on the array board 71 . This source driver IC 14 outputs an ON/OFF signal to the switch 641 . This on/off signal is raised by the level shifter circuit 693 formed on the array board 71 and turns on and off the switch 641 . Incidentally, the switch 641 and the level shifter circuit 693 are formed simultaneously or successively in the process of forming the pixel transistor. Of course, an external circuit (IC) may be formed separately and mounted on the array board 71 . the

This ON/OFF signal is output from the terminal 761a of the IC 14 according to the precharge condition described earlier. Therefore, it goes without saying that this application and driving method of the precharge voltage is also applicable to the example shown in FIG. 92 . The voltage (signal) output from the terminal 761a is as low as 5V or less. This voltage (signal) is passed through the level shifter circuit 693 to have an amplitude raised to the on/off logic level of the switch 641 . the

With the above structure, a power supply voltage capable of driving the programming current Iw within the operating voltage range is sufficient for the source driver circuit (IC) 14 . The precharge voltage PV does not pose a problem to the array panel 71 having a high operating voltage. Therefore, the precharge voltage can be sufficiently applied up to the level of the anode voltage (Vdd). the

If the switch 1521 in FIG. 89 is formed (set) in the source driver circuit (IC) 14, there is also a problem of voltage resistance. This is because, for example, if the voltage Vdd of the pixel 16 is higher than the power supply voltage of the IC 14, there is a danger that a voltage high enough to damage the IC 14 is applied to the terminal 761 of the IC 14. the

An example that can solve this problem is shown in Figure 91. A switch circuit 641 is formed (provided) on the array board 71 . The structure, specifications, etc. of the switch circuit 641 are the same or similar to those described with reference to FIG. 92 . the

The switch circuit 641 is provided in front of the output of the IC 14 and in the center of the source signal line 18 . When the switch 641 is turned on, the current Iw used to program the pixel 16 flows into the source driver circuit (IC) 14 . When the switch 641 is turned off, the source driver circuit (IC) 14 is disconnected from the source signal line 18 . By controlling the switch 641, it is possible to realize the driving system illustrated in FIG. 90 and the like. the

The voltage (signal) output from the terminal portion 761a is 5 V or lower, as in the case of FIG. 92 . This voltage (signal) is passed through the level shift circuit 693 so that it has an amplitude raised up to the on/off logic level of the switch 641 . the

With the above structure, the power supply voltage capable of driving the programmed current Iw within the operating voltage range is sufficient for the source driver circuit (IC). Since the switch 641 also operates at the power supply voltage of the array board 71, even if this voltage is applied from the pixel 16 to the source signal line 18, neither the switch 641 nor the source driver circuit (IC) 14 is damaged. the

Incidentally, it goes without saying that both the switch 641 provided (formed) at the center of the source signal line 18 in FIG. structure shown in Figures 91 and 92). the

As described earlier, when the driver transistor 11a and select transistors (11b and 11c) of the pixel 16 are P-channel transistors, as shown in FIG. 1, a penetration voltage is generated. This is because the potential fluctuation of the gate signal line 17a permeates to one end of the capacitor 19 through the G-S capacitance (parasitic capacitance) of the selection transistors (11b and 11c). This voltage is set to Vgh when the P-channel transistor 11b is turned off. As a result, the terminal voltage of the capacitor 19 shifts slightly to the Vdd side. Therefore, the voltage at the gate terminal of the selection transistor 11a rises to produce a darker black display. This results in a normal black display. the

However, although a full black display of the 0th gradation can be obtained, it is difficult to display the 1st gradation and its ilk. In other cases, large gradation jumps may occur between the 0th and 1st gradations, or black reappearance may occur in particular gradation ranges. To solve this problem, the structure in Fig. 71 can be used. This structure is characterized by a function including leveling the output current value. The main purpose of trimmer capacitor circuit 711 is to compensate for this bleed voltage. It can also be used to adjust the black level so that even though the image data is at black level 0, some current (tens of nA) will still flow. the

Basically, Figure 71 is the same as Figure 64 except that a trimming capacitor circuit (encircled by the dashed line in Figure 71) has been added to the output stage. In FIG. 71, 3 bits (K0, K1, K2) are used as current trimming control signals. The 3 bits of this control signal make it possible to add a current value 0 to 7 times larger than that of the third-generation current source to the output current. the

The above is a basic overview of the source driver circuit (IC) 14 according to the present invention, and now, the source driver circuit (IC) 14 according to the present invention will be described in more detail. the

The current I(A) flowing through the EL element 15 and the emission luminance B(nt) have a linear relationship. That is, the current I(A) flowing through the EL element 15 is proportional to the emission luminance B(nt). In current drive, each stage (hierarchy level) is supplied by a current (cell transistor 634 (single cell)). the

Human vision has a square-law characteristic with respect to brightness. In other words, the square change of brightness is perceived as a linear brightness change. However, according to the relationship shown in FIG. 83, the current I(A) flowing through the EL element 15 is proportional to the emission luminance B(nt) in both the low luminance region and the high luminance region. Therefore, if the luminance is changed step by step (with a gap of one gradation), the low-gradation portion (dark area) greatly changes in each step (loss of shadow sharpness occurs). In the high-gradation portion (white area), since the luminance change approximately coincides with the linear portion of the quadratic curve, the luminance is perceived to change at equal intervals in each level. Therefore, especially how to display a black display area becomes a problem in the current driving in which the stages are supplied as current increments, ie in the current driving source driver circuit (IC) 14 . the

To solve this problem according to the invention, the output current slope is reduced in the low-level area (from level 0 (full black display) to level (R1)) and increased in the high-level area (from level R1 to the highest level (R )) output current slope, as shown in Figure 79. That is, in the low-level area, the current increment per level (in each stage) is reduced, and in the high-level area, the current increment per level (in each level) is increased. By changing the amount of change in current between the two stratification regions in Figure 79, it is possible to make the stratification characteristic curve close to the quadratic curve, thus eliminating the loss of shadow definition in the low stratification region, in Fig. 79 and its like The level-current characteristic curve illustrated in the same figure is called a gray scale curve. the

Incidentally, although in the above example, two current slopes were used—in the low-level region and in the high-level region—this is not limiting. It goes without saying that three or more slopes may be used. However, it goes without saying that the use of two slopes is preferable because it simplifies the circuit structure. Preferably, the grayscale curve may generate 5 or more slopes. the

The technical concept of the present invention lies in the use of two or more values of each level current increment in the current drive source original driver circuit (IC) and its similar circuits (basically, the circuit uses current output. Therefore, the display is not limited to active matrix type, and includes simple matrix type). the

In EL and other current-driven displays, the brightness of the display is proportional to the amount of current applied. Therefore, according to the source driver circuit (IC) 14 of the present invention, by adjusting the reference current providing the basis for the current flowing through one current source (one unit transistor) 634, the brightness of the display screen can be easily adjusted. the

In an EL display panel, there is a variation in luminous efficiency among R, G, and B, and a color purity deviates from NTSC (National Television System Committee) standards. Therefore, to obtain the best white balance, it is necessary to optimize the ratio between R, G and B. This optimization is done by adjusting the RGB reference currents individually. For example, the reference current for R is set to 2 μA, the reference current for G is set to 1.5 μA, and the reference current for B is set to 3.5 μA. Preferably, at least one of the reference currents for different colors can be changed, adjusted, controlled, as described above. the

The source driver circuit (source driver IC) 14 according to the present invention reduces the current reflection factor of the first stage current source 631 in FIGS. 67, 148, etc. (for example, the current flowing through the transistor 632b is reduced to 1/100, That is, if the reference current is 1μA, it is reduced to 10nA), making it possible to roughly adjust the reference current from the outside and accurately adjust the small current within the chip. Needless to say, the above items apply not only to the reference currents Ib and Ic in FIGS. the

An adjustment circuit for the reference current in the low-level area and an adjustment circuit for the reference current in the high-level area were installed to obtain the grayscale curve in FIG. 79 . Incidentally, Fig. 79 shows the method of gradation control by the one-point polygon gradation circuit. This is intended for ease of explanation, but the invention is not limited to this case. Needless to say, multi-point polygonal gray circuits can be used. the

Also, although not shown, an adjustment circuit for reference current in the low-level region and an adjustment circuit for reference current in the high-level region are separately provided for R, G, and B so that R , G and B make adjustments. Of course, if white balance is done by fixing one color and adjusting the reference current for two colors (i.e., R and B if G is fixed), then only two colors are used for reference in the low-level area. A regulating circuit for the current and a regulating circuit for the reference current are provided in the high-level area. the

In the case of current driving, the current that has flowed through the EL element has a linear relationship with the luminance, as also illustrated in FIG. 83 . In order to adjust the white balance by mixing R, G, and B, it is sufficient to adjust the reference current for R, G, and B at a predetermined brightness. In other words, if the white balance is adjusted by adjusting the reference currents for R, G, and B at a predetermined luminance, basically, the white balance can be obtained over the entire range of gradations. Therefore, the present invention is characterized not only by the single-point polygon or multi-point polygon grayscale curve generator circuit (generating means), but also by the adjusting means including adjusting the reference current for R, G and B. The above case is a circuit arrangement used only by a current-controlled EL display, not a liquid crystal display circuit. the

The gamma curve in Figure 79 creates a problem when used with LCD screens. To obtain RGB white balance, the grayscale curve must have the same turning point position (level R1 ) for R, G, and B. The current drive according to the invention can accommodate this problem because it makes equal relative positions between R, G and B in the gray scale curve. Also, the ratio between the slope in the low-level region and the slope in the high-level region must be the same among R, G, and B. The current drive according to the invention can accommodate this problem because it makes equal relative positions between R, G and B in the gray scale curve. the

Therefore, although there is a difference in slope between R, G, and B, the current driving according to the present invention is based on the relationship between the current I applied to the pixel 16 and the emission luminance of the EL element 15 as illustrated in FIG. Illustrates that the linear relationship works under the principle. The use of this relationship makes it possible to realize grayscale circuits on a small scale without disturbing the white balance in each level. the

The gradation circuit of the present invention, for example, increments 10nA per gradation in the low-gradation area (corresponding to the slope of the gray-scale curve in the low-gradation area). In the high-level region, it is incremented by 50nA per level (equivalent to the slope of the grayscale curve in the high-level region). the

Incidentally, the ratio of the current increment per gradation in the high gradation area to the current increment per gradation in the low gradation area is referred to as the gray scale current ratio. According to this example, the grayscale current ratio is 50nA/10nA=5. The same grayscale current ratio should be used for R, G and B. In other words, the current (programmed current) flowing through the EL element 15 is controlled by keeping the gray scale current ratio for R, G and B the same. the

Fig. 80 shows an example of a grayscale curve. In Fig. 80(a), there is an increase in current at large per-level increments in both low and high stratum regions, and in Fig. 80(a) Smaller incremental currents per level increase. However, in both Figures 80(a) and 80(b), the gray scale current ratios for R, G and B are the same. the

If in this way R, G and B maintain the same gray-scale current ratio and adjust the current, it becomes easier to construct this circuit. Then it only needs to construct a constant current circuit for generating a reference current to be applied to a low-level part, and a constant-current circuit for generating a reference current to be applied to a high-level part for each color in R, G, and B, and construct (set) A current regulator that relatively regulates the flow through the constant current circuit will suffice. the

FIG. 77 shows a circuit structure for changing the output current while maintaining the gray scale current ratio constant, when maintaining the gray scale current between the reference current source 771L for the low current area and the reference current source 771H for the high current area The current control circuit 772 varies the currents flowing through the current sources 633L and 633H while the ratio is constant. the

Preferably, the temperature of the display screen is detected by a temperature detecting circuit 781 formed in the IC chip (circuit) 14, as illustrated in FIG. 78 . This is because organic EL elements for R, G, and B vary in temperature characteristics related to their materials. This temperature detection is performed using a bipolar transistor formed in the temperature detection circuit 781. This is based on the principle that the junctions of bipolar transistors change their state with temperature, causing the output current of the bipolar transistor to vary with temperature. This detected temperature is fed back to the temperature control circuit 782 set (formed) for each color so that the current control circuit 772 compensates for the temperature. the

Incidentally, a suitable grayscale ratio is between 3 and 10 (both inclusive). More preferably, the grayscale ratio is between 4 and 8 (inclusive). Preferably, the grayscale current ratio is, inter alia, between 5 and 7 inclusive. The above relationship will be referred to as the first relationship. the

It is suitable to set a transition point (level R1 in Fig. 79) between the low-level part and the high-level part between 1/32 and 1/4 of the maximum number of levels K (including these two values) (For example, if the maximum number of levels K is 64 levels corresponding to 6-bit data, the transition point should be set to be between the second level (=64/32) and the sixteenth level (=64/4) More preferably, the transition point (level R1 in FIG. 79) between the low-level part and the high-level part is set to be between 1/6 and 1/4 of the maximum number k of levels between (including these two values) (for example, if the maximum number K of levels is 64 levels corresponding to 6-bit data, then the transition point should be set to between the fourth level (=64/16) and the sixteenth level levels (=64/4). Even better, it is set between 1/10 and 1/5 of the maximum number K of levels (including these two values) (by the way, the Any fractional part is rounded off. For example, if the maximum number K of levels is 64 levels corresponding to 6-bit data, then the transition point should be set to between the sixth level (=64/10) and the twelfth level ( =64/5). The relationship above will be called the second relationship.

Incidentally, the above description refers to the gradation current ratio between two current regions. However, this second relationship also applies to the gray-scale electrical-current ratio between three or more current drivers (ie, there are two or more turning points). That is, the relationship holds for any two of any three or more slopes. the

By satisfying the first and second relations, it is possible to obtain normal image display without loss of shadow definition. the

FIG. 82 shows an example in which a plurality of current-driven source driver circuits (ICs) according to the present invention are used for one display screen. The present invention assumes the use of multiple source driver ICs 14 . The source driver IC 14 has slave/master (S/M) terminals. the

When the S/M terminal is set to a high potential, the source driver circuit 14 works as a master chip, and outputs a reference current through a reference current output terminal (not shown). This current flows to the INL and INH terminals (in FIGS. 73 and 74 ) of the slave ICs 14 (14a and 14c). When the S/M terminal is set to a low potential, the source driver circuit 14 operates as a slave chip and receives a reference current from the master chip through a reference current input terminal (not shown). This current flows to the INL and INH terminals in FIGS. 73 and 74. the

Between the reference current input terminal and the reference current output terminal, different reference currents flow for different colors in two levels: low and high, and in the case of RGB three colors, this means 6 (=3×6 ) kind of reference current. Incidentally, in the above example, although two kinds of reference currents are used for each color, this is not restrictive, but three or more reference currents may be used for each color. the

According to the current drive of the present invention, the turning point (level R1 and its ilk) can be changed, as illustrated in FIG. 81 . In FIG. 81( a ), the low-level part and the high-level part are divided by the level R1, while in FIG. 81(b), the low-level part and the high-level part are divided by the level R2. In this way, the location of the turning point can be selected from among a plurality of locations. the

Specifically, the present invention can obtain 64 levels of display. The turning point can be set at any of the following positions: none, second level, fourth level, eighth level, and sixteenth level. Incidentally, the reason why the turning point can be the second, fourth, eighth, or sixteenth level is that the full black display corresponds to the Oth level. If an all-black display corresponds to the first level, the turning point may be the third, fifth, ninth, seventeenth, or thirty-third level. Thus, if the turning point is set to the nth level (or (n+1)th level if the full black display corresponds to the first level), where n is a power of 2, the fabrication of the circuit structure is easier . the

Fig. 73 is a block diagram showing a portion of a current source circuit for a low current region. Fig. 74 is a block diagram showing a current source portion for a high current region and a trimmer capacitor current circuit portion. As shown in FIG. 73, the reference current INL is supplied to the low current source circuit portion. Basically, this current is used as a cell current, and many cell transistors 634 are required to operate according to the input data L0 to L4. And the total current flows as the programmed current IwL for the low current part. the

Also as shown in FIG. 74, the reference current INH is supplied to the high current source circuit portion. Basically, this current is used as the cell current, many cell transistors 634 required to operate according to HO to L5, and the total current flows as the programmed current IwH for the low current part. the

The above situation applies to the trimming capacitor current circuit part. As shown in Fig. 74, the reference current INH is applied thereto. Basically, this current is used as a cell current, many cell transistors 634 required to operate according to the input data AK0 to AK2, and the total current flows as the current IwK corresponding to the trimming current. the

The programming current Iw flowing to the source signal line 18 is given by Iw=IwH+IwL+IwK. The ratio of IwH to IwL, that is, the grayscale current ratio should satisfy the first relationship described earlier. the

As illustrated in Figures 73 and 74, the on/off switch 641 is composed of a converter 732 and an analog switch 731, and the analog switch 731 is composed of a P-channel transistor and an N-channel transistor. This structure can reduce The on-resistance is small, and the voltage drop between the cell transistor 634 and the source signal line 18 is minimized. Needless to say, this also applies to other examples of the invention. the

Now, a description will be given of the low-current circuit portion in FIG. 73 and the large-current circuit portion in FIG. 74. The source driver circuit (IC) 14 according to the present invention is composed of 5 bits (L0 to L4) in the circuit portion of low current and 6 bits (H0 to H5) in the circuit portion of high current. Incidentally, data fed to this circuit from the outside consists of 6 bits D0 to D5 (64 gradations for each color). The 6-bit data is converted into 5-bit data (LO to L4) and 6-bit data (H0 to H5) in the high-current circuit part, and then, the programmed current corresponding to the image data Iw is added to the source signal line. That is, the 6-bit input data is converted into 11-bit data (=5+6). This makes it possible to form grayscale curves with high accuracy. the

As described above, the 6-bit input data is converted into 11-bit data (=5+6). According to the invention, the bit count (H) is equal to the bit count of the input data (D) in the high current region of the circuit, and the bit number (L) is equal to the bit count of the input data (D) in the low current region of the circuit. The special number is reduced by 1. Incidentally, the bit count (L) may be the bit number of the input data (D) minus 2 in the low current region of the circuit. This structure optimizes the gradation curve in the low current region and the gradation curve in the high current region for image display on the EL panel. the

Control methods for the circuit control data (LO to L4) in the low current region and the circuit control data (H0 to H4) in the high current region will be described below with reference to FIGS. 84 and 86 . the

The features of the present invention are shown by the operation of the transistor 634a connected to the L4 terminal cell in FIG. The cell transistor 634a is composed of transistors used as current sources for a single cell. By turning this transistor on and off, the programmed current Iw can be easily controlled (on/off control). the

Fig. 84 shows signals applied to the low current signal line (L) and the high current signal line (H) when the low current area and the high current area are divided by the fourth hierarchy. Incidentally, although in FIGS. 84 to 86, the 0th to 18th hierarchies are shown, actually there are hierarchies up to the sixty-third hierarchy. Thus, layers higher than the eighteenth are omitted in each figure. When the appropriate value in the table is "1", the switch 641 is turned on to connect the appropriate cell transistor 634 to the source signal line 18, and when the appropriate value in the table is "0", the switch 641 is turned off. the

Referring to FIG. 84, in the 0th level corresponding to full black display, (L0 to L4) = (0, 0, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0 ). Therefore, all the switches 641 are open, and the programmed current applied to the source signal line 18 is zero. the

In the first level, (LO to L4) = (1, 0, 0, 0, 0) and (HO to H5) = (0, 0, 0, 0, 0). Therefore, one cell transistor 634 in the low current region is connected to the source signal line 18 . In the high current region no cell current source is connected to the source signal line 18 . the

In the second level, (L0 to L4) = (0, 1, 0, 0, 0) and (HO to H5) = (0, 0, 0, 0, 0). Therefore, in the low current region, the two unit transistors 634 are connected to the source signal line 18 . No cell current source is connected to the source signal line 18 in the high current region. the

In the third level, (LO to L4) = (1, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, in the low current region, the two switches 641La and 641Lb are turned on, and the three unit transistors 634 are connected to the source signal line 18 . In the high current region, a cellless current source is connected to the source signal line 18 . the

In the fourth level, (L0 to L4) = (1, 1, 0, 0, 1) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, in the low current region, the three switches 641La, 641Lb, and 641Le are turned on, and the four unit transistors 634 are connected to the source signal line 18 . In the high current region, a cellless current source is connected to the source signal line 18 . the

In the fifth and higher levels, there is no change in the low current region, i.e., (Lo to L4) = (1, 1, 0, 0, 1), however, in the high current region, in the fifth level (HO to H5) = (1, 0, 0, 0, 0). Therefore, the switch 641Ha is turned on in the high current region, and a unit current source 641 is connected to the source signal line 18 . the

In the sixth hierarchy, (H0 to H5)=(0, 1, 0, 0, 0). Therefore, in the high current region, the switch 641Hb is turned on, and the two unit current sources 641 are connected to the source signal line 18 . Similarly, in the seventh hierarchy, (H0 to H5)=(1, 1, 0, 0, 0). Therefore, in the high current region, the two switches 641Ha and 641Hb are turned on, and the three unit current sources 641 are connected to the source signal line 18 . In the eighth hierarchy (HO to H5) = (0, 0, 1, 0, 0). Therefore, in the high current region, the switch 641Hc is turned on, and the four unit current sources 641 are connected to the source signal line 18, as illustrated in FIG. 84 . Successively, the switch 641 is turned on and off in turn, and the programmed current Iw is supplied to the source signal line 18 . the

The above operation is characterized in that, after the turning point, the programming current Iw applied to the high-level part is added by the current for the low-level part to the current corresponding to each stage (level) in the high-level part. A change point between the low current region and the high current region, specifically, in the high current region, a low current IwL is added to the programmed current Iw. So, calling it a "change point" might not be accurate. A trimming current IwK is also added. the

Also, the control bit (L), in the low level region, does not change (precisely, the point or location of the current change) after a level step. At this time, the L4 terminal in FIG. 73 is set to "1", the switch 641e is turned on, and a current flows through the unit transistor 643a. the

Therefore, in the fourth hierarchy in FIG. 84, in the lower-level portion, four unit transistors (current sources) 634 are in operation. In the fifth level, four unit transistors (current sources) 634 are in operation in the lower level part, and one transistor (current source) 634 is in operation in the upper level. Similarly, in the sixth hierarchy, four unit transistors (current sources) 634 are in operation in the lower-level part, and two transistors (current sources) 634 are in operation in the upper-level part. Thus, in the fifth level corresponding to the turning point and in subsequent levels, there are as many current sources 634 as levels (4 in this example) remaining on below the turning point in the lower level region, while current sources 634 in the higher level region Sources 634 are turned on sequentially corresponding to this level. the

It can be seen that at terminal L4 in FIG. 73, the cell transistor 634a is effectively operating. Without this transistor 643a, in the high-level part, the cell transistor 634 would be turned on after the third level. Therefore, the change points do not fall on powers of 2, such as 4, 8 or 16. Powers of 2 form only when a signal goes to "1". the

This makes it easy to judge whether a signal line weighted by 2 is set to "1". Therefore, the scale of hardware required for this judgment can be reduced. In other words, IC chip logic circuits can be simplified, making it possible to design ICs with small-area chips (resulting in low cost). the

FIG. 85 is an explanatory diagram illustrating signals applied to the low current signal (L) and high current signal lines (H) when the low current area and the high current area are divided by the eighth hierarchy. the

Referring to FIG. 85, in the 0th level corresponding to full black display, (L0 to L4) = (0, 0, 0, 0, 0) and (HO to H5) = (0, 0, 0, 0, 0 ). As in the case in Figure 84. Therefore, all the switches 641 are turned off, and the programming current Iw supplied to the source signal line 18 is zero. the

Similarly, in the first hierarchy, (L0 to L4)=(1,0,0,0,0) and (HO to H5)=(0,0,0,0,0). Therefore, one unit transistor 634 is connected to the source signal line 18 in the low current region. In the high current region, a cellless current source is connected to the source signal line 18 . the

In the second level, (LO to L4) = (0, 1, 0, 0, 0) and (HO to H5) = (0, 0, 0, 0, 0). Therefore, in the low current region, the two unit transistors 634 are connected to the source signal line 18 . In the high current region, no current source is connected to the source signal line 18 . the

In the third level, (L0 to L4)=(1,1,0,0,0) and (H0 to H5)=(0,0,0,0,0). Therefore, in the low current region, the two switches 641La and 641Lb are turned on, and the three unit transistors 634 are connected to the source signal line 18 . In the high current region, a cellless current source is connected to the source signal line 18 . the

Similarly, in the fourth hierarchy, (L0 to L4)=(0,0,1,0,0,) and (H0 to H5)=(0,0,0,0,0). In the fifth hierarchy, (L0 to L4)=(1,0,1,0,0) and (HO to H5)=(0,0,0,0,0). In the sixth level, (LO to L4) = (0, 1, 1, 0, 0,) and (H0 to H5) = (0, 0, 0, 0, 0). In the seventh level, (LO to L4)=(1,1,1,0,0,) and (HO to H5)=(0,0,0,0,0). the

The eighth level corresponds to change points (turning point positions). In the eighth hierarchy, (L0 to L4) = (1, 1, 1, 0, 1) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, in the low current region, the four switches 641La, 641Lb, 641Lc, and 641Le are turned on, and the eight unit transistors 634 are connected to the source signal line 18 . In the high current region, no current source is connected to the source signal line 18 . the

In the eighth and higher levels, there is no change in the low current region. That is, (LO to L4)=(1, 1, 1, 0, 1). However, in the high current region, (HO to H5) = (1, 0, 0, 0, 0) in the ninth hierarchy. Therefore, in the high current region, the switch 641Ha is turned on and a current source 641 is connected to the source signal line 18 . the

Similarly, in the high current region, the number of cell transistors 634 increases one by one as the level step increases. Specifically, at (HO to H5)=(0, 1, 0, 0, 0) at the tenth level. In the high current region, the switch 641Hb is turned on and the two cell current sources 641 are connected to the source signal line 18 . Similarly, in the eleventh level, (H0 to H5)=(1, 1, O, O, O). In the high current region, the two switches 641Ha and 641Hb are turned on and the three cell currents 641 are connected to the source signal line 18 . In the 12th level, (HO to H5) = (0, 0, 1, 0, 0). In the high current region, the switch 641Hc is turned on and the four unit current sources 641 are connected to the source signal line 18 . Next, the switch 641 is sequentially turned on and off and the programming current Iw is supplied to the source signal line 18, as illustrated in FIG. 84 . the

FIG. 86 is an explanatory diagram illustrating signals applied to the low current signal line (L) and the high current signal line (H) when the low current area and the high current area are divided by the 16th hierarchy. The basic operations are the same as those in Figs. 84 and 85 . the

Specifically, referring to FIG. 86, in the Oth level corresponding to all black display, (LO to L4)=(0,0,0,0,0) and (HO to H5)=(0,0,0, 0, 0), as in the case in Fig. 85. Therefore, all the switches 641 are turned off and the programming current Iw supplied to the source signal line 18 is zero. Similarly, from the first to the 16th hierarchy, (HO to H5) = (0, 0, 0, 0, 0) in the high current region. Therefore, one unit transistor 634 is connected to the source signal line 18 in the low current region. In the high current region, a cellless current source is connected to the source signal line 18 . That is, only L0 to L4 vary in the low current region. the

Specifically, in the first level, (LO to L4) = (1, 0, 0, 0, 0), in the second level, (L0 to L4) = (0, 1, 0, 0, 0 ), in the third level, (1, 1, 0, 0, 0), and in the fourth level, (L0 to L4)=(0, 0, 1, 0, 0). This continues to level 16. Specifically, in the 15th level, (L0 to L4) = (1, 1, 1, 1, 0) and in the 16th level, (L0 to L4) = (1, 1, 1, 1, 1 ). In the 16th level, there is only the fifth bit (D4) among DO to D5 representing the opening of the levels. Therefore, it can be determined from the data signal line (D4) that the data DO to D5 represent the 16th level. This reduces the hardware scale for logic circuits. the

The 16th level corresponds to a change point (turning point position). Rather, it should be said that level 17 corresponds to a change point. At the 16th level (L0 to L4) = (1, 1, 1, 1, 1), and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, in the low current region, the four switches 641La, 641Lb, 641Lc, 641d, and 641Le are turned on and the 16 unit transistors 634 are connected to the source signal line 18 . In the high current region, a cellless current source is connected to the source signal line 18 . the

In the 16th and higher levels, there is no change in the low current region, ie (L0 to L4) = (1, 1, 1, 0, 1). However, in the high current region, in the 17th hierarchy, (HO to H5) = (1, 0, 0, 0, 0). Therefore, in the high current region, the switch 641Ha is turned on and one unit transistor 641 is connected to the source signal line 18 . the

Similarly, in the high current region, the number of cell transistors 634 increases one by one as the level step increases. Specifically, in the 18th hierarchy, (H0 to H5)=(0, 1, 0, 0, 0). In the high current region, the switch 641Hb is turned on and the two cell current sources 641 are connected to the source signal line 18 . Similarly, in the 19th level, (HO to H5) = (1, 1, 0, 0, 0). In the high current region, the two switches 641Ha and 641Hb are turned on and the three unit current sources 641 are connected to the source signal line 18 . In the 20th level, (HO to H5) = (0, 0, 1, 0, 0). Therefore, in the high current region, the switch 641Hc is turned on and the four unit current sources 641 are connected to the source signal line 18 . the

The above approach leads to extremely easy logic processing, such as turning on (or turning off in another configuration) current sources (transistors of a single cell) 634, equal in number to powers of 2 or placing them at change points (turning point positions ) is connected to the source signal line 18. the

For example, if the turning point location corresponds to the fourth level (4 is a power of 2), as illustrated in FIG. 84, at this location, four current sources (single cells) 634 are turned on. Then, in the high current region, a current source (single cell) 634 is added in subsequent layers. the

On the other hand, if the turning point location corresponds to the 8th level (8 is a power of 2), as illustrated in FIG. 85, at this location, 8 current sources (single cells) 634 are turned on. Then, in the high current region, a current source (single cell) 634 is added in subsequent layers. The present invention realizes not only the gradation control circuit for 64-gradation display, but also the gradation control circuit for any gradation display (including 16-gradation display with 4,096 colors and 16,700,000 gradations) with a small hardware structure. 256 levels of color display) possible. the

Incidentally, although in the examples described with reference to Figs. 84, 85 and 86, it has been stated that the change point is set to the n-th level, where n is a power of 2, but only in the full black display corresponding to the 0th level The time is right. If an all black display corresponds to the first level, then n+1. the

It is important in the present invention to provide multiple current regions (low current region, high current region, etc.) and to be able to judge (process) change points between current regions with a small number of signal inputs. For example, the technical concept behind the present invention is that if a power of 2 is used, only one signal line needs to be detected, thereby greatly reducing the hardware scale. Also, adding a current source 634a reduces the processing required for that case. the

In the case of negative logic, the change point can be set to 1, 3, 7, 15 or the like instead of 2, 4, 8 or the like. Also, although it has been stated that level 0 corresponds to a full black display, this is not restrictive. For example, in the case of 64-level display, the 63rd level can be designated as full black display, and the 0th level can be designated as maximum white display. If so, consider the opposite direction to handle the point of change. Therefore, it may not be processed in terms of powers of 2. the

The change point (position of turning point) is not limited to a single grayscale curve. Circuits according to the invention allow for two or more turning point locations. For example, the turning point positions can be set to the fourth and 16th levels. Alternatively, the turning point positions may be set to more than 2 positions such as the fourth, 16th, and 32nd levels. the

In the above example, the turning point is set at the nth level, where n is a power of 2, but this is not restrictive. For example, the turning point can be set to a level given by the sum of 8 and 8, both of which are powers of 2 (2+8=10, ie two signal lines are required for judgment). Alternatively, the turning point can be set to a level given by the sum of 2, 8, and 16, these three numbers are all powers of 2 (2+8+16=28; that is, three signal lines are required for judgment ). If that is the case, the scale of hardware required for judgment or processing is more or less increased, but it is not difficult to solve as far as the circuit structure is concerned. And, needless to say, the above contents are included in the technical scope of the present invention. the

As shown in FIG. 87 , the source driver circuit (IC) 14 according to the present invention is composed of three current output circuits 704 . They are the current output circuit 704a of the high current region operating in the high current region, the current output circuit 704b of the low current region operating in the low and high current regions, and the current output circuit 704b of the low current region outputting the trimming current. the

The current output circuit 704a for the high current region and the current output circuit 704c for trimming the current work together with the reference current source 771a, which outputs a large current as the reference current. The current output circuit 704b in the low current area works together with the reference current source 771b, and it outputs a low current as the reference current. the

As described earlier, the number of current output circuits is not limited to three, the current output circuit 704a in the high current region, the current output circuit 704b in the low current region, and the current output circuit 704c for trimming the current. The source driver circuit (IC14 may be composed of two current output circuits 704—the current output circuit 704a of the high current region and the current output circuit 704b of the low current region—or three or more current output circuits 704. And, it may be related The circuit output circuit 704 is set to form a reference current source 771, or a common reference current source 771 is installed for all current output circuits 704.

The current output circuit 704 is controlled by hierarchical data, and the unit transistors 634 operate among them by the current drawn from the source signal line 18 . The described case and unit transistor 634 operates synchronously with the horizontal scanning period (1H) signal. That is, current is fed for a period of 1H (if the cell transistor is an N-channel transistor) according to appropriate hierarchical data. the

On the other hand, the gate driver circuit 12 selects the gate signal line 17a substantially one-to-one in synchronization with the 1-H signal. That is, in synchronization with the 1-H signal, the gate signal line 17a(1) is selected in the first horizontal scanning period, the gate signal line 17a(2) is selected in the second horizontal scanning period, and the gate signal line 17a( 3) is selected in the third horizontal scanning period, and the gate signal line 17a(4) is selected in the fourth horizontal scanning period. the

However, between the moment when the first gate signal line 17a is selected and the moment when the second gate signal line 17a is selected, there is a period during which no gate signal line 17a is selected (non-selected period, See t1) in Figure 88. The rising period and falling period of the first gate signal line 17a are necessary for the non-selection period in order to secure the on/off control period for the selection transistor 11d. the

If the turn-on voltage is applied to any one of the gate signal lines 17a, and the transistor 11b and the selection transistor 11c of the pixel 16 are turned on, the programming current Iw flows from the Vdd supply (anode voltage) to the source signal through the driver transistor 11a Line 18. The programming current Iw flows through the cell transistor 634 (over the period t2 in FIG. 88). Incidentally, a parasitic capacitance C occurs in the source signal line 18 (this parasitic capacitance is caused by the capacitance at the junction of the source signal line and the gate signal line). the

However, when no gate signal line 17a is selected (non-selected period; t1 in FIG. 88), there is no current path on the transistor 11a. As the cell transistor 634 passes current, charges from the parasitic capacitance on the source signal line 18 are absorbed. This lowers the potential of the source signal line 18 (part A in FIG. 88). When the potential of the source signal line 18 is lowered, it takes time for the next image data write current. the

To solve this problem, a switch 641a is formed at an output terminal of the source terminal 761, as illustrated in FIG. 89 . In addition, a switch 641b is formed, that is, provided, in the output stage of the current output circuit 704c for trimming the current. the

During the non-selected period t1, the control signal is applied to the control terminal S1, and the switch 641a is turned off. During the selected period t2, the switch 641a is turned on (conducting). When the switch 641a is turned on, the programmed current Iw=IwH+IwL+IwK flows. When the switch 641a is open, the circuit Iw does not flow. Therefore, as illustrated in Figure 90, this potential drops to the level indicated by A in Figure 88 (no change). Incidentally, the channel width W of the analog switch 731 in the switch 641 should be between 10 μm and 100 μm (both dimensions included). The channel width W of the analog switch must be 10 μm or larger in order to reduce the on-resistance value. However, it must not be larger than 100 μm, because too large a W will increase the parasitic capacitance. More preferably, the channel width is between 15 and 60 μm (both dimensions included). the

The switch 641b controls only when the lower level is displayed. When low-level display (black display), the gate potential of the transistor 11a of the pixel 16 must be close to Vdd (therefore, when black is displayed, the potential of the source signal line 18 must be close to Vdd). Also, during black display, the programming current is small, and once the potential falls as indicated in FIG. 88, it takes time for the potential to return to normal. the

Therefore, during low-level display, the non-selection period t1 must be avoided. In contrast, during high-level display, since the programming current Iw is large, the non-selection period t1 often poses no problem. Therefore, according to the present invention, when an image is written for high-level display, both the switch 641a and the switch 641b are kept turned on even during the non-selection period. Moreover, the fine-tuning current IwK must be disconnected to obtain the maximum black display. When an image is written for low-level display, even during the non-selection period, the switch 641a is kept on and the switch 641b is kept off. Switch 641b is controlled through terminal S2. the

Incidentally, during the non-selection period t1, it is also possible to keep the switch 641a off (non-conductive) and keep the switch 641b on (conductive) for both the low-level display and the high-level display. Of course, during the non-selection period t1, the switches 641a and 641b may be kept open (non-conductive) for both the low-level display and the high-level display. In both cases, whichever occurs, the switch 641 can be controlled by controlling the control terminals S1 and S2. Incidentally, the control terminals S1 and S2 are controlled by command control. the

For example, the control terminal S2 sets a period of t3 to logic 0 in such a manner as to overlap the non-selected period t1. This control eliminates the situation indicated by A in FIG. 88 . When the level indicates that the black display is deeper than a certain level, the control terminal S1 is set to logic 0. The trimming current IwK is then stopped to create a darker black display. the

In a typical driver IC, protection diodes 1671 are formed near the output (see FIG. 167). A protection diode 1671 is formed to prevent IC14 from being damaged by external static electricity. Usually, these protection diodes 1671 are formed between the output wiring 643 and the power supply Vcc or between the output wiring 643 and the ground. the

The protection diode 1671 is effective against electrostatic damage. However, static electricity is regarded as a capacitor (parasitic capacitance) in an equivalent circuit. In current driving, there is a parasitic capacitance at the output terminal 643 which makes it difficult to write current. the

The present invention provides a solution to this problem. The source driver IC 14 is fabricated with a protection diode 1671 formed at the output stage. The manufactured source driver IC 14 is mounted on the array board 71 , and the output terminal 761 is connected to the source signal line 18 . After connecting the output terminal 761 to the source signal line 18, the output wiring 643 is cut at points a and b with a laser 1502, as illustrated in FIG. 169(a), to cut off the protection diode 1671. And, as illustrated in Figure 169(b), the laser 1502 is aimed at points c and d to cut the wire. Therefore, the protection diode 1671 becomes isolated. the

In this way, by disconnecting the protection diode 1671 , that is, the isolation diode 1671 from the output wiring 643 , it is possible to prevent the generation of parasitic capacitance in the protection diode 1671 . In addition, since the protection diode 1671 is disconnected from the output wiring 643 after mounting the IC 14 , that is, the isolation protection diode 1671 does not suffer from electrostatic damage. the

Incidentally, the laser light 1502 is aimed at the back surface of the array plate 71 as illustrated in FIG. 168 . The array plate 71 made of glass has light transparency. Therefore, the laser light 1502 can pass through the array plate 71 . the

In the above examples it has been assumed that a source driver circuit IC14 is provided on the display screen. However, the present invention is not limited to this configuration. Multiple source driver ICs 14 may be mounted on the display screen. FIG. 93 shows an example in which three source driver ICs 14 are mounted on the display screen. the

As also described with reference to FIG. 82 , the source driver IC 14 according to the present invention supports the use of two or more current-driven source driver circuits (ICs) 14 . Therefore, the source driver IC 14 has slave/master (S/M) endpoints. When the S/M terminal is set to a high potential, the source driver circuit 14 works as a master chip, and outputs a reference current through a reference current output terminal (not shown). Of course, the logic on the S/M side can be reversed. the

Slave/master switching can be performed by an instruction to the source driver IC 14 . The reference current is transmitted via the cascaded current connection 931 . When the S/M terminal is set to low potential, IC 14 works as a slave chip and receives a reference current from the master chip through a reference current input terminal (not shown). This current flows to the INL and INH terminals in FIGS. 73 and 74. the

As an example, the reference current is generated by the current output circuit 704 right at the center of the IC chip 14 . The reference current for the master chip is adjusted with an external resistor or an electronic regulator of the internal ladder current before the reference current is applied. the

A control circuit (command decoder) and the like are also formed in the center of the IC chip 14 . The reason why the reference current source is formed in the center of the chip is to minimize the distance to the reference current generator circuit and the programmed current output terminal 761 . the

In the structure of FIG. 93, the reference current is transmitted from the master chip 14b to two slave chips (14a and 14c). Upon receiving this reference current, the slave chips generate the first generation, second generation, and third generation currents according to the received reference current. Incidentally, the master chip 14b transfers current to the slave chip as current-based transfer between circuit reflection circuits (see FIG. 67). The use of current-based transfer not only eliminates bonding wires on the screen, but also eliminates deviations in the reference current between chips. the

Figure 94 conceptually illustrates the location of the endpoints between which the reference current is passed. In the center of the IC chip, the reference current signal line 932 is connected to the signal output terminal 941i. The current (or voltage; see FIG. 76) applied to the reference current signal line 932 has been compensated for the temperature characteristic of the EL material. Also, aging of the EL material has been compensated. the

The current sources ( 631 , 632 , 633 and 634 ) are driven in the chip 14 according to the current (voltage) applied to the reference current signal line 932 . The reference current generated here is output as a reference current for the slave chip through the current mirror circuit. The reference current for the slave chip is output from the terminal 941o. At least one terminal 941 o is provided (formed) on each side of the current output circuit 704 . In FIG. 94, two ends 9410 are provided (formed) on each side. The reference current is transmitted to the slave chip 14a through the cascaded signal lines 931a1, 931a2, 931b1, and 931b2. Incidentally, it is also possible to correct the deviation by feeding back the reference current applied to the slave chip 14a to the master chip 14b. Problems encountered in modular organic EL panels include the resistance values of the anode wiring 951 and the cathode wiring. In an organic EL display panel, although the EL element 15 requires a relatively low driving voltage, the current flowing through the EL element 15 is large. Therefore, it is necessary to increase the size of the anode wiring and the cathode wiring for supplying current to the EL element 15 . For example, even in a 2-inch class EL panel, if a polymeric EL material is used, a current of 200 mA or more must flow through the anode wiring 951 . In order to reduce the voltage drop in the anode wiring 951, the resistance value of the anode wiring 951 must be reduced to 1Ω or less. However, with the array board 71, the wiring on which has been formed by thin film vapor deposition, it is difficult to reduce its resistance value. So the width of the graph must be increased. However, to deliver 200mA with minimal voltage drop, the wire must be at least 2mm wide. the

Fig. 105 shows the structure of a conventional EL panel. Built-in gate driver circuits 12 a and 12 b are formed (arranged) on both sides of the display screen 50 . The source driver circuit 14p (built-in source driver circuit) is formed by the same process as that of the pixel 16 transistor. the

Anode wire 951 is provided on the right side of the screen. A Vdd voltage is applied to the anode connection 951 . For example, the width of the anode wire 951 is 2 mm or more. An anode wire 951 extending along the bottom of the screen branches to the top of the screen. The number of branches is equal to the number of pixel columns. For example, a QCIF screen has 528 (=176*RGB) pixel columns. On the other hand, the source signal line 18 is led out from the built-in source driver circuit 14p. The source signal line 18 continues from the top of the screen to the bottom. The power supply wiring 1051 of the built-in gate driver circuit 12 is also arranged on the left and right sides of the screen. the

Therefore, the screen width on the right side of the display cannot be reduced. Today, screen width is important for display screens for mobile phones and their ilk. It is also important to provide equal screen widths on the left and right of the screen. However, it is difficult to reduce the screen width with the structure in FIG. 105 . the

To solve this problem, in the display panel according to the present invention, an anode wiring 951 is provided (formed) on the array surface behind the source driver IC 14, as shown in FIG. 106 . The source driver circuit (IC) 14 is made of a semiconductor chip, and the panel is mounted on the array board 71 using COG (chip on glass) technology. The anode wiring 951 can be provided (formed) on the source driver IC 14 because under the chip 14 there is a space of 10 [mu]m to 30 [mu]m perpendicular to the board. the

As shown in FIG. 105, if the source driver circuit 14P is directly formed on the array board 71, it is difficult to form the anode line 951 (basically the anode line 951) above or below the source driver circuit 14P due to the number of masks, productivity and noise problems. , anode voltage line, and main anode line). the

And, as illustrated in FIG. 106, a common anode line 962 is formed, and the basic anode line 951 and the common anode line 962 are short-circuited by the connection anode line 961, one of which is to form the connection anode line 961 at the IC chip. central. Connecting the anode line 961 eliminates the potential difference between the basic anode line 951 and the common anode line 962 . Another point is that the anode line 952 is branched from the common anode line 962 . This structure eliminates the routing of the anode wiring 951, such as the one in Fig. 105, and therefore, a reduction in screen width can be obtained. the

If the length of the common anode wire 962 is 20 mm, if the wiring width is 150 μm, and if the sheet resistance of the wiring is 0.05Ω/port, then the resistance value is 20000 (μm)/150 (μm)×0.05Ω=about 7Ω. If both ends of the common anode line 962 are connected to the basic anode line 951 through the connecting anode line 961c, the common anode line 962 is powered from both sides, and therefore, the apparent resistance value is 3.5Ω (=7Ω/2). If this value is converted into a lumped distribution coefficient, the apparent resistance value of the common anode line 962 is further halved and becomes 2Ω or less. Even with an anode current of 100mA, the voltage drop across the common anode line 962 is 0.2v or less. Also, if the common anode line 962 and the basic anode line 951 are short-circuited through the connecting anode line 961b in the center, there is almost no voltage drop. the

The feature of the present invention is by forming the basic anode line 951 below the IC14, forming the common anode line 962, electrically connecting the common anode line 962 to the basic anode line 951 (connecting the anode line 961), and branching the anode line 952 from the common anode line 962 to show. the

Incidentally, the pixel structure according to the present invention is described by taking the pixel structure in FIG. 1 as an example. Therefore, the cathode electrode is described as a solid electrode (an electrode common to each pixel 16), and the anode electrode is described as a wiring. However, depending on the structure of the driver transistor 11a (N-ditch or P-ditch) or depending on the pixel structure, it is necessary to use a solid electrode as an anode and lay a metal wire as a cathode. Therefore, the present invention is not limited to the laying of anode wires. The present invention relates to anodes or cathodes requiring wiring. Therefore, if the cathode needs to be laid as a wire, the description herein for the anode applies to the cathode. the

In order to reduce the resistance value of the anode wire (basic anode wire 951, common anode wire 962, connecting anode wire 961, anode wire 952), electroless plating, electrolytic plating, or other methods can be used after laying film wiring or before making patterns The technique uses layering of conductive materials to form thick films. The use of a thick film increases the cross-sectional area of the wiring and thus lowers the resistance value. The items above apply similarly to the cathode. They also apply to the gate signal line 17 and the source signal line 18 . the

It is effective to provide and use the common anode line 962, which is powered from both sides through the connection anode line 961, and the formation of the connection anode line 961b (961c) in the center reinforces this effect. Also, the basic anode line 951, the common anode line 962, and the connection anode line 961 form a loop, which weakens the electric field generated in the IC14. the

Preferably, the common anode wire 962 and the basic anode wire 951 are made of the same metal material. The connecting cathode limit 961 is also made of the same metal material. Also, the anode lines are realized by using a metal material or a structure forming an array, and have a low resistance value. Usually, they are implemented using the same metal material and structure (SD thin layer) as the source signal line 18 . The same material cannot be used where the common anode line 962 intersects the source signal line 18 . Therefore, another metal material (same material and structure as the gate signal line 17; GE thin layer) is used for the intersections, which are then electrically insulated with an insulating film. Of course, the anode line can be constructed by laminating a film made of the same material as the source signal line 18 and a film made of the same material as the gate signal line 17 . the

Incidentally, although it has been described that a wiring such as an anode wiring (cathode wiring) is laid on the back surface of the source driver IC 14 to supply current to the EL element 15, this is not restrictive. For example, the gate driver circuit 12 can be constructed with one IC chip, and this IC can be mounted by COG. Then, an anode wiring and a cathode wiring are laid and formed on the back surface of the gate driver IC 12 . the

Therefore, the present invention relates to making a driver IC with a semiconductor chip, mounting this IC directly on a substrate such as an array board 71, and forming (manufacturing) a driver IC for an EL display device or the like in a space on the back side of this IC chip. Power to the unit or grounding patterns such as anode and cathode connections. the

The above items will be described in more detail with reference to other drawings. Fig. 95 is an explanatory diagram illustrating a part of a display screen according to the present invention. In FIG. 95, dotted lines indicate positions where IC chips 14 are to be placed. That is, basic anode lines (anode voltage lines, i.e., anode wiring before branching) are formed (disposed) on the back of the IC chip 14 and the front of the array board 71. In this example of the present invention, although it is stated that the anode wiring 951 is formed on the backside of the IC chips (12 and 14) before branching, this is only for ease of explanation. For example, instead of the anode wiring 951 being formed before branching, a cathode wiring or a cathode film may be formed (provided) before branching. In addition, the power supply wiring 1051 of the gate driver circuit 12 may also be provided or formed. the

The IC chip 14 has its current output (current input) terminal 741 connected to the connection terminal 953 formed on the array board 71 by the COG technique. A connection terminal 953 is formed on one end of each source signal line 18 . The connecting ends 953 are arranged in a staggered arrangement of mutually alternating 953a and 953b. A connection terminal 953 is formed on one end of the source signal line, and a terminal electrode for detection is formed on the other end. the

Although it has been described that the IC chip according to the present invention is a current-driven driver IC (through which the pixels are programmed with current), this is not restrictive. For example, the present invention is also applicable to an EL panel (device) equipped with a voltage-driven driver IC by which pixels are programmed with a voltage, as shown in FIGS. 43, 53, and the like. the

An anode wire 952 (anode wire after branching) is provided between the connection terminals 953a and 953b. That is, anode wires 952 branched from thick, low-resistance primary anode lines 951 are formed between connection terminals 953 and routed along each pixel 16 column. Therefore, the anode wiring 952 and the source signal line 18 are formed (arranged) in parallel. This structure (formation) makes it possible to apply the voltage Vdd to each pixel without selecting the path of the basic anode line 951 to the screen side, as shown in FIG. the

Figure 96 illustrates this further in more detail. Fig. 96 differs from Fig. 95 in that instead of being provided between the connection terminals 953, the anode wire is branched from a common anode wire 962 formed separately. This common anode line 962 is connected to the basic anode line 951 through a connecting anode line 961 . the

FIG. 96 illustrates the backside of the IC chip 14 seen through the IC chip 14. FIG. The IC chip 14 includes a current output circuit 704 that outputs the programmed current Iw to the output terminal 761 . Basically, the output terminal 761 and the current output circuit 704 are arranged in order. In the center of the IC chip 14, there is a circuit for generating the basic current for the first-generation current source and a control circuit. Therefore, in the center of the IC chip 14, the output terminal 761 is not formed. This is because the current output circuit 704 is not formed at the center of the IC chip 14 . the

According to the present invention, in the portion of the current output circuit 704a in the high current region of FIG. 96, any output terminal 761 is not equipped with this IC chip because there is no output circuit. Incidentally, it is often the case that although a control circuit is formed, an output circuit is not formed at the center of an IC chip such as a source driver. In view of these, the present invention does not form (dispose) any output terminal 761 at the center of the IC chip 14 . Of course, it is not the case when the output terminal 761 is formed (disposed) at the center of the IC chip 14 . the

According to the present invention, the connection anode line 961 is formed at the center of the IC chip 14. Referring to FIG. However, it goes without saying that the connection anode line 961 is formed on the surface of the array board 71. The width of the connecting anode line 961 is between 50 and 1000 μm (both dimensions included). And, the resistance value (maximum resistance value) relative to this length should be 100Ω or less. the

The base anode wire 951 and the common anode wire 962 should be shorted through the connecting anode wire 961 to minimize the voltage drop caused by the current flowing through the common anode wire 962 . That is, the connection anode line 961 as a component of the present invention utilizes the fact that there is no output circuit at the center of the IC chip, and the present invention prevents the output terminal 761 from being conventionally formed at the center of the IC chip as a void base by removing the Some electrical effects that would occur if the inactive pedestal contact was connected to the anode line 961 . the

However, if the dummy pedestal is electrically isolated from the basic substrate (ground of the chip) or other structures in the IC chip, then even if the dummy pedestal contacts the connection anode line 961, there is no problem at all. Therefore, it goes without saying that the dummy pedestal can also be formed in the center of the IC chip. the

More precisely, the connection anode line 961 and the common anode line 962 are formed (arranged) as shown in FIG. 99. First, the connection anode line 961 has a thick portion (961a) and a thin portion (961b). This thick part (961a) is intended to reduce the resistance value. This thin portion (961b) is used to form the connection anode line 961b between the output terminals 963 and connect it to the common anode line 962. the

The basic anode line 951 and the common anode line 962 are short-circuited not only through the central connection anode line 961b but also through the right and left connection anode lines 961c. That is, the common anode line 962 and the basic anode line 951 are short-circuited through the three connection anode lines 961 . With this structure, even if a large current flows through the common anode line 962, the common anode line 962 is less susceptible to a voltage drop. This is because the IC chip 14 is generally 2 mm or more in width, making it possible to increase the width of the basic anode line 951 formed under the IC chip 14 (reduce the resistance). Therefore, at some locations, the low-impedance base anode line 951 and common anode line 962 are shorted by the connection anode line 961 , reducing the voltage drop on the common anode line 962 . the

The voltage drop on the common anode line 962 can be reduced by this method, because the basic anode line 951c can be set (formed) under the IC chip 14, so the connecting anode line 961c can be set (formed) on the left side of the IC chip 14 and the right side, but the connection anode line 961b may be provided (formed) at the center of the IC chip 14. the

Also, in FIG. 99, a basic anode wire 951 and a cathode power supply wire (basic cathode wire) 991 are laminated with an insulating film interposed therebetween. This laminate forms a capacitor, this structure is called an anode capacitor structure, this capacitor acts as a power path capacitor, and thus absorbs sharp current changes in the primary anode line 951 . If the display area of the EL display device is Smm ² , the capacitance of the capacitor is C(pf), preferably, the capacitance of the capacitor satisfies M/200≤C≤M/10 or less. More preferably, it satisfies M/200≤C≤N/20 or less. A small C makes it difficult to absorb changes in current, but too large a C makes the formation area of the capacitor too large, which is not practical at this time.

Incidentally, it has been stated that in FIG. 99 and the like illustrated examples, the basic anode line 951 is provided under the IC chip 14, and it goes without saying that this also applies to the cathode line. Furthermore, in FIG. 99, the basic anode line 951 may be replaced by a basic cathode line 991. A technical concept of the present invention is to construct a driver from a semiconductor chip, mount this semiconductor chip on an array board 71 or a flexible board, and arrange (form) wiring on the back side of the semiconductor chip to supply power to the EL element 15 or ground potential ( current), etc. the

Therefore, this semiconductor chip can be not only the source driver IC 14 but also the gate driver circuit 12 or a power supply IC. And, the technical concept of the present invention includes mounting a semiconductor chip on a flexible board, and laying (forming) a power supply or ground pattern for the EL element 15 or the like on the back side of the semiconductor chip and in the space of the flexible board. Of course, both the source driver IC14 and the gate driver IC12 may be composed of semiconductor chips and mounted on the array board 71 through COG. Then, power or ground patterns can be formed on the backside of the chip. Also, although it has been stated that the power supply or ground pattern is intended for the EL element 15, this is not restrictive and the power supply may also be intended for the source driver circuit 4 or the gate driver circuit 12. In addition, the technical concept of the present invention is applicable not only to EL display devices but also to liquid crystal display devices. It is also suitable for FDP, PDP and other displays. The above items are also true for other examples of the invention. the

Fig. 97 shows another example of the present invention. The main difference between Fig. 97 and Figs. 95, 96, and 99 is that in Fig. 97, many thin connecting anode lines 961d are branched from the basic anode line 951, while in Fig. 95 they are short-circuited with the common anode line 962, and the anode Wires 952 are provided between connection terminals 953 . Also, the thin connection anode line 961d and the source signal line 18 connected to the connection terminal 953 are laminated with the insulating film 102 provided therebetween. the

The anode line 961d is connected to the basic anode line 951 in the contact hole 971d, and the anode line lead 952 is connected to the common anode line 962 in the contact hole 971b. In other respects (connection of anode lines 961a, 961b, 961c and anode capacitors, etc.), Fig. 97 is similar to Figs. 96 and 99, and thus description thereof is omitted. the

之间(包括这两个厚度)。更佳的是在800和2000 

之间(包括这两个厚度)。因为小的薄膜厚 度将增加在连接阳极线961d和源信号线18中的寄生电容，并往往造成在连接阳极线961d和源信号线18之间的短路，所以不是理想的。另一方面，厚的薄膜厚度将使绝缘薄膜的形成更花费时间，导致长的制造时间和高的成本，并且，在上侧做接线变得有困难。 FIG. 98 shows a sectional view taken along the line aa' in FIG. 99 . In FIG. 98(a), the source signal line 18 and the connection anode line 961d of substantially the same width are laminated with the insulating film 102a provided therebetween. Preferably, the thickness of the insulating film 102a is between 500 and 300 angstroms

Between (including these two thicknesses). Even better at 800 and 2000

Between (including these two thicknesses). A small film thickness is not ideal because it will increase the parasitic capacitance in the connection anode line 961d and the source signal line 18, and tend to cause a short circuit between the connection anode line 961d and the source signal line 18. On the other hand, a thick film thickness will make the formation of the insulating film more time-consuming, resulting in long manufacturing time and high cost, and it becomes difficult to make wiring on the upper side.

Possible materials for the insulating film 102 include, for example, not only inorganic materials such as SiO ₂ and SiN _x , but also organic materials such as polyvinyl alcohol (PVA) resins, epoxy resins, polypropylene resins, phenolic resins, Acrylic resin, polyimide resin. Needless to say, Al23, Ta203 and the like are also included among the possible materials. Also, as illustrated in FIG. 98(a), an insulating film 102b is formed in the outermost layer to protect the wiring 961 and the like connected thereto from corrosion and mechanical damage.

In FIG. 98(b), a connecting anode line 961d thinner than the source signal line 18 is provided on top of this source signal line 18 with an insulating film 102a provided therebetween. This structure prevents a step in the source signal line 18 from causing a short circuit between the source signal line 18 and the connection anode line 961d. In the structure shown in FIG. 98(b), it is preferable that the width of the connecting anode line 961d is narrower than that of the source signal line 18 by 0.5 [mu]m or more. More preferably, the anode connection line 961d is narrower than the source signal line 18 by 0.8 μm or more. the

Although it has been described with reference to FIG. 98(b) that the connecting anode line 961d narrower than the source signal line 18 is provided on top of the source signal line 18 with an insulating film 102a interposed therebetween, it is also possible to The source signal line 18 narrower than the connection anode line 961d is disposed on top of the connection anode line 961d with an insulating film 102a interposed therebetween, as illustrated in FIG. 98(c). Other items are the same as those in other examples, so descriptions thereof are omitted. the

FIG. 100 shows a cross-sectional view of the IC chip 14 . Basically, the structure is according to the structure in Fig. 99, but they can be similarly or analogously applied to Figs. 96, 97, etc. the

Fig. 100(b) shows a cross-sectional view taken along line A-A' in Fig. 99 . As can be seen from FIG. 100( b ), the output pad 761 is not formed (disposed) at the center of the IC chip 14 . This output base is connected to the source signal line 18 of the display screen. A bump is formed on the output base 761 by electroplating or ball bonding. The bumps should be 10 to 40 μm high (both heights included). Of course, it is obvious that the bumps can be formed by gold plating techniques (electroplating or electroless plating). the

The bumps are electrically connected to the source signal line 18 through a conductive bonding layer (not shown) made of silver (Ag), gold (Au), nickel (Ni), carbon (C), tin dioxide (SnO2 ) and similar materials in flake powder mixed with epoxy or phenolic based resins, or from UV curable resins. A conductive bonding layer (adhesive resin) 1001 is formed on the bumps by transfer or other techniques. And, the bump and the source signal line 18 are bonded with ACF resin 1001 by heat pressing. the

Incidentally, the technique for connecting the bump, that is, the output pad 761, to the source signal line 18 is not limited to those described above. In addition, film carrier technology (film carrier technique) can be used to replace mounting IC14 on the array board. Also, a polyimide film or the like can be used for the connection to the source signal line 18 . Fig. 100(a) shows a partial sectional view where the source signal line 18 and the common anode line 962 overlap (see Fig. 98). the

Anode line 952 is branched off from common anode line 962 . There are 528=(176*RGB) anode wires 952 in a QCIF screen. The voltage Vdd (anode voltage) illustrated in FIG. 1 and its ilk is provided through the anode lead 952 . If the EL element 15 is made of a low-molecular heavy material, a current of up to 200 μA flows through one anode wire 952, so a current of about 100 mA (200 μA×528) flows through the common anode wire 962. the

Therefore, in order to maintain a voltage drop of 0.2 V or less on the common anode line 962, the maximum value of the path resistance of the flowing current must be maintained at 2Ω or less (assuming that a current of 100 mA flows). According to the present invention, since the connecting anode line 961 is formed at three positions as shown in FIG. 99, the resistance value of the common anode line 962 can be easily minimized in the design of the concentrated distribution line. If many connection anode lines 961d are formed, as shown in FIG. 97, the voltage drop on the common anode line 962 can be almost eliminated. the

One problem is the effect of parasitic capacitance (referred to as common anode parasitic capacitance) in the overlapping portion of the common anode line 962 and the source signal line 18 . Basically, in current driving, the presence of parasitic capacitance in the source signal line 18 makes it difficult to write black display current to the source signal line 18 . Therefore, parasitic capacitance must be minimized. the

This common anode parasitic capacitance must be no more than 1/10 of the parasitic capacitance (referred to as display parasitic capacitance) generated by a source signal line 18 in the display area. For example, if the displayed parasitic capacitance is 10(pF), the anode parasitic capacitance must be 1(pF) or less. More preferably, the anode parasitic capacitance is not greater than 1/20 of the display parasitic capacitance. If it is shown that the parasitic capacitance is 10 (pF), the anode parasitic capacitance must be 0.5 (pF) or less, the line width of the common anode line 962 (M in FIG. 103 ) and the film thickness of the insulating film 102 (see FIG. 101 ) is determined taking this into consideration. the

The basic anode line 951 is formed (provided) under the IC chip 14 . Needless to say, its line width should be as thick as possible to reduce resistance. In addition, it is preferable that the basic anode wire 951 is equipped with a light shielding function. the

Figure 102 shows an explanatory diagram. Needless to say, if the basic anode line 951 is formed of a metal material to a desired film thickness, it will have a function of shielding light. If the basic anode line 951 cannot be made thick enough or made of a transparent material such as ITO, one or more light-absorbing films or light-reflecting films are stacked below the IC chip 14 and above the basic anode line 951 (Basically, on the surface of the array plate 71). The light-shielding film (basic anode line 951) in FIG. 102 does not need to perfectly shield light. It may have openings. Also, it can have diffractive or scattering effects. In addition, a light-shielding film composed of a multi-layer light interference film may also be formed by lamination, that is, provided on the basic anode line 951 . the

Of course, a reflector plate (sheet) or a light absorbing plate (sheet) made of metal foil, plate, or sheet may also be arranged, inserted or formed in the gap between the array plate 71 and the IC chip 14 . Needless to say, it is also possible to provide, insert or form a reflector plate (sheet) or a light absorbing plate (sheet) made of an organic or inorganic material instead of metal foil. Or a light-absorbing material or a light-reflecting material in a gel or liquid state may be inserted or formed in the gap between the array board 71 and the IC chip 14 . Preferably, the light-absorbing material or light-reflecting material in a gel or liquid state is cured by heating or exposing to light. Incidentally, for ease of explanation, it is assumed that the basic anode wire 951 is made of a light-shielding film ( light-reflecting film). the

As shown in FIG. 102, the basic anode line 951 is formed on the surface of the array plate 71 (not limited to this surface). If the light does not reach the rear surface of the IC chip 14, the idea of a light-shielding film or a light-reflecting film can be satisfied. Therefore, it goes without saying that the basic anode line 951 and the like can be formed on the inner surface or inner layer of the array plate 71 . Alternatively, a basic anode line 951 (an arrangement or structure functioning as a reflective film or a light-shielding film) may be formed on the rear surface of the array board 71 as long as it prevents or reduces light entering the IC 14. the

Although it has been described with reference to FIG. 102 and the like that the light-shielding film and the like are formed on the array plate 71, this is not restrictive, and the light-shielding film and the like can be directly formed. formed on the rear surface of the IC chip 14 . In that case, an insulating film 102 (not shown) is formed on the rear surface of the IC chip 14, and a light shielding film, a reflective film or the like is formed on the insulating film. When the source driver circuit 14 is directly formed on the array board 71 (by low-temperature polysilicon technology, high-temperature polysilicon technology, solid-phase growth technology, or driver structure of amorphous silicon technology), then the light shielding formed on the array board 71 The source driver circuit 14 is formed on a light absorbing film, a light absorbing film, or a reflective film. the

A large number of transistor elements such as a current source 634 passing a minute current are formed on the IC chip 14 (circuit forming section in FIG. 102 ). When light enters a transistor element (such as the cell transistor 634) passing a minute current, a phenomenon such as photoconduction occurs, making the values of the output current (programmed current Iw), first-generation current, second-generation current, etc. abnormal ( cause changes, etc.), especially, in the case of organic EL or other self-luminous elements, the light generated by the EL element 15 is scattered and reflected within the array plate 71, resulting in strong radiation at a place different from the display screen 50. of light. This radiated light, upon entering the circuit of the circuit forming section 1021 of the IC chip 14, causes a photoconductive phenomenon. Therefore, the measurement of the photoconductive phenomenon is the measurement of a problem unique to the EL display device. the

In order to solve this problem, the present invention constructs the basic anode line 951 on the array plate 71, and uses it as a light-shielding film. The formation area of the basic anode line 951 covers the circuit forming section 1021, as shown in FIG. 102, and by the light-shielding film (basic anode line 951) thus formed, it is possible to completely prevent the photoconductive phenomenon. When the screen is refreshed, current flows through the EL power supply wires such as the basic anode wire 951, causing some changes in their potential in particular. However, since the potential changes slowly every horizontal scanning period, it can be regarded as the ground potential (ie, there is actually no change in potential). Therefore, the basic anode line 951 or the basic cathode line not only performs the function of shielding light, but also performs the function of electric shielding. the

In the case of organic EL or other self-luminous elements, since the light generated by the EL element 15 is scattered and reflected within the array plate 71 , intense light is radiated from a place different from the display screen 50 . In order to prevent or reduce the scattered reflected light, a light-absorbing thin film 1011 is formed in the non-functional area, and the light that has an effect on image display in this area is not passed through, as shown in FIG. 101 (on the other hand, The active area is the display screen 50 and the area around it). A light-absorbing film is formed on the outer surface of the sealing cover 85 (light-absorbing film 1011a), the inner surface of the sealing cover 85 (light-absorbing film 1011c), and the side surface of the substrate 70 (light-absorbing film 1011d), which are different from the image display area. The area on the substrate (light-absorbing film 1011b) and the like. Incidentally, instead of the light-absorbing film, a light-absorbing sheet or a light-absorbing wall may be provided. In addition, the concept of light absorption also includes methods or structures that scatter light by scattering it. In a broader sense, also includes methods or structures that confine light by reflection. the

Possible materials for the absorbent film include, for example, organic materials such as acrylic resins containing carbon, organic resins with black pigments dispersed therein, and gelatin or casein colored with black acid dyes like filters. In addition, they include not only green and red pigments, which evolve into black pigments when mixed, but also a fluorine-based pigment, which evolves into black pigments on its own. Moreover, they also include PrMnO3 thin films formed by sputtering, phthalocyanine thin films formed by plasma polymerization, and the like. the

All of the above materials evolve into black materials, but materials that evolve a complementary color to the color evolved through the display element are also available for light absorbing films. For example, light absorbing materials for color filters can be used by modifying them so as to provide the desired light absorbing properties. Basically, a natural resin colored with a dye can be used as in the case of the black light absorbing material described above. It is also possible to use plastic in which the dye is dispersed. If so, the available range of pigments is wider than in the black pigment example, and includes azo dyes, anthraquinone dyes, phthalocyanine dyes, and triphenylmethane dyes, and a suitable one or A combination of two or more of them. the

In addition, metallic materials can also be used as light-absorbing thin films. Possible materials include, for example, hexavalent chromium, which is black in color and acts as a light absorbing film. In addition, light-scattering materials such as porcelain white glass and titanium oxide can also be used. By scattering light, the result may often be absorption of light. the

Incidentally, the sealing cover 85 is bonded to the array plate 71 using the sealing resin 1031 containing the resin beads 1012 having a diameter from 4 μm to 15 μm both inclusive. The sealing cap 85 is set and fixed without applying pressure. the

The example illustrated in FIG. 99 involves forming (disposing) the common anode line 962 close to the IC chip 14, but this is not restrictive. For example, the common anode line 962 can be formed close to the display screen 50, as described in FIG. Sections placed parallel to each other. If the signal line 18 and the anode lead 952 are placed at a short distance from each other, a parasitic capacitance will be generated between them. This problem can be solved if the common anode line 952 is placed close to the display screen 50 as shown in FIG. 103 . It is preferable that the distance K (see FIG. 103 ) from the display screen 50 to the common anode line 962 is 1 mm or less. the

Preferably, the common anode line 962 is made of the same metal material as the source signal line 18 to minimize their resistance, according to the present invention, it is made of such as thin copper (Cu) film, thin aluminum (Al ) films made of Ti/Al laminates, alloys, or amalgams of metallic materials (SD metals). Therefore, at the intersection of the source signal line 18 and the common anode line 962, the same metal material (GE metal) as the gate signal 17 is used to replace this material to prevent short circuit. The gate signal line is made of a metal material, a molybdenum/tungsten (Mo/W) laminate. the

In general, the sheet resistance of the gate signal line 17 is higher than that of the source signal line 18 . This is common to liquid crystal display devices. But in the current driving type organic EL panel, the current flowing through the source signal line 18 is as weak as 1 to 5 µA. Therefore, even if the source signal line 18 has a high resistance, almost no voltage drop is caused, so normal image display can be obtained. In the liquid crystal display device, image data is written into the source signal line 18 by a voltage method. Therefore, if the source signal line 18 has a high resistance, it is impossible to write an image in one horizontal scanning period. the

However, with current driving according to the present invention, a high resistance value (ie, a high sheet resistance value) of the source signal line 18 does not pose a problem. Therefore, the sheet resistance of the source signal line 18 can be higher than that of the gate signal line 17 . Therefore, in the EL panel of the present invention, the source signal line 18 can be made (formed) of GE metal, and the gate signal line 17 can be made (formed) of SD metal, as illustrated in FIG. 104 (with LCD display is reversed). In a broad sense, in a current-driven EL display panel, the wiring resistance of the source signal line 18 is higher than that of the gate signal line 17 . the

In addition to the structures in FIGS. 99 and 103, the structure in FIG. 107 includes a power supply wiring 1051 for driving the gate driver circuit 12, which is routed from the right side of the display screen 50 through the bottom side. The left side of the screen 50 is displayed. That is, the gate driver circuits 12a and 12b have a common power supply. the

However, it is preferable that the gate driver circuit 12a of the selection gate signal line 17a (which controls the selection transistors 11b and 11c) and the gate driver circuit 17b of the selection gate signal line 17b (which controls the transistor 11a and the current flowing through the EL element 15) The driver circuits 12b have different power supply voltages. In particular, it is preferable that the magnitude (difference between the turn-on voltage and the turn-off voltage) of the gate signal line 17a is small. This is because the smaller the amplitude of the gate signal line 17a, the smaller the voltage penetrating into the capacitor 19 in the pixel 16 (see FIG. 1, etc.). On the other hand, the amplitude of the gate signal line 17b cannot be reduced because the gate signal line 17b has to control the EL element 15. the

Therefore, as illustrated in FIG. 108, the voltages applied to the gate driver circuit 12a are Vha (off voltage for the gate signal line 17a) and V1a (turn-on voltage for the gate signal line 17a), while the applied voltage The voltages to the gate driver circuit 12a are Vhb (off voltage for the gate signal line 17b) and Vla (turn-on voltage for the gate signal line 17b). The relationship of Vla<Vlb should be satisfied. Incidentally, Vha and Vhb are approximately equal. the

Typically, N-channel transistors and P-channel transistors are used for the gate driver circuit 12, but preferably, only P-channel transistors are used. This is because it will reduce the number of masks used in array fabrication. Increase yields, and improve productivity. Therefore, as illustrated in Figures 1, 2, etc., P-channel transistors are not only used in the gate driver circuit 12, but should also be used in the pixel 16, if N-channel transistors and P-channel transistors are used in the gate driver circuit, 10 masks are required, but if only P-channel transistors are used, 5 layers of masks are required. the

However, if only P-channel transistors are used for circuits such as the gate driver circuit 12, on the array board 71, no level shifter can be formed. This is because the level shifter uses N-channel transistors and P-channel transistors. the

To solve this problem, the present invention integrates the function of the level shifter into the power supply IC1091. Fig. 109 shows an example of this case. The power supply IC 1091 generates a driving voltage of the gate driver circuit 12 , an anode voltage and a cathode voltage of the EL element 15 , and a driving voltage of the source driving circuit 14 . the

To generate the anode and cathode voltages of the EL element 15 of the gate driver circuit 12, the power supply IC 1091 needs to use a high-voltage semiconductor process. This voltage resistance level shifts the signal voltage to the gate driver circuit 12 . Also, as illustrated in FIG. 205 , a level shifter circuit 2041 may be formed in the source driver IC 14 . Level shifter circuits 2041 may be formed on the left and right sides of the source driver IC 14 . When using more than one source driver IC 14 as shown in FIG. 205 , one circuit in the level shifter circuit 2041 is used in each source driver IC 14 . the

In FIG. 205, one level shifter circuit 2041a is used in the source driver IC 14a. The gate control data is raised by the level shifter circuit 2041a to become a gate driver control signal 2043a, and controls the gate driver circuit 12a. Also, a level shifter circuit 2041b is used in the source driver IC 14b. The gate control data is raised by the level shifter circuit 2041b to become a gate driver control signal 2043b, and controls the gate driver circuit 12b. the

The structure in FIG. 109 is used for level shifting and driving the gate driver circuit 12. The source driver IC 14 is fed with input data (image data, commands, and control data) 992 , which also includes control data for the gate driver circuit 12 . The source driver IC 14 has a voltage resistance (operating voltage) of 5 (V). On the other hand, the gate driver circuit 12 has an operating voltage of 15 (V). It is necessary to shift the signal output from the source driver circuit 14 to the gate driver circuit 12 from a potential of 5 (V) to 15 (V). Level shifting is performed by a power supply circuit (IC) 1091 . In FIG. 109, a data signal for controlling this gate driver circuit 12 is called a power supply IC control signal 1092. the

After receiving the data signal 1092 for controlling the gate driver circuit 12, the power supply circuit 1091 uses the built-in level shifter circuit to level shift it, and outputs the resulting signal as the gate driver circuit control signal 1093 to This gate driver circuit 12 is controlled. the

A description will now be given of the gate driver circuit 12 according to the present invention, which is included in the array board 71 and uses only P-channel transistors. As described earlier, by using only P-channel transistors for the pixels 16 and gate driver circuit 12 (i.e., the transistors formed on the array plate 71 are only P-channel transistors, that is, no N-channel transistors are used), there is It is possible to reduce the number of masks used in array fabrication, increase yield, and improve productivity, and, since attention is focused only on improving the performance of the P-channel transistor, it is possible to easily improve its performance as a result. For example, lowering the threshold voltage (Vt) (making it closer to 0 (V)) and reducing variation in Vt is easier than in the case of a CHOS structure (a configuration employing P-channel transistors). the

Taking an example, according to the present invention, a gate driver circuit 12, each placed on the phase bases (shift registers), is formed, i.e. constructed, on the left and right sides of the display screen 50, as illustrated in FIG. 106 of. Although it is assumed that circuits such as gate driver circuit 12 (including the transistors of pixel 16) are formed or constructed at temperatures of 450 degrees (Celsius) or less using low temperature polysilicon technology, this is not limiting of. It is also possible to use transistors produced by high-temperature polysilicon technology at temperatures of 450 degrees (Celsius) or higher, or CGS semiconductor films produced by solid-state growth. In addition, organic transistors can also be used. Alternatively, transistors are formed or constructed from amorphous silicon technology. the

One of the gate driver circuits 12 is a gate driver circuit 12a on the selection side. It controls the pixel transistor 11 by applying a turn-on voltage or a turn-off voltage to the gate signal line 17a. Another gate driver circuit 12b turns on and off the current flowing through the EL element 15 . the

Although the example of the present invention is described by mainly taking the pixel structure in FIG. 1 as an example, this is not restrictive. It goes without saying that the present invention is also applicable to other pixel structures shown in Figs. 50, 51, 54 and the like. And, if this structure or the driving system of the gate driver circuit 12 according to the present invention is combined with a display screen, a display device or an information display device according to the present invention, more characteristic effects will be produced, but needless to say, even when using In other configurations, the gate driver 12 can also produce characteristic effects. the

Incidentally, the structure, ie layout, of the gate driver circuit 12 discussed below is not limited to a self-luminous device such as an organic EL display panel. It can also be used in liquid crystal displays, electromagnetic displays, etc. For example, a liquid crystal display panel may use the structure or configuration of the gate driver circuit 12 according to the present invention to control the selection switching elements of the pixels. If two gate driver circuits 12 are used, one of them may be used to select the pixel switching element. Instead the other can be connected to one terminal of the retention capacitor in each pixel, this scheme is called independent CC drive. Needless to say, the structure described with reference to FIGS. 111 , 113 and the like can be used not only for the gate driver circuit 12 but also for a circuit such as a shift register of the source driver circuit 14 . the

Preferably, the gate driver circuit 12 described herein can be used as reference in FIGS. , 92, 93, 103, 104, 105, 106, 107, 108, 109, 176, 181, 187, 188, 208, etc. are realized in the gate driver circuit 12 described earlier, that is, adopted. the

FIG. 111 is a block diagram of the gate driver circuit 12 according to the present invention. Although only four stages are illustrated for ease of explanation, basically as many unit gate output circuits 1111 as there are gate signal lines 17 are formed, ie provided. the

As illustrated in Figure 111, the gate driver circuit 12 (12a and 12b) according to the present invention includes signal terminals: 4 clock pulse terminals (SCKO, SCK1, SCK2 and SCK3), 1 enable terminal (data signal (SSTA )) and 2 switching terminals (DIRA and DIRB, which make the phases of the signals 180° out of phase with each other) to reverse the direction of shifting. They also include power supply terminals, which include L power supply terminals (VBB) and H power supply terminals (Vd). the

Since only P-channel transistors are used in the gate driver circuit 12 here, no level shifter circuits (circuits for converting low voltage logic signals to high voltage logic signals) can be incorporated into this gate driver circuit. Therefore, a level shifter circuit is provided or formed in the power supply circuit IC 1091 shown in FIG. 109 and the like. the

The power supply circuit (IC) 1091 generates potentials required for the turn-on voltage (the selected voltage of the pixel 16 transistor) and the turned-off voltage (the non-selected voltage of the pixel 16 transistor) to be output from the gate driver circuit 12 to the gate signal line 17 Voltage. Thus, the semiconductor process used for the power supply IC (circuit) 1091 has sufficient voltage resistance. Therefore, logic signals can be easily level-shifted (LS) by the power supply IC1091. To this end, the gate driver current 12 control signal output from a controller (not shown) is fed into the power supply IC 1091 and level shifted there before being fed into the gate driver circuit 12 according to the invention. Source driver circuit 14 control signals output from the controller are directly fed into circuits such as source driver circuit 14 according to the present invention (without level shifting). the

However, the present invention does not limit all transistors formed on the array panel 71 to P-channel transistors. By using only P-channel transistors for the gate driver circuit 12 as described later with reference to FIGS. 111 and 113, it is possible to reduce the width of the phosphor screen. In the case of a 2.2-inch QCIF panel, if the 6-µm rule is adopted, the width of the gate driver circuit 12 can be constructed to be 600 µm. Even including wiring to supply power to the gate driver circuit 12, the width will be 700 μm. If CMOS (N-channel and P-channel transistors) were used for a similar circuit structure, this width would increase to 1.2mm. Therefore, if only P-channel transistors are used for the gate driver circuit 12, it is possible to obtain the characteristic effect of reduction in phosphor screen width. the

Also, if the pixels 16 are constructed from P-channel transistors, they will be well matched to the gate driver circuit 12 using P-channel transistors. When the voltage goes low, the P-channel transistors (select transistors 11b and 11c and transistor 11d in the structure of FIG. 1) are turned on. On the other hand, this lower voltage also serves as the selected voltage for the gate driver circuit 12 . As can be seen from the structure in Fig. 113, if this lower level is used as the selected level, a good match is obtained for the gate driver with P-channel. This is because this low level cannot be maintained for a long period of time. On the other hand, a higher voltage can be maintained for a long period of time. the

Also, by using a P-channel for a driver transistor (transistor 11a in FIG. Also, current can be passed from Vdd of the anode potential to the EL element 15 in the positive direction. In view of the above, it is preferred that the transistors in pixel 16 and gate driver circuit 12 be P-channel. Therefore, the use of P-channel transistors as transistors (driver transistors and itching transistors) in the pixel 16 and gate driver circuit 12 according to the present invention is not merely a matter of design. the

In this sense, a level shifter (LS) circuit can be directly formed on the array board 71 . That is, N-channel transistors and p-channel transistors are used for the level shifter (LS) circuit. The logic signal from the controller (not shown) is boosted from the level shifter circuit formed directly on the array board 71 so that it will match the logic level of the gate driver circuit 12 made of P-channel transistors. The boosted logic voltage is applied to the gate driver circuit 12 . the

Incidentally, this level shifter circuit can be made of a semiconductor chip and mounted on the array board 71 using a technique such as COG. Also, the source driver circuit 14 is basically made of a semiconductor chip, and mounted on the array board 71 using COG technology, as illustrated in FIG. 109 and the like. However, this does not limit the source driver circuit 14 to be formed as a semiconductor chip, and it can be formed directly on the array board 71 using polysilicon technology. If a P-channel transistor is used as the transistor 11 of the pixel 16, the programming current flows in the direction from the pixel 16 to the source signal line 18. FIG. Therefore, an N-channel transistor should be used as the cell current circuit 634 of the source driver circuit (see FIGS. 73 and 74). That is, the source driver circuit 14 should be configured such that it can draw the programming current Iw. the

Therefore, if the driver transistor of the pixel 16 (in the case of FIG. 1 ) is a P-channel transistor, the unit transistor 634 of the source driver circuit 14 must be an N-channel transistor to ensure that the source driver circuit 14 will draw the programming current Iw . In order to form the source driver circuit 14 on the array board 71, it is necessary to use a mask (process) both for the N-channel transistor and for the P-channel transistor. Conceptually, in the display panel (display device) of the present invention, P-channel transistors are used for the pixels 16 and gate driver circuit 12, while N-channel transistors are used for source driver transistors that source current sources. the

Incidentally, for ease of explanation, in this example of the present invention, the pixel structure in FIG. 1 is used. However, the technical concept of the present invention related to the adoption of the selection transistor (transistor 11c in FIG. 1) as the pixel 16 and the P-channel transistor for the gate driver circuit 12 is not limited to the pixel structure in FIG. It goes without saying that, for example, in the case of a current-driven pixel structure, it is also applicable to a current-reflecting pixel structure such as that illustrated in FIG. 42 . And in the case of a voltage-driven pixel structure, it also applies to two types of transistors such as illustrated in FIG. 62 (the selection transistor is the transistor 11b and the driver transistor is the transistor 11a). Of course, it is also applicable to the structure of the gate driver 12 in Figs. 111 and 113, and they can be combined to constitute a device. Therefore, the items described above and also the items described below are not limited to the pixel structure or the like. the

The use of select transistors for pixels 16 and P-channel transistors for gate driver circuits is not limited to organic El or other self-emitting devices (panel or display devices). For example, it is also suitable for LCD screens and FEDs (Field Emission Displays). the

Switching terminals (DIRA and DIRB) apply common signals to all cell gate output circuits 1111. It can be seen from the equivalent circuit in Figure 113 that the switching terminals (DIRA and DIRB) are fed with supply values of opposite polarity. To reverse the scanning direction of the shift register, the polarity of the voltage values fed to the switching terminals (DIRA and DIRB) is reversed. the

Incidentally, the circuit configuration in Fig. 1111 includes four clock signal lines. According to the invention, 4 is the optimum number. However, this is not limiting, and the present invention may employ less or more than 4 clock signal lines. the

The clock pulse signals (SCKO, SCK1, SCK2, and SCK3) are fed differently between adjacent cell gate output circuits 1111. For example, in the cell gate output circuit 1111a, OC is fed by the clock pulse terminal SCKO, and RST is fed by the clock pulse terminal SCK2. This is also the case with respect to the cell gate output circuit 1111c. However, in the cell gate output circuit 1111b adjacent to the cell gate output circuit 1111a (the cell gate output circuit at the next stage), OC is fed by the clock pulse terminal SCK1, and RST is fed by the clock pulse terminal SCK3. In this way, each different cell gate output circuit 1111 is fed by the clock terminal in a different way: 0C is fed by SCKO and RST is fed by SCK2, and in the next stage, 0C is fed by SCK1 and RST is fed by SLK3 , in the next stage, OC is fed by SCKO and RST is fed by SCK2, etc. the

Fig. 113 shows a circuit configuration of a cell gate output circuit 1111 using only P-channel transistors. FIG. 114 is a timing chart for explaining the circuit configuration of FIG. 113. FIG. 112 is the time scale of the multiple levels in FIG. 113 . Therefore, by understanding FIG. 113, it is possible to understand the overall operation. This operation can be understood with reference to the timing diagram in FIG. 114 in conjunction with the equivalent circuit diagram of FIG. 113 and need not be explained in the text. Therefore, a detailed description of transistor operations will be omitted. the

When the driver circuit is composed of P-channel transistors alone, it is basically difficult to maintain the gate signal line 17 at the H level (Vd voltage in FIG. 113). It is also difficult to maintain them at L level (VBB voltage in FIG. 113) for a long time, but they can be properly maintained at H level for a short period such as during selection of pixel rows. The signal fed into the IN terminal and the SCK clock pulse fed into the RST terminal change the state of n1 relative to n2. Although n2 and n4 have potentials of the same polarity, the SCK clock pulse fed to the 0C terminal further lowers the potential level of n4. On the contrary, the Q terminal is maintained at L level (the ON voltage is output from the gate signal line 17) for the same period. The signal output to the SQ terminal or the Q terminal is transferred to the cell gate output circuit 711 in the next stage. the

In the circuit structures of Figures 111 and 113, by controlling the IN (INA and INB) terminals and the signal timing applied to the clock pulse terminal, it is possible to adopt two modes of the same circuit structure: a gate signal line 17 is selected , as shown in FIG. 115(a), and the mode in which two signal lines 17 are selected, as shown in FIG. 115(b). the

In the gate driver circuit 12a on the selection side, FIG. 115(a) shows a driving mode in which one row of pixels is selected while being shifted once (normal driving) on a row-by-row basis. Fig. 115(b) shows a structure in which two pixel rows are selected at a time. This driving mode corresponds to the driving for simultaneous selection of a plurality of pixel rows (51a and 51b) described with reference to FIGS. 27 and 28 (in which the structure of one dummy pixel row is adopted). Two adjacent lines are selected while shifting once on a line-by-line basis. Especially according to the driving method in Fig. 115(b), when the pixel row (51a) holds the last video, the pixel row 51b is precharged. This condition makes the pixel 16 easy to write on. That is, the present invention can switch between two drive modes by manipulating signals applied to the terminals. the

Incidentally, although 115(b) shows a mode in which adjacent rows of pixels 16 are selected, as shown in FIG. 116, it is also possible to select rows of pixels 16 other than adjacent rows (FIG. 116 illustrates that every third pixel row is selected). In the structure shown in Fig. 113, pixel rows are controlled to form groups of 4 rows. From among the 4 pixel rows, it is possible to determine whether to select one pixel row or 2 consecutive pixel rows. The number of pixel rows in each group is limited by the number of clock pulses (SCK), four in this case. If 8 clock pulses (SCK) are used, pixel rows can be controlled to form groups of 8 rows. the

The operation of the gate driver circuit 12a on the selection side is shown in FIG. 115 . In Fig. 115(a), one row of pixel rows is selected at a time, and the selected position is shifted synchronously by one row of pixels and the horizontal synchronous signal. In Fig. 115(b), two rows of pixel rows are selected at a time, and The selection position is shifted by one row of pixels in synchronization with the horizontal sync signal. the

As illustrated in FIG. 182 , the connection anode line 961 is wired from the anode connection terminal 1821 , and the connection anode line 961 formed on both sides of the source driver IC 14 is electrically connected through a switch 2021 formed below the IC 14 . the

A common anode line 962 is formed, that is, provided on the output side of the source driver IC 14 . Anode wire 952 is branched off from common anode wire 962 . There are 528 (=176×RGB) anode lines 952 in a QCIF panel. The voltage Vdd (anode voltage) illustrated in FIG. 1 and its ilk is supplied through the anode lead 952 . A current up to the order of 200 A flows through an anode wire 952 if the EL element 15 is made of a low molecular weight material. Therefore, a current of about 100 mA (200 μA×528) flows through the common anode wire 833 . the

In order to reduce the voltage drop in the universal connection anode line 961 and the anode lead 952, it is suggested to form the universal connection anode line 961a on the upper side of the display screen 50, form the universal connection anode line 961b on the lower side of the display screen 50, and The top and bottom of the short circuit the anode wires 952, as illustrated in Figure 183. the

It is also preferred to provide source driver circuits 14 at the top and bottom of the screen 50, as illustrated in FIG. 184 . It is also possible to divide the display screen 50 into a display screen 50a and a display screen 50b, and drive the display screen 50a with the source driver circuit 14a, and drive the display screen 50b with the source driver circuit 14b, as illustrated in FIG. 185 . the

Fig. 201 is a block diagram of a power supply circuit according to the present invention. Reference numeral 2012 denotes a control circuit which controls the midpoint potential of the resistors 2015a and 2015b and outputs a gate signal of the transistor 2016. The power supply Vpc is supplied to the primary side of the transformer 2011, and the primary side current is transmitted to the secondary side under the control of on/off of the transistor 2016. Reference numeral 2013 denotes a rectifying diode, and 2014 denotes a smoothing capacitor. the

Anode voltage Vdd has a regulated output voltage to resistor 2015b. Vss represents the cathode voltage. As illustrated in FIG. 202, one of two voltages can be selectively output as the cathode voltage Vss. Switch 2021 is provided for this selection. In graph 202, -9 (V) is selected by switch 2021. the

The switch 2021 operates according to the output from the temperature sensor 2022 . When the screen temperature is low, -9 (V) is selected as the voltage Vss. When the screen temperature is equal to or higher than a certain level, -6(V) is selected. This is because the EL element 15 has temperature dependence, and the terminal voltage of the EL element becomes higher on the low temperature side. Incidentally, although it has been described with reference to FIG. 202 that one of the two voltages is selected as Vss (cathode voltage), this is not restrictive, and the voltage Vss can be selected from three voltages. The above items apply similarly to Vdd. the

By allowing a voltage to be selected from a plurality of temperatures according to the screen temperature, as shown in FIG. 202, it is possible to reduce the power consumption of the screen. This is because the voltage Vs-s can be lowered when the temperature is equal to or lower than a certain level. Generally, a lower Vss (=-6(V)) can be used. Incidentally, the switch 2021 can be made as illustrated in FIG. 202 . By using the center tap of the transformer 2011 in FIG. 202, a plurality of voltages Vss can be easily generated. This situation similarly applies to the anode voltage Vdd. the

Fig. 205 is an explanatory diagram illustrating potential setting. The source driver IC14 is based on GND. The power supply to the source driver IC14 is Vcc. Vcc can be steered to coincide with the anode voltage (Vdd). According to the present invention, Vcc<Vdd is seen from the viewpoint of power consumption. the

The cut-off voltage Vgh of the gate driver 12 is set to be equal to or higher than the voltage Vdd. Preferably, Vdd+0.5(V)<Vgh<Vdd+2.5(V) should be satisfied. The turn-on voltage Vg1 can be led to be consistent with Vss, but it is preferable to satisfy Vss(V)<Vg1<-0.5(V). the

It is important to take measures against the heat generated from the EL display. As a measure against heat generation, a chassis 2062 made of metal material is mounted on the back of the screen (opposite side of the light-emitting surface of the display screen 50), as shown in Figure 206. For better heat dissipation, the chassis 2062 has protrusions and recesses 2063 . Furthermore, an adhesive layer (in the case of FIG. 206, a sealing cover 85) is provided between the chassis 2061 and the panel. Materials with good thermal conductivity are used for the bonding layer. Possible materials include, for example, silicone resin paste and silicone paste. These materials are often used as an adhesive between the regulator IC and the radiator board. Incidentally, it is not strictly necessary for the bonding layer to have an adhesive function as long as it can function to keep the chassis 2061 and the panel in close contact with each other. the

An aperture 2071 is provided on the back of the chassis 2062, as illustrated in Figure 207(a). Small holes 2071 are provided to release excess resin when bonding the chassis 2062 and screen together. Also, the shape of the small hole is different between the center and the periphery of the screen, as shown in Figure 207(a), in order to adjust the thermal resistance of the chassis 2062, so as to make the temperature of the screen uniform. In Fig. 207(a), the small hole 2071c around the screen is made larger than the small hole 2071a at the center of the screen, thereby increasing the thermal resistance around the screen. Therefore, heat loss is less likely to occur around the screen. This results in a uniform heat distribution over the entire screen surface. Incidentally, the small hole 2071 may be circular, for example, as illustrated in Fig. 207(b). the

Fig. 208 illustrates a structure of a display screen according to the present invention. A flexible board 84 is mounted on one side of the array board 71 . A power supply circuit 82 and a flexible board 84 are provided on the flexible board. Fig. 209 shows a sectional view taken along line A-A' in Fig. 208. However, in Figure 209 the flex plate 84 has been bent and the chassis 2062 has been installed. As can be seen from FIG. 209 , the transformer 2011 of the power supply circuit 82 is contained in the space formed by the sealing cover 85 . This makes it possible to reduce the thickness of the EL panel (EL panel module). the

Next, a description will be given of examples of display devices according to the present invention which operate the driving system according to the present invention. Fig. 57 is a plan view of a mobile phone as an example of an information terminal. An antenna 571, numeric keys 572 and the like are housed in the housing 573. Reference numerals 572 and the like represent on-off keys, power keys, and frame rate switching keys for displaying colors. the

The number key 572 can be made to switch between the color modes as follows: press it once to enter the 8-color display mode, press it again to enter the 4096-color display mode, and press it again to enter the 260,000-color display mode display mode. This key is a toggle switch that toggles between the various color display modes each time it is pressed. Incidentally, the color change key can be displayed separately. If so, three (or more) number keys 572 are required. the

In addition to push button switches, the number keys 572 may be toggle switches or other mechanical switches. Speech recognition can also be used for switching. For example, the switch can be made so that when the user speaks a phrase such as "high definition display", "4096-color display mode" or "low color display mode" into the handset, it will change the display screen 50 of the display screen displayed in color. This situation can be easily realized using existing speech recognition technology. the

Also, the display color can be switched electrically. It is also possible to use a touch screen which allows the user to make selections by touching a menu which appears on the display portion 21 of the display screen. In addition, the display color can be switched according to the number of times the switch is pressed or according to the rotation or direction as in the case of the positioning ball. the

Instead of the display color switching key 572, a key for changing the frame rate or a key for switching between a moving picture and a still picture may be used. A key may switch two more items at the same time: for example, between frame rates and between moving and still pictures. Also, the key can be made to gradually (continuously) change the frame rate when pressed and held. For this reason, between the capacitor C and the resistor R of the oscillator, the capacitor R can be made variable, or replaced by an electronic regulator. Alternatively, a trimmer capacitor can be used as capacitor C of the oscillator. Such a key can also be realized by forming a plurality of capacitors on a semiconductor chip, selecting one or more capacitors, and connecting the capacitors in parallel. the

Furthermore, an embodiment using an EL display panel, an EL display device, or a display method according to the present invention will be described with reference to the drawings. the

Fig. 58 is a sectional view of a viewfinder according to an embodiment of the present invention. For ease of explanation, it is illustrated schematically. Also, some parts are enlarged. be narrowed, or omitted. For example, an eyepiece is omitted in FIG. 58 . The above items also apply to other drawings. the

The inner surface of housing 573 is dark or black. This is to prevent stray light emitted from the EL display panel (EL display device) 574 from being diffusely reflected inside the housing 573 to lower display contrast. On the lead-out side of the display screen, a phase plate (λ/4) 108, a polarizing plate 109, etc. are provided. This situation has been described with reference to FIGS. 10 and 11. FIG. the

The exit pupil 581 is equipped with a magnifying lens 582 , and the observer focuses the displayed image 50 on the display screen 574 by adjusting the position of the exit pupil 581 in the housing 573 . the

If the convex lens 583 is arranged on the lead-out side of the display screen 574 as required, the principal rays entering the magnifying lens 582 can be converged. This makes it possible to reduce the diameter of the magnifying lens 1582, and thus reduce the size of the viewfinder. the

Fig. 59 is a perspective view of a video camera. The camera has a photographing (imaging) lens 592 and a camera housing 573 . The photographing lens 592 and the housing (viewfinder) 573 are mounted back to back to each other. Viewfinder 573 (see also Fig. 58) is fitted with an eyepiece protector. The viewer views the image 50 on the display screen 574 through the eyepiece protective layer. the

The EL display screen according to the present invention is also used as a display monitor. The display screen 50 is freely pivotable at one point on the bracket 591. The display screen 50 can be stored in the storage compartment 593 when not in use. the

Switch 594 is a changeover switch, or control switch, and performs the following functions. The switch 594 is a display mode changeover switch. Switch 594 is also suitable for use with devices such as cell phones. The switching 594 of the display mode will now be described. the

The driving methods according to the present invention include a method of passing N times larger current through the EL elements 15 to illuminate them for 1/M periods equal to 1F. By changing this lighting period, it is possible to digitally change the brightness. For example, specifying N=4, a 4 times larger current flows through the EL element 15 . If the lighting period is 1/M, by switching M between 1, 2, 3 and 4, it is possible to change the brightness from 1 to 4 times. Incidentally, it is possible to switch M between 1, 1.5, 2, 3, 4, 5, 6, etc. the

The switching operation described above is useful for mobile phones, because the mobile phone displays the display screen 50 very brightly when the power is turned on, and then reduces the display brightness after a certain period of time to save power. It is also used to let the user set the desired brightness. For example, outdoors, the brightness of the screen is greatly increased. This is because the screen cannot be seen at all due to the bright surrounding environment. However, the EL element 15 rapidly degrades under the condition of high-brightness continuous display. Therefore, the screen 50 is designed to return to normal brightness for a short period of time if it is displayed very brightly. In case the user wants to display this screen 50 again at high brightness, a button should be provided which increases the display brightness when pressed. the

Thus, the user can change the brightness of the display with the switch 594 . It is preferable that the display brightness can be automatically changed according to the mode setting, or that the brightness of the external light can be detected automatically. Preferably, display brightness such as 50%, 60%, 80%, etc. is available to the user. the

Preferably, the display screen 50 adopts a Gaussian display. That is, the center of the display screen 50 is bright, while the periphery is relatively dark. Visually, the display screen 50 appears bright if the center is bright even if the periphery is dark. According to subjective evaluation, as long as the periphery is at least 70% as bright as the center, there is not much difficulty. Even with the surrounding brightness reduced to 50%, there was little issue. According to the self-luminous display screen of the present invention, adopt the above-described N times pulse driving (a kind of N times larger current flows through the EL element 15 to illuminate them to be equal to the 1/M period method of 1F), from the screen produces a Gaussian distribution from top to bottom. the

Specifically, the M value is increased at the upper and lower portions of the screen and decreased at the center of the screen. This is done by adjusting the operating speed of the shift register of the gate driver circuit 12 . The brightness of the left and right sides of the screen is adjusted by multiplying the table data by the video data. By reducing the ambient brightness (at a viewing angle of 0.9) to 50% through the above operations, it is possible to reduce power consumption by 20% compared with 100% brightness. By reducing the ambient brightness (at a viewing angle of 0.9) to 70%, it is possible to reduce power consumption by up to 15% compared to 100% brightness. the

Preferably, a toggle switch is provided to enable and disable Gaussian display. This is because if a Gaussian display is used, the screen cannot be seen at all outdoors. Therefore, the user can change the display brightness with a button switch, the display brightness can be automatically changed according to the mode setting, or the display brightness can be automatically changed by detecting the brightness of external light. Preferably, display brightness settings such as 50%, 60%, 80%, etc. are available to the user. the

LCD screens use a backlight that produces a fixed Gaussian distribution. Therefore, they cannot allow and disallow Gaussian distributions. The ability to enable and disable Gaussian distribution is unique to self-illuminating display devices. the

A fixed frame rate can cause interference with indoor lighting such as fluorescent lights, causing flickering. Specifically, if the EL element 15 is operated on a 60-Hz AC, a fluorescent lamp illuminated on the 60-Hz AC may cause weak interference, making it appear as if the screen is flickering slowly. To avoid this, the frame rate can be changed. The present invention has the ability to change the frame rate. Also, it enables to change the value of N or M in N-times pulse driving (a method of passing N times larger current through the EL elements 15 to illuminate them for 1/M period equal to 1F). the

By means of switch 594 the above capabilities are achieved. When the switch 594 is pressed more than once, according to the menu on the screen 50, toggles between the above skills. the

Incidentally, the above items are not limited to mobile phones, needless to say, they apply to TVs, monitors, etc. Also, it is preferable to provide icons on the display screen so that the user can know which display mode he/she is in at a glance. The items above apply similarly to the items below. the

A device such as an EL display according to the present invention can be applied not only to a video camera but also to a digital camera such as that shown in FIG. 60, a general camera, and the like. This display device is used as the screen 50 attached to the camera body 601 . The camera body 601 is equipped with not only the shutter 603 but also the switch 594 . the

The display screens described above have a relatively small display area. However, as the display area is 30 inches or larger, the display screen 50 tends to warp. To deal with this situation, the present invention puts the display screen in the frame 611 and attaches a connector 614 so that the frame can be hung up as shown in FIG. 61 . The display screen is mounted on a surface such as a wall using connectors 614 . the

The large size screen increases the weight of the display screen, and as a countermeasure against this, the display screen is mounted on a bracket 613 on which a plurality of pillars 612 are attached to support the weight of the display screen. The strut 612 can be moved from side to side as indicated by A. Also, they can be shrunk as B points out. Therefore, the display device can be installed even in a small site. the

In the TV set among Fig. 61, a protective film is covered with a protective film on its screen surface. One purpose of the protective film is to protect the surface of the display screen from being cracked by being hit by something. AIR coating is formed on the surface of the protective film. Also, the surface is molded to reduce glare caused by extraneous light on the display screen. the

A gap is formed between the protective film and the display screen by spraying beads or the like. Thin protrusions are formed on the back of the protective film to maintain a gap between the protective film and the display. This gap prevents the transmission of impacts from the protective film to the display. the

Also, it is useful to inject an optical coupling agent into the space between the protective film and the display screen. The optical coupling reagent may be a liquid such as ethanol or glycol, a gel such as acrylic resin, or a solid resin such as epoxy resin. This optical coupling reagent prevents reflections at the interface and acts as a buffer material. the

The protective film may be, for example, polycarbonate film (sheet), polypropylene film (sheet), acrylic film (sheet), polyester film (sheet), PVA film (sheet) and the like. In addition, it is obvious that an engineering resin film (ABS, etc.) can be used. Also, it can be made of an inorganic material such as annealed glass. Instead of using a protective film, the surface of the display screen can be replaced with epoxy resin, phenolic resin, and acrylic resin with a thickness of 0.5mm to 2.0mm to produce a similar effect. Also, it is useful for molding the surface of the resin. the

It is also useful for surface coating of protective film or coating with fluorine. This will make it easy to remove dust from the surface with detergent. Moreover, the protective film can be made thick, not only for the surface of the screen, but also for the front light. the

The display screen according to this example of the invention can be used in combination with a three-sided free structure. This three-sided free structure is useful especially when the pixels are constructed with amorphous silicon technology. And, in the case of forming a panel using the amorphous silicon technology, since it is difficult to control variations in transistor characteristics during the production process, N-pulse driving according to the present invention, reset driving, dummy pixel driving, or Drivers such as these are preferred. That is, the transistors according to the invention are not limited to those produced by polysilicon technology, but they may be produced by amorphous silicon technology. the

Incidentally, driving according to the present invention such as N-fold pulse driving (FIGS. 13, 16, 19, 20, 22, 24, 30, etc.) Displays with transistors 11 formed from amorphous silicon technology are more efficient. This is because adjacent transistors have nearly equal characteristics when formed from amorphous silicon technology. Therefore, even if the transistor is driven by the additional resulting current, the drive current for each individual transistor is close to the target value, (particularly for the N-fold pulse drive in FIGS. 22, 24 and 30, for the The pixel structure of the transistor is effective). the

The duty cycle control driving, reference current control, N-fold pulse driving, and other driving methods and driving circuits according to the present invention described herein are not limited to organic EL display panels. Needless to say, they are also applicable to other displays such as Field Emission Displays (FED), as shown in FIG. 221 . the

In the FED shown in FIG. 221, a protrusion 2213 (corresponding to the pixel electrode in FIG. 10) emitting electrons in a matrix is formed on a substrate 71. A pixel includes a holding circuit 2214 (corresponding to a capacitor in FIG. 1) which holds image data received from a video signal circuit 2212 (corresponding to a source driver circuit 14 in FIG. 1). Also, the control electrode 2211 is disposed in front of the electron emission protrusion 2213 . A voltage signal is applied to the control electrode 2211 through an on/off control circuit 2215 (corresponding to the gate driver circuit 12 in FIG. 1). the

If the peripheral circuit shown in FIG. 222 is added, the pixel structure in FIG. 221 can be driven by N-fold pulses, duty factor controlled driving, and the like. The image data signal from the video signal circuit 2212 is supplied to the source signal line 18. A selection signal of the pixels 16 is applied to the selection signal line 2221 through the on/off control circuit 2215a, whereby the pixels 16 are selected one by one and image data is written in them. Also, an ON/OFF signal is applied to the ON/OFF signal line 2222 through the ON/OFF control circuit 2215b, and therefore, the FED of the pixel is subjected to ON/OFF control (duty factor control). the

The technical concept described in this example of the present invention can be applied to video cameras, projectors, 3D televisions, projection televisions, and the like. It is also applicable to viewfinders, mobile phone monitors, PHS, personal digital auxiliary devices and their monitors, and digital cameras and their monitors. the

And, this technical concept is also applicable to xerographic copier systems, top-mounted monitors, direct view monitors, notebook personal computers, video cameras, and electronic general cameras. And, it is suitable for ATM monitors, public phones, video phones, personal computers, and watches and their display screens. the

Also, it is obvious that this technical concept can be applied to display monitors of home appliances, pocket game machines and their monitors, backlight panels for display screens, or lighting devices for home or business use. Preferably, the lighting device is constructed such that the color temperature can be changed. The color temperature can be changed by forming RGB pixels in stripes or in a matrix of dots and adjusting the current flowing through them. Also, this technical concept can be applied to display devices for advertisements or advertising posters, RGB traffic lights, police lights, and the like. the

Also, an organic EL display panel is useful as a light source for a scanner. RGB dot matrix is used as light source, and the image is read out along with the light directed at the object. It goes without saying that this light may be monochromatic. In addition, this matrix is not limited to an active matrix, and may be a simple matrix. The use of adjustable color temperature will improve the accuracy of imaging. the

Furthermore, an organic EL display panel is useful as a backlight for a liquid crystal display panel. By forming the RGB pixels of an EL display (backlight) in stripes or in a dot matrix, and adjusting the current flowing through them, the color temperature and brightness can be easily changed. In addition, an organic EL display screen that provides a surface light source makes it easy to generate a Gaussian distribution that makes the center of the screen brighter and the periphery of the screen darker. Also, an organic EL display panel is useful as a backlight panel of a field sequential liquid crystal display panel which is sequentially scanned with R, G, and B lights. And, even if these backlight screens are turned on and off, by inserting black, they can be used as backlight screens for liquid crystal display screens for film display. the

Industrial Applicability

The source driver circuit of the present invention, in which transistors constituting current mirrors are formed adjacent to each other, can reduce variations in output current caused by deviations in threshold values. Therefore, it can reduce the brightness irregularity of the EL display panel, and has a great practical effect. the

Moreover, the display screens of the present invention, display devices, etc. provide different effects according to their respective structures, including high quality, high film display performance, low energy consumption, low cost, high brightness, etc.,

Incidentally, since the present invention can provide a power-saving information display device, it does not consume much power. And, since it reduces size and weight, it does not waste resources. Moreover, it properly secures a high-resolution display. Therefore, the present invention is friendly to both the global environment and the space environment. the

Claims (9)

1. An EL display device having a display screen in which pixels provided with EL elements are arranged in a matrix on a substrate, characterized in that, comprising: A driver IC chip configured on the substrate and equipped with a source driver circuit that outputs a programmed current or a programmed voltage to the pixel; Disposing all or part of the basic anode lines between the substrate and the driver IC chip; a common anode line arranged between the driver IC chip and the pixel display area; at least one connecting anode wire connecting said basic anode wire and said common anode wire; An anode wiring branched from the common anode line to supply current or voltage to the pixel. 2. The EL display device according to claim 1, wherein the basic anode line is arranged to shield a circuit forming portion of the driver IC chip from light. 3. The EL display device according to claim 1 , further comprising an output switching circuit arranged in the output section of the source driver circuit and turning on and off the output of the programmed current or the programmed voltage . 4. The EL display device according to claim 1, wherein: a drive transistor that supplies current to the EL element, a switching transistor that supplies a signal applied to the source signal line to the driving transistor, A capacitor is arranged between the gate terminal of the driving transistor and the output terminal of the switching transistor. 5. The EL display device according to claim 1, wherein a a drive transistor that supplies current to the EL element, forming a switching transistor in the current path, turning the switching transistor on and off, controlling the current, A strip-shaped non-display area and a display area can be formed on the display screen of the EL display device. 6. The EL display device according to claim 1, wherein red pixels, green pixels, blue pixels, and white pixels are arranged in a matrix on a display screen of the EL display device. 7. The EL display device according to claim 1, wherein on the display screen of the EL display device, pixels of the first color and pixels of the second color are arranged in a matrix, The size of the first color pixel is different from the size of the second color pixel. 8. The EL display device according to claim 1, wherein generating a strip-shaped non-display area and a display area on the display screen, An image can be displayed by moving the non-display area and the display area in the vertical direction of the display screen. 9. The EL display device according to claim 1, wherein It also has a detection method for detecting the brightness of external light, generating a strip-shaped non-display area and a display area on the display screen, The ratio of the non-display area to the display area is changed according to the output value or control of the detection means.

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