[go: up one dir, main page]

TW202232712A - 具有天線的封裝結構及其製作方法 - Google Patents

具有天線的封裝結構及其製作方法 Download PDF

Info

Publication number
TW202232712A
TW202232712A TW111101526A TW111101526A TW202232712A TW 202232712 A TW202232712 A TW 202232712A TW 111101526 A TW111101526 A TW 111101526A TW 111101526 A TW111101526 A TW 111101526A TW 202232712 A TW202232712 A TW 202232712A
Authority
TW
Taiwan
Prior art keywords
layer
antenna
circuit
metal
processing
Prior art date
Application number
TW111101526A
Other languages
English (en)
Other versions
TWI788191B (zh
Inventor
陳先明
馮磊
王聞師
黃本霞
Original Assignee
大陸商珠海越亞半導體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大陸商珠海越亞半導體股份有限公司 filed Critical 大陸商珠海越亞半導體股份有限公司
Publication of TW202232712A publication Critical patent/TW202232712A/zh
Application granted granted Critical
Publication of TWI788191B publication Critical patent/TWI788191B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6677High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Details Of Aerials (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Support Of Aerials (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本發明公開了一種具有天線的封裝結構,包括封裝體、天線線路、互連線路、外層線路和晶片,封裝體的內部封裝有第一導通通孔柱和第二導通通孔柱,天線線路設置在封裝體的第一表面和側壁,互連線路封裝在封裝體內,且通過第一導通通孔柱與天線線路連接,外層線路設置在封裝體的第二表面,且通過第二導通通孔柱與互連線路連接,外層線路還連接有導電引腳,晶片封裝在封裝體內,且與互連線路或外層線路連接。本發明還公開一種具有天線的封裝結構的製作方法。本發明在封裝體的表面和側壁佈置天線線路,可以充分利用封裝體的佈線空間,有利於佈置更多天線線路,以及延長天線的長度,使提升天線線路的信號傳輸品質。

Description

具有天線的封裝結構及其製作方法
本發明涉及半導體封裝技術領域,特別涉及一種具有天線的封裝結構及其製作方法。
隨著技術的進步,無線通訊設備通常將包含發送和接收射頻信號的天線設置在電路板的不同部分上,並通過電路的走線進行互連,然而,天線和電路板這兩個部件都可能產生單獨的製造成本,並且分立式的天線安裝方式已無法滿足電子設備的高集成化和小型化的要求,因此天線封裝技術逐步成為先進封裝行業的焦點。
目前的天線封裝技術,大都是在晶片(包括被動元件和裸晶片)完成塑封後,在塑封體的第一表面或下表面使用重新佈線層的製作方法形成天線層,或者使天線層分別位於塑封體或封裝基板的上下表面。在該類封裝技術中,天線層結構要額外佔用塑封體表面原本用於佈置重新佈線層走線的面積,或者佔用封裝基板表面的面積,故而對整體封裝走線的設計和製造工藝產生了一定的限制。天線的長度和信號的收發有直接關係,5G通訊下頻譜眾多,為了滿足更多的天線配置,需要設置不同的天線長度,天線長度決定了封裝介質層的厚度,使天線封裝體無法達到微型化的要求。
另外,因信號品質與傳送速率的要求,需要配置更多的天線,而現有無線通訊模組中,天線結構為平面型,且基板的長寬尺寸均為固定,致使線路佈線空間(層數)有限,因而限制天線結構的功能,無法滿足信號的空間覆蓋,使信號的收發收到影響,從而使天線結構難以達到通訊系統運作的需求。
本發明旨在至少解決現有技術中存在的技術問題之一。為此,本發明提出一種具有天線的封裝結構及其製作方法,在嵌埋基板的表面及側壁佈置天線,能夠佈置更多、更長的天線線路。
第一方面,根據本發明實施例的具有天線的封裝結構,包括封裝體,內部封裝有第一導通通孔柱和第二導通通孔柱;天線線路,設置在所述封裝體的第一表面和側壁;互連線路,封裝在所述封裝體內,且通過所述第一導通通孔柱與所述天線線路連接;外層線路,設置在所述封裝體的第二表面,且通過所述第二導通通孔柱與所述互連線路連接,所述外層線路還連接有導電引腳;晶片,封裝在所述封裝體內,且與所述互連線路或所述外層線路連接。
根據本發明實施例的具有天線的封裝結構,至少具有如下有益效果:
本發明在封裝體的表面和側壁佈置天線線路,可以充分利用封裝體的佈線空間,有利於佈置更多天線線路,以及延長天線的長度,使提升天線線路的信號傳輸品質。
根據本發明的一些實施例,位於所述封裝體側壁的天線線路為階梯結構。
根據本發明的一些實施例,所述第一導通通孔柱包括多段縱向連接的層間通孔柱,相鄰兩段所述層間通孔柱之間設置有墊盤。
根據本發明的一些實施例,所述封裝體內且位於所述墊盤的同一層內設置有內層天線線路,所述內層天線線路與相應的所述墊盤連接。
第二方面,根據本發明實施例的具有天線的封裝結構的製作方法,包括:
提供具有第一金屬層的承載板,並在所述第一金屬層上加工至少一層天線層,所述天線層內封裝有第一犧牲金屬柱以及與所述第一金屬層連接的第一導通通孔柱;
在最後一層所述天線層的基礎上加工器件封裝層,所述器件封裝層包括互連線路、第二導通通孔柱和封裝腔體,所述第二導通通孔柱與所述互連線路連接;
在所述封裝腔體內封裝晶片後,在所述器件封裝層的基礎上加工第二金屬層;
分板並將所述第一金屬層加工成表面天線線路以及將所述第二金屬層加工成外層線路;
去除所述第一犧牲金屬柱,以獲得凹槽;
在所述凹槽的內壁加工側壁天線線路,所述側壁天線線路與所述表面天線線路連接;
在所述外層線路上加工導電引腳;
沿所述凹槽進行切割,以獲得封裝體。
根據本發明實施例的具有天線的封裝結構的製作方法,至少具有如下有益效果:本發明在封裝體的表面和側壁佈置天線線路,可以充分利用封裝體的佈線空間,有利於佈置更多天線線路,以及延長天線的長度,使提升天線線路的信號傳輸品質。
根據本發明的一些實施例,在所述第一金屬層上加工至少一層天線層,包括以下步驟:
根據生產資料,在所述第一金屬層上通過圖形轉移和圖形電鍍的方式加工第一段的層間通孔柱和第一段的第一犧牲金屬柱,以獲得第一層天線層半成品;
對第一層所述天線層半成品進行疊層壓合,以獲得第一層天線層。
根據本發明的一些實施例,在所述第一金屬層上加工至少一層天線層,還包括以下步驟:
減薄處理,對壓合後的所述天線層進行減薄處理,以暴露前一段的所述層間通孔柱和前一段的所述第一犧牲金屬柱;
圖形製作,在前一段的所述層間通孔柱和前一段的所述第一犧牲金屬柱上通過圖形轉移的方式加墊盤,或者,在前一段的所述層間通孔柱和前一段的所述第一犧牲金屬柱上通過圖形轉移的方式加墊盤和內層天線線路,所述內層天線線路與相應的所述墊盤連接;
半成品加工,根據生產資料,通過圖形轉移和圖形電鍍的方式在墊盤的基礎上加工後一段的所述層間通孔柱和後一段的所述第一犧牲金屬柱,以獲得次一層的天線層半成品;
疊層壓合,對次一層的所述天線層半成品進行疊層壓合;
根據生產資料,重複磨板、圖形製作、半成品加工和疊層壓合,直至完成多層所述天線層的加工。
根據本發明的一些實施例,在最後一層所述天線層的基礎上加工器件封裝層,包括以下步驟:
對最後一層所述天線層進行減薄處理;
在減薄後的所述天線層上通過圖形轉移、圖形電鍍和疊層壓合的方式加工至少一層互連線路層,所述互連線路位於所述互連線路層上。
根據本發明的一些實施例,在最後一層所述天線層的基礎上加工器件封裝層,還包括以下步驟:
在最後一層所述互連線路層上且位於所述封裝腔體內的互連線路上加工保護金屬;
在所述最後一層所述互連線路層上加工所述第二導通通孔柱以及在所述保護金屬上加工第二犧牲金屬柱,以獲得器件封裝層半成品;
對所述器件封裝層半成品進行疊層壓合以及減薄處理;
通過蝕刻的方式去除所述第二犧牲金屬柱和所述保護金屬,以形成所述封裝腔體。
根據本發明的一些實施例,在所述封裝腔體內封裝晶片,包括以下步驟:
將所述晶片貼裝在所述封裝腔體內,並使所述晶片的引腳與位於所述封裝腔體內的所述互連線路連接;
對所述封裝腔體進行塑封。
根據本發明的一些實施例,在所述封裝腔體內封裝晶片,包括以下步驟:
將所述晶片貼裝在所述封裝腔體內,並使所述晶片的引腳朝向遠離所述互連線路層的一側;
對所述封裝腔體進行塑封。
根據本發明的一些實施例,在所述器件封裝層的基礎上加工第二金屬層,包括以下步驟:
通過鐳射鑽孔的方式暴露所述晶片的引腳;
通過圖形轉移和圖形電鍍的方式在所述器件封裝層的基礎上加工所述第二金屬層,並使所述第二金屬層與所述晶片的引腳連接。
根據本發明的一些實施例,在所述凹槽的內壁加工側壁天線線路,包括以下步驟:
在所述凹槽的內壁加工金屬種子層;
在所述第一金屬層和所述第二金屬層上加工感光遮蔽膜,並在所述感光遮蔽膜對應於所述凹槽的位置開窗;
在所述凹槽內沉積金屬,以形成所述側壁天線線路;
去除所述感光遮蔽膜和所述金屬種子層。
根據本發明的一些實施例,所述凹槽的內壁為階梯結構。
根據本發明的一些實施例,在所述外層線路上加工導電引腳之前,還包括以下步驟:
在所述外層線路上加工阻焊層,並在所述阻焊層對應於所述導電引腳的位置開窗。
本發明的附加方面和優點將在下面的描述中部分給出,部分將從下面的描述中變得明顯,或通過本發明的實踐瞭解到。
下面詳細描述本發明的實施例,所述實施例的示例在附圖中示出,其中自始至終相同或類似的標號表示相同或類似的元件或具有相同或類似功能的元件。下面通過參考附圖描述的實施例是示例性的,僅用於解釋本發明,而不能理解為對本發明的限制。
在本發明的描述中,若干的含義是一個或者多個,多個的含義是兩個以上,大於、小於、超過等理解為不包括本數,以上、以下、以內等理解為包括本數。如果有描述到第一、第二只是用於區分技術特徵為目的,而不能理解為指示或暗示相對重要性或者隱含指明所指示的技術特徵的數量或者隱含指明所指示的技術特徵的先後關係。
本發明的描述中,除非另有明確的限定,設置、安裝、連接等詞語應做廣義理解,所屬技術領域技術人員可以結合技術方案的具體內容合理確定上述詞語在本發明中的具體含義。
請參照圖16和圖17,本實施例公開了一種具有天線的封裝結構,包括封裝體700、天線線路、互連線路310、外層線路510和晶片400,封裝體700的內部封裝有第一導通通孔柱220和第二導通通孔柱320,天線線路包括表面天線線路120和側壁天線線路130,表面天線線路120設置在封裝體700的第一表面上,側壁天線線路130設置在封裝體700的側壁上,互連線路310封裝在封裝體700內,且通過第一導通通孔柱220與天線線路連接,外層線路510設置在封裝體700的第二表面,且通過第二導通通孔柱320與互連線路310連接,外層線路510還連接有導電引腳600,晶片400封裝在封裝體700內,且與互連線路310或外層線路510連接。需要說明的是,互連線路310設置在互連線路層上,互連線路層的層數為一層或多層,相鄰的互連線路層之間通過第三導通通孔柱連接。
本實施例在封裝體700的第一表面和側壁佈置天線線路,可以充分利用封裝體700的佈線空間,有利於佈置更多天線線路,以及延長天線的長度,使天線線路從單一平面轉變為立體多面,提升天線線路的信號傳輸品質,而且本實施例將天線線路和晶片400進行集成化封裝,使封裝體700更加輕薄。
在應用過程中,為了充分利用封裝體700側壁的佈線空間,將封裝體700的側壁分為多個呈階梯狀縱向分佈的區域,相應的,位於封裝體700側壁的天線線路為階梯結構,有利於進一步延長天線線路的長度,從而提升天線線路的信號傳輸品質。
請繼續參照圖16或圖17,第一導通通孔柱220包括多段縱向連接的層間通孔柱221,相鄰兩段層間通孔柱221之間設置有墊盤240,其中,墊盤240用於連接相鄰的兩段層間通孔柱221,以便於層間通孔柱221的加工。
為了能夠更加充分利用封裝體700的佈線空間,封裝體700內且位於墊盤240的同一層內設置有內層天線線路,內層天線線路與相應的墊盤240連接,可以實現天線線路的多層佈線和立體佈線,有利於延長天線線路的長度,從而提升天線線路的信號傳輸品質。
為了進一步理解本實施例的具有天線的封裝結構的技術方案,本發明實施例還公開該嵌埋基板的製作方法。
一種具有天線的封裝結構的製作方法,包括:
步驟S100、請參照圖1、圖2和圖3,提供具有第一金屬層110的承載板100,並在第一金屬層110上加工至少一層天線層200,天線層200內封裝有第一犧牲金屬柱210以及與第一金屬層連接的第一導通通孔柱220。
在本實施例中,承載板100可採用表面附有可拆卸銅箔的覆銅板,其中,覆銅板表面的銅箔為第一金屬層110。需要說明的是,覆銅板可以為單面覆銅板或雙面覆銅板,為了便於對本實施例的製作方法進行表述,本實施例以雙面覆銅板的其中一面為例進行描述,但值得理解的是,在實際生產時可在雙面覆銅板的兩面銅箔上進行對稱式製作。在本實施例中,第一金屬層110用於加工後續的表面天線線路120,天線線路位於天線層200上,根據實際應用需求,天線層200的層數可以是一層或多層,天線層200內的第一犧牲金屬柱210便於後續去除以形成凹槽230,以及便於加工後續的側壁天線線路130,需要說明的是,本實施例的天線線路包括表面天線線路120和側壁天線線路130,可以使天線線路從傳統的單一表面佈線轉變為立體多面佈線,有利於充分利用有限的佈線空間,佈置更多的天線線路,以及延長天線的長度,提升天線線路的信號傳輸品質。第一導通通孔柱220用於實現天線線路與其它線路之間的互連,值得理解的是,第一導通通孔柱220的長度可根據天線層200的數量進行適應性調整。
在上述步驟S100中,在第一金屬層110上加工至少一層天線層200,包括以下步驟:
步驟S110、請參照圖2,根據生產資料,在第一金屬層110上通過圖形轉移和圖形電鍍的方式加工第一段的層間通孔柱221和第一段的第一犧牲金屬柱210,以獲得第一層天線層半成品。
值得理解的是,圖形轉移和圖形電鍍的加工方式在本技術領域中均為公知常識,在本實施例中不再進行累述。
步驟S120、請參照圖2和圖3,對第一層天線層半成品進行疊層壓合,以獲得第一層天線層200,疊層壓合的材料採用低介電常數、低損耗的介質材料,介質材料覆蓋於層間通孔柱221和第一犧牲金屬柱210,經過疊層壓合後,介質材料將層間通孔柱221和第一犧牲金屬柱210包裹在內側,實現層間通孔柱221和第一犧牲金屬柱210的封裝、固定和保護。
根據實際應用需求,天線層200的層數為一層或多層,當天線層200的層數是一層時,單段的層間通孔柱221即為第一導通通孔柱220,可以用於連接後續的天線線路和互連線路。當需要加工多層天線層200時,在上述步驟S100中,在第一金屬層110上加工至少一層天線層200,還包括以下步驟:
步驟S130、減薄處理,對壓合後的天線層200進行減薄處理,以暴露前一段的層間通孔柱221和前一段的第一犧牲金屬柱210,以便於實現層間互連。減薄處理的加工方式採用機械磨板。
步驟S140、圖形製作,請參照圖4,在前一段的層間通孔柱221和前一段的第一犧牲金屬柱210上通過圖形轉移的方式加墊盤240,或者,在前一段的層間通孔柱221和前一段的第一犧牲金屬柱210上通過圖形轉移的方式加墊盤240和內層天線線路,內層天線線路與相應的墊盤240連接。需要說明的是,墊盤240的位置可根據生產資料需要進行設置,墊盤240可以僅設置在層間通孔柱221上,或者,墊盤240設置在層間通孔柱221以及部分第一犧牲金屬柱210上。墊盤240可以增大相鄰兩段層間通孔柱221或第一犧牲金屬柱210之間的接觸面積,以便於加工相鄰的兩段層間通孔柱221或第一犧牲金屬柱210。
步驟S150、半成品加工,請參照圖5,根據生產資料,通過圖形轉移和圖形電鍍的方式在墊盤240的基礎上加工後一段的層間通孔柱221和後一段的第一犧牲金屬柱210,以獲得次一層的天線層半成品。需要說明的是,在此步驟中第一導通通孔柱220包括多段層間通孔柱221以及連接在相鄰兩端層間通孔柱221之間的墊盤240,第一犧牲金屬柱210的段數可以少於層間通孔柱221的段數,即可以在部分或全部天線層200加工第一犧牲金屬柱210。
步驟S160、疊層壓合,對次一層的天線層半成品進行疊層壓合;
步驟S170、請參照圖4、圖5和圖6,根據生產資料,重複磨板、圖形製作、半成品加工和疊層壓合,直至完成多層天線層200的加工。
步驟S200、請參照圖6至圖10,在最後一層天線層200的基礎上加工器件封裝層300,器件封裝層300包括互連線路310、第二導通通孔柱320和封裝腔體330,第二導通通孔柱320與互連線路310連接。
封裝腔體330用於在後續步驟中對晶片400進行貼裝和封裝,第二導通通孔柱320用於實現互連線路310與後續的外層線路510之間層間連接,互連線路310與晶片400之間直接或間接連接,從而實現信號的傳輸。
在步驟S200中,在最後一層天線層200的基礎上加工器件封裝層300,包括以下步驟:
步驟S210、請參照圖6,對最後一層天線層200進行減薄處理,以暴露天線層200內的金屬,例如層間通孔柱221或第一犧牲金屬柱210,減薄的加工方式採用磨板處理。
步驟S220、請參照圖7,在減薄後的天線層200上通過圖形轉移、圖形電鍍和疊層壓合的方式加工至少一層互連線路層,互連線路310位於互連線路層上,相鄰兩層互連線路層的互連線路310之間通過第三導通通孔柱進行連接。
根據不同的設計需求,晶片400可以與互連線路310直接連接,或者與外層線路510連接,並通過外層線路510與互連線路310間接連接。
請參照圖8,對於晶片400與互連線路310直接連接的方式,在步驟S200中,在最後一層天線層200的基礎上加工器件封裝層300,還包括以下步驟:
步驟S230、在最後一層互連線路層上且位於封裝腔體330內的互連線路310上加工保護金屬340。其中,位於封裝腔體330內的互連線路310用作與晶片400連接的焊盤,為了在形成封裝腔體330時對焊盤進行保護,在焊盤上沉積保護金屬340,並通過保護金屬340覆蓋焊盤區域,以實現焊盤的保護,保護金屬340可以是鎳、鈦等。
步驟S240、請參照圖9,在最後一層互連線路層上加工第二導通通孔柱320以及在保護金屬340上加工第二犧牲金屬柱350,以獲得器件封裝層半成品。根據生產資料,通過圖形轉移和圖形電鍍的方式加工,以獲得第二導通通孔柱320和第二犧牲金屬柱350,可以實現互連線路310與後續的外層線路510之間的連接。
步驟S250、對器件封裝層半成品進行疊層壓合以及減薄處理,以便於露出器件封裝層300表面的金屬。
步驟S260、請參照圖10,通過蝕刻的方式去除第二犧牲金屬柱350和保護金屬340,以形成封裝腔體330。其中,位於封裝腔體330內的互連線路310在去除保護金屬340後,可用作連接晶片400的焊盤。
步驟S300、請參照圖11和圖12,在封裝腔體330內封裝晶片400後,在器件封裝層300的基礎上加工第二金屬層500。
在步驟S200加工得到的器件封裝層300中設置有封裝腔體330,在封裝腔體330內封裝晶片400後,為了便於製作外層線路510,在器件封裝層300的基礎上加工第二金屬層500。
對於晶片400與互連線路310直接連接的方式,在上述步驟S300中,在封裝腔體330內封裝晶片400,包括以下步驟:
步驟S310a、請參照圖11,將晶片400貼裝在封裝腔體330內,並使晶片400的引腳與位於封裝腔體330內的互連線路310連接;
步驟S320a、對封裝腔體330進行塑封,使封裝材料填充封裝腔體330,以便於將晶片400進行包封和固定。
步驟S400、請參照圖12和圖13,分板並將第一金屬層110加工成表面天線線路120以及將第二金屬層500加工成外層線路510。
當完成第二金屬層500的加工後,將去除承載板100以便於露出第一金屬層110,從而便於表面天線線路120的製作,在本實施例中,表面天線線路120和外層線路510的製作均可根據生產資料通過圖形轉移和圖形電鍍的方式進行加工,而圖形轉移和圖形電鍍的加工方式在本技術領域中均為公知常識,在本實施例中不再進行累述。
步驟S500、請參照圖13和圖14,去除第一犧牲金屬柱210,以獲得凹槽230。
為了能夠加工側壁天線線路130,可以通過蝕刻的方式去除第一犧牲金屬柱210,以獲得凹槽230,凹槽230的內壁為側壁天線線路130提供支撐。
步驟S600、請參照圖14,在凹槽230的內壁加工側壁天線線路130,側壁天線線路130與表面天線線路120連接。
在上述步驟S600中,在凹槽230的內壁加工側壁天線線路130,包括以下步驟:
步驟S610、在凹槽230的內壁加工金屬種子層,以便於提高凹槽230內壁與後續的側壁天線線路130之間的結合力,金屬種子層可以通過濺射的方式進行加工。
步驟S620、在第一金屬層110和第二金屬層500上加工感光遮蔽膜,並在感光遮蔽膜對應於凹槽230的位置開窗,以便於露出凹槽230。
步驟S630、在凹槽230內沉積金屬,以形成側壁天線線路130;
步驟S640、去除感光遮蔽膜和金屬種子層。
根據實際應用的需求,凹槽230的內壁為平整結構或階梯結構,相應的,位於封裝體700側壁的天線線路為階梯結構,有利於進一步延長天線線路的長度,從而提升天線線路的信號傳輸品質。
步驟S700、在外層線路510上加工導電引腳600。
請參照圖15,上述步驟S700、在外層線路510上加工導電引腳600之前,還包括以下步驟:步驟S701、在外層線路510上加工阻焊層800,並在阻焊層800對應於導電引腳600的位置開窗,在外層線路510上加工阻焊層800,可以對外層線路510進行保護,在阻焊層800上開窗,可以露出導電引腳600的焊盤,以便於導電引腳600的加工。
步驟S800、請參照圖15和圖16,沿凹槽230進行切割,以獲得封裝體700。
本實施例的製作方法在封裝體700的表面和側壁佈置天線線路,可以充分利用封裝體700的佈線空間,有利於佈置更多天線線路,以及延長天線的長度,使天線線路從單一平面轉變為立體多面,提升天線線路的信號傳輸品質,而且本實施例將天線線路和晶片400進行集成化封裝,使封裝體700更加輕薄。
請參照圖17,對於晶片400與外層線路510連接的方式,在上述步驟S300中,在封裝腔體330內封裝晶片400,包括以下步驟:
步驟S310b、將晶片400貼裝在封裝腔體330內,並使晶片400的引腳朝向遠離互連線路層的一側,需要說明的是,在晶片400貼裝時,可以通過黏結劑材料331將晶片400固定在封裝腔體330內,其中,黏結劑材料331可以採用導電銀漿或DAF(die attach film,晶片貼膜)材料等。
步驟S320b、對封裝腔體330進行塑封。
對於晶片400與外層線路510連接的方式,在上述步驟S300中,在器件封裝層300的基礎上加工第二金屬層500,包括以下步驟:
步驟S330、通過鐳射鑽孔的方式暴露晶片400的引腳;
步驟S340、通過圖形轉移和圖形電鍍的方式在器件封裝層300的基礎上加工第二金屬層500,並使第二金屬層500與晶片400的引腳連接。當第二金屬層500被加工成外層線路510後,可以實現晶片400與外層線路510連接,需要說明的是,晶片400的引腳可通過銅柱與外層線路510連接,銅柱的加工可在外層線路510加工時通過圖形電鍍的方式獲得。
上面結合附圖對本發明實施例作了詳細說明,但是本發明不限於上述實施例,在所屬技術領域普通技術人員所具備的知識範圍內,還可以在不脫離本發明宗旨的前提下作出各種變化。
100:承載板 110:第一金屬層 120:表面天線線路 130:側壁天線線路 200:天線層 210:第一犧牲金屬柱 220:第一導通通孔柱 221:層間通孔柱 230:凹槽 240:墊盤 300:器件封裝層 310:互連線路 320:第二導通通孔柱 330:封裝腔體 331:黏結劑材料 340:保護金屬 350:第二犧牲金屬柱 400:晶片 500:第二金屬層 510:外層線路 600:導電引腳 700:封裝體 800:阻焊層 S100:步驟 S110:步驟 S120:步驟 S130:步驟 S140:步驟 S150:步驟 S160:步驟 S170:步驟 S200:步驟 S210:步驟 S220:步驟 S230:步驟 S240:步驟 S250:步驟 S260:步驟 S300:步驟 S310a:步驟 S310b:步驟 S320a:步驟 S320b:步驟 S330:步驟 S340:步驟 S400:步驟 S500:步驟 S600:步驟 S610:步驟 S620:步驟 S630:步驟 S640:步驟 S700:步驟 S701:步驟 S800:步驟
本發明的上述和/或附加的方面和優點從結合下面附圖對實施例的描述中將變得明顯和容易理解,其中: 圖1至圖15為本發明實施例的具有天線的封裝結構的製作方法的中間過程的基板剖面結構示意圖。 圖16為本發明實施例的具有天線的封裝結構的結構示意圖之一。 圖17為本發明實施例的具有天線的封裝結構的結構示意圖之二。
120:表面天線線路
130:側壁天線線路
220:第一導通通孔柱
221:層間通孔柱
240:墊盤
310:互連線路
320:第二導通通孔柱
330:封裝腔體
400:晶片
510:外層線路
600:導電引腳
700:封裝體
800:阻焊層

Claims (15)

  1. 一種具有天線的封裝結構,其中,包括: 封裝體,內部封裝有第一導通通孔柱和第二導通通孔柱; 天線線路,設置在所述封裝體的第一表面和側壁; 互連線路,封裝在所述封裝體內,且通過所述第一導通通孔柱與所述天線線路連接; 外層線路,設置在所述封裝體的第二表面,且通過所述第二導通通孔柱與所述互連線路連接,所述外層線路還連接有導電引腳; 晶片,封裝在所述封裝體內,且與所述互連線路或所述外層線路連接。
  2. 如請求項1所述的具有天線的封裝結構,其中,位於所述封裝體側壁的天線線路為階梯結構。
  3. 如請求項2所述的具有天線的封裝結構,其中,所述第一導通通孔柱包括多段縱向連接的層間通孔柱,相鄰兩段所述層間通孔柱之間設置有墊盤。
  4. 如請求項3所述的具有天線的封裝結構,其中,所述封裝體內且位於所述墊盤的同一層內設置有內層天線線路,所述內層天線線路與相應的所述墊盤連接。
  5. 一種具有天線的封裝結構的製作方法,其中,包括: 提供具有第一金屬層的承載板,並在所述第一金屬層上加工至少一層天線層,所述天線層內封裝有第一犧牲金屬柱以及與所述第一金屬層連接的第一導通通孔柱; 在最後一層所述天線層的基礎上加工器件封裝層,所述器件封裝層包括互連線路、第二導通通孔柱和封裝腔體,所述第二導通通孔柱與所述互連線路連接; 在所述封裝腔體內封裝晶片後,在所述器件封裝層的基礎上加工第二金屬層; 分板並將所述第一金屬層加工成表面天線線路以及將所述第二金屬層加工成外層線路; 去除所述第一犧牲金屬柱,以獲得凹槽; 在所述凹槽的內壁加工側壁天線線路,所述側壁天線線路與所述表面天線線路連接; 在所述外層線路上加工導電引腳; 沿所述凹槽進行切割,以獲得封裝體。
  6. 如請求項5所述的具有天線的封裝結構的製作方法,其中,在所述第一金屬層上加工至少一層天線層,包括以下步驟: 根據生產資料,在所述第一金屬層上通過圖形轉移和圖形電鍍的方式加工第一段的層間通孔柱和第一段的第一犧牲金屬柱,以獲得第一層天線層半成品; 對第一層所述天線層半成品進行疊層壓合,以獲得第一層天線層。
  7. 如請求項6所述的具有天線的封裝結構的製作方法,其中,在所述第一金屬層上加工至少一層天線層,還包括以下步驟: 減薄處理,對壓合後的所述天線層進行減薄處理,以暴露前一段的所述層間通孔柱和前一段的所述第一犧牲金屬柱; 圖形製作,在前一段的所述層間通孔柱和前一段的所述第一犧牲金屬柱上通過圖形轉移的方式加墊盤,或者,在前一段的所述層間通孔柱和前一段的所述第一犧牲金屬柱上通過圖形轉移的方式加墊盤和內層天線線路,所述內層天線線路與相應的所述墊盤連接; 半成品加工,根據生產資料,通過圖形轉移和圖形電鍍的方式在墊盤的基礎上加工後一段的所述層間通孔柱和後一段的所述第一犧牲金屬柱,以獲得次一層的天線層半成品; 疊層壓合,對次一層的所述天線層半成品進行疊層壓合; 根據生產資料,重複磨板、圖形製作、半成品加工和疊層壓合,直至完成多層所述天線層的加工。
  8. 如請求項5所述的具有天線的封裝結構的製作方法,其中,在最後一層所述天線層的基礎上加工器件封裝層,包括以下步驟: 對最後一層所述天線層進行減薄處理; 在減薄後的所述天線層上通過圖形轉移、圖形電鍍和疊層壓合的方式加工至少一層互連線路層,所述互連線路位於所述互連線路層上。
  9. 如請求項8所述的具有天線的封裝結構的製作方法,其中,在最後一層所述天線層的基礎上加工器件封裝層,還包括以下步驟: 在最後一層所述互連線路層上且位於所述封裝腔體內的互連線路上加工保護金屬; 在所述最後一層所述互連線路層上加工所述第二導通通孔柱以及在所述保護金屬上加工第二犧牲金屬柱,以獲得器件封裝層半成品; 對所述器件封裝層半成品進行疊層壓合以及減薄處理; 通過蝕刻的方式去除所述第二犧牲金屬柱和所述保護金屬,以形成所述封裝腔體。
  10. 如請求項9所述的具有天線的封裝結構的製作方法,其中,在所述封裝腔體內封裝晶片,包括以下步驟: 將所述晶片貼裝在所述封裝腔體內,並使所述晶片的引腳與位於所述封裝腔體內的所述互連線路連接; 對所述封裝腔體進行塑封。
  11. 如請求項9所述的具有天線的封裝結構的製作方法,其中,在所述封裝腔體內封裝晶片,包括以下步驟: 將所述晶片貼裝在所述封裝腔體內,並使所述晶片的引腳朝向遠離所述互連線路層的一側; 對所述封裝腔體進行塑封。
  12. 如請求項11所述的具有天線的封裝結構的製作方法,其中,在所述器件封裝層的基礎上加工第二金屬層,包括以下步驟: 通過鐳射鑽孔的方式暴露所述晶片的引腳; 通過圖形轉移和圖形電鍍的方式在所述器件封裝層的基礎上加工所述第二金屬層,並使所述第二金屬層與所述晶片的引腳連接。
  13. 如請求項5所述的具有天線的封裝結構的製作方法,其中,在所述凹槽的內壁加工側壁天線線路,包括以下步驟: 在所述凹槽的內壁加工金屬種子層; 在所述第一金屬層和所述第二金屬層上加工感光遮蔽膜,並在所述感光遮蔽膜對應於所述凹槽的位置開窗; 在所述凹槽內沉積金屬,以形成所述側壁天線線路; 去除所述感光遮蔽膜和所述金屬種子層。
  14. 如請求項5或13所述的具有天線的封裝結構的製作方法,其中,所述凹槽的內壁為階梯結構。
  15. 如請求項5所述的具有天線的封裝結構的製作方法,其中,在所述外層線路上加工導電引腳之前,還包括以下步驟: 在所述外層線路上加工阻焊層,並在所述阻焊層對應於所述導電引腳的位置開窗。
TW111101526A 2021-02-05 2022-01-13 具有天線的封裝結構及其製作方法 TWI788191B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110158558.2 2021-02-05
CN202110158558.2A CN113035845B (zh) 2021-02-05 2021-02-05 具有天线的封装结构及其制作方法

Publications (2)

Publication Number Publication Date
TW202232712A true TW202232712A (zh) 2022-08-16
TWI788191B TWI788191B (zh) 2022-12-21

Family

ID=76460111

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111101526A TWI788191B (zh) 2021-02-05 2022-01-13 具有天線的封裝結構及其製作方法

Country Status (5)

Country Link
US (1) US11984414B2 (zh)
JP (1) JP7316399B2 (zh)
KR (1) KR102811697B1 (zh)
CN (1) CN113035845B (zh)
TW (1) TWI788191B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI863419B (zh) * 2023-04-28 2024-11-21 大陸商訊芯電子科技(中山)有限公司 天線裝置以及天線裝置的製造方法
TWI870951B (zh) * 2022-09-29 2025-01-21 大陸商珠海越亞半導體股份有限公司 半導體封裝結構及其製備方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115172328A (zh) * 2022-07-25 2022-10-11 安徽龙芯微科技有限公司 一种多芯片封装用的导电组件及其制作方法
CN115732332A (zh) * 2022-11-08 2023-03-03 珠海越亚半导体股份有限公司 一种基板制作方法、嵌埋基板以及半导体
WO2024171760A1 (ja) * 2023-02-16 2024-08-22 ローム株式会社 絶縁チップおよび絶縁チップの製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3695123B2 (ja) * 1997-04-18 2005-09-14 株式会社村田製作所 アンテナ装置およびそれを用いた通信機
JP2005005985A (ja) 2003-06-11 2005-01-06 Sony Chem Corp アンテナ素子及びアンテナ実装基板
JP4126664B2 (ja) 2004-08-04 2008-07-30 日立金属株式会社 アンテナ装置及びこれを用いた通信機器
JP2012165329A (ja) 2011-02-09 2012-08-30 Alps Electric Co Ltd 通信モジュール
EP2736001A1 (fr) * 2012-11-27 2014-05-28 Gemalto SA Module électronique à interface de communication tridimensionnelle
US9252077B2 (en) * 2013-09-25 2016-02-02 Intel Corporation Package vias for radio frequency antenna connections
US10050013B2 (en) * 2015-12-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
DE102016103790B8 (de) 2016-03-03 2021-06-02 Infineon Technologies Ag Herstellung einer Packung unter Verwendung eines platebaren Verkapselungsmaterials
JP6728917B2 (ja) 2016-04-12 2020-07-22 Tdk株式会社 電子回路モジュールの製造方法
EP3449532B1 (en) * 2016-04-28 2024-02-28 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with integrated antenna arrangement, electronic apparatus, radio communication method
US9974160B1 (en) 2016-12-28 2018-05-15 Raytheon Company Interconnection system for a multilayered radio frequency circuit and method of fabrication
CN108666300A (zh) * 2017-03-31 2018-10-16 欣兴电子股份有限公司 芯片封装结构及其制造方法
US10867938B2 (en) * 2017-09-25 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
KR102059814B1 (ko) * 2018-07-12 2019-12-27 삼성전기주식회사 안테나 모듈
US10971461B2 (en) * 2018-08-16 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN109244046B (zh) * 2018-10-26 2024-10-25 盛合晶微半导体(江阴)有限公司 扇出型天线封装结构及封装方法
KR102565123B1 (ko) 2018-12-14 2023-08-08 삼성전기주식회사 안테나 모듈 및 이를 포함하는 전자기기
CN109768031A (zh) * 2019-03-04 2019-05-17 中芯长电半导体(江阴)有限公司 天线的封装结构及封装方法
TWI689019B (zh) * 2019-05-29 2020-03-21 力成科技股份有限公司 天線整合式封裝結構及其製造方法
CN110739526B (zh) * 2019-10-29 2021-07-13 中国科学院微电子研究所 天线射频前端封装制造方法
CN111403297A (zh) * 2020-03-26 2020-07-10 甬矽电子(宁波)股份有限公司 Ic射频天线结构的制作方法、ic射频天线结构和半导体器件
CN111585002B (zh) * 2020-05-20 2021-05-14 甬矽电子(宁波)股份有限公司 双向喇叭封装天线结构、其制作方法和电子设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI870951B (zh) * 2022-09-29 2025-01-21 大陸商珠海越亞半導體股份有限公司 半導體封裝結構及其製備方法
TWI863419B (zh) * 2023-04-28 2024-11-21 大陸商訊芯電子科技(中山)有限公司 天線裝置以及天線裝置的製造方法

Also Published As

Publication number Publication date
JP2022120812A (ja) 2022-08-18
US11984414B2 (en) 2024-05-14
KR102811697B1 (ko) 2025-05-21
TWI788191B (zh) 2022-12-21
KR20220113274A (ko) 2022-08-12
CN113035845B (zh) 2022-07-12
JP7316399B2 (ja) 2023-07-27
CN113035845A (zh) 2021-06-25
US20220254741A1 (en) 2022-08-11

Similar Documents

Publication Publication Date Title
TWI788191B (zh) 具有天線的封裝結構及其製作方法
US8034664B2 (en) Method of fabricating passive device applied to the three-dimensional package module
CN107123601B (zh) 一种高散热器件封装结构和板级制造方法
US20220254695A1 (en) Embedded package structure and preparation method therefor, and terminal
CN112335034B (zh) 半导体装置
US20100326707A1 (en) Methal-based package substrate, three-dimensional multi-layered package module using the same, and manufacturing method thereof
CN114641135A (zh) 嵌有连接结构的基板
TW201513280A (zh) Ic載板、具有該ic載板的半導體器件及製作方法
CN110364496A (zh) 一种芯片封装结构及其封装方法
US20210398894A1 (en) Manufacturing method of package carrier
WO2019227956A1 (zh) 一种无线传输模组及制造方法
US7067907B2 (en) Semiconductor package having angulated interconnect surfaces
US7013560B2 (en) Process for fabricating a substrate
CN114585147A (zh) 印刷电路板和电子组件封装件
CN110364490A (zh) 一种芯片封装结构及其封装方法
US6207354B1 (en) Method of making an organic chip carrier package
KR20100034157A (ko) 반도체 패키지용 다열 리드리스 프레임 및 이를 이용한 반도체 패키지의 제조방법
US20130329386A1 (en) Package carrier and manufacturing method thereof
KR20230060446A (ko) 신호-열 분리형 tmv 구조 및 그 제작 방법
US20090288861A1 (en) Circuit board with buried conductive trace formed thereon and method for manufacturing the same
KR101015762B1 (ko) 반도체 패키지의 제조 방법
US20090001547A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
US20250126715A1 (en) Printed circuit board
JP3363065B2 (ja) 半導体パッケージ用チップ支持基板の製造法及び半導体装置
JP4099072B2 (ja) 部品内蔵モジュール