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TW202231146A - 電子裝置及其製造方法 - Google Patents

電子裝置及其製造方法 Download PDF

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Publication number
TW202231146A
TW202231146A TW110102694A TW110102694A TW202231146A TW 202231146 A TW202231146 A TW 202231146A TW 110102694 A TW110102694 A TW 110102694A TW 110102694 A TW110102694 A TW 110102694A TW 202231146 A TW202231146 A TW 202231146A
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Taiwan
Prior art keywords
conductive
electronic device
micro
substrate
semiconductor structures
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TW110102694A
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English (en)
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TWI881025B (zh
Inventor
陳顯德
Original Assignee
優顯科技股份有限公司
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Priority to TW110102694A priority Critical patent/TWI881025B/zh
Priority to US17/583,364 priority patent/US11955453B2/en
Priority to CN202210086746.3A priority patent/CN114793387A/zh
Publication of TW202231146A publication Critical patent/TW202231146A/zh
Application granted granted Critical
Publication of TWI881025B publication Critical patent/TWI881025B/zh

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    • H—ELECTRICITY
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    • H10F77/50—Encapsulations or containers
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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Abstract

一種電子裝置之製造方法；置備一基板結構；基板結構包括一基板、多個微半導體結構、與多個導電件；依一預塗圖樣塗覆一非導電材料於基板結構上，非導電材料沿基板附著導電件；以及非導電材料於基板依一絕緣圖樣形成一非導電部；其中，非導電部包括一個或多個非導電件，非導電部附著其中一個或多個導電件；絕緣圖樣與預塗圖樣呈部分重合。

Description

電子裝置及其製造方法
本發明係關於一種電子裝置及其製程，特別是關於一種微半導體結構之電子裝置及其製程。
傳統上在一目標電路基板上建立導電結構的方式可為錫膏印刷(Solder Paste Printing)、或球格陣列(Ball Grid Array,BGA)等表面黏著技術(Surface Mounting Technology,SMT)；然而，該等表面黏著技術，在精度上無法匹配於尺寸低於100微米的微電子器件。或，傳統上在目標電路基板上塗覆異方性導電膏(Anisotropic Conductive Paste,ACP)；然而，傳統的異方性導電膏或導電膠，為了適配目標電路基板上，導電墊片與導電墊片之間的不同距離，或為了適配具有不同尺度(scale)導電墊片的目標電路基板，通常採用較高粒子填充率的異方性導電膏或導電膠，導電粒子在塗覆膏(熱固膏或熱塑膏)內部呈三維分布，以對導電墊片最高機率地起到導電作用。因此，僅存在有少部分的導電粒子能在目標電路基板上對導電墊片起到導電作用，其餘佔多數的導電粒子則隨塗覆膏的固化而被一併封存於 目標電路基板，而使成本更高的導電粒子因此被浪費。然而對微發光二極體而言，尺寸相當小(例如50微米或以下)，無法以傳統的打線接合或共晶接合的設備進行電極的電連接。
由此可見，對微米或以下尺寸的微微半導體結構或微半導體結構進行電連接，業界亟需有對應的方式。
本發明提供一種電子裝置與電子裝置的製造方法，將微米級或微米級以下的微半導體結構電連接至一基板上。
於此，本發明提出一種電子裝置，包括一基板、多個微半導體結構、多個導電件、與一非導電部。基板具有相對之一第一面與一第二面；該些微半導體結構佈設於基板之第一面；該些導電件電連接該些微導體結構至基板；各個導電件由微半導體結構之一電極或其中一電極、與基板上與之對應之一導電墊片所構成；非導電部佈設於基板之第一面；非導電部包括一個或多個非導電件，其中一個或多個非導電件附著對應其中一些或該些微半導體結構之一些或該些多個導電件。
一些實施例中，各個導電件為銅、鎳、錫、銀、鎵、金、與銦元素之一的金屬材、或至少包含前述任一元素或至少包含前述元素的任何組合所形成的合金材或共金材。
一些實施例中，該非導電部為具有矽氧烷鏈(-Si-O-Si-)之聚合物。
一些實施例中，該非導電部為具有環氧基(-CH-O-CH-)之聚合物。
一些實施例中，該非導電部之環氧值小於0.25。
一些實施例中，非導電部為一光阻。
一些實施例中，其中一非導電件完全包覆所對應之該或該些導電件。
一些實施例中，其中一非導電件至少包覆所對應之該或該些微半導體結構的一部分。
一些實施例中，該些非導電件彼此分離且獨立。
一些實施例中，該些非導電件彼此連接。
一些實施例中，其中各導電件定義有電極與導電墊片之一接合介面；各非導電件之高度大於所對應的該或該些導電件的接合介面。
一些實施例中，各個微半導體結構對應連接其中二導電件。
一些實施例中，導電件之高度大於或等於2μm、小於或等於6μm。
一些實施例中，導電件之寬度小於或等於20μm。
一些實施例中，位於其中一微半導體結構之二導電件之間的距離小於或等於30μm。
一些實施例中，各個微半導體結構為具水平式、垂直式或覆晶式電極之微米級或微米級以下的光電晶粒。
於此，本發明提出一種電子裝置的製造方法，包括下列步驟：
置備一基板結構；基板結構包括一基板、多個微半導體結構、與多個導電件；各導電件電連接基板所對應之該微半導體結構；
依一預塗圖樣塗覆一非導電材料於基板結構上，非導電材料為一流體，非導電材料沿基板附著導電件；以及
非導電材料於該基板依一絕緣圖樣形成一非導電部；其中，非導電部包括一個或多個非導電件，其中一非導電件附著其中多個導電件；絕緣圖樣與預塗圖樣呈部分重合。
一些實施例中，於置備基板結構之步驟中：電連接該些微半導體結構與基板；其中，基板具有多個導電墊片，各微半導體結構朝該基板的一面具有至少一電極，各導電件由其中一導電墊片與各微半導體結構之一電極或其中一電極所構成。
一些實施例中，於置備基板結構之步驟中：熱壓合或雷射銲接其中一導電墊片與各微半導體結構對應之一電極或其中一電極，形成其中一導電件。
一些實施例中，於置備該基板結構之步驟中：各導電件為銅、鎳、錫、銀、鎵、金、與銦元素之一的金屬材、或至少包含前述任一元素或至少包含前述元素的任何組合所形成的合金材或共金材。
一些實施例中，於塗覆非導電材料之步驟中：於相鄰的一些微半導體結構之間塗覆一個非導電材料。
一些實施例中，於塗覆非導電材料之步驟中：同時或依序塗覆該些非導電材料。
於形成非導電部之步驟前：於室溫靜置已塗覆該非導電材料之基板結構1~24小時。
於形成非導電部之步驟前：於40~80攝氏度靜置已塗覆該非導電材料之基板結構0.1~4小時。
一些實施例中，於塗覆非導電材料之步驟中：非導電材料的黏滯性為小於或等於3Pa．s。
一些實施例中，於塗覆非導電材料之步驟中：非導電材料所形成的非導電部包括多個非導電件；各個非導電件附著對應其 中一些微半導體結構之該些導電件。
一些實施例中，於塗覆非導電材料之步驟中：該些非導電件彼此分離且獨立。
一些實施例中，於形成非導電部之步驟後，移除該基板結構上各個微半導體結構的殘留物。
S1~S4、S11~S12、S2a、S3a、S42、S42a:步驟
10、10’:基板
P10:導電墊片
20、20’:微半導體結構
P20:電極
20r:殘留物
30:導電件
E1、E2:端
ES:接合介面
40、40’、40”、40x~40z、40a~40f:非導電件
20R:紅色發光二極體微米級晶粒
20G:綠色發光二極體微米級晶粒
20B:藍色發光二極體微米級晶粒
P:畫素單位
100、100’、100”、100x~z:電子裝置
200:攜載裝置
300、300’、300”、300A:基板結構
400、400a~400d:非導電材料
500:酸液
圖1A至圖1E、圖2為本發明電子裝置不同實施例之示意圖；
圖3、圖3A至圖3C，為不同本發明電子裝置之製造方法的不同實施例的流程圖；
圖4A至圖4D，為圖3的製程示意圖；
圖5、圖6，分別表示電子裝置上的預塗圖樣與絕緣圖樣；以及
圖7A至圖7C為對應圖3A的製程示意圖。
本文用字係解釋在先如後：本文用字「微」半導體結構、「微」半導體器件係同義使用且泛指微米或微米以下的尺度。本文用字「半導體結構」、「半導體器件」同義使用且廣泛地係指一半導體材料、晶粒、結構、器件、一器件之組件、或一半成品。本文用字 「半導體結構」包含高品質單晶半導體及多晶半導體、經由高溫處理而製造之半導體材料、摻雜半導體材料、有機及無機半導體，以及具有一或多個額外半導體組件或非半導體組件之組合半導體材料及結構(諸如，介電層或材料，或導電層或材料)。半導體元件包含(但不限於)電晶體、包含太陽能電池之光伏打器件、二極體、光電二極體、發光二極體、雷射二極體、天線、積體電路及感測器之半導體器件及器件組件；此外，半導體元件可指形成一功能性半導體器件或產品之一部件或部分。本文用字「基板」指用於接收微半導體結構之非原生基板；其可為製程的中間基板或最終基板。原生基板或非原生基板之材料的實施例包含高分子聚合物或非高分子聚合物，例如塑膠或樹脂，更例如聚萘二甲酸乙二酯、聚對苯二甲酸伸乙基酯(polyethylene terephthalate，PET或PETE)、聚醯亞胺(PI)、聚乙烯(Polyethylene,PE)、聚氯乙烯(Polyvinylchloride,PVC)、聚苯乙烯(PS)、壓克力(丙烯，acrylic)、氟化聚合物(Fluoropolymer)、聚酯纖維(polyester)或尼龍(nylon)，或例如金屬、金屬箔、半導體、陶瓷、玻璃、可撓性玻璃、石英、藍寶石、或矽基為主的材料，或例如金屬-玻璃纖維複合材料、金屬-陶瓷複合材料，或例如前述材料以任何形式組成的複合材料等。此外，「基板」上具主動元件之主動電路，主動元件例如矽基之積體電路(Silicon IC)或薄膜電晶體(thin film transistor,TFT)，或「基板」上 為不具主動元件的被動電路，例如導電圖層等。本文用字「電子裝置」，可例如為應用於顯示面板、廣告看板、天線裝置、感測裝置、背光模組或照明裝置等光電半導體裝置或微波陣列裝置；若光電半導體裝置為顯示器時，其可為單色或全彩顯示器。
以下茲配合圖式、圖號說明、元件符號，詳細介紹本發明之具體實施例如后；在圖式中，類似元件符號大體上指示相同、功能上類似及/或結構上類似的元件；此外，元件符號僅供對元件、流程、步驟等說明之用，而對元件之間的順序、上下層關係的限定，除非以文內定義，否則僅供例示與說明。
以下，請配合參照圖1、圖1A、圖1B、與圖2。如圖1所示，本發明揭露一種電子裝置100，包括一基板10、多個微半導體結構20、多個導電件30、與一非導電部。基板10具有相對之一第一面F1與一第二面F2；多個微半導體結構20佈設於基板10之第一面F1；多個導電件30佈設於基板10之第一面F1。非導電部包括一個或多個非導電件40；非導電件40彼此獨立。各個導電件30由該些微半導體結構20之其中一電極、與基板10之對應之一導電墊片所構成；各個非導電件40具有連接基板10的一端E1、連接微半導體結構20的另一端E2、位於兩端間之一接合介面ES；其中，接合介面ES係指微半導體結構20的電極與基板10的導電墊片的介面。非導電部佈設於基板10之第一面F1， 其中一個或多個非導電件40附著對應其中一些微半導體結構20之多個導電件30。一些實施例中，一個非導電件40附著對應其中一些或該些微半導體結構20之該些導電件30；一些實施例中，其中一些非導電件40附著對應其中一些或該些微半導體結構20之該些導電件30；一些實施例中，該些非導電件40附著對應其中一些或該些微半導體結構20之該些導電件30；一些實施例中，非導電件40附著所對應微半導體結構20的至少一部分；一些實施例中，非導電件40於對應導電件30上至少附著至接合介面ES。
本實施例中，微半導體結構20以微光電二極體為例，各微半導體結構20可以為具水平式、垂直式或覆晶式電極之一微米級或微米級以下的微光電晶粒；可理解的是，微米(micro meter,μm)級亦包括數百μm、100μm、或100μm以下(例如50μm、80μm)；微米級以下可包含奈米級，例如50nm、10nm、5nm。各導電件30為銅、鎳、錫、銀、鎵、金、與銦元素之一的金屬材、或至少包含前述任一元素或至少包含前述元素的任何組合所形成的合金材或共金材。本實施例中，非導電件40彼此分離且獨立、且數量與導電件30的數量呈一對一配置。
一些實施例中，微半導體結構20與基板10之間以兩個導電件30電連接。在一些實施例中，各導電件30之高度大於或等於2 微米(micro meter,μm)、小於或等於6μm；例如，各導電件30之高度可以是2μm、3μm、4μm、5μm、6μm。在一些實施例中，導電件30之寬度小於或等於20μm；例如，導電件30之寬度可以是3μm、5μm、8μm、15μm、20μm。在一些實施例中，位於其中一微半導體結構20之兩個導電件30之間的距離大於或等於3μm、小於或等於30μm；例如，兩個導電件30之間的距離可以是3μm、5μm、8μm、10μm、15μm、20μm、30μm。在一些實施例中，各非導電件40具有大於或等於0.5μm之高度；例如，各非導電件40之高度可為2μm、3μm。在一些實施例中，各非導電件40之高度可高於接合介面ES與基板10的第一面F1的距離，但並不侷限。可以理解的是，各非導電件40之高度係自基板10的第一面F1起算。
一些實施例中，至少其中一非導電件40完全包覆所對應的其中一個或一些微半導體結構20其中一個或一些導電件30。一些實施例中，非導電件40其中一端(E1、E2)之徑寬大於中間段ES之徑寬。一些實施例中，各非導電件40為具有矽氧烷鏈(-Si-O-Si-)之聚合物。一些實施例中，各非導電件40的為具有環氧基(-CH-O-CH-)之聚合物；一些實施例中，各非導電件40之環氧值小於0.25。
在一些實施例中，非導電件40’與導電件30呈一對多配置，例如圖1A中的微半導體結構20與基板10之間以兩個導電件30 電連接，一個非導電件40’同時附著兩個導電件30，如圖1A所示之電子裝置100’；此時，非導電件40’與微半導體結構20呈一對一配置；在一些實施例中，非導電件40’未填滿微半導體結構20中的兩個導電件30，本發明並不限制。
在一些實施例中，非導電件40”與導電件30仍然呈一對多配置，且非導電件40”與微半導體結構20亦呈一對多配置，如圖1B所示之電子裝置100”；即一個非導電件40”同時附著兩個相鄰的微半導體結構20中的其中一個導電件30，圖1B以一個非導電件40”同時附著兩個相鄰的微半導體結構20中的兩個導電件30為例。本實施例中，並不限制非導電件40”是否填滿對應一個微半導體結構20中的兩個導電件30之間，例如其中一非導電件40”未填滿對應一個微半導體結構20的兩個導電件30之間，另一非導電件40”填滿對應一個微半導體結構20中的兩個導電件30之間。
在一些實施例中，不論非導電件40x與導電件30、非導電件40x與微半導體結構20的配置，非導電件40'''進一步附著至所對應之一個或多個微半導體結構20的頂緣或頂面，如圖1C所示之電子裝置100x，即非導電件40x的高度相當於或超過微半導體結構20與導電件30的整體高度；或，非導電件40y附著至所對應的微半導體結構20的側壁，如圖1D所示之電子裝置100y，即非導電件40y的高度不超 過微半導體結構20與導電件30的整體高度；或，非導電件40z附著至所對應的導電件30的側壁，如圖1E所示之電子裝置100z，即非導電件40z的高度不超過導電件30的整體高度；一些實施例中，非導電件40於對應導電件30上至少附著接合介面ES，或不受限制。
又，圖2則以兩個以上且各自獨立的非導電件40”為例，各個非導電件40”同時附著多個相鄰的微半導體結構20中的至少一個導電件30，本實施例是以兩個相鄰的微半導體結構20為例，且不同的非導電件40”可同時附著不同數量的微半導體結構20，本發明並不限制。
以下，請配合參照圖3、圖4A至圖4D、圖5與圖6；圖3係說明上述電子裝置100的製作方法；圖4A至圖4D係對應圖3中步驟的示意圖；圖5與圖6分別表示步驟S2的預塗圖樣與步驟S3的絕緣圖樣。
如圖3所示的步驟S1至步驟S3。
步驟S1：置備如圖4B之一基板結構300。基板結構300包括一基板10、多個微半導體結構20、與多個導電件30；各導電件30電連接基板10與所對應之微半導體結構20。其中，各導電件30具有電連接基板10之一第一端E1、與相對第一端E1且電連接所對應微半導體結構20之一第二端E2。其中，步驟S1更進一步包括步驟S11與步驟 S12：
步驟S11：如圖4A，使多個微半導體結構20’置於一攜載裝置200，並使攜載裝置200具有多個微半導體結構20’的一面與一基板10’彼此迫近。此時，微半導體結構20’朝基板的一面具有至少一電極P20、基板10’朝微半導體結構20’的一面具有多個導電墊片P10。
步驟S12：通過熱壓合或雷射銲接，使微半導體結構20’的電極P20對應連接基板10’的導電墊片P10，形成如圖4B的導電件30。導電件30定義有兩個電極P10、P20的接合介面ES。
步驟S2：如圖4C，塗覆一非導電材料400於基板結構300上，非導電材料400為一流體狀態，沿基板基板10’附著導電件30。
一些實施例中，非導電材料400與基板10’之間的附著力大於非導電材料400之內聚力，或不受限制。一些實施例中，非導電材料400可為黏滯性(Viscosity)小於或等於3Pa．s的流體，例如，非導電材料400可為黏滯性小於或等於2Pa．s的流體、或小於或等於1Pa．s的流體。非導電材料400可於基板10’的第一面F1擴散並迫近鄰近的一個或一些微半導體結構20’。一些實施例中，基板10’可至少於第一面F1形成極性，可提高非導電材料400與基板10’的附著力。又，由於非導電材料400與基板結構300上的導電件30之間的附著力大於非料導電材400之內聚力，非導電材料400可因毛細現象攀附並包覆導電件30的 至少一部分；一些實施例中，非導電件40於對應的導電件30上至少附著至接合介面ES，或不受限制。在一些實施例中，非導電材料400完全包覆導電件30，如圖4D所示，非導電材料400於對應的導電件30由第一端E1包覆至第二端E2。
一些實施例中，非導電材料400為具有環氧基(-CH-O-CH-)之聚合物；一些實施例中，非導電材料400之環氧值小於0.25。一些實施例中，非導電材料400為具有矽氧烷鏈(-Si-O-Si-)之聚合物。
本實施例中，非導電材料400的黏滯性小於或等於3泊(poise,Pa．s)，或進一步非導電材料400為黏滯性小於或等於3泊(poise,Pa．s)的一聚合物。一些實施例中，非導電材料400的黏滯性小於或等於2泊或1泊。一些實施例中，各非導電材料400具有耐酸性。
為便於理解，塗覆非導電材料400於基板結構300上所根據的預塗圖樣，可參閱圖5中同時繪示多種塗覆非導電材料的多種預塗圖樣，但並不限於此。例如，如圖5，基板結構300上以多個微半導體結構為一畫素單位P(以彩色顯示為例，並以點鏈線(dot-and-dash line)表示)，包括紅色發光二極體微米級晶粒20R、綠色發光二極體微米級晶粒20G、藍色發光二極體微米級晶粒20B；在不同畫素單位P中，一個非導電材料400a可塗覆於相鄰4個畫素單位P之間；在不同畫素單位P中，一個非導電材料400b可塗覆於相鄰2個畫素單位P的其中一角； 在不同畫素單位P中，一個非導電材料400c可沿X軸塗覆於相鄰2個畫素單位P之間；在不同畫素單位P中，一個非導電材料400d可沿Y軸塗覆於相鄰2個畫素單位P之間；在同一畫素單位P中，多個非導電材料可對應且各自附著多個微半導體結構的導電材(圖未繪示)。在一些實施例中，該些非導電材料可陣列塗覆、隨機塗覆、旋轉塗覆或非規律塗覆。在一些實施例中，可同時或依序塗覆該些非導電材料。
步驟S3：非導電材料400於基板10上依一絕緣圖樣形成一非導電部；其中，非導電部附著該些導電件30；絕緣圖樣與預塗圖樣呈部分重合。
一些實施例中，基板10塗覆非導電材料400後，可於室溫靜置1~24小時，形成前述的非導電部；其中，室溫例如為20~30攝氏度。
一些實施例中，基板10塗覆非導電材料400後，可加熱40~80攝氏度並靜置0.1~4小時，形成前述的非導電部。
此外，非導電材料400所形成之導電部可包括一個或多個非導電件40；各個非導電件40附著對應其中一些或該些微半導體結構的一個或多個導電件30。為便於理解，仍以基板結構300上以多個畫素單位P為例，於圖6中同時繪示於基板結構300’上多種形成非導電部(非導電件)的多種絕緣圖樣，但並不限於此。例如，在同一畫素 單位P中，多個非導電材料40可對應且各自附著多個微半導體結構的至少一導電材；在同一畫素單位P中，一個非導電件40a可對應附著多個微半導體結構的多個導電材；在不同畫素單位P中，一個導電件40b可沿X軸對應附著相鄰2個畫素單位P中多個微半導體結構的多個導電材；在不同畫素單位P中，一個導電件40c可對應附著相鄰4個畫素單位P中多個微半導體結構的多個導電材；在不同畫素單位P中，一個導電件40c可對應附著相鄰4個畫素單位P中多個微半導體結構的多個導電材，同一導電件40c呈連續不中斷；在選用在不同畫素單位P中，一個導電件40d、40e、40f可對應附著相鄰4個畫素單位P中多個微半導體結構的多個導電材，區別在於，導電件40d、40e、40f具有程度不一的空缺，於本發明中仍可作為同一導電材。
請配合參照圖3A、與圖7A至圖7C，如圖3A所示的步驟S1至步驟S4。由於基板結構300”上的各個微半導體結構20自剝離一基材(圖未示)後，尚留有如圖7A的一殘留物20r，例如鎵(Gallium)；故於圖3A中更包括一步驟S4：移除殘留物20r。
其中，移除殘留物的方法包括：將基板結構300”連同微半導體結構20置於如圖7B的一酸液500中，酸洗基板結構300”上的各個微半導體結構20並移除其殘留物22r，使微半導體結構20有更好的發光效率，形成一基板結構300A。非導電部(非導電件)可進一步保 護導電件30不受酸液腐蝕。一些實施例中，酸液500包括鹽酸。
或者，請再配合參照圖3B，移除殘留物的方法包括如步驟S4a：將基板結構300”連同微半導體結構20置於攝氏溫度大於或等於30度的一液態物質中，移除基板結構300”上的各個微半導體結構20的殘留物20r。一些實施例中，液態物質可例如為水或乙醇或異丙醇。
或者，更進一步在步驟S4a中：於基板結構300”連同微半導體結構20置於液態物質中時，同時提供超音波震動。
圖3C的實施例中，採用另一種非導電材料。
步驟S1：仍是置備一基板結構。基板結構包括一基板、多個微半導體結構、與多個導電件，在此不再贅述。
步驟2：塗覆一非導電材料於基板結構上，非導電材料沿基板附著導電件，非導電材料可因毛細現象攀附並附著導電件的至少一部分。與前述實施例不同的是，本實施例的非導電材料為一液態光阻材料。
步驟3a：對基板結構上的非導電材料進行微影製程(photolithography)，以依一絕緣圖樣形成一非導電部。其中，微影製程可包括但不限於：對光阻材料的軟烤(前烘)、曝光(例如紫外線波長的準分子雷射)、顯影、去光阻等步驟。
圖3D的實施例中，採用又一種新的非導電材料。
本實施例中，步驟S1、步驟S3(步驟S3a)，不再贅述。
步驟2a：塗覆一非導電材料於基板結構上，非導電材料沿基板附著導電件，非導電材料可因毛細現象攀附並攀附導電件的至少一部分。與前述實施例不同的是，本實施例的非導電材料為深色塗料。可理解的是，本實施例的非導電材料可為本發明中所提及的任何一種材料，再另參雜吸收可見光的光吸收物質而形成深色塗料，例如為黑色塗料。藉此，當電子裝置為光電裝置時，黑色塗料可降低外部環境光在電子裝置的影響，以提高電子裝置的對比效果。可以理解的是，在一些實施例中，本實施例的非導電材料為全面性(或幾近全面性)地塗覆。
由於微半導體結構的尺寸相當小，其設置密度可相對提高，使得製得的電子裝置100或應用於光電半導體裝置的基板結構300”可具有比較高的置件密度，本發明不但能以簡便製法達成電子裝置100，更具有以較低成本、較高效率的方法保護導電件的優勢。
綜上所述，在本發明之電子裝置、以及電子裝置的製造方法，於微半導體結構與基板間先行(利用熱壓合或雷射銲接)完成導電件，再點塗非導電材料，使非導電材料與導電件之間因毛細現象而攀附、附著導電件的至少一部分，其功效包含如下(但不限於此)：
1、各個微半導體結構與基板之間可逕行利用熱壓合或雷射銲接製成導電件，流體態之非導電材料施於各個微半導體結構與基板間因毛細現象而攀附前述導電件的至少一部分，製程不僅簡化，也降低製程成本。
2、各個微半導體結構與基板之間的導電件可由非導電部附著而可至少與基板之間具有較佳的穩定性。
3、省略如異方性導電膏或導電膠的導電粒子，大幅降低成本。
4、各個微半導體結構與基板之間的導電件可由非導電部附著而能抗酸，有利於在後續進行的為酸洗製程時，移除微半導體結構上的殘留物而不破壞導電件的接合介面。
5、當利用溫水(或中性物質流體)移除微半導體結構上的殘留物時，既不破壞導電件裸露(如果有)的接合介面，製程也相對簡便、且成本大幅降低。
6、當電子裝置為光電裝置時，非導電材料為深色塗料時，可降低外部環境光對電子裝置的影響；並進一步提高電子裝置的對比效果。
7、允許此等超薄、易碎及/或微半導體結構的可撓應用而不導致對微半導體結構本身之損壞。
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。
S1~S3、S11~S12:步驟

Claims (28)

  1. 一種電子裝置，包括：
    一基板，具有相對之一第一面與一第二面；
    多個微半導體結構，佈設於該基板之該第一面；
    多個導電件，電連接該些微導體結構至該基板；各該導電件由該些微半導體結構之其中一電極、與該基板之對應之一導電墊片所構成；以及
    一非導電部，佈設於該基板之該第一面；該非導電部包括一個或多個非導電件，其中一該或多個非導電件附著對應其中一些或該些微半導體結構之一些或該些多個導電件。
  2. 如請求項1所述的電子裝置，其中：各該導電件為銅、鎳、錫、銀、鎵、金、與銦元素之一的金屬材、或至少包含前述任一元素或至少包含前述元素的任何組合所形成的合金材或共金材。
  3. 如請求項1所述的電子裝置，其中：該非導電部為具有矽氧烷鏈(-Si-O-Si-)之聚合物。
  4. 如請求項1所述的電子裝置，其中：該非導電部為具有環氧基(-CH-O-CH-)之聚合物。
  5. 如請求項5所述的電子裝置，其中：該非導電部之環氧值小於0.25。
  6. 如請求項1所述的電子裝置，其中：該非導電部為一光阻。
  7. 如請求項1所述的電子裝置，其中：其中一該非導電件完全包覆所對應之該或該些導電件。
  8. 如請求項1所述的電子裝置，其中：其中一該非導電件至少包覆所對應之該或該些微半導體結構的一部分。
  9. 如請求項1所述的電子裝置，其中：該些非導電件彼此分離且獨立。
  10. 如請求項1所述的電子裝置，其中：該些非導電件彼此連接。
  11. 如請求項1所述的電子裝置，其中：各該導電件定義有電極與導電墊片之一接合介面；各該非導電件之高度大於所對應的該或該些導電件的接合介面。
  12. 如請求項1所述的電子裝置，其中：各該微半導體結構對應其中二該導電件。
  13. 如請求項1所述的電子裝置，其中：該導電件之高度大於或等於2μm、小於或等於6μm。
  14. 如請求項1所述的電子裝置，其中：該導電件之寬度小於或等於20μm。
  15. 如請求項12所述的電子裝置，其中：位於其中一該微半導體結構之二該導電件之間的距離小於或等於30μm。
  16. 如請求項1所述的電子裝置，其中：各該微半導體結構為具水平式、垂直式或覆晶式電極之微米級或微米級以下的光電晶粒。
  17. 一種電子裝置的製造方法，包括：
    置備一基板結構；該基板結構包括一基板、多個微半導體結構、與多個導電件；各該導電件電連接該基板與所對應之該微半導體結構；
    依一預塗圖樣塗覆一非導電材料於該基板結構上，該非導電材料為一流體沿該基板附著所對應該或該些導電件；以及
    該非導電材料於該基板結構之該基板依一絕緣圖樣形成一非導電部；其中，該非導電部附著該些導電件；該絕緣圖樣與該預塗圖樣呈部分重合。
  18. 如請求項17所述電子裝置的製造方法，其中，於置備基板結構之步驟中：
    電連接該些微半導體結構與該基板；其中，該基板具有多個導電墊片，各該微半導體結構朝該基板的一面具有至少一電極，各該導電件由其中一該導電墊片與各該微半導體結構之其中一電極所構成。
  19. 如請求項17所述電子裝置的製造方法，其中，於置備基板結構之步驟中：
    熱壓合或雷射銲接其中一該導電墊片與各該微半導體結構對應之一該電極，形成其中一該導電件。
  20. 如請求項17所述電子裝置的製造方法，其中，於置備該基板結構之步驟中：
    各該導電件為銅、鎳、錫、銀、鎵、金、與銦元素之一的金屬材、或至少包含前述任一元素或至少包含前述元素的任何組合所形成的合金材或共金材。
  21. 如請求項17所述電子裝置的製造方法，其中，於塗覆非導電材料之步驟中：
    於相鄰的其中一些微半導體結構之間塗覆一該非導電材料。
  22. 如請求項21所述電子裝置的製造方法，其中，於塗覆非導電材料之步驟中：
    同時或依序塗覆該些非導電材料。
  23. 如請求項17所述電子裝置的製造方法，其中，於形成非導電部之步驟前：
    於室溫靜置已塗覆該非導電材料之該基板結構1~24小時。
  24. 如請求項17所述電子裝置的製造方法，其中，於形成非導電部之步驟前：
    於40~80攝氏度靜置已塗覆該非導電材料之該基板結構0.1~4小時。
  25. 如請求項17所述電子裝置的製造方法，其中，於塗覆非導電材料之 步驟中：
    該非導電材料的黏滯性為小於或等於3Pa．s。
  26. 如請求項17所述電子裝置的製造方法，其中，於形成非導電部之步驟中：
    該非導電材料所形成之該非導電部包括多個非導電件；各該非導電件附著對應其中一些微半導體結構之該些導電件。
  27. 如請求項26所述電子裝置的製造方法，其中，於形成非導電部之步驟中：
    該些非導電件彼此分離且獨立。
  28. 如請求項17所述電子裝置的製造方法，其中，於形成非導電部之步驟後：
    移除該基板結構上各個微半導體結構的殘留物。
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