TW202207635A - Signal receiving device - Google Patents

Abstract

A signal receiving device includes a first amplifier, a duty cycle adjuster and a common mode feedback circuit. The first amplifier receives an input signal, a reference voltage and a bias voltage. The first amplifier generates a first common current, based on the first common current, generates a first output signal and a second output signal according to the input signal and the reference voltage where the first and second output signals are complementary. The duty cycle adjuster charges a selected capacitor by the first output signal or the second output signal to generate a sensing voltage, and generates a common reference voltage according to the sensing voltage. The common mode feedback circuit generates the bias voltage by comparing the common reference voltage and the reference voltage.

Description

signal receiving device

The present invention relates to a signal receiving device, and more particularly, to a signal receiving device capable of adjusting the duty cycle of an output signal.

In the prior art, the pre-amplifier in the signal receiver is often realized through a differential amplifier. The differential amplifier operates based on a common current, and the voltage value of the output signal can be determined according to the magnitude of the current flowing through the differential transistor.

In the conventional technical field, since the magnitude of the shared current is fixed, when the on-voltage of the differential transistor varies due to process drift or environmental factors, the conductance value of the differential transistor will change accordingly. Such changes may make the duty cycle of the output signal generated by the differential amplifier unable to maintain the correct range, resulting in the phenomenon of distortion of the received signal.

The invention provides a signal receiving device which can dynamically adjust the duty cycle of the output signal.

The signal receiving device of the present invention includes a first amplifier, a duty cycle adjuster and a common mode feedback circuit. The first amplifier receives the input signal, the reference voltage and the bias voltage. The first amplifier generates a first common current according to the bias voltage, and generates a complementary first output signal and a second output signal according to the comparison input signal and the reference voltage based on the first common current. The duty cycle adjuster receives the first output signal and the second output signal, performs charging and discharging operations on the selected capacitor according to the first output signal or the second output signal to generate a sensing voltage, and generates a common reference voltage according to the sensing voltage. The common mode feedback circuit receives the common reference voltage, and generates a bias voltage according to the comparison of the common reference voltage and the reference voltage.

Based on the above, the embodiments of the present invention provide a duty cycle adjuster to detect the change of the duty cycle of the output signal of the amplifier, and adjust the bias voltage of the amplifier for generating the common current according to the change of the duty cycle of the output signal. In this way, the distortion of the output signal of the amplifier due to the change of the transductance value can be compensated to maintain the correctness of the output signal.

FIG. 1 is a schematic diagram of a signal receiving apparatus according to an embodiment of the present invention. The signal receiving apparatus 100 includes an amplifier 110 , a duty cycle adjuster 120 and a common mode feedback circuit 130 . The amplifier 110 receives the input signal Vin, the reference voltage Vref and a bias voltage Vbias. The amplifier 110 generates a common current according to the bias voltage Vbias, and based on the common current, generates a complementary output signal Vout1 and an output signal Vout1_n according to the comparison of the input signal Vin and the reference voltage Vref. The amplifier 110 may be a differential amplifier circuit. The amplifier 110 can determine the common-mode voltage levels of the output signals Vout1 and Vout1_n according to the common current generated by the bias voltage Vbias.

The duty cycle adjuster 120 is coupled to the amplifier 110 . The duty cycle adjuster 120 receives complementary output signals Vout1 and Vout1_n. The duty cycle adjuster 120 performs charging and discharging operations on a selected capacitor according to the output signal Vout1 or the output signal Vout1_n, thereby generating a sensing voltage. The duty cycle adjuster 120 generates the common reference voltage Vcom_ref according to the sensing voltage.

In this embodiment, the duty cycle adjuster 120 performs charging and discharging operations on the selected capacitor by making one of the output signal Vout1 and the output signal Vout1_n to sense the duty cycle of the output signal Vout1 and the output signal Vout1_n, and The common reference voltage Vcom_ref is obtained according to the generated sensing voltage.

The common reference voltage Vcom_ref is provided to the common mode feedback circuit 130 . The common mode feedback circuit 130 further receives the reference voltage Vref, and adjusts the voltage value of the bias voltage Vbias according to the comparison of the common reference voltage Vcom_ref and the reference voltage Vref.

According to the above, by adjusting the voltage value of the bias voltage Vbias, the common current in the amplifier 110 can be adjusted. In this way, when the on-voltage of the differential transistor in the amplifier 110 varies, the conductance value of the differential transistor can be automatically adjusted by adjusting the current flowing through the differential transistor, so as to maintain the output signal Vout1 and the duty cycle of the output signal Vout1_n.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram illustrating an implementation of a duty cycle adjuster according to an embodiment of the present invention. The duty cycle adjuster 200 includes a sensing circuit 210 and a common reference voltage generating circuit 220 . The sensing circuit 210 receives the output signal Vout1 and the output signal Vout1_n. A selected capacitor can be set in the sensing circuit 210, and the selected capacitor is charged and discharged based on the output signal Vout1 or the output signal Vout1_n, thereby generating the sensing voltage VA. The sensing circuit 210 provides the sensing voltage VA to the common reference voltage generating circuit 220 . The common reference voltage generating circuit 220 provides a plurality of threshold voltages, and compares the sensing voltage VA with the plurality of threshold voltages, thereby generating a plurality of comparison results. The common reference voltage generating circuit 220 adjusts the voltage value of the common reference voltage Vcom_ref according to the obtained comparison result.

For details, please refer to the circuit diagram of another implementation manner of the duty cycle adjuster according to the embodiment of the present invention shown in FIG. 3 . The duty cycle adjuster 300 includes a sensing circuit 310 and a common reference voltage generating circuit 320 . In this embodiment, the sensing circuit 310 includes a differential pair 311, a current source 312, loads RL1, RL2, capacitors CA, CB, operational amplifiers OP1, OP2, and resistors RE1, RE2. The differential pair 311 is composed of transistors M1 and M2. The loads RL1 and RL2 are respectively coupled to the first terminals of the transistors M1 and M2, and the loads RL1 and RL2 are coupled to the reference power terminal VDD in common. The first ends of the transistors M1 and M2 respectively form two load ends of the differential pair 311 . The control terminals of the transistors M1 and M2 respectively form two input terminals of the differential pair 311 and receive the output signals Vout1 and Vout1_n respectively.

In addition, the second terminals of the transistors M1 and M2 are connected to each other and form a common terminal of the differential pair 311 . The current source 312 is constructed by the transistor M3. The transistor M3 is coupled between the common terminal of the differential pair 311 and the reference power terminal VSS, and the control terminal of the transistor M3 is coupled to the operational amplifier OP2.

Current source 312 provides current IT as a common current for differential pair 310 . The transistors M1 and M2 respectively generate currents I1 and I2 according to the received output signals Vout1 and Vout1_n, wherein the sum of the currents I1 and I2 is equal to the current IT.

On the other hand, the capacitor CA is connected in series between the first terminal of the transistor M1 and the reference power terminal VSS, and the capacitor CB is connected in series between the first terminal of the transistor M2 and the reference power terminal VSS. The capacitors CA and CB can be charged and discharged according to the voltage values on the first terminals of the transistors M1 and M2, respectively, so as to generate the sensing voltages VA and VB respectively.

In this embodiment, the capacitor CA is coupled to the common reference voltage generating circuit 320, so the capacitor CA can be used as the selected capacitor. In other embodiments of the present invention, the capacitor CB can also be coupled to the common reference voltage generating circuit 320, and the capacitor CB can be used as the selected capacitor, which is not limited.

In terms of operation details, since the output signal Vout1 is a signal that repeatedly transitions between the first voltage and the second voltage (for example, the first voltage is greater than the second voltage), when the output signal Vout1 is equal to the relatively large first voltage, the current The current I1 of the load RL1 rises and the sense voltage VA falls. When the output signal Vout1 is equal to the relatively small second voltage, the current I1 flowing through the load RL1 drops, and the sensing voltage VA rises. Therefore, the duty cycle of the output signal Vout1 may be inversely proportional to the voltage value of the sensing voltage VA. Therefore, according to the change of the voltage value of the sensing voltage VA, the change of the duty cycle of the output signal Vout1 can be obtained.

Incidentally, in this embodiment, the operational amplifiers OP1 and OP2 are used to generate the bias voltage received by the current source 312 . The operational amplifier OP1 receives the reference voltage Vref, and the output terminal of the operational amplifier OP1 is coupled to the positive input terminal of the operational amplifier OP2. The negative input terminal of the operational amplifier OP2 is coupled to the resistor string formed by the resistors RE1 and RE2. The resistors RE1 and RE2 are coupled between the reference power terminals Vref_res and VSS.

The common reference voltage generating circuit 320 includes a decoder 321 , a threshold voltage generator 322 , a voltage divider 323 , a comparator OP3 and a comparator OP4 . The decoder 321 is an analog digitizer. The threshold voltage generator 322 is formed by a plurality of resistors Ra, Rb and Rc. The resistors Ra, Rb, and Rc are sequentially coupled in series between the reference power terminal Vref_res and the reference power terminal VSS. The threshold voltage generator 322 divides the reference power provided by the reference power terminal Vref_res through the resistors Ra, Rb and Rc to generate a plurality of threshold voltages. In this embodiment, the threshold voltage generator 322 has three resistors Ra, Rb and Rc, and can generate two threshold voltages.

The comparators OP3 and OP4 can be constructed by operational amplifiers. The positive input terminal of the comparator OP3 receives the sensing voltage VA, and the negative input terminal of the comparator OP3 is coupled to the connection terminal of the resistors Ra and Rb, and receives the first threshold voltage. The negative input terminal of the comparator OP4 receives the sensing voltage VA, and the positive input terminal of the comparator OP4 is coupled to the connection terminals of the resistors Rb and Rc, and receives a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage threshold voltage.

The comparators OP3 and OP4 compare the sensing voltage VA with the first threshold voltage and the second threshold voltage, and generate comparison results A and B, respectively. Wherein, when the sensing voltage VA is greater than the first threshold voltage and greater than the second threshold voltage, the comparators OP3 and OP4 can respectively generate a logic high level comparison result A and a logic low level comparison result B ; When the sensing voltage VA is less than the first threshold voltage, but greater than the second threshold voltage, the comparators OP3 and OP4 can respectively generate a logic low level comparison result A and a logic low level comparison result B; When the sensing voltage VA is less than the first threshold voltage and less than the second threshold voltage, the comparators OP3 and OP4 can generate a logic low level comparison result A and a logic high level comparison result B, respectively.

The decoder 321 receives the comparison results A and B, and decodes the comparison results A and B, thereby generating an adjustment code COD. The voltage divider 323 includes resistors R1 and R2. Resistors R1 and R2 are coupled in series between the reference power terminals Vref_res and VSS. The resistors R1 and R2 divide the reference power provided by the reference power terminal Vref_res to generate a common reference voltage Vcom_ref. Wherein, in this embodiment, the resistor R2 is a variable resistor. The resistance value of the resistor R2 can be determined according to the adjustment code COD. By increasing the resistance value of the resistor R2 , the voltage value of the common reference voltage Vcom_ref can be increased. On the contrary, by decreasing the resistance value of the resistor R2 , the voltage value of the common reference voltage Vcom_ref can be decreased.

Regarding the relationship between the adjustment action of the common reference voltage Vcom_ref and the sensing voltage VA and the comparison results A and B in this embodiment, see Table 1 below:

Table 1: Working period Sensing voltage VA Comparison result A Comparison result B Vcom_ref 50% 1V L L maintain 30% 1.2V H L reduce 70% 0.8V L H promote

In Table 1, L represents a logic low level, and H represents a logic high level. When the sensing voltage VA is 1V, the comparison results A and B are both logic low levels (L). At this time, the duty cycle of the output signal Vout1 is 50%, and there is no need to adjust the voltage value of the common reference voltage Vcom_ref; when When the sensing voltage VA is 1.2V, the comparison results A and B are the logic high level (H) and the logic low level (L) respectively. At this time, the duty cycle of the output signal Vout1 is 30%, and the common reference voltage can be lowered. The voltage value of Vcom_ref increases the duty cycle of the output signal Vout1; when the sensing voltage VA is 0.8V, the comparison results A and B are respectively a logic low level (L) and a logic high level (H). The duty cycle of the output signal Vout1 is 70%, and the voltage value of the common reference voltage Vcom_ref can be increased to reduce the duty cycle of the output signal Vout1.

Incidentally, in this embodiment, the resistor R1 can also be set as a variable resistor, and the resistor R1 can receive the adjustment code COD to adjust the provided resistance value, thereby generating the common reference voltage Vcom_ref. Under such a mechanism, under the condition that the voltage value of the common reference voltage Vcom_ref needs to be increased, the adjustment code COD generated by the decoder 321 needs to reduce the resistance value of the resistor R1. On the contrary, when the voltage value of the common reference voltage Vcom_ref needs to be lowered Under the condition of the same value, the adjustment code COD generated by the decoder 321 needs to increase the resistance value of the resistor R1.

Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of a signal receiving apparatus according to another embodiment of the present invention. The signal receiving apparatus 400 includes amplifiers 410 and 440 , a common mode feedback circuit 430 and a duty cycle adjuster 420 . Amplifier 410 may serve as a pre-amplifier. The amplifier 410 receives the input signal Vin, the reference voltage Vref, and the bias voltage Vbias. The amplifier 410 generates a common current according to the bias voltage Vbias, and based on the common current, generates complementary output signals Vout1 and Vout1_n according to the comparison input signal Vin and the reference voltage Vref. The amplifier 440 is coupled to the output terminal of the amplifier 410, receives the output signals Vout1 and Vout1_n, and receives the bias voltage Vbias. The amplifier 440 generates a common current according to the bias voltage Vbias, and generates a post-stage output signal Vout2 according to the output signals Vout1 and Vout1_n based on the common current.

The common mode feedback circuit 430 is coupled to the amplifiers 410 and 440 to generate the bias voltage Vbias according to the reference voltage Vref and the common reference voltage Vcom_ref. In this embodiment, the common mode feedback circuit 430 can be implemented by any common mode feedback circuit (CMFB circuit) well known to those skilled in the art, without any specific limitation.

The duty cycle adjuster 420 is coupled to the amplifier 410 and the common mode feedback circuit 430 . For the implementation details of the duty cycle adjuster 420 , reference may be made to the implementation of the foregoing embodiments (eg, the duty cycle adjuster 300 in FIG. 3 ), and details are not described herein.

For the implementation details of the common mode feedback circuit, reference may be made to the circuit diagram of the implementation of the common mode feedback circuit according to the embodiment of the present invention shown in FIG. 5 . In FIG. 5 , the common mode feedback circuit 500 includes amplifiers OP51 , OP52 and a transistor M51 . The two input terminals of the amplifier OP51 receive the reference voltage Vref synchronously, and the output terminal of the amplifier OP51 is coupled to the positive input terminal of the amplifier OP52. The transistor M51 serves as a current source of the amplifier OP51 and is coupled between the amplifier OP51 and the reference power terminal VSS. The negative input terminal of the amplifier OP52 receives the common reference voltage Vcom_ref and is used to generate the bias voltage Vbias. In addition, the bias voltage Vbias is also supplied to the gate terminal of the transistor M51.

It is worth mentioning that, in the embodiment of the present invention, the circuit structure of the amplifier OP51 may be the same as that of the amplifiers 110 and 410 in the embodiments of FIGS. 1 and 4 .

In summary, the embodiment of the present invention senses the duty cycle of the output signal of the amplifier, and adjusts the voltage value of the common reference voltage through the common mode feedback circuit, so as to compensate for the variation in the on-voltage of the differential transistor of the amplifier and maintain the output The duty cycle of the signal is in the valid range.

100, 400: Signal receiving device 110, 410, 440, OP51, OP52: Amplifier 120, 200, 420: duty cycle adjuster 130, 430, 500: Common mode feedback circuit 210: Sensing circuit 220: common reference voltage generation circuit 311: Differential pair 312: Current source 321: decoder 323: Voltage divider A, B: Comparison results COD: adjustment code RL1, RL2: load CA, CB: Capacitor OP1, OP2: operational amplifier OP3, OP4: Comparator RE1, RE2, Ra, Rb, Rc, R1, R2: Resistance M1~M3, M51: Transistor VDD, VSS, Vref1_res: Reference power terminal I1, I2, IT: Current VA, VB: Sensing voltage Vin: input signal Vref: reference voltage Vbias: bias voltage Vout1, Vout1_n: output signal Vout2: Post-stage output signal Vcom_ref: common reference voltage

FIG. 1 is a schematic diagram of a signal receiving apparatus according to an embodiment of the present invention. FIG. 2 is a schematic diagram illustrating an implementation of a duty cycle adjuster according to an embodiment of the present invention. FIG. 3 is a circuit diagram of another implementation of the duty cycle regulator according to the embodiment of the present invention. FIG. 4 is a schematic diagram of a signal receiving apparatus according to another embodiment of the present invention. FIG. 5 is a circuit diagram illustrating an implementation of a common mode feedback circuit according to an embodiment of the present invention.

100: Signal receiving device

110: Amplifier

120: Duty cycle adjuster

130: Common mode feedback circuit

Vin: input signal

Vref: reference voltage

Vbias: bias voltage

Vout1, Vout1_n: output signal

Vcom_ref: common reference voltage

Claims (10)

A signal receiving device, comprising: a first amplifier receives an input signal, a reference voltage and a bias voltage, the first amplifier generates a first common current according to the bias voltage, and based on the first common current, compares the input signal and the the reference voltage to generate a complementary first output signal and a second output signal; A duty cycle adjuster receives the first output signal and the second output signal, performs charging and discharging operations on a selected capacitor according to the first output signal or the second output signal to generate a sensing voltage, and generates a sensing voltage according to the first output signal or the second output signal. sensing the voltage to generate a common reference voltage; and A common mode feedback circuit receives the common reference voltage, and generates the bias voltage according to the comparison between the common reference voltage and the reference voltage. The signal receiving device of claim 1, wherein the duty cycle adjuster comprises: a sensing circuit that performs charging and discharging operations on the selected capacitor according to the first output signal or the second output signal to generate the sensing voltage; and A common reference voltage generating circuit provides a plurality of threshold voltages to be compared with the sensing voltage to generate a plurality of comparison results, and adjust the voltage value of the common reference voltage according to the comparison results. The signal receiving device of claim 2, wherein the sensing circuit comprises: a differential pair, with a common terminal receiving a first current, and two input terminals of the differential pair respectively receiving the first output signal and the second output signal; a current source coupled to the common terminal of the differential pair and coupled to a first reference power terminal, the current source providing the first current; a first load and a second load, respectively coupled to the two load terminals of the differential pair, the first load and the second load are jointly coupled to a second reference power terminal; and A first capacitor and a second capacitor are respectively coupled to the two load terminals of the differential pair, and are jointly coupled to the first reference power terminal. The signal receiving device of claim 3, wherein the first capacitor or the second capacitor is the selected capacitor. The signal receiving device of claim 2, wherein the sensing voltage is inversely proportional to the duty cycle of the first output signal or the second output signal. The signal receiving device according to claim 2, wherein the common reference voltage generating circuit comprises: a threshold voltage generator for dividing the voltage with respect to a first reference power source to generate the threshold voltages; a plurality of comparators, respectively receiving the threshold voltages, each of the comparators compares the sensing voltage with each of the threshold voltages to generate the comparison results; and a digital-to-analog converter, generating a plurality of adjustment codes according to the comparison results of the bits; and a voltage divider having a first resistor and a second resistor coupled in series, the first resistor and the second resistor divide the voltage of the first reference power source to generate the common reference voltage, the first resistor or The second resistor is a variable resistor, and the adjustment codes are used to adjust the resistance value of the variable resistor. The signal receiving device as claimed in claim 6, wherein the digital-to-analog converter is a decoder, which decodes the comparison results of the digital bits to generate the adjustment codes. The signal receiving device of claim 6, wherein when the threshold voltages are the first threshold voltage and the second threshold voltage, when the sensing voltage is between the first threshold voltage and the first threshold voltage When the two threshold voltages are between, the common reference voltage generating circuit does not adjust the voltage value of the common reference voltage; when the sensing voltage is greater than the first threshold voltage and greater than the second threshold voltage, the common reference voltage generates The circuit reduces the voltage value of the common reference voltage; when the sensing voltage is less than the first threshold voltage and less than the second threshold voltage, the common reference voltage generating circuit adjusts the voltage value of the common reference voltage. The signal receiving device of claim 6, wherein the threshold voltage generator comprises: A first resistor, a second resistor and a third resistor are sequentially coupled in series between the first reference power supply and the second reference power supply, and the coupling end of the first resistor and the second resistor provides a first A threshold voltage, the coupling end of the second resistor and the third resistor provides a second threshold voltage. The signal receiving device according to claim 1, further comprising: a second amplifier, receiving the first output signal, the second output signal and the bias voltage, generating a second common current according to the bias voltage, based on the second common current, according to the first output signal and The second output signal is used to generate a post-stage output signal.

Images