CN114124001B

CN114124001B - Signal receiving device

Info

Publication number: CN114124001B
Application number: CN202010875843.1A
Authority: CN
Inventors: 吴镇宇; 陈君政
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2020-08-27
Filing date: 2020-08-27
Publication date: 2024-12-24
Anticipated expiration: 2040-08-27
Also published as: CN114124001A

Abstract

The present invention provides a signal receiving device. The signal receiving device includes a first amplifier, a duty cycle adjuster and a common mode feedback circuit. The first amplifier receives an input signal, a reference voltage and a bias voltage. The first amplifier generates a first common current according to the bias voltage, and generates a complementary first output signal and a second output signal according to the first common current and by comparing the input signal and the reference voltage. The duty cycle adjuster performs charging and discharging operations on a selected capacitor according to the first output signal or the second output signal to generate a detection voltage, and generates a common reference voltage according to the detection voltage. The common mode feedback circuit generates a bias voltage according to comparing the common reference voltage and the reference voltage to compensate for the distortion generated by the first amplifier due to the change in the transconductance value.

Description

Signal receiving device

Technical Field

The present invention relates to a signal receiving apparatus, and more particularly, to a signal receiving apparatus capable of adjusting duty cycle (duty cycle) of an output signal.

Background

In the prior art, the pre-amplifier in the signal receiver is often implemented by a differential amplifier. The differential amplifier operates based on a common current, and the voltage value of the output signal can be determined according to the magnitude of the current flowing through the differential transistor.

In the prior art, the magnitude of the common current is fixed, and when the turn-on voltage of the differential transistor varies due to process drift or environmental factors, the sensing value of the differential transistor correspondingly varies. Such variations may cause the duty cycle of the output signal generated by the differential amplifier to be unable to be maintained within a correct range, and distort the received signal.

Disclosure of Invention

The invention is directed to a signal receiving device capable of dynamically adjusting the duty ratio of an output signal.

According to an embodiment of the present invention, a signal receiving apparatus includes a first amplifier, a duty cycle adjuster, and a common mode feedback circuit. The first amplifier receives an input signal, a reference voltage, and a bias voltage. The first amplifier generates a first common current according to the bias voltage, and generates a first output signal and a second output signal which are complementary according to the comparison input signal and the reference voltage based on the first common current. The duty ratio adjuster receives the first output signal and the second output signal, performs charge and discharge actions on the selected capacitor according to the first output signal or the second output signal to generate a detection voltage, and generates a common reference voltage according to the detection voltage. The common mode feedback circuit receives the common reference voltage and generates a bias voltage according to comparing the common reference voltage with the reference voltage.

According to the above embodiments, the duty cycle adjuster is provided to detect the change of the duty cycle of the output signal of the amplifier, and adjust the bias voltage of the amplifier for generating the common current according to the change of the duty cycle of the output signal. Therefore, the distortion of the output signal of the amplifier caused by the change of the transduction value can be compensated, and the accuracy of the output signal can be maintained.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Fig. 1 shows a schematic diagram of a signal receiving apparatus according to an embodiment of the invention;

FIG. 2 shows a schematic diagram of a duty cycle adjuster implementation of an embodiment of the present invention;

FIG. 3 shows a circuit diagram of another implementation of a duty cycle adjuster according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a signal receiving apparatus according to another embodiment of the present invention;

fig. 5 shows a circuit diagram of a implementation of a common mode feedback circuit of an embodiment of the present invention.

Description of the reference numerals

100. 400, A signal receiving device;

110. 410, 440, OP51, OP 52;

120. 200, 420, duty cycle adjuster;

130. 430, 500, common mode feedback circuits;

a detection circuit 210;

220 a common reference voltage generating circuit;

311 differential pair;

312, a current source;

321, a decoder;

323, a voltage divider;

A. b, comparing the results;

COD is an adjusting code;

RL1 and RL2 are loads;

CA. CB, capacitance;

OP1, OP2, operational amplifier;

OP3, OP4, comparator;

RE1, RE2, ra, rb, rc, R1, R2;

M1-M3, M51 are transistors;

VDD, VSS, vref _res, reference power supply terminal;

i1, I2 and IT are currents;

VA, VB, detecting voltage;

vin is an input signal;

Vref, reference voltage;

Vbias, bias voltage;

Vout1, vout 1_n;

vout2, the post output signal;

Vcom_ref: common reference voltage.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1 is a schematic diagram of a signal receiving apparatus according to an embodiment of the invention. The signal receiving apparatus 100 includes an amplifier 110, a duty ratio adjuster 120, and a common mode feedback circuit 130. The amplifier 110 receives an input signal Vin, a reference voltage Vref, and a bias voltage Vbias. The amplifier 110 generates a common current according to the bias voltage Vbias, and generates complementary output signals Vout1 and Vout1_n according to comparing the input signal Vin with the reference voltage Vref based on the common current. The amplifier 110 may be a differential amplifying circuit. The amplifier 110 can determine the common mode level of the output signals Vout1 and Vout1_n according to the common current generated by the bias voltage Vbias.

The duty cycle adjuster 120 is coupled to the amplifier 110. The duty cycle adjuster 120 receives the complementary output signals Vout1 and Vout1_n. The duty ratio adjuster 120 performs a charging/discharging operation on a selected capacitor according to the output signal Vout1 or the output signal Vout1_n to generate a detection voltage. The duty ratio adjuster 120 generates the common reference voltage vcom_ref according to the detection voltage.

In the present embodiment, the duty ratio adjuster 120 performs a charging/discharging operation on the selected capacitor by one of the output signal Vout1 and the output signal Vout1_n to detect the duty ratio of the output signal Vout1 and the output signal Vout1_n, and obtains the common reference voltage vcom_ref according to the generated detection voltage.

The common reference voltage vcom_ref is supplied to the common mode feedback circuit 130. The common mode feedback circuit 130 receives the reference voltage Vref, and adjusts the voltage value of the bias voltage Vbias according to comparing the common reference voltage vcom_ref with the reference voltage Vref.

According to the above, the common current in the amplifier 110 can be adjusted by adjusting the voltage value of the bias voltage Vbias. In this way, when the turn-on voltage of the differential transistor in the amplifier 110 varies, the current flowing through the differential transistor can be adjusted to automatically adjust the transduction value of the differential transistor, so as to maintain the duty ratio of the output signal Vout1 and the output signal Vout 1_n.

Referring now to fig. 2, fig. 2 is a schematic diagram illustrating a duty cycle adjuster according to an embodiment of the invention. The duty cycle adjuster 200 includes a detection circuit 210 and a common reference voltage generation circuit 220. The detection circuit 210 receives the output signal Vout1 and the output signal Vout1_n. The detection circuit 210 may set a selected capacitor, and perform a charge-discharge operation on the selected capacitor based on the output signal Vout1 or the output signal Vout1_n to generate the detection voltage VA. The detection circuit 210 provides the detection voltage VA to the common reference voltage generation circuit 220. The common reference voltage generating circuit 220 provides a plurality of threshold voltages, and compares the detection voltage VA with the plurality of threshold voltages to generate a plurality of comparison results. The common reference voltage generating circuit 220 adjusts the voltage value of the common reference voltage vcom_ref according to the obtained comparison result.

For details, please refer to fig. 3, which is a circuit diagram illustrating another implementation of the duty cycle adjuster according to an embodiment of the present invention. The duty cycle adjuster 300 includes a detection circuit 310 and a common reference voltage generation circuit 320. In the present embodiment, the detection circuit 310 includes a differential pair 311, a current source 312, loads RL1, RL2, capacitors CA, CB, operational amplifiers OP1, OP2, and resistors RE1, RE2. The differential pair 311 is composed of transistors M1 and M2. Loads RL1 and RL2 are coupled to the first terminals of transistors M1 and M2, respectively, and loads RL1 and RL2 are commonly coupled to the reference power terminal VDD. The first ends of the transistors M1 and M2 form two load ends of the differential pair 311, respectively. The control terminals of the transistors M1 and M2 respectively form two input terminals of the differential pair 311, and respectively receive the output signals Vout1 and Vout1_n.

In addition, the second terminals of the transistors M1 and M2 are connected to each other and form a common terminal of the differential pair 311. The current source 312 is constructed by a transistor M3. The transistor M3 is coupled between the common terminal of the differential pair 311 and the reference power terminal VSS, and the control terminal of the transistor M3 is coupled to the operational amplifier OP2.

The current source 312 provides a current IT as the common current of the differential pair 310. The transistors M1 and M2 generate currents I1 and I2 according to the received output signals Vout1 and Vout1_n, respectively, wherein the sum of the currents I1 and I2 is equal to the current IT.

On the other hand, the capacitor CA is connected in series between the first terminal of the transistor M1 and the reference power terminal VSS, and the capacitor CB is connected in series between the first terminal of the transistor M2 and the reference power terminal VSS. The capacitors CA and CB can be charged and discharged according to the voltage values at the first ends of the transistors M1 and M2, respectively, and accordingly generate the detection voltages VA and VB, respectively.

In this embodiment, the capacitor CA is coupled to the common reference voltage generating circuit 320, so the capacitor CA can be used as the selected capacitor. In other embodiments of the present invention, the capacitor CB may be coupled to the common reference voltage generating circuit 320 and used as the selected capacitor, without limitation.

In detail, since the output signal Vout1 is a signal that repeatedly changes state between the first voltage and the second voltage (e.g., the first voltage is greater than the second voltage), the current I1 flowing through the load RL1 increases and the detection voltage VA decreases when the output signal Vout1 is equal to the relatively large first voltage. When the output signal Vout1 is equal to the relatively small second voltage, the current I1 flowing through the load RL1 decreases and the detection voltage VA increases. Accordingly, the duty ratio of the output signal Vout1 may be inversely proportional to the voltage value of the detection voltage VA. Also, therefore, the change in the duty ratio of the output signal Vout1 can be known from the change in the voltage value of the detection voltage VA.

Incidentally, in the present embodiment, the operational amplifiers OP1 and OP2 are used to generate the bias voltage received by the current source 312. The operational amplifier OP1 receives the reference voltage Vref, and an output terminal of the operational amplifier OP1 is coupled to a positive input terminal of the operational amplifier OP 2. The negative input terminal of the operational amplifier OP2 is coupled to the resistor string formed by the resistors RE1 and RE 2. The resistors RE1 and RE2 are coupled between the reference power terminals vref_res and VSS.

The common reference voltage generating circuit 320 includes a decoder 321, a threshold voltage generator 322, a voltage divider 323, a comparator OP3 and a comparator OP4. The decoder 321 is an analog-to-digital converter. The threshold voltage generator 322 is formed of a plurality of resistors Ra, rb, and Rc. The resistors Ra, rb and Rc are serially coupled between the reference power terminal vref_res and the reference power terminal VSS in sequence. The threshold voltage generator 322 divides the reference power provided by the reference power terminal vref_res through resistors Ra, rb and Rc to generate a plurality of threshold voltages. In the present embodiment, the threshold voltage generator 322 has three resistors Ra, rb, and Rc, and can generate two threshold voltages.

The comparators OP3 and OP4 may be implemented by operational amplifiers. The positive input terminal of the comparator OP3 receives the detection voltage VA, and the negative input terminal of the comparator OP3 is coupled to the connection terminals of the resistors Ra and Rb and receives the first threshold voltage. The negative input end of the comparator OP4 receives the detection voltage VA, and the positive input end of the comparator OP4 is coupled to the connection end of the resistor Rb and Rc and receives a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.

The comparators OP3 and OP4 compare the detection voltage VA with the first threshold voltage and the second threshold voltage, and generate comparison results a and B, respectively. The comparators OP3 and OP4 may generate a comparison result a with a logic high level and a comparison result B with a logic low level when the detection voltage VA is greater than the first threshold voltage and greater than the second threshold voltage, respectively, the comparators OP3 and OP4 may generate a comparison result a with a logic low level and a comparison result B with a logic low level when the detection voltage VA is less than the first threshold voltage and less than the second threshold voltage, respectively.

The decoder 321 receives the comparison results a and B, and decodes the comparison results a and B to generate the adjustment code COD. The voltage divider 323 includes resistors R1 and R2. The resistors R1 and R2 are coupled in series between the reference power terminals vref_res and VSS. The resistors R1 and R2 divide the reference power provided by the reference power terminal vref_res to generate the common reference voltage vcom_ref. In this embodiment, the resistor R2 is a variable resistor. The resistance value of the resistor R2 can be determined according to the adjustment code COD. The voltage value of the common reference voltage vcom_ref can be raised by increasing the resistance value of the resistor R2, and the voltage value of the common reference voltage vcom_ref can be lowered by decreasing the resistance value of the resistor R2.

For the relationship between the adjustment operation of the common reference voltage vcom_ref, the detection voltage VA and the comparison result A, B in the present embodiment, see the following table 1:

Table 1:

Duty cycle	Detection voltage VA	Comparison result A	Comparison result B	Vcom_ref
					50%	1V	L	L	Maintenance of
30%	1.2V	H	L	Lowering
					70%	0.8V	L	H	Lifting up

In table 1, L represents a logic low level, and H represents a logic high level. When the detected voltage VA is 1V, the comparison result A, B is a logic low level (L), the duty ratio of the output signal Vout1 is 50%, the voltage value of the common reference voltage vcom_ref does not need to be adjusted, when the detected voltage VA is 1.2V, the comparison result A, B is a logic high level (H) and a logic low level (L), the duty ratio of the output signal Vout1 is 30%, the voltage value of the common reference voltage vcom_ref is adjustable to increase the duty ratio of the output signal Vout1, and when the detected voltage VA is 0.8V, the comparison result A, B is a logic low level (L) and a logic high level (H), the duty ratio of the output signal Vout1 is 70%, the voltage value of the common reference voltage vcom_ref is increased, and the duty ratio of the output signal Vout1 is decreased.

Incidentally, in the present embodiment, the resistor R1 may be set as a variable resistor, and the resistor R1 may receive the adjustment code COD to adjust the provided resistance value, so as to generate the common reference voltage vcom_ref. Under such a mechanism, the adjustment code COD generated by the decoder 321 needs to lower the resistance value of the resistor R1 under the condition that the voltage value of the common reference voltage vcom_ref needs to be raised, and the adjustment code COD generated by the decoder 321 needs to raise the resistance value of the resistor R1 under the condition that the voltage value of the common reference voltage vcom_ref needs to be lowered.

Referring to fig. 4, fig. 4 is a schematic diagram of a signal receiving apparatus according to another embodiment of the invention. The signal receiving apparatus 400 includes amplifiers 410, 440, a common mode feedback circuit 430, and a duty cycle adjuster 420. The amplifier 410 may act as a pre-amplifier. The amplifier 410 receives an input signal Vin, a reference voltage Vref, and a bias voltage Vbias. The amplifier 410 generates a common current according to the bias voltage Vbias, and generates complementary output signals Vout1 and Vout1_n according to comparing the input signal Vin with the reference voltage Vref based on the common current. The amplifier 440 is coupled to the output of the amplifier 410, receives the output signals Vout1 and Vout1_n, and receives the bias voltage Vbias. The amplifier 440 generates a common current according to the bias voltage Vbias, and generates a post-stage output signal Vout2 according to the output signals Vout1 and Vout1_n based on the common current.

The common mode feedback circuit 430 is coupled to the amplifiers 410 and 440, and generates the bias voltage Vbias according to the reference voltage Vref and the common reference voltage vcom_ref. In the present embodiment, the common mode feedback circuit 430 may be implemented by any common mode feedback circuit (common mode feedback circuit, CMFB circuit) known to those skilled in the art, and is not particularly limited.

The duty cycle adjuster 420 is coupled to the amplifier 410 and the common mode feedback circuit 430. The implementation details of the duty cycle adjuster 420 can be found in the implementation of the foregoing embodiment (e.g., the duty cycle adjuster 300 of fig. 3), which is not described herein.

For implementation details of the common mode feedback circuit, reference may be made to the circuit diagram of the implementation of the common mode feedback circuit of the embodiment of the present invention shown in fig. 5. In fig. 5, the common mode feedback circuit 500 includes amplifiers OP51, OP52 and a transistor M51. The two input terminals of the amplifier OP51 synchronously receive the reference voltage Vref, and the output terminal of the amplifier OP51 is coupled to the positive input terminal of the amplifier OP 52. The transistor M51 is used as a current source of the amplifier OP51 and is coupled between the amplifier OP51 and the reference power source terminal VSS. The negative input terminal of the amplifier OP52 receives the common reference voltage vcom_ref and is used to generate the bias voltage Vbias. In addition, the bias voltage Vbias is also supplied to the gate terminal of the transistor M51.

It should be noted that, in the embodiment of the present invention, the circuit architecture of the amplifier OP51 may be the same as that of the amplifiers 110 and 410 in the embodiment of fig. 1 and 4.

According to the embodiment of the invention, the duty ratio of the output signal of the amplifier is detected, and the voltage value of the common reference voltage is adjusted through the common mode feedback circuit, so that the variation generated by the on voltage of the differential transistor of the amplifier can be compensated, and the duty ratio of the output signal is maintained in the effective range.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims

1. A signal receiving apparatus, comprising:

A first amplifier for receiving an input signal, a reference voltage and a bias voltage, wherein the first amplifier generates a first common current according to the bias voltage, and generates a first output signal and a second output signal which are complementary according to the comparison of the input signal and the reference voltage based on the first common current;

A duty ratio adjuster for receiving the first output signal and the second output signal, performing charge and discharge operations on the selected capacitor according to the first output signal or the second output signal to generate a detection voltage, and generating a common reference voltage according to the detection voltage, and

A common mode feedback circuit for receiving the common reference voltage, generating the bias voltage according to comparing the common reference voltage with the reference voltage,

The duty cycle adjuster includes:

A detection circuit for generating the detection voltage by performing charge and discharge actions on the selected capacitor according to the first output signal or the second output signal, and

The common reference voltage generating circuit provides a plurality of threshold voltages for comparison with the detection voltage to generate a plurality of comparison results, and adjusts the voltage value of the common reference voltage according to the plurality of comparison results.

2. The signal receiving apparatus of claim 1, wherein the detection circuit comprises:

The differential pair is provided with a common terminal for receiving a first current, and two input terminals of the differential pair respectively receive the first output signal and the second output signal;

A current source coupled to the common terminal of the differential pair and coupled to a first reference power terminal, the current source providing the first current;

A first load and a second load respectively coupled to two load terminals of the differential pair, the first load and the second load being commonly coupled to a second reference power terminal, and

The first capacitor and the second capacitor are respectively coupled to the two load ends of the differential pair and are commonly coupled to the first reference power supply end.

3. The signal receiving apparatus of claim 2, wherein the first capacitance or the second capacitance is the selected capacitance.

4. The signal receiving apparatus of claim 1, wherein the detection voltage is inversely proportional to a duty cycle of the first output signal or the second output signal.

5. The signal receiving apparatus of claim 1, wherein the common reference voltage generating circuit comprises:

a threshold voltage generator dividing a voltage for a first reference power source to generate the plurality of threshold voltages;

A plurality of comparators for receiving the threshold voltages respectively, each of the comparators comparing the detection voltage with each of the threshold voltages to generate a plurality of comparison results, and

A digital-to-analog converter for generating multiple adjustment codes according to the multiple comparison results of the numbers, and

The voltage divider is provided with a first resistor and a second resistor which are coupled in series, the first resistor and the second resistor divide the voltage for the first reference power supply to generate the common reference voltage, the first resistor or the second resistor is a variable resistor, and the plurality of adjusting codes are used for adjusting the resistance value of the variable resistor.

6. The signal receiving apparatus of claim 5, wherein the digital-to-analog converter is a decoder that decodes the plurality of comparison results for the numbers to generate the plurality of adjustment codes.

7. The signal receiving apparatus of claim 5, wherein the common reference voltage generating circuit does not adjust the voltage value of the common reference voltage when the plurality of threshold voltages are a first threshold voltage and a second threshold voltage, wherein the common reference voltage generating circuit adjusts the voltage value of the common reference voltage when the plurality of threshold voltages are between the first threshold voltage and the second threshold voltage, wherein the common reference voltage generating circuit adjusts the voltage value of the common reference voltage when the plurality of threshold voltages are greater than the first threshold voltage and greater than the second threshold voltage, and wherein the common reference voltage generating circuit adjusts the voltage value of the common reference voltage when the plurality of threshold voltages are less than the first threshold voltage and less than the second threshold voltage.

8. The signal receiving apparatus of claim 5, wherein the threshold voltage generator comprises:

The first resistor, the second resistor and the third resistor are sequentially coupled in series between the first reference power supply and the second reference power supply, the coupling end of the first resistor and the second resistor provides a first threshold voltage, and the coupling end of the second resistor and the third resistor provides a second threshold voltage.

9. The signal receiving apparatus of claim 1, further comprising:

and the second amplifier is used for receiving the first output signal, the second output signal and the bias voltage, generating a second common current according to the bias voltage, and generating a rear-stage output signal according to the first output signal and the second output signal based on the second common current.