TW202117943A - Multi-chip three-dimensional stacked package with fan-out structure - Google Patents
Multi-chip three-dimensional stacked package with fan-out structure Download PDFInfo
- Publication number
- TW202117943A TW202117943A TW108138760A TW108138760A TW202117943A TW 202117943 A TW202117943 A TW 202117943A TW 108138760 A TW108138760 A TW 108138760A TW 108138760 A TW108138760 A TW 108138760A TW 202117943 A TW202117943 A TW 202117943A
- Authority
- TW
- Taiwan
- Prior art keywords
- electronic
- packaging structure
- item
- electronic packaging
- components
- Prior art date
Links
- 239000000463 material Substances 0.000 claims description 69
- 239000011248 coating agent Substances 0.000 claims description 61
- 238000000576 coating method Methods 0.000 claims description 61
- 238000005253 cladding Methods 0.000 claims description 47
- 238000004100 electronic packaging Methods 0.000 claims description 38
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 36
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 36
- 238000012360 testing method Methods 0.000 claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 239000004020 conductor Substances 0.000 claims description 26
- 229910052732 germanium Inorganic materials 0.000 claims description 26
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 26
- 239000000203 mixture Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 25
- 229910052718 tin Inorganic materials 0.000 claims description 25
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 239000000956 alloy Substances 0.000 claims description 18
- 229910045601 alloy Inorganic materials 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- 229910017052 cobalt Inorganic materials 0.000 claims description 18
- 239000010941 cobalt Substances 0.000 claims description 18
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 18
- 229910052737 gold Inorganic materials 0.000 claims description 18
- 239000010931 gold Substances 0.000 claims description 18
- 229910052742 iron Inorganic materials 0.000 claims description 18
- 239000007769 metal material Substances 0.000 claims description 18
- 229910052759 nickel Inorganic materials 0.000 claims description 18
- 239000011368 organic material Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 14
- 238000004806 packaging method and process Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 8
- 238000007639 printing Methods 0.000 claims description 8
- 238000007650 screen-printing Methods 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims 3
- 238000001312 dry etching Methods 0.000 claims 2
- 238000007761 roller coating Methods 0.000 claims 2
- 238000001039 wet etching Methods 0.000 claims 2
- 239000003292 glue Substances 0.000 claims 1
- 238000007731 hot pressing Methods 0.000 claims 1
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 238000001459 lithography Methods 0.000 claims 1
- 238000003754 machining Methods 0.000 claims 1
- 239000002470 thermal conductor Substances 0.000 claims 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 17
- 229910052799 carbon Inorganic materials 0.000 description 17
- 230000010354 integration Effects 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
- 238000013440 design planning Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000010295 mobile communication Methods 0.000 description 3
- 238000013473 artificial intelligence Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
本發明提出一個扇出型多晶片立體堆疊模組封裝架構,此結構中至少包含複數個電子元件與中介元件,該中介元件可具單面、雙面或多層佈線電路並具有平面或上下電性(接地、電訊、電力或熱導)連 接功能;且該複數個電子元件以共平面或非共平面方式與該中介元件連結形成晶片組,並以有機材料完全或部分包覆該晶片組;該有機材料包覆之晶片組可具有從電子元件扇出至有機包覆體之線路,且該包覆材料可具有複數個電性通道連結有機包覆體之一端或兩端,且該電性通道可與晶片相連接、與中介元件相連接或與該扇出至有機包覆體之線路相連接。其目的在於使封裝結構可以有更佳的功能整合,更靈活的設計規劃,並減少封裝體的體積。 The present invention provides a fan-out type multi-chip three-dimensional stacked module package structure, which includes at least a plurality of electronic components and intermediary components. The intermediary components can have single-sided, double-sided, or multilayer wiring circuits and have planar or upper and lower electrical properties. (Grounding, telecommunications, power or thermal conductivity) connection And the plurality of electronic components are connected with the intermediary element in a coplanar or non-coplanar manner to form a chip set, and the chip set is completely or partly covered with an organic material; the organic material coated chip set can have from The electronic component fan out to the circuit of the organic coating body, and the coating material can have a plurality of electrical channels connected to one end or both ends of the organic coating body, and the electrical channel can be connected to the chip and to the intermediate component. Connect or connect with the fan-out circuit to the organic coating body. Its purpose is to enable the package structure to have better function integration, more flexible design planning, and reduce the volume of the package body.
電子產品近年來由於行動通訊、巨量資料、5G與人工智慧時代的到來,不論是物流、製造、醫療與食衣住行等各領域都離不開此範疇,在此需求中,對於電子產品要求更高的頻寬、更低的延遲速度以及更低的能耗。為達到這些需求,使得過去半導體產業由設計、製造、封裝與硬體整合之垂直供應鏈生態進行改變,系統廠、晶圓代工廠、封測廠、設備商與材料商等將進行合作與重組,將不同功能、材質與技術之異質晶片和系統架構整合,創造高價值的終端產品,成為主流技術與方向。在各個立體封裝堆疊形式中,利用在晶片製作導通孔的封裝方式可縮短晶片間電訊傳遞路徑,減少訊號產生雜訊的情形,然而隨著電子產品之電路愈精巧,電路元件之分佈密度過高、複雜的製程技術、較長的設計時間與較高的製作成本等,使得異質整合系統構裝技術興起,將系統帶向更高整合度以及更高功能。其中,具功能模塊之模組化的電子系統架構更為近期重要的異質整合趨勢。本發明提出一種扇出型多晶片立體堆疊模組封裝架構的異質整合架構,除可提高系統之整合度,同時兼具更靈活的設計規劃,以及減少封裝體的體積。 In recent years, due to the advent of mobile communications, huge amounts of data, 5G and artificial intelligence, various fields such as logistics, manufacturing, medical care, food, clothing, housing and transportation are inseparable from this category. In this demand, there is a need for electronic products. Requires higher bandwidth, lower delay speed and lower energy consumption. In order to meet these needs, the past semiconductor industry has undergone changes from the vertical supply chain ecology of design, manufacturing, packaging and hardware integration. System factories, foundries, packaging and testing plants, equipment vendors and material vendors will cooperate and reorganize. , Integrating heterogeneous chips with different functions, materials and technologies and system architecture to create high-value terminal products and become the mainstream technology and direction. In each of the three-dimensional package stacking forms, the use of through-hole packaging on the chip can shorten the telecommunications transmission path between the chips and reduce the noise generated by the signal. However, as the circuits of electronic products become more sophisticated, the distribution density of circuit components is too high , Complicated process technology, long design time and high production cost, etc., have caused the rise of heterogeneous integration system construction technology, which will bring the system to higher integration and higher functions. Among them, the modular electronic system architecture with functional modules is more recent important heterogeneous integration trend. The present invention provides a heterogeneous integration architecture of a fan-out multi-chip three-dimensional stacked module packaging architecture, which not only improves the integration of the system, but also has more flexible design planning and reduces the volume of the package.
習知堆疊型積體電路晶片封裝如美國專利字號9,679,882中,揭露一種高密度積體電路晶片封裝結構,請參閱圖1A;該封裝結構採用晶片堆疊方式形成,是將晶片主動面均朝向同方向進行堆疊,各晶片的溝通是藉由光敏感材料層中導通孔將訊號傳遞至光敏感材料表
面後進行訊號的傳遞,如前述第二晶片132與第三晶片133之間並不以矽穿孔作為電連接通路,而是利用光敏感材料中的複數個導通孔與重佈線路形成電連通路,固可對多晶片進行整合堆疊,然而,此堆疊方式的訊號傳遞方法將導致訊號傳遞的延遲,且對於堆疊晶片的輸出/輸入金屬墊的位置有所限制,如圖一中的第二晶片132,其輸出/輸入金屬墊必須位於第三晶片133尺寸外圍,意即第二晶片132尺寸必須大於第三晶片133尺寸,抑或擺放位置必須錯開,因此限制了晶片種類的選用,對於同質晶片的整合與堆疊則不適用。
A conventional stacked integrated circuit chip package, such as US Patent No. 9,679,882, discloses a high-density integrated circuit chip package structure, please refer to Figure 1A; the package structure is formed by stacking chips, with the active surfaces of the chips facing the same direction For stacking, the communication of each chip is through the via hole in the photosensitive material layer to transmit the signal to the photosensitive material table
Signal transmission is performed behind the surface. For example, the
中華民國專利公告號I3953185中提出一種使用嵌入式晶片載板之薄型立體堆疊封裝結構,其中此結構中第一電子元件晶片201與第二電子元件晶片202以電子元件朝外的方式相互貼附,並利用晶片載板206進行該電子元件晶片組的承載。晶片間藉由晶片載板上的導通孔結構,將電子元件晶片電訊與晶片載板上之導通孔相互連接,達到訊號垂直導通與立體堆疊封裝之目的。然而,晶片間的訊號傳遞必須透過導通孔將訊號相互傳遞,在高速傳輸應用時會造成訊號的延遲,且對於兩個以上之多晶片如何進行訊號傳遞並未多做說明。
The Republic of China Patent Publication No. I3953185 proposes a thin three-dimensional stacked package structure using an embedded chip carrier. In this structure, the first
鑒於具功能模塊之模組化的電子系統架構之異質整合趨勢在行動通訊與高速運算等需求下,為減低高整合度晶片之製作成本、智慧財產權成本、製作複雜度與上市時間,如何發展出一種高密度、可重複使用、可高速傳輸與高可靠度之架構,同時設計、組裝可依據應用需求功能作適當彈性調整之多個微電子元件封裝結構,實為當前急需解決的問題。 In view of the heterogeneous integration trend of modular electronic system architecture with functional modules, under the requirements of mobile communication and high-speed computing, how to reduce the production cost, intellectual property cost, production complexity and time to market of highly integrated chips A high-density, reusable, high-speed transmission, and high-reliability architecture, and the design and assembly of multiple microelectronic component packaging structures that can be adjusted flexibly according to application requirements and functions are currently urgent problems.
鑑於前述技術之缺失,具系統高度整合之多個電子元件堆疊電子封裝將成為行動通訊、巨量資料、5G與人工智慧領域應用之重要架構,本發明具有以下之目的:本發明提出一利用扇出型多晶片立體堆疊模組封裝架構,此結構中至少包含複數個電子元件與中介元件,該中介元件可具單面、雙面或多層佈線電路並具有平面或上下電性(接地、電訊、電力或熱導)連接功能;且該複數個電子元件以共平面或 非共平面方式與該中介元件連結形成晶片組,並以有機材料完全或部分包覆該晶片組;該有機材料包覆之晶片組可具有從電子元件扇出至有機包覆體之線路,且該包覆材料可具有複數個電性通道連結有機包覆體之一端或兩端,且該電性通道可與晶片相連接、與中介元件相連接或與該扇出至有機包覆體之線路相連接。其目的在於使封裝結構可以有更高的傳輸速度、更佳的功能整合、更靈活的設計規劃,並減少封裝體的體積。 In view of the lack of the aforementioned technology, a stacked electronic package with multiple electronic components with a high degree of system integration will become an important framework for applications in the fields of mobile communications, massive data, 5G, and artificial intelligence. The present invention has the following objectives: The present invention proposes a utilization fan Out-type multi-chip three-dimensional stacked module packaging structure, this structure contains at least a plurality of electronic components and intermediary components, the intermediary components can have single-sided, double-sided or multi-layer wiring circuit and have planar or upper and lower electrical (grounding, telecommunications, Power or thermal conductivity) connection function; and the plurality of electronic components are coplanar or The non-coplanar way is connected with the intermediate element to form a chip set, and the chip set is completely or partly covered with organic material; the chip set covered with organic material may have a circuit fan-out from the electronic component to the organic covering body, and The cladding material can have a plurality of electrical channels connected to one end or both ends of the organic cladding body, and the electrical channels can be connected with the chip, connected with the intermediate element or with the circuit fan-out to the organic cladding body Phase connection. Its purpose is to enable the package structure to have higher transmission speed, better function integration, more flexible design planning, and reduce the volume of the package body.
本發明其一目的在於改善電子元件間的傳輸速度與整合度問題,此架構可將所需功能之晶片有效堆疊與傳輸,並至少一個電子元件與中介元件間以主動元件層對主動元件層構裝,再搭配其他電子元件以最適化方式配置,形成一個新形態的晶片模組,使各種同質或異質電子元件間的整合度大幅提升。 One purpose of the present invention is to improve the transmission speed and integration problems between electronic components. This architecture can effectively stack and transmit chips with required functions, and at least one electronic component and an intermediate component have an active component layer to an active component layer structure. It is installed, and then configured with other electronic components in an optimal way to form a new form of chip module, which greatly improves the integration of various homogenous or heterogeneous electronic components.
本發明之另一目的在於設計的靈活性,可對於各應用需求,將所需功能電子元件在此架構中擺置,達到封裝模組內的高效能電性傳輸,以及各單元間的搭配運用,使整體系統效能最佳化。 Another purpose of the present invention is the flexibility of design. For each application requirement, the required functional electronic components can be placed in this structure, so as to achieve high-efficiency electrical transmission in the package module, and the matching and use of each unit. , To optimize the overall system performance.
本發明之另一目的在於減少電子元件堆疊封裝結構厚度,本發明將多個電子元件與中介元件以共平面或非共平面方式進行堆疊,再以扇出型重佈線路及複數個電性通道進行整合,利用該方式可使晶片堆疊封裝結構高度有效降低。 Another object of the present invention is to reduce the thickness of the electronic component stacked package structure. The present invention stacks a plurality of electronic components and intermediate components in a coplanar or non-coplanar manner, and then re-distributes the circuit and a plurality of electrical channels in a fan-out type. For integration, this method can effectively reduce the height of the chip stack package structure.
為達成前述目的,本發明所提出之扇出型多晶片立體堆疊模組封裝架構,至少包含複數個電子元件與中介元件,該中介元件可具單面、雙面或多層佈線電路並具有平面或上下電性連接功能;且該複數個電子元件以共平面或非共平面方式與該中介元件連結形成晶片組,並以有機材料完全或部分包覆該晶片組;該有機材料包覆之晶片組可具有從電子元件扇出至有機包覆體之線路,且該包覆材料可具有複數個電性通道連結有機包覆體之一端或兩端,且該電性通道可與晶片相連接、與中介元件相連接或與該扇出至有機包覆體之線路相連接。 In order to achieve the foregoing objectives, the fan-out multi-chip three-dimensional stacked module package structure proposed by the present invention includes at least a plurality of electronic components and intermediary components. The intermediary components can have single-sided, double-sided or multilayer wiring circuits and have flat or The upper and lower electrical connection function; and the plurality of electronic components are connected with the intermediate element in a coplanar or non-coplanar manner to form a chip set, and the chip set is completely or partially covered with an organic material; the chip set covered by the organic material It can have circuits that fan out from the electronic component to the organic coating, and the coating material can have a plurality of electrical channels connected to one end or both ends of the organic coating, and the electrical channels can be connected to the chip and The intermediate element is connected or connected with the circuit from the fan-out to the organic covering body.
本發明之前述與其他目的、特徵、以及優點,將藉由下文中參照圖示 之較佳實施例之詳細說明得以更明確。 The foregoing and other objects, features, and advantages of the present invention will be referred to in the following The detailed description of the preferred embodiment is more clear.
本發明揭露一種多晶片立體堆疊封裝結構。詳言之,本發明利用多晶片整合封裝設計方式,將電子晶片進行堆疊封裝,可形成一具有更高整合性與減少封裝體積之整合架構。該發明之實施例詳細說明如下,唯所述之較佳實施例做一說明,並非用以限定本發明。 The invention discloses a multi-chip three-dimensional stacked packaging structure. In detail, the present invention uses a multi-chip integrated packaging design method to stack and package electronic chips to form an integrated structure with higher integration and reduced packaging volume. The embodiments of the present invention are described in detail as follows. Only the preferred embodiments described are described, and are not intended to limit the present invention.
圖2A至圖2H為本發明之電子晶片堆疊封裝單元結構截面示意圖,用以闡述本發明之堆疊單元結構。圖二A中第一電子元件201,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第一電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第二電子元件晶片202,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第二電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。中介元件203具雙面佈線電路並具有平面與上下電性連接功能,該前述第一電子元件與第二電子元件,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組207;該中介元件材料可為矽、鍺、氧化矽、氧化鋁、有機材料,或以上元素之混合或與他種元素之組合。有機包覆材料208,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路209。電性通道210位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合;該電性通道亦為一熱之良導體,具有導熱之特性。
2A to 2H are schematic cross-sectional diagrams of the structure of the electronic chip stacked package unit of the present invention, for explaining the structure of the stacked unit of the present invention. The first
圖2B中,第一電子元件201,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第一電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第二電子元件晶片202,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;
該第二電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。中介元件203具雙面佈線電路並具有平面與上下電性連接功能,該前述第一電子元件與第二電子元件,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組207;該中介元件材料可為矽、鍺、氧化矽、氧化鋁、有機材料,或以上元素之混合或與他種元素之組合。有機包覆材料208,以完全包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路209。電性通道210位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合;該電性通道亦為一熱之良導體,具有導熱之特性。
In FIG. 2B, the first
如圖2C中,第一電子元件201,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第一電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第二電子元件晶片202,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第二電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。中介元件203具單面佈線電路並具有平面與上下電性連接功能,該前述第一電子元件與第二電子元件,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組207;該中介元件材料可為矽、鍺、氧化矽、氧化鋁、有機材料,或以上元素之混合或與他種元素之組合。有機包覆材料208,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路209。電性通道210位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合;該電性通道亦為一熱之良導體,具有導熱之特性。
As shown in FIG. 2C, the first
如圖2D所繪,第一電子元件201,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第一電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第二電子元件晶片202,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第二電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。中介元件203具雙面佈線電路並具有平面與上下電性連接功能,該前述第一電子元件與第二電子元件,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組207;該中介元件材料可為矽、鍺、氧化矽、氧化鋁、有機材料,或以上元素之混合或與他種元素之組合。有機包覆材料208,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體兩側之線路209與211。電性通道210位於有機包覆體中,且該電性通道扇出至有機包覆體兩側之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合;該電性通道亦為一熱之良導體,具有導熱之特性。
As depicted in Figure 2D, the first
如圖2E,第一電子元件201,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第一電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第二電子元件晶片202,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第二電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第三電子元件晶片212,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第三電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。中介元件203具雙面佈線電路並具有平面與上下電性連接功能,該前述複數個電子元件,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組
207;該中介元件材料可為矽、鍺、氧化矽、氧化鋁、有機材料,或以上元素之混合或與他種元素之組合。有機包覆材料208,以完全包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路209。電性通道210位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合;該電性通道亦為一熱之良導體,具有導熱之特性。
2E, the first
圖2F中第一電子元件201,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第一電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第二電子元件晶片202,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第二電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。中介元件203具多層佈線電路並具有平面與上下電性連接功能,該前述第一電子元件與第二電子元件,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組207;該中介元件材料可為矽、鍺、氧化矽、氧化鋁、有機材料,或以上元素之混合或與他種元素之組合。有機包覆材料208,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路209。電性通道210位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合;該電性通道亦為一熱之良導體,具有導熱之特性。
In the first
如圖2G所繪,第一電子元件201,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第一電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第二電子元件晶片202,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組
合;該第二電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。中介元件203具雙面佈線電路並具有平面與上下電性連接功能,該前述第一電子元件與第二電子元件,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組207;該中介元件材料可為矽、鍺、氧化矽、氧化鋁、有機材料,或以上元素之混合或與他種元素之組合。有機包覆材料208,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路209。電性通道210位於有機包覆體中,且該電性通道與該扇出至有機包覆體之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合;該電性通道亦為一熱之良導體,具有導熱之特性。第二電性通道220位於有機包覆體中,且該電性通道與中介元件相連接及該扇出至有機包覆體之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合。
As depicted in Figure 2G, the first
如圖2H所繪,第一電子元件201,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第一電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。第二電子元件晶片202,該晶片其材料組成可為矽、鍺、錫、碳,或以上元素與它種具半導體特性元素之組合;該第二電子元件層,該電子元件可為主動電子元件、被動電子元件、感測元件、測試元件、微機電晶片或以上電子元件之組合。中介元件203具雙面佈線電路並具有平面與上下電性連接功能,該前述第一電子元件與第二電子元件,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組207;該中介元件材料可為矽、鍺、氧化矽、氧化鋁、有機材料,或以上元素之混合或與他種元素之組合。有機包覆材料208,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體倆側之線路209與211。電性通道210位於有機包覆體中,且該電性通道與該扇出至有機包覆體之兩側線路相連接;該電性通道材料可為銅、鎳、鐵、
鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合;該電性通道亦為一熱之良導體,具有導熱之特性。第二電性通道220位於有機包覆體中,且該電性通道與中介元件相連接及該扇出至有機包覆體之線路相連接;該電性通道材料可為銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合。
As depicted in Figure 2H, the first
圖3A至圖3F為本發明之第二實施例,為本發明之電子晶片堆疊封裝單元結構。圖3A中,中介元件303具雙面佈線電路,並具有平面與上下電性連接功能。第一電子元件301以及第二電子元件晶片302,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組307。有機包覆材料308,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路309。電性通道310位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接。電訊接點314位於該電子封裝結構外側,可用以與其他半導體元件相連接或用為測試接點或作為具測試功能之電子封裝結構;該電訊接點,可利用網版印刷、模板印刷、滾筒式塗佈、噴墨塗佈、植球、微影技術或其他適合之方式形成;該電訊接點材料,可為錫、銀、銦、銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合。
3A to 3F are the second embodiment of the present invention, which is the structure of the electronic chip stacked package unit of the present invention. In FIG. 3A, the
圖3B中,中介元件303具雙面佈線電路,並具有平面與上下電性連接功能。第一電子元件301以及第二電子元件晶片302,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組307。有機包覆材料308,以完全包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路309。電性通道310位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接。電訊接點314位於該電子封裝結構外側,可用以與其他半導體元件相連接或用為測試接點或作為具測試功能之電子封裝結構;該電訊接點,可利用網版印刷、模板印刷、滾筒式塗佈、噴墨塗佈、植球、微影技術或其他適合之方式形成;該電訊接點材料,可為錫、銀、銦、銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種
具導電性之材料的組合。
In FIG. 3B, the
如圖3C,中介元件303具單面佈線電路,並具有平面與上下電性連接功能。第一電子元件301以及第二電子元件晶片302,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組307。有機包覆材料308,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路309。電性通道310位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接。電訊接點314位於該電子封裝結構外側,可用以與其他半導體元件相連接或用為測試接點或作為具測試功能之電子封裝結構;該電訊接點,可利用網版印刷、模板印刷、滾筒式塗佈、噴墨塗佈、植球、微影技術或其他適合之方式形成;該電訊接點材料,可為錫、銀、銦、銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合。
As shown in FIG. 3C, the
如圖3D所繪,中介元件303具雙面佈線電路,並具有平面與上下電性連接功能。第一電子元件301以及第二電子元件晶片302,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組307。有機包覆材料308,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體兩側之線路309與311。電性通道310位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接。電訊接點314位於該電子封裝結構外側,可用以與其他半導體元件相連接或用為測試接點或作為具測試功能之電子封裝結構;該電訊接點,可利用網版印刷、模板印刷、滾筒式塗佈、噴墨塗佈、植球、微影技術或其他適合之方式形成;該電訊接點材料,可為錫、銀、銦、銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合。
As depicted in FIG. 3D, the
如圖3E,中介元件303具雙面佈線電路,並具有平面與上下電性連接功能。第一電子元件301、第二電子元件晶片302與第三電子元件312,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組307。有機包覆材料308,以部分包覆
方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路309。電性通道310位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接。電訊接點314位於該電子封裝結構外側,可用以與其他半導體元件相連接或用為測試接點或作為具測試功能之電子封裝結構;該電訊接點,可利用網版印刷、模板印刷、滾筒式塗佈、噴墨塗佈、植球、微影技術或其他適合之方式形成;該電訊接點材料,可為錫、銀、銦、銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合。
As shown in FIG. 3E, the
圖3F中,中介元件303具多層佈線電路,並具有平面與上下電性連接功能。第一電子元件301以及第二電子元件晶片302,至少其中一個電子元件之主動層面向該中介元件,並與中介元件之重佈線路連接形成晶片組307。有機包覆材料308,以部分包覆方式包覆該晶片組,且該晶片組可具有從電子元件扇出至有機包覆體一側之線路309。電性通道310位於有機包覆體中,且該電性通道與扇出至有機包覆體之線路相連接。電訊接點314位於該電子封裝結構外側,可用以與其他半導體元件相連接或用為測試接點或作為具測試功能之電子封裝結構;該電訊接點,可利用網版印刷、模板印刷、滾筒式塗佈、噴墨塗佈、植球、微影技術或其他適合之方式形成;該電訊接點材料,可為錫、銀、銦、銅、鎳、鐵、鋁、鈷、金、或以上金屬材料合金或他種具導電性之材料的組合。
In FIG. 3F, the
圖4為本發明之第三實施例,說明本發明之電子元件堆疊封裝單元結構之電性通道與電訊接點相對位置之截面示意圖。如圖4A所示,將電性通道、扇出線路與電訊接點之相對位置說明如圖4B至4D,包含:有機包覆材料408,該有機包覆材內含電性通道410,圖4B說明電訊接點414位於電性通道410之一端正下方,以及電訊接點415位於電性通道410之另一端正上方。圖4C說明電訊接點414位於電性通道410之一端正下方,以及電訊接點416位於與電性通道410連接之扇出線路411上方。圖4D說明電訊接點417位於與電性通道410連接之扇出線路下方,以及電訊接點416位於與電性通道410連
接之扇出線路411上方。且前述之電訊接點414、415、416與417均可與前述封裝結構內部電子元件之測試訊號相連通,形成一具測試功能之電子封裝結構。
4 is a third embodiment of the present invention, illustrating a cross-sectional schematic diagram of the relative positions of the electrical channels and the telecommunication contacts of the electronic component stacked package unit structure of the present invention. As shown in FIG. 4A, the relative positions of the electrical channels, fan-out lines, and telecommunication contacts are illustrated in FIGS. 4B to 4D, including: an
圖5為本發明之第四實施例,說明本發明之電子元件堆疊封裝單元結構之電性通道結構示意圖。圖5A與圖5B說明本發明架構中的堆疊封裝單元500內的電性通道510,其形狀可以是具有轉折形狀。
5 is a fourth embodiment of the present invention, illustrating a schematic diagram of the electrical channel structure of the electronic component stacked package unit structure of the present invention. 5A and 5B illustrate the
圖6為本發明之第五實施例,說明本發明之電子元件堆疊封裝單元結構可藉由複數個該電子封裝結構單元體形成非共平面之立體堆疊電子封裝結構,其中所述位於電子封裝結構之該電性通道,可利用前述該扇出至有機包覆體之線路進行電訊傳遞,使該複數個電子封裝結構單元體間電性導通如圖6A至6C。圖6A為電子元件堆疊封裝單元200藉由從電子元件扇出至有機包覆體一側之線路209與另一電子元件堆疊封裝單元200之扇出線路209進行連接。圖6B為電子元件堆疊封裝單元300藉由電訊接點314與另一電子元件堆疊封裝單元300之電訊接點314進行連接。
6 is a fifth embodiment of the present invention, illustrating that the electronic component stacked package unit structure of the present invention can form a non-coplanar three-dimensional stacked electronic package structure by using a plurality of the electronic package structure unit bodies, wherein the electronic package structure is located The electrical channel can use the aforementioned fan-out circuit to the organic cladding body for telecommunications transmission, so that the plurality of electronic packaging structure unit bodies are electrically connected as shown in Figs. 6A to 6C. 6A shows that the electronic component stacked
本發明較佳實施例說明如上,而熟悉此領域技藝,在不脫離本發明之精神範圍內,當可做些許更動潤飾,其專利保護範圍更當視後附之申請專利範圍及其等同領域而定。 The preferred embodiments of the present invention are described above, and if you are familiar with the skills in this field, you can make some modifications without departing from the spirit of the present invention. The scope of patent protection is more dependent on the scope of the attached patent application and its equivalent fields. set.
110‧‧‧錫球 110‧‧‧Tin ball
112‧‧‧球下金屬層 112‧‧‧Metal layer under the ball
114‧‧‧重佈線 114‧‧‧Rewiring
132‧‧‧第二晶片 132‧‧‧Second chip
133‧‧‧第三晶片 133‧‧‧third chip
141‧‧‧晶圓 141‧‧‧wafer
200‧‧‧電子晶片堆疊封裝單元結構 200‧‧‧Electronic chip stacked package unit structure
201‧‧‧第一電子元件 201‧‧‧The first electronic component
202‧‧‧第二電子元件 202‧‧‧Second electronic component
203‧‧‧中介元件 203‧‧‧Intermediary components
204‧‧‧第一佈線電路 204‧‧‧First wiring circuit
205‧‧‧第二佈線電路 205‧‧‧Second wiring circuit
206‧‧‧電性連接凸塊 206‧‧‧Electrical connection bump
207‧‧‧晶片組 207‧‧‧Chipset
208‧‧‧有機包覆體 208‧‧‧Organic coating
209‧‧‧第一扇出線路 209‧‧‧The first fan-out line
210‧‧‧電性通道 210‧‧‧Electrical channel
211‧‧‧第二扇出線路 211‧‧‧The second fan-out line
212‧‧‧第三電子元件 212‧‧‧Third electronic component
213‧‧‧多層佈線電路中介元件 213‧‧‧Intermediate components for multilayer wiring circuits
220‧‧‧第二電性通道 220‧‧‧Second electrical channel
300‧‧‧電子晶片堆疊封裝單元結構 300‧‧‧Electronic chip stacked package unit structure
301‧‧‧第一電子元件 301‧‧‧The first electronic component
302‧‧‧第二電子元件 302‧‧‧Second electronic component
303‧‧‧中介元件 303‧‧‧Intermediary components
304‧‧‧第一佈線電路 304‧‧‧First wiring circuit
305‧‧‧第二佈線電路 305‧‧‧Second wiring circuit
306‧‧‧電性連接凸塊 306‧‧‧Electrical connection bump
307‧‧‧晶片組 307‧‧‧Chipset
308‧‧‧有機包覆體 308‧‧‧Organic coating
309‧‧‧第一扇出線路 309‧‧‧The first fan-out line
310‧‧‧電性通道 310‧‧‧Electrical channel
311‧‧‧第二扇出線路 311‧‧‧The second fan-out line
312‧‧‧第三電子元件 312‧‧‧Third electronic component
313‧‧‧多層佈線電路中介元件 313‧‧‧Intermediate components for multilayer wiring circuits
314‧‧‧電訊接點 314‧‧‧Telecom Contact
400‧‧‧電子晶片堆疊封裝單元結構 400‧‧‧Electronic chip stacked package unit structure
401‧‧‧第一電子元件 401‧‧‧The first electronic component
402‧‧‧第二電子元件 402‧‧‧Second electronic component
403‧‧‧中介元件 403‧‧‧Intermediary components
404‧‧‧第一佈線電路 404‧‧‧First wiring circuit
405‧‧‧第二佈線電路 405‧‧‧Second wiring circuit
406‧‧‧電性連接凸塊 406‧‧‧Electrical connection bump
408‧‧‧有機包覆體 408‧‧‧organic coating
409‧‧‧第一扇出線路 409‧‧‧The first fan-out line
410‧‧‧電性通道 410‧‧‧electrical channel
414‧‧‧電訊接點 414‧‧‧Telecom Contact
415‧‧‧與電性通道直接相連接之電訊接點 415‧‧‧Telecom contacts directly connected to electrical channels
416‧‧‧與電性通道藉由佈線電路連接之電訊接點 416‧‧‧Telecom contacts connected to electrical channels by wiring circuits
500‧‧‧電子晶片堆疊封裝單元結構 500‧‧‧Electronic chip stacked package unit structure
501‧‧‧第一電子元件 501‧‧‧First electronic component
502‧‧‧第二電子元件 502‧‧‧Second electronic component
503‧‧‧中介元件 503‧‧‧Intermediary components
504‧‧‧第一佈線電路 504‧‧‧First wiring circuit
505‧‧‧第二佈線電路 505‧‧‧Second wiring circuit
506‧‧‧電性連接凸塊 506‧‧‧Electrical connection bump
508‧‧‧有機包覆體 508‧‧‧Organic coating
509‧‧‧第一扇出線路 509‧‧‧The first fan-out line
510‧‧‧電性通道 510‧‧‧Electrical channel
514‧‧‧電訊接點 514‧‧‧Telecom Contact
600‧‧‧電子晶片堆疊封裝結構 600‧‧‧Electronic chip stack package structure
601‧‧‧第一電子晶片堆疊封裝單元結構 601‧‧‧First electronic chip stack package unit structure
602‧‧‧第二電子晶片堆疊封裝單元結構 602‧‧‧Second electronic chip stacked package unit structure
603‧‧‧第一扇出線路 603‧‧‧The first fan-out line
604‧‧‧第二扇出線路 604‧‧‧The second fan-out line
605‧‧‧第三電子晶片堆疊封裝單元結構 605‧‧‧The third electronic chip stack package unit structure
606‧‧‧第四電子晶片堆疊封裝單元結構 606‧‧‧The fourth electronic chip stacked package unit structure
607‧‧‧電訊接點 607‧‧‧Telecom Contact
本發明之較佳實施例將於下述說明中輔以下列圖形做更詳細的闡述: The preferred embodiment of the present invention will be explained in more detail in the following description with the following figures:
圖1A為習知利用光敏感材料中的複數個導通孔與重佈線路形成電連通路之多晶片進行整合堆疊晶片封裝結構之示意圖。 FIG. 1A is a schematic diagram of a conventional multi-chip integrated stacked chip package structure using a plurality of vias in a photosensitive material and re-layout lines to form electrical communication paths.
圖2A至圖2H為本發明之第一實施例,為本發明電子晶片堆疊封裝單元結構截面圖。 2A to 2H are the first embodiment of the present invention, and are cross-sectional views of the structure of the electronic chip stack package unit of the present invention.
圖3A至圖3F為本發明之第二實施例,為本發明電子晶片堆疊封裝單元結構截面圖。 3A to 3F are the second embodiment of the present invention, and are cross-sectional views of the structure of the electronic chip stack package unit of the present invention.
圖4A至圖4D為本發明第三實施例,其中電訊接點可不在導通孔之上方或下方。 4A to 4D show the third embodiment of the present invention, in which the telecommunication contact point may not be above or below the via hole.
圖5為本發明之第四實施例,其中電性通道可具有轉折形狀。 Figure 5 is a fourth embodiment of the present invention, in which the electrical channel may have a turning shape.
圖6為本發明之第五實施例,其中電子元件堆疊封裝單元結構可藉由複數個該電子封裝結構單元體形成立體堆疊結構。 FIG. 6 is a fifth embodiment of the present invention, in which the electronic component stacked packaging unit structure can form a three-dimensional stacked structure by using a plurality of the electronic packaging structure unit bodies.
200‧‧‧電子晶片堆疊封裝單元結構 200‧‧‧Electronic chip stacked package unit structure
201‧‧‧第一電子元件 201‧‧‧The first electronic component
202‧‧‧第二電子元件 202‧‧‧Second electronic component
203‧‧‧中介元件 203‧‧‧Intermediary components
204‧‧‧第一佈線電路 204‧‧‧First wiring circuit
205‧‧‧第二佈線電路 205‧‧‧Second wiring circuit
206‧‧‧電性連接凸塊 206‧‧‧Electrical connection bump
207‧‧‧晶片組 207‧‧‧Chipset
208‧‧‧有機包覆體 208‧‧‧Organic coating
209‧‧‧第一扇出線路 209‧‧‧The first fan-out line
210‧‧‧電性通道 210‧‧‧Electrical channel
211‧‧‧第二扇出線路 211‧‧‧The second fan-out line
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108138760A TW202117943A (en) | 2019-10-21 | 2019-10-21 | Multi-chip three-dimensional stacked package with fan-out structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108138760A TW202117943A (en) | 2019-10-21 | 2019-10-21 | Multi-chip three-dimensional stacked package with fan-out structure |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202117943A true TW202117943A (en) | 2021-05-01 |
Family
ID=77020661
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108138760A TW202117943A (en) | 2019-10-21 | 2019-10-21 | Multi-chip three-dimensional stacked package with fan-out structure |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW202117943A (en) |
-
2019
- 2019-10-21 TW TW108138760A patent/TW202117943A/en unknown
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11309304B2 (en) | Stackable electronic package and method of fabricating same | |
KR100611267B1 (en) | High performance, low cost microelectronic circuit package with interposer | |
US7902648B2 (en) | Interposer configured to reduce the profiles of semiconductor device assemblies, packages including the same, and methods | |
JP6097837B2 (en) | System in package with RF die embedded in coreless substrate | |
US7224062B2 (en) | Chip package with embedded panel-shaped component | |
US6495912B1 (en) | Structure of ceramic package with integrated passive devices | |
TW202145465A (en) | Modular stacked silicon package assembly | |
US7495330B2 (en) | Substrate connector for integrated circuit devices | |
KR20030064887A (en) | Multiple tier array capacitor and methods of fabrication therefor | |
CN103098207A (en) | Stacked semiconductor chip device with thermal management | |
KR20140057982A (en) | Semiconductor package and method of manufacturing the semiconductor package | |
CN101207101A (en) | Pattern mask structure and method for dry etching | |
CN108074898A (en) | Semiconductor packages | |
CN111199957A (en) | Three-dimensional packaging structure integrating chip and antenna and preparation method thereof | |
CN108807331A (en) | Electronic package and manufacturing method thereof | |
KR20210147990A (en) | Microelectronic arrangement and method for manufacturing the same | |
TW202117943A (en) | Multi-chip three-dimensional stacked package with fan-out structure | |
JPH04290258A (en) | Multichip module | |
CN211208440U (en) | Three-dimensional packaging structure integrating chip and antenna | |
CN111883513A (en) | Chip packaging structure and electronic equipment | |
CN216435894U (en) | Package structure and stack structure | |
TWI716198B (en) | Chip-package device | |
US11309288B2 (en) | Electronic system, die assembly and device die | |
Brown et al. | Thermal management issues and evaluation of a novel, flexible substrate, 3-dimensional (3-D) packaging concept | |
Chen et al. | An overview of electrical and mechanical aspects of electronic packaging |