TW202107942A - Light-emitting diode driving apparatus and light-emitting diode driver - Google Patents

Abstract

A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.

Description

Light-emitting diode driving device and light-emitting diode driver

The invention provides a light-emitting diode (LED) driving device.

In LED display systems, cascaded LED driver transmission interfaces are usually used. In the cascaded LED driver transmission interface, since the clock signal and data signal are single-ended signals, the transfer rate of the clock signal and data signal will vary depending on the voltage swing range of the clock signal and the data signal, and the difference in the clock signal line. Parasitic capacitance and environmental noise are limited. In addition, the skew between the clock signal and the data signal in each LED driver in the cascaded LED driver may cause another problem and further limit the transmission rate of the data signal and the clock signal.

Recently, with the increasing demand for high-resolution and better performance LED display systems, a more creative technology is needed to eliminate the deviation between the data signal and the clock signal of the cascaded LED driver to improve the data signal and the clock signal. The transmission rate of the signal.

Nothing in this article should be taken as an admission that any part of this disclosure is knowledge in the prior art.

The present invention introduces an LED driving device. The LED driving device has a differential signal interface and eliminates the deviation between the data signal and the clock signal of the cascaded LED driver. In addition, the LED driving device reduces power consumption and chips by sequentially enabling the cascaded LED drivers without using first-in first-out (FIFO) memory in the cascaded LED drivers. area.

In an embodiment of the present disclosure, the LED driving device includes: a controller that outputs a first data packet differential signal and a first clock differential signal; an N-level LED driver, wherein the first stage of the N-level LED driver The LED driver receives the first data packet differential signal and the first clock differential signal and outputs a second data packet differential signal and a second clock differential signal. The Mth in the N-level LED driver The stage LED driver receives the M-th data packet differential signal and the M-th clock differential signal and outputs the (M+1)th data packet differential signal and the (M+1)-th clock differential signal.

In the embodiment of the present disclosure, the LED driver includes: a differential input (DI) data packet signal receiver, which receives a data packet differential signal; a differential input clock signal receiver, which receives a clock differential signal; The output data packet signal transmitter, which outputs the next-stage data packet differential signal; the differential output clock signal transmitter, which outputs the next-stage clock differential signal; and the timing control circuit, based on the data packet differential signal and the The clock differential signal controls the output timing of the next-stage data packet differential signal and the next-stage clock differential signal.

In summary, in the LED driving device provided by the present disclosure, by sequentially enabling the cascaded LED drivers without using FIFO memory in the cascaded LED drivers, the chip area and power consumption cost will be reduced. And by using a differential signal interface and eliminating the deviation between the data signal and the clock signal of the cascaded LED driver, the transmission rate of the data signal and the clock signal will be improved.

In order to make the foregoing content easier to understand, several embodiments accompanied with drawings are described in detail below.

The embodiments of the present disclosure are described below with reference to the drawings.

FIG. 1 is a schematic diagram of an LED driving device 100 according to an embodiment of the present disclosure. The LED driving device 100 includes a plurality of LED drivers 101, a controller 102 and a plurality of LEDs 103. The plurality of LED drivers 101 includes cascaded N-level LED drivers from LED driver 1 to LED driver N, and N is a positive integer. The controller 102 outputs the data signal DATA including the first data packet differential signal and the clock signal SCLK including the first clock differential signal to the first-stage LED driver 1, and the first-stage LED driver 1 receives the first data packet The differential signal and the first clock differential signal and the second data packet differential signal and the second clock differential signal are output to the second stage LED driver 2, and the Mth stage LED driver M receives the Mth data packet difference And output the (M+1)th data packet differential signal and the (M+1)th clock differential signal, and M and N are positive integers, and M is equal to or less than N. The frequency of the M-th data packet differential signal is K times the frequency of the M-th clock differential signal, and K is a real number.

FIG. 2A is a schematic diagram of the LED driver 101a in the LED driving device 100 according to an embodiment of the present disclosure. As shown in FIGS. 1 and 2A, the M-th LED driver M includes a differential-input (DI) receiver (RX) 202, a timing control circuit 203, and a DO (differential-output) transmitter (TX) 201. The DI RX 202 in the LED driver M receives the M-th data packet differential signal and the M-th clock differential signal, where the output of DI RX 202 is coupled to the input of the timing control circuit 203, and the input of DO TX 201 is coupled to the timing control The output of the circuit 203. The LED driver M transmits the (M+1)th data packet differential signal and the (M+1)th clock differential signal to the LED driver (M+1). The timing control circuit 203 controls the output timing of the (M+1)th data packet differential signal and the (M+1)th clock differential signal according to the Mth data packet differential signal and the Mth clock differential signal. FIG. 2B is a schematic diagram of the LED driver 101b in the LED driving device 100 according to another embodiment of the present disclosure. As shown in FIGS. 1 and 2B, the LED driver 101b includes, but is not limited to, two LED drivers 101a (LED driver 1 101a_1 and LED driver 2 101a_2). The data input terminal of LED driver 1 101a_1 receives the first data packet differential signal, the clock input terminal of LED driver 1 101a_1 and LED driver 2 101a_2 receives the first clock differential signal, and the data output terminal of LED driver 1 101a_1 outputs the first data packet differential signal. Second data packet differential signal, the data input terminal of LED driver 2 101a_2 receives the second data packet differential signal, the data output terminal of LED driver 2 101a_2 outputs the third data packet differential signal, and the clock output terminal of LED driver 2 101a_2 The third clock differential signal is output. FIG. 2C is a schematic diagram of the LED driver 101c in the LED driving device 100 according to another embodiment of the present disclosure. As shown in FIGS. 1 and 2C, the LED driver 101c includes but is not limited to two LED drivers 101a (LED driver 1 101a_1 and LED driver 2 101a_2). The data input terminals of LED driver 1 101a_1 and LED driver 2 101a_2 receive the first data packet differential signal, the clock input terminal of LED driver 1 101a_1 and the clock input terminal of LED driver 2 101a_2 receive the first clock differential signal, The data output terminal of the LED driver 2 101a_2 outputs the third data packet differential signal, and the clock output terminal of the LED driver 2 101a_2 outputs the third clock differential signal.

As shown in FIG. 2A, the timing control circuit 203 includes: a deviation cancellation circuit having an input coupled to the first output of the DI RX 202; a delay-locked loop DLL circuit having a second output coupled to the DI RX 202 Output and input coupled to the second input of DO TX 201; a first register DFF1 having a first input coupled to the output of the deviation cancellation circuit and a second input coupled to the second output of DI RX 202; and a second The register DFF2 has a first input coupled with the output of the first register DFF1, a second input coupled with the output of the DLL circuit, and an output coupled with the first input of the DO TX 201.

3 is a schematic diagram of DO TX 201a and DI RX 202a of the M-th LED driver M in the LED driving device 100 according to another embodiment of the present disclosure. The DI RX 202a of the M-th LED driver M includes: a current mirror circuit, including a current source I _b , an N-type metal oxide semiconductor (N-type metal oxide semiconductor, NMOS) transistor Mbn2a, and an NMOS transistor Mbn2b, providing a first Bias current I _DC ; a pair of source coupled transistors, including NMOS transistors Mn3a and NMOS transistors Mn3b, are coupled to the current mirror circuit, and receive the M-th data packet differential signal and the first through the differential inputs IN+ and IN- M clock differential signals are output from differential outputs OUT+ and OUT-; a load circuit is coupled to the pair of source coupled transistors and adjusts the voltage signal swing range of differential outputs OUT+ and OUT-, where DI RX 202a can also be a single-ended output.

The DO TX 201a of the M-th LED driver M includes: an error amplifier, which outputs a first error voltage signal AV _b1 and a second error voltage signal AV _b2 according to the common mode voltage VCM signal; a bias current control circuit, including an NMOS transistor Mbn1 and A P-type metal oxide semiconductor (PMOS) transistor Mbp1 _{provides a second bias current according to the first error voltage signal AV b1} and the second error voltage signal AV _b2 ; and a DIDO inverter, including NMOS transistors Mn1, Mn2 and PMOS transistors Mp1, Mp2, DIDO inverters have differential inputs IN+ and IN- coupled with DI RX 202a and output the (M+1) data packet from the differential outputs OUT+ and OUT- Differential signal and (M+1)th clock differential signal. Resistor R _{1 is} used to sense the common-mode voltage of the (M+1)th data packet differential signal and the (M+1)th clock differential signal, and feed the sensed common-mode voltage back to the error amplifier Non-inverting input. The resistor 2R _{0 is} used to match the output impedance of the DO TX 201a of the M-th LED driver M with the input impedance of the DI RX 202a of the (M+1)-th LED driver (M+1), where DO TX 201a is also Can be single-ended input.

FIG. 4 shows the relationship between DO TX 201a in the M-th LED driver M in the LED driving device 100 and DI RX 202a in the (M+1)-th LED driver (M+1) in the LED driving device 100 according to another embodiment of the present disclosure. Schematic diagram of differential signal transmission. DATA_OUT+ and DATA_OUT- (ie, the (M+1)th data packet differential signal) are used between the M-th LED driver M and the (M+1)th LED driver (M+1) in the LED driving device 100 Examples of data signal transmission, but not limited to this. The M-th LED driver M sets the common mode voltage of the (M+1)th data packet differential signal by setting the common mode voltage VCM signal to the input signal of the inverting input of the error amplifier of DO TX 201a. As shown in FIG. 4, the M-th LED driver M sets the common mode voltage of the (M+1)th data packet differential signal from VCM2 to VCM1 and from VCM1 to VCM2.

The DI RX 202a in the (M+1)th LED driver (M+1) receives the (M+1)th data packet differential signal, and the VCM detector 202b detects the (M+1)th data packet differential signal Common mode voltage level. The VCM detector 202b includes a comparator that compares the common mode voltage level of the differential signal of the (M+1)th data packet with the reference voltage level VREF, and when the common mode voltage level of the differential signal of the (M+1)th data packet is Enable DI RX 202a when the mode voltage level is greater than the reference voltage level VREF.

5 is a signal flow of the common mode voltage VCM signal, the clock signal SCLK, and the data signal DATA of the LED drivers 1 to N in the LED driving device 100 according to an embodiment of the present disclosure. As shown in Figures 1 and 5, the controller 102 outputs the first data packet differential signal (data packet 1) to the first-level LED driver 1. After the first-level LED driver 1 receives the data packet 1, the first The first-level LED driver 1 sets the common-mode voltage VCM signal of the first-level LED driver 1 from VCM1 to VCM2, and the first-level LED driver 1 sets the common-mode voltage VCM signal of the first-level LED driver 1 from VCM1 to VCM2 After that, the first-level LED driver 1 outputs the second data packet differential signal (data packet 2) to the second-level LED driver 2. After the second-level LED driver 2 receives the data packet 2, the second-level LED driver 2 sets the common mode voltage VCM signal of the second-level LED driver 2 from VCM1 to VCM2, and so on.

6 is a signal flow of the common mode voltage VCM signal, the clock signal SCLK and the data signal DATA of the LED drivers 1 to N in the LED driving device 100 according to another embodiment of the present disclosure. As shown in Figures 1 and 6, the controller 102 reads back the first data packet differential signal (data packet 1) from the first-level LED driver 1. After the controller 102 reads back the data packet 1, the first-level LED Driver 1 sets the common mode voltage VCM signal of the first stage LED driver 1 from VCM2 to VCM1, and after the first stage LED driver 1 sets the common mode voltage VCM signal of the first stage LED driver 1 from VCM2 to VCM1, it controls The device 102 reads back the second data packet differential signal (data packet 2) from the second-level LED driver 2. After the controller 102 reads back the data packet 2, the second-level LED driver 2 sets the common mode voltage VCM signal of the second-level LED driver 2 from VCM2 to VCM1, and so on.

FIG. 7 is a schematic diagram of an LED driving device 300 according to another embodiment of the present disclosure. Compared with the LED driving device 100 shown in FIG. 1, the LED driver 301 also includes a DEIN input and a DEOUT output, and the signal DEM is an enable signal of the M-th LED driver M. As shown in FIG. 7, the M-th LED driver M receives the enable signal DEM and outputs the enable signal DE(M+1) to enable the (M+1)-th LED driver (M+1).

FIG. 8 is a signal flow of the enable signal DE, the clock signal SCLK, and the data signal DATA of the LED driver 301 in the LED driving device 300 according to an embodiment of the present disclosure. As shown in Figures 7 and 8, at the beginning, the enable signal DE1 enables the first stage LED driver 1, and the controller 102 outputs the first data packet differential signal (data packet 1) to the first stage LED driver 1, after the first-level LED driver 1 receives the data packet 1, the first-level LED driver 1 enables the second-level LED driver 2, and the first-level LED driver 1 pairs the second-level LED driver 2 After enabling, the first-level LED driver 1 outputs the second data packet differential signal (data packet 2) to the second-level LED driver 2. After the second-level LED driver 2 receives the data packet 2, the second-level LED driver 2 enables the third-level LED driver 3, and so on.

In another embodiment of the present disclosure, as shown in FIGS. 7 and 8, the enable signal DE1 enables the first-level LED driver 1 at the beginning, and the controller 102 returns from the first-level LED driver 1 Read the differential signal of the first data packet (data packet 1). After the controller 102 reads the data packet 1 back from the first-level LED driver 1, the first-level LED driver 1 enables the second-level LED driver 2, and After the first-level LED driver 1 enables the second-level LED driver 2, the controller 102 reads back the second data packet differential signal (data packet 2) from the second-level LED driver 2. After the controller 102 reads back the data packet 2 from the second-level LED driver 2, the second-level LED driver 2 enables the third-level LED driver 3, and so on.

FIG. 9 is a flowchart of sequentially enabling the LED drivers in the LED driving device 300 according to an embodiment of the present disclosure. In step S901, the M-th LED driver M receives the M-th data packet differential signal. In step S902, after receiving the M-th data packet differential signal, the M-th LED driver M enables the (M+1)-th LED driver (M+1). In step S903, after the (M+1)th stage LED driver (M+1) is enabled, the Mth stage LED driver M outputs the (M+1)th data packet differential signal.

FIG. 10 is a flowchart of sequentially setting the TX VCM signal of the LED driver in the LED driving device 100 according to an embodiment of the present disclosure. In step S1001, the M-th LED driver M receives the M-th packet differential signal. In step S1002, after receiving the M-th data packet differential signal, the M-th LED driver M sets the emitter common mode voltage VCM of the M-th LED driver M from VCM1 to VCM2. In step S1003, after setting the emitter common mode voltage VCM of the M-th LED driver M from VCM1 to VCM2, the M-th LED driver M outputs the (M+1)th packet differential signal.

FIG. 11 is a flowchart of sequentially enabling the LED drivers in the LED driving device 300 according to another embodiment of the present disclosure. In step S1101, the controller 102 reads back the M-th data packet differential signal from the M-th LED driver M. In step S1102, after the M-th data packet differential signal is read back to the controller 102, the M-th LED driver M enables the (M+1)-th LED driver (M+1).

FIG. 12 is a flowchart of sequentially setting the TX VCM signals of the LED drivers in the LED driving device 100 according to another embodiment of the present disclosure. In step S1201, the controller 102 reads back the M-th data packet differential signal from the M-th LED driver M. In step S1202, after the M-th data packet differential signal is read back to the controller 102, the M-th LED driver M sets the emitter common mode voltage VCM of the M-th LED driver M from VCM2 to VCM1.

FIG. 13 is a schematic diagram of the LED driver 101d in the LED driving device 100 according to another embodiment of the present disclosure. The M-th LED driver M may also include a frequency divider 1301, a red-green-blue (Red-Green-Blue, RGB) pulse width modulation (PWM) engine and an adjustable gain current source. The M-th LED driver M receives the M-th clock differential signal (ie, SCKIN) and uses the frequency divider 1301 to divide the frequency of the M-th clock differential signal to output a signal GCLK. The signal GCLK (ie, gray code clock) can be a single-ended signal or a differential signal, and drives the RGB PWM engine to generate different pulse width signals corresponding to different RGB data signals to control the plurality of LEDs 103 The grayscale value.

FIG. 14 is a schematic diagram of a frequency divider 1301 according to another embodiment of the present disclosure. The dividing frequency of the frequency divider 1301 can be a rational number expressed as N1/N2, and N1 and N2 are two positive integers. For example, the frequency divider 1301 may include a number of P (ie, P is an integer equal to or greater than 1) cascaded DFF (ie, D-type flip flop) to use the frequency divider 2 ^P performs frequency division operation. FIG. 14 shows an example of three cascaded DFFs (ie, DFF1, DFF2, and DFF3). The output Q of DFF1 is coupled to the input DB of DFF1, and the output QB of DFF1 is coupled to the input D of DFF1. DFF2 and DFF3 are configured the same as DFF1. Each of the cascaded DFFs uses the frequency divider 2 to perform the frequency division operation, and the total frequency divider provided by the frequency divider 1301 is 2 ³ (that is, the frequency of the signal GCLK (GCLK, GCLKB is a differential pair) is the signal 1/8 of the frequency of DCLK (DCLK and DCLKB are differential pairs).

According to the above embodiments, the LED driving devices 100 and 300 reduce the chip area and power consumption cost by sequentially enabling the cascaded LED drivers without using FIFO memory in the cascaded LED drivers. The differential signal interface and the elimination of the deviation between the data signal and the clock signal of the cascaded LED driver can improve the transmission rate of the data signal and the clock signal.

The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments, and various modifications and changes can be made within the scope of the gist of the invention described in the scope of the invention application.

100, 300: LED driver 101, 101a, 101b, 101c, 101d, 101a_1, 101a_2, 301: LED driver 102: controller 103: light-emitting diode 201, 201a: transmitter 202, 202a: receiver 202b: total Modulus voltage detector 203: timing control circuit 1301: frequency divider DATA: data SCLK: clock signal CLK: clock signal RX: receiver TX: transmitter DFF, DFF1, DFF2, DFF3: D-type flip-flop/temporary storage DI, DO: differential input, differential output VCM, VCM1, VCM2: common mode voltage S901~S903, S1001~S1003, S1101~S1103, S1201~S1202: steps R ₀ , R ₁ : resistors Mp1, Mp2 Mbp1: PMOS transistors Mn1, Mn2, Mbn1, Mbn2a, Mbn2b, Mn3a, Mn3b: NMOS transistor I _b : current source I _DC : first bias current AV _b1 : first error voltage signal AV _b2 : second error voltage Signal VDD: power supply voltage DATA_OUT+, DATA_OUT-: data package differential signal VREF: reference voltage level DE: enable signal D, DB: input DCLK, GCLK: signal SCKIN: M-th clock differential signal Q, QB: input

FIG. 1 is a schematic diagram of a light emitting diode (LED) driving device according to an embodiment of the present disclosure. 2A to 2C are schematic diagrams of the LED driver in the LED driving device according to different embodiments of the present disclosure. FIG. 3 is a schematic diagram of a transmitter (TX) and a receiver (receiver, RX) in an LED driving device according to another embodiment of the present disclosure. 4 is a schematic diagram of differential signal transmission between TX in the M-th LED driver and RX in the (M+1)-th LED driver in the LED driving device according to another embodiment of the present disclosure. FIG. 5 is a signal flow of the common mode voltage VCM signal, the clock signal SCLK and the data signal DATA of the LED driver in the LED driving device according to an embodiment of the present disclosure. FIG. 6 is a signal flow of the VCM signal, the clock signal SCLK and the data signal DATA of the LED driver in the LED driving device according to another embodiment of the present disclosure. FIG. 7 is a schematic diagram of an LED driving device according to another embodiment of the present disclosure. FIG. 8 is a signal flow of the enable signal DE, the clock signal SCLK, and the data signal DATA of the LED driver in the LED driving device according to an embodiment of the present disclosure. FIG. 9 is a flowchart of sequentially enabling the LED drivers in the LED driving device according to an embodiment of the present disclosure. FIG. 10 is a flowchart of sequentially setting the TX VCM signal of the LED driver in the LED driving device according to an embodiment of the present disclosure. FIG. 11 is a flowchart of sequentially enabling the LED drivers in the LED driving device according to another embodiment of the present disclosure. FIG. 12 is a flowchart of sequentially setting the TX VCM signal of the LED driver in the LED driving device according to another embodiment of the present disclosure. FIG. 13 is a schematic diagram of an LED driver in an LED driving device according to another embodiment of the present disclosure. FIG. 14 is a schematic diagram of a frequency divider according to another embodiment of the present disclosure.

100: LED driver

101: LED driver

102: Controller

103: LED

DATA: data signal

SCLK: clock signal

SDIN: Data input

SDOUT: data output

SCKIN: clock input

SCKOUT: clock output

OUTR, OUTG, OUTB: data output

Claims (31)

A light emitting diode (LED) driving device includes: N-level light-emitting diode driver, wherein the first-level light-emitting diode driver in the N-level light-emitting diode driver receives the first data packet differential signal and the first clock differential signal and outputs the second data packet A differential signal and a second clock differential signal, the M-th light-emitting diode driver in the N-level light-emitting diode driver receives the M-th data packet differential signal and the M-th clock differential signal and outputs the (M+1) data packet differential signal and (M+1)th clock differential signal, and M and N are positive integers, and M is equal to or less than N. The light-emitting diode driving device according to claim 1, wherein the M-th level light-emitting diode driver further includes: A differential input data packet signal receiver, which receives the M-th data packet differential signal; A differential input clock signal receiver, which receives the M-th clock differential signal; A differential output data packet signal transmitter, which outputs the (M+1)th data packet differential signal; A differential output clock signal transmitter, which outputs the (M+1)th clock differential signal; and A timing control circuit for controlling the (M+1)th data packet differential signal and the (M+1)th clock difference according to the Mth data packet differential signal and the Mth clock differential signal The output timing of the motion signal. The light emitting diode driving device according to claim 2, wherein the timing control circuit includes: A deviation cancellation circuit, the input of the deviation cancellation circuit is coupled to the output of the differential input data packet signal receiver; A delay locked loop (DLL) circuit, the input of the delay locked loop circuit is coupled to the output of the differential input clock signal receiver and the input of the differential output clock signal transmitter; A first register whose input is coupled to the output of the deviation cancellation circuit and the output of the differential input clock signal receiver; and A second register, the input of the second register is coupled to the output of the first register and the output of the delay locked loop circuit, and the output of the second register is coupled to the Differential output data packet signal transmitter input. The light emitting diode driving device according to claim 2, wherein the differential input data packet signal receiver includes: A current mirror circuit, which provides a first bias current; A pair of source coupled transistors, coupled to the current mirror circuit and receiving the M-th data packet differential signal; A load circuit coupled to the pair of source coupled transistors; and The common mode voltage detector enables the differential input data packet signal receiver according to the common mode voltage level of the M-th data packet differential signal. The light emitting diode driving device according to claim 4, wherein the common mode voltage detector includes a comparison that compares the common mode voltage level of the M-th data packet differential signal with a reference voltage level Device. The light-emitting diode driving device according to claim 2, wherein the differential output data packet signal transmitter includes: An error amplifier, which outputs a first error voltage signal and a second error voltage signal according to the common mode voltage signal; A bias current control circuit, which provides a second bias current according to the first error voltage signal and the second error voltage signal; and A differential input and differential output inverter is coupled to the input of the bias current control circuit and the error amplifier and outputs the (M+1)th data packet differential signal. The light-emitting diode driving device according to claim 6, wherein the M-th data packet differential signal and the (M+1)-th data packet differential signal are separated by a time interval according to the common mode voltage signal , And in the time interval after the M-th light-emitting diode driver receives the M-th data packet differential signal, the M-th light-emitting diode driver changes the common-mode voltage signal from the first A common mode voltage level is set to the second common mode voltage level. The light-emitting diode driving device according to claim 6, wherein the M-th data packet differential signal and the (M+1)-th data packet differential signal are separated by a time interval according to the common mode voltage signal , And in the time interval after the controller reads back the M-th data packet differential signal from the M-th LED driver, the M-th LED driver reduces the common mode voltage The signal is set from the third common mode voltage level to the fourth common mode voltage level. The light-emitting diode driving device according to claim 2, wherein the M-th light-emitting diode driver outputs an enable signal in a time interval so that the M-th light-emitting diode driver receives After the differential signal of the Mth data packet, the (M+1)th stage light-emitting diode driver is enabled. The light-emitting diode driving device according to claim 2, wherein the M-th light-emitting diode driver outputs an enable signal in a time interval, so that the controller receives an enable signal from the M-th light-emitting diode. After the driver reads back the M-th data packet differential signal, the driver enables the (M+1)-th stage light-emitting diode driver. The light emitting diode driving device according to claim 1, wherein the frequency of the M-th data packet differential signal is K times the frequency of the M-th clock differential signal, and K is a real number. The light-emitting diode driving device according to claim 1, wherein the data output terminal of the first-level light-emitting diode driver is coupled to the data input terminal of the second-level light-emitting diode driver, and the first-level light-emitting diode driver The clock input terminal of the diode driver is coupled to the clock input terminal of the second-stage light-emitting diode driver, and the first-stage light-emitting diode driver receives the first data packet differential signal and the The first clock differential signal, the second-stage light-emitting diode driver outputs a third data packet differential signal and a third clock differential signal. The light-emitting diode driving device according to claim 1, wherein the data input terminal of the first-level light-emitting diode driver is coupled to the data input terminal of the second-level light-emitting diode driver, and the first-level light-emitting diode driver The clock input terminal of the diode driver is coupled to the clock input terminal of the second-stage light-emitting diode driver, and the first-stage light-emitting diode driver receives the first data packet differential signal and the The first clock differential signal, the second-stage light-emitting diode driver outputs a third data packet differential signal and a third clock differential signal. The light-emitting diode driving device according to claim 1, wherein the M-th level light-emitting diode driver further includes: The frequency divider receives the M-th clock differential signal and divides the frequency of the M-th clock differential signal to output a Gray code clock to control the gray scale values of a plurality of light-emitting diodes. The light emitting diode driving device according to claim 14, wherein the frequency division number of the frequency divider is a rational number equal to or greater than one. The light emitting diode driving device according to claim 14, wherein the frequency divider includes at least one cascaded d-type flip-flop. The light-emitting diode driving device according to claim 16, wherein the frequency division number of the frequency divider is substantially equal to 2 ^P , where P is the number of the at least one cascaded d-type flip-flop. A light emitting diode (LED) driver, including: Differential input data packet signal receiver, receiving a data packet differential signal; Differential input clock signal receiver, receiving one-clock differential signal; Differential output data packet signal transmitter, output the next-level data packet differential signal; Differential output clock signal transmitter, which outputs the next-level clock differential signal; and The timing control circuit controls the output timing of the next-stage data packet differential signal and the next-stage clock differential signal according to the data packet differential signal and the clock differential signal. The light emitting diode driver according to claim 18, wherein the timing control circuit includes: A deviation cancellation circuit, the input of the deviation cancellation circuit is coupled to the output of the differential input data packet signal receiver; A delay locked loop (DLL) circuit, the input of the delay locked loop circuit is coupled to the output of the differential input clock signal receiver and the input of the differential output clock signal transmitter; A first register whose input is coupled to the output of the deviation cancellation circuit and the output of the differential input clock signal receiver; and A second register, the input of the second register is coupled to the output of the first register and the output of the delay locked loop circuit, and the output of the second register is coupled to the Differential output data packet signal transmitter input. The light-emitting diode driver according to claim 18, wherein the differential input data packet signal receiver includes: A current mirror circuit, which provides a first bias current; A pair of source coupled transistors, coupled to the current mirror circuit and receiving the data packet differential signal; A load circuit coupled to the pair of source coupled transistors; and The common mode voltage detector enables the differential input data packet signal receiver according to the common mode voltage level of the data packet differential signal. The light emitting diode driver according to claim 20, wherein the common mode voltage detector includes a comparator that compares the common mode voltage level of the data packet differential signal with a reference voltage level. The light-emitting diode driver according to claim 18, wherein the differential output data packet signal transmitter includes: An error amplifier, which outputs a first error voltage signal and a second error voltage signal according to the common mode voltage signal; A bias current control circuit, which provides a second bias current according to the first error voltage signal and the second error voltage signal; and A differential input and differential output inverter is coupled to the input of the bias current control circuit and the error amplifier and outputs the next-stage data packet differential signal. The light-emitting diode driver according to claim 22, wherein the data packet differential signal and the next-level data packet differential signal are separated by a time interval according to the common mode voltage signal, and in the light-emitting two The light emitting diode driver sets the common mode voltage signal from a first common mode voltage level to a second common mode voltage level in the time interval after the polar body driver receives the data packet differential signal . The light-emitting diode driver according to claim 22, wherein the data packet differential signal and the next-level data packet differential signal are separated by a time interval according to the common mode voltage signal, and the controller slave The light emitting diode driver sets the common mode voltage signal from a third common mode voltage level to a fourth common mode in the time interval after the light emitting diode driver reads back the data packet differential signal Voltage level. The light-emitting diode driver according to claim 18, wherein the light-emitting diode driver outputs an enable signal in a time interval, so that the light-emitting diode driver receives the data packet differential signal Then enable the next-level LED driver. The light-emitting diode driver according to claim 18, wherein the light-emitting diode driver outputs an enable signal in a time interval, so that the controller reads back the data packet from the light-emitting diode driver After the differential signal, the next-level LED driver is enabled. The light emitting diode driver according to claim 18, wherein the frequency of the data packet differential signal is K times the frequency of the clock differential signal, and K is a real number. The light-emitting diode driver according to claim 18, wherein the light-emitting diode driver further includes: The frequency divider receives the clock differential signal and divides the frequency of the clock differential signal to output a Gray code clock to control the gray scale value of the light emitting diode. The light-emitting diode driver according to claim 28, wherein the frequency division number of the frequency divider is a rational number equal to or greater than one. The light-emitting diode driver according to claim 28, wherein the frequency divider includes at least one cascaded d-type flip-flop. The light-emitting diode driver according to claim 30, wherein the frequency division number of the frequency divider is substantially equal to 2 ^P , where P is the number of the at least one cascaded d-type flip-flop.

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