CN107612527A - Differential clocks drive circuit - Google Patents
Differential clocks drive circuit Download PDFInfo
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- CN107612527A CN107612527A CN201710574979.7A CN201710574979A CN107612527A CN 107612527 A CN107612527 A CN 107612527A CN 201710574979 A CN201710574979 A CN 201710574979A CN 107612527 A CN107612527 A CN 107612527A
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Abstract
Differential clocks drive circuit, is related to integrated circuit technique.The present invention includes following part：First stage drive circuit, it inputs termination differential voltage input, and it exports termination adder；Adder, its output end is as final output end；Delay circuit, it inputs termination differential voltage input；Second stage drive circuit, it inputs the output end of termination delay circuit, and it exports termination adder；Impulse generator, its first input interface connect the output end of delay circuit, and its second input interface connects differential voltage input, and it exports the input of termination third level drive circuit；Third level drive circuit, it exports termination adder；Invention enhances high-frequency signal, when exporting clock signal so as to which full swing input clock signal is converted into the low amplitude of oscillation again, compensate for the high frequency attenuation of interconnection line.
Description
Technical field
The present invention relates to integrated circuit technique.
Background technology
When the clock signal of Gigahertz is transmitted in Clock Tree, in order to improve the noise of clock distribution, shake, dutycycle
The problems such as distortion and deflection, industry have been widely used the scheme of differential signal.In the rail-to-rail signal of routine, height electricity
Conversion between flat needs to consume substantial amounts of time and power consumption.But after the amplitude of oscillation of signal reduces, changed between low and high level
Time reduce, the power of consumption reduces.Using differential signal, the noise margin of low amplitude of oscillation clock signal can be improved.Therefore
The scheme of low swing differential clock can be used in Clock Tree network.Rail-to-rail differential clock signal is transformed into transmitting terminal
Low swing differential clock signal, in receiving terminal again by low swing differential recovering clock signals into rail-to-rail differential clock signal, supply
Logic circuit uses.
If full swing differential clock signal is only converted into simple low swing differential clock signal by clock driver circuit,
That needs to place multiple repeater amplified signals on the interconnection line direction of signal transmission.And in whole frequency range, have
One approximately equalised gain, therefore the high frequency attenuation of interconnection line can not be compensated.
Therefore, when full swing input clock signal is converted into low amplitude of oscillation output clock signal, it is necessary to a kind of more preferable
Drive circuit, realization drive whole interconnection line in integrated circuits.
The content of the invention
The technical problem to be solved by the invention is to provide one kind to drive differential clock signal onto interconnection line,
And full swing differential clock signal is converted into the drive circuit of low swing differential clock signal.
It is differential clocks drive circuit that the present invention, which solves the technical scheme that the technical problem uses, it is characterised in that bag
Include following part：
First stage drive circuit, it inputs termination differential voltage input, and it exports termination adder；
Adder, its output end is as final output end；
Delay circuit, it inputs termination differential voltage input；
Second stage drive circuit, it inputs the output end of termination delay circuit, and it exports termination adder；
Impulse generator, its first input interface connect the output end of delay circuit, and its second input interface connects differential voltage
Input, it exports the input of termination third level drive circuit；
Third level drive circuit, it exports termination adder；
First stage drive circuit, the second stage drive circuit and third level drive circuit are all used for amplified difference signal.Enter one
Step, first stage drive circuit includes：
The first PMOS and the second NMOS tube of series connection, being connected in series for the two a little connect the first driving output line, the two
The first input point that grid connects as the first stage drive circuit input；
The 3rd PMOS and the 5th NMOS tube of series connection, being connected in series for the two a little connect the second driving output line, the two
The second input point that grid connects as the first stage drive circuit input；
The source electrode of first PMOS and the source electrode of the 3rd PMOS connect, the source electrode of the second NMOS tube and the 5th NMOS tube
Source electrode connects.
Second stage drive circuit includes：
The tenth PMOS and the 11st NMOS tube of series connection, being connected in series for the two a little connect the first driving output line, the two
The second input point for connecting as the second stage drive circuit input of grid；
The 12nd PMOS and the 13rd NMOS tube of series connection, being connected in series for the two a little connect the second driving output line, and two
The first input point that the grid of person connects as the second stage drive circuit input；
The source electrode of tenth PMOS and the source electrode of the 12nd PMOS connect, the source electrode and the 13rd of the 11st NMOS tube
The source electrode of NMOS tube connects.
Because the present invention is that differential signal is handled, therefore the input of involved circuit unit all includes two inputs
Point, output end also include two output points.
The present invention produces one by the way that the first stage drive circuit and the second stage drive circuit is used in combination, in clock edge transition
Pulse width is equal to the pulse signal of delay circuit, enhances high-frequency signal, so as to again change full swing input clock signal
When exporting clock signal into the low amplitude of oscillation, the high frequency attenuation of interconnection line compensate for.
Brief description of the drawings
Fig. 1 is the block diagram of differential clocks drive circuit provided in an embodiment of the present invention；
Fig. 2 is delay circuit schematic diagram provided in an embodiment of the present invention；
Fig. 3 is differential clocks drive circuit schematic diagram provided in an embodiment of the present invention；
Fig. 4 is the timing diagram of part signal in Fig. 3 circuits；
Fig. 5 is the timing diagram of part signal in Fig. 3 circuits.
Embodiment
The present invention includes：
First stage drive circuit, using rail-to-rail differential clock signal as input signal source；
Delay circuit, it is connected with the first stage drive circuit, using rail-to-rail differential input clock signal as input signal source, and
Produce a delay output；
Second stage drive circuit, using the output of delay circuit as input signal source；
Impulse generator, using the differential output signal of rail-to-rail differential input signal and delay circuit as input, and produce
One pulse width is equal to the pulse signal of delay circuit delays time；
Third level drive circuit, it is connected with pulse-generator circuit output, and opening using the pulse signal as the circuit
Close control signal；
Adder, the output phase of the circuit and the first stage drive circuit, the second stage drive circuit and third level drive circuit
Connect, and produce a primary differential signal clock output signal.The primary differential signal clock output signal of adder is by by
The differential output signal of one stage drive circuit, the differential output signal of the second stage drive circuit and the difference of third level drive circuit
Caused by output signal is added together.
It is as follows referring to Fig. 1~3, more specifically embodiment：
Differential clocks drive circuit, including following part：
First stage drive circuit 10, it inputs termination differential voltage input, and it exports termination adder；
Adder 100, its output end is as final output end；
Delay circuit 15, it inputs termination differential voltage input；
Second stage drive circuit 20, it inputs the output end of termination delay circuit 15, and it exports termination adder；
Impulse generator 25, its first input interface connect the output end of delay circuit 15, and its second input interface connects difference
Voltage input end, it exports the input of termination third level drive circuit 30；
Third level drive circuit 30, it exports termination adder；
First stage drive circuit 10, the second stage drive circuit 20 and third level drive circuit 30 are all used to amplify difference letter
Number.
First stage drive circuit 10 includes：
The the first PMOS T1 and the second NMOS tube T2 of series connection, being connected in series for the two a little connect the first driving output line 110,
The first input point that the grid of the two connects as the input of the first stage drive circuit 10；
The 3rd PMOS T3 and the 5th NMOS tube T5 of series connection, being connected in series for the two a little connect the second driving output line 108,
The second input point that the grid of the two connects as the input of the first stage drive circuit 10；
First PMOS T1 source electrode and the 3rd PMOS T3 source electrode connect, the second NMOS tube T2 source electrode and the 5th
NMOS tube T5 source electrode connects.
Second stage drive circuit 20 includes：
The tenth PMOS T10 and the 11st NMOS tube T11 of series connection, being connected in series for the two a little connect the first driving output line
110, the second input point that the grid of the two connects as the input of the second stage drive circuit 20；
The 12nd PMOS T12 and the 13rd NMOS tube T13 of series connection, being connected in series for the two a little connect the second driving output
Line 108, the first input point that the grid of the two connects as the input of the second stage drive circuit 20；
Tenth PMOS T10 source electrode and the 12nd PMOS T12 source electrode connect, the 11st NMOS tube T11 source electrode
Connect with the 13rd NMOS tube T13 source electrode.
The third level drive circuit 30 includes：
20th PMOS T20, it is arranged between high level end and the second driving output line 108；
32nd PMOS T32, it is arranged between high level end and the first driving output line 110；
30th NMOS tube T30, it is arranged between ground level end and the second driving output line 108；
22nd NMOS tube T22, it is arranged between ground level end and the first driving output line 110；
First input point of the 30th NMOS tube T30 grid as the input of third level drive circuit 30, passes through one
Phase inverter is connected with the 32nd PMOS T32 grid；
Second input point of the 22nd NMOS tube T22 grid as the input of third level drive circuit 30, passes through one
Individual phase inverter is connected with the 20th PMOS T20 grid.
Embodiment：
Such as Fig. 1, rail-to-rail differential voltage (such as Vdd and 0) is inputted IN_P (positive input) 2 to the present invention and IN_N is (negative defeated
Enter) 0 it is converted into primary differential signal component voltage output OUT_P (positive output) 104 and OUT_N (negative output) 102.Export OUT_N 102
Corresponding is input IN_P 2, and it is input IN_N 0 to export corresponding to OUT_P 104.Input IN_P 2 and IN_N 0 is connected to the
One stage drive circuit 10 (gain alpha), delay circuit 15 (delay time T), the and (pulse width duration of impulse generator 25
τ)。
The output signal 1 and 3 of delay circuit 15 is connected to the second stage drive circuit 20 (gain beta) and pulse signal generator
25.The input signal 1 and 3 of second stage drive circuit is the signal of input signal IN_P 2 and IN_N 0 after τ postpones.Second
The output of stage drive circuit is 22 and 24.The negative output 22 of second stage drive circuit 20 drives in adder 100 with the first order
The positive output 14 of circuit 10 is added, the positive output 24 of the second stage drive circuit 20 in adder 100 with the first stage drive circuit
10 negative output 12 is added.
Impulse generator 25 produces the differential pulse signal that a duration is τ on its output line 26 and 28.Pulse
Generator output line 26 and 28 is connected to third level drive circuit 30.Third level drive circuit 30 produces separately in burst length τ
Outer electric current is to output line 32 and 34.The output of third level drive circuit is 32 and 34.The negative output of third level drive circuit 30
32 negative output 12 with the first stage drive circuit 10 in adder 100 is added, and the positive output 34 of third level drive circuit 30 exists
Positive output 14 in adder 100 with the first stage drive circuit 10 is added.
Adder 100 receives the input 12/14 of 10 from the first stage drive circuit, the output 20 of the second stage drive circuit
Output 22/24 and third level drive circuit 30 output 32/34.Adder 100 is connected with variable resistor 107, and the resistance connects
It is connected between the difference output OUT_N 102 of adder 100 and OUT_P 104.Variable resistor R107 is used for aiding in controlling 102 Hes
The amplitude of oscillation of differential output voltage between 104.Output OUT_N 102 and OUT_P 104 is connected on interconnection line.In interconnection line
The other end equally there is also variable resistor, reduces reflection.
As two recommending output mode current driving circuits, the first stage drive circuit 10 (gain alpha) and second level differential driving
Circuit 20 (gain beta) provides most of line driving current to interconnection line.The tail current source T9 of first stage drive circuit 10 and
The tail current source T14 of secondary drive circuit 20 is unequal.The gain beta of second stage drive circuit 20 and the first stage drive circuit 10
Gain alpha is unequal.In embodiment, the gain beta of the second stage drive circuit 20 is less than the gain alpha of the first stage drive circuit 10.With
The function for the second stage drive circuit 20 that adder 100 is connected is, when differential input signal IN_P 2 and IN_N 0 are postponed into τ
Between after signal amplify β times and reverse.The effect of second stage drive circuit 20 is the output electricity for increasing adder 100 in high frequency treatment
Stream, compensate the high frequency loss on connecting line.
Third level drive circuit 30 is to improve the switching rate of difference output 102 and 104.Pulse signal generator 25
The pulse signal that a duration is τ is produced, the pulse signal opens the time span τ of third level drive circuit 30.Remaining when
Between, third level drive circuit is closed, and does not consume quiescent dissipation.Except the second stage drive circuit 20 can increase adder
100 outside the output current of high frequency treatment, and third level drive circuit can be further, but the high frequency for smaller increasing adder 100 is defeated
Go out electric current.
Fig. 2 is a delay circuit schematic diagram.Delay circuit 15 includes the phase inverter of one group of serial connection, for example is labeled as
151 delay 1, labeled as 152 delay 2, labeled as 153 delay 3, and labeled as 154 delay 4.One at 0/2
Input signal, x (t), time τ can be delayed by, x (t- τ) is exported at 1/3.Although Fig. 2 shows four phase inverters, only
It is intended to illustrate, minimum two inverter circuits can be included in the delay circuit of other embodiment.
Fig. 3 is a specific differential clocks drive circuit schematic diagram.Purpose is explained and is merely illustrative in order to simplify,
Reference number in circuit is identical with Fig. 1.One or more optional function modular circuit in Fig. 1 can be used.Such as figure
Dotted line frame 10 in 3, dotted line frame 20, the first stage drive circuit in circuit difference corresponding diagram 1 in dotted line frame 25, and dotted line frame 30
10, the second stage drive circuit 20, pulse signal generator 25, third level drive circuit 30.It is in figure one corresponding to dotted line frame 15
Delay circuit 15.
Transistor T15 in Fig. 3 is used for setting current mirror, and input reference current is labeled as electric current " I ".Second road current mirror
There is transistor T6 to be coupled to transistor T7.The transistor T8 of 3rd road current mirror is driven by the first stage drive circuit 10 and the second level
Dynamic circuit 20 is respectively coupled to transistor T9 and transistor T14." the electricity with the second road current mirror of electric current I of 3rd road current mirror
Stream I ' is proportional therefore also proportional to reference current I.The positive pole common mode node 112 of the 3rd road current mirror in embodiment
It is connected with the first stage drive circuit 10 and the second stage drive circuit, and the first stage drive circuit 10 has negative pole common mode node 114
There is negative pole common mode node 116 with the second stage drive circuit 20.Substantially, the 3rd road current mirror has two branch roads：First branch road
It is from 112 to 114, second branch road is from 112 to 116.The electric current (I 2) of second branch road and the electric current (I 1) of tie point into
Proportionate relationship.Therefore, I 2=γ I 1, I 1+ I 2=I ", γ are ratio Changshu.In one embodiment, the first order drives in figure one
The tail current source of circuit 10 is I 1, and the tail current source of the second stage drive circuit 20 is I 2.
First stage drive circuit 10 includes the first PMOS transistor T1, is connected in series with the second nmos pass transistor T2, the 3rd
PMOS transistor T3 and the 5th nmos pass transistor T5 is connected in series.First output signal 12 of the first stage drive circuit is connected to
Between one PMOS transistor T1 and the second nmos pass transistor T2, the second output signal 14 of the first stage drive circuit is connected to crystal
Between pipe T3 and T5.First PMOS transistor T1 and the 3rd PMOS transistor T3 is connected to the first node 112, the 2nd NMOS crystal
Pipe T2 and the 5th nmos pass transistor T5 are connected to the second node 114.First PMOS transistor T1's and the second nmos pass transistor T2
The grid that grid receives input signal IN_P 2, the 3rd PMOS transistor T3 and the 5th nmos pass transistor T5 receives input signal
IN_N 0.Signal IN_N 0 and IN_P 2 is rail-to-rail differential input signal.The He of output signal 12 of first stage drive circuit 10
14 be first order small-signal differential output signal.Output signal 12 and 14 corresponds to input signal IN_P 2 and IN_N 0 respectively.It is defeated
Go out signal 12 and be connected to OUT_N 102, output signal 14 is connected to OUT_P 104.
Delay circuit 15 receives input signal IN_N 0, and delay time T produces signal 1.Equally, delay circuit 15 receives
Input signal IN_P 2, and delay time T produces signal 3.
Second stage drive circuit 20 includes the tenth PMOS transistor T10, is connected in series with the 11st nmos pass transistor T11,
12nd PMOS transistor T12 and the 13rd nmos pass transistor T13 is connected in series.Output signal 22 be connected to transistor T12 and
Between T13, output signal 24 is connected between transistor T10 and T11.Transistor T10 and T12 are connected to node the 113, the 11st
Nmos pass transistor T11 and the 13rd nmos pass transistor T13 are connected to the 3rd node 116.Tenth PMOS transistor T10 and the 11st
Nmos pass transistor T11 grid receives the PMOS transistor T12 of input signal the 1, the 12nd and the 13rd from delay circuit 15
Nmos pass transistor T13 grid receives the input signal 3 from delay circuit 15.Signal labeled as 1 and 3 is rail-to-rail difference
Input signal.The output signal 22 and 24 of second stage drive circuit 20 is second level small-signal differential output signal.Output signal
22 and 24 correspond to input signal 3 (IN_P 2 postpones signal) and 1 (IN_N 0 postpones signal) respectively.Output signal 22 connects
To OUT_P 104, output signal 14 is connected to OUT_N 102.
Pulse signal generator circuit 25 includes two and door 172 and 178, and their output PP and NP is connected respectively to
Nmos pass transistor T30 and T22.Also, PMOS transistor T32 is connected to by phase inverter 166 with door 172, with door 178 by anti-
Phase device 164 is connected to PMOS transistor T20.Therefore, nmos pass transistor T30 and PMOS transistor T32 is opened and simultaneously closed off simultaneously.
Equally, nmos pass transistor T22 and PMOS transistor T20 is opened and simultaneously closed off simultaneously.
Signals 2 ' and IN_P 2 of the IN_P 2 after phase inverter 170 is anti-phase are received with door 172 by delay circuit 15 to prolong
The signal 3 to lag.Signals 0 ' and IN_N 0 of the IN_N 0 after phase inverter 176 is anti-phase, which are received, with door 178 passes through delay circuit
Signal 1 after 15 delays.The pulse signal PP that a duration is τ is produced in node 28 with door 172, with door 178 in node
26 produce the opposite pulse signal NP that a duration is τ.
Third level drive circuit 30 receives and comes from pulse signal PP and NP caused by impulse generator 25, and in the burst length
Interior increase OUT_P 104 and OUT_N 102 output current.In burst length τ, when PP is logic level 1, transistor
T30 is opened, and PP makes PP ' be changed into logic level 0 after phase inverter 166 is anti-phase, therefore opens transistor T32.Transistor
T30 is released electric charge by line 34 from OUT_P 104, therefore allows it to become more negative.Transistor T32 is by line 36 to OUT_N 102
Electric charge is injected, therefore allows it to become to correct.Similarly, in burst length τ, when NP is logic level 1, transistor T22 is beaten
Open, and NP makes NP ' be changed into logic level 0 after phase inverter 164 is anti-phase, therefore open transistor T20.Transistor T22 leads to
Cross line 32 to release electric charge from OUT_N 102, therefore allow it to become more negative.Transistor T20 injects electricity by line 38 to OUT_P 104
Lotus, therefore allow it to become to correct.
With reference to figure 1 and Fig. 3, in one embodiment of the invention, adder includes two driving output lines：
Second driving output line 108, receives the output signal 14 from the first stage drive circuit 10, is driven from the second level
The output signal 22 of circuit 20, also from the output signal 34 and 38 of third level drive circuit 30；
First driving output line 110, receives the output signal 12 from the first stage drive circuit 10, is driven from the second level
The output signal 24 of circuit 20, also from the output signal 32 and 36 of third level drive circuit 30.
The signal code of reception is added by the second driving output line 108, and result is output into OUT_P 104.First drives
The signal code of reception is added by dynamic output line 110, and result is output into OUT_N 102.OUT_N 102 and OUT_P 104
Output is primary differential signal sub-signal, and corresponding with rail-to-rail input signal IN_P 2 and IN_N 0 respectively.
Fig. 4 is the timing diagram of the part signal in Fig. 3, and the output signal and the second level for describing the first stage drive circuit are driven
The composite result of dynamic circuit output signal.First group of waveform 210 is the oscillogram of rail-to-rail differential input signal, it is assumed that solid line table
Show positive signal IN_P 2 oscillogram, dotted line represents negative signal IN_N 0 oscillogram.Logic 1 can be expressed as IN_P=
Vdd (224 He) IN_N=0 (226), logical zero can be expressed as IN_P=0 (230 He) IN_N=Vdd (228).Second group of waveform
211 illustrate rail-to-rail input signal 2 caused letter on output line 110 after the first stage drive circuit reversely amplifies α times
Number oscillogram.In order that oscillogram looks concise, in addition to rail-to-rail input signal, remaining only depict with it is defeated
The oscillogram of the coherent signal of outlet 110 illustrates how circuit works.Similarly it is applied to output line 111.The correspondence of output line 110
The related rail-to-rail input signal of the first stage drive circuit be IN_P 2, the second stage drive circuit phase corresponding to output line 110
The rail-to-rail input signal closed is IN_N=0.3rd group of waveform 212 represents that rail-to-rail input signal 0 is prolonged by delay circuit 15
The oscillogram of signal 1 after slow time τ.4th group of waveform 213 is signal 1 after the second stage drive circuit reversely amplifies β times
The oscillogram of caused signal on output line 110.5th group of waveform 216 is the output signal and second of the first stage drive circuit
The oscillogram for the signal that stage drive circuit output signal synthesizes on output line 110.
The 4th group of oscillogram 216 in Fig. 4, the level value 272 where when output line 110 starts are corresponding IN_P=0
Value, it is assumed that 272 value is 800mv.Drive circuit is sign-changing amplifier, and input low level, output is high level.In the period
In τ 208, when IN_P from 0 be converted to Vdd and signal 24 remain value 248 it is constant when, signal 14 changes (234) to being worth from value 232
236, driving output line 110 is from the transformation (274) of value 272 to value 276.Assuming that 276 value is 350mv.After period τ 208,
Because for signal 1 from Vdd transformations (240) to 0, signal 24 can change (252) to value 254 from value 248.Therefore, output line 110 is from value
276 (350mv) are converted to value 280 (500mv).In next period τ 209, when IN_P is converted to 0 and signal 24 from Vdd
Remain value 254 it is constant when, it be high level that signal 14 changes (238) from value 236, drives output line 110 from value 280 (500mv)
Be converted to value 284, it is assumed that 284 value is 950mv.After period τ 209, because signal 0 is believed from 0 transformation (244) to Vdd
Numbers 24, which can change (258), arrives value 260.Therefore, output line 110 changes (286) to value 288 (800mv) from value 284 (950mv).
Rail-to-rail differential input signal in Fig. 4 first group of waveform and the 5th group of waveform table diagram 1 and Fig. 3, IN_N 0
With the small-signal difference reversed-phase output signal on IN_P 2, and output line 110.Second stage drive circuit 20 increases in signal hopping edge
The voltage difference on output line is added, such as in figure four has been 300mv.
Fig. 5 is the timing diagram of some signals in Fig. 3, further describes third level drive circuit in the hopping edge of signal
Increase the voltage difference on output line.First group of signal 210 in Fig. 5 is that rail arrives as first group of signal 210 in Fig. 4
The oscillogram of rail differential input signal.The 6th group of waveform 220 is that the 5th group of waveform 216 is electric plus third level driving in Fig. 4 in Fig. 5
The output primary differential signal sub-signal OUT_N 102 and OUT_P 104 that the Signal averaging that road 30 exports obtains.Second group of ripple in Fig. 5
Shape 214 is the waveform for the signal that first group of rail-to-rail differential input signal obtains after inverter, and signal 2 ' is signal 2
The signal waveforms obtained after the output of phase inverter 170, signal 0 ' are the letters that signal 0 obtains after the output of phase inverter 176
Number oscillogram.The 3rd group of signal 212 is identical with the 3rd group of signal 212 in Fig. 4 in Fig. 5, represents rail-to-rail differential input signal
IN_P 2 and IN_N 0 corresponds to the oscillogram of obtained signal 3 and 1 respectively after the delay time T of delay circuit 15.4th group
Waveform shows the pulse signal PP exported in figure three with door 172 oscillogram.When PP is Vdd, nmos pass transistor T30 is beaten
Open, signal 34 can pull down OUT_P 104, signal level is become more negative.Equally, when PP is Vdd, PP ' is 0, PMOS crystal
Pipe T32 is opened, and signal 36 can pull up OUT_N 102, make signal level become to correct.5th group of waveform shows anti-phase in figure three
The oscillogram for the pulse signal NP ' that device 164 exports.When NP ' is 0, PMOS transistor T20 is opened, and signal 38 can pull up OUT_P
104, make signal level become to correct.Equally, when NP is Vdd, nmos pass transistor T22 is opened, and signal 32 can pull down OUT_N
102, signal level is become more negative.
6th group of waveform 220 is small-signal differential output signal, is rail in first group of waveform 210 corresponding to OUT_N 102
It is rail-to-rail input signal IN_N 0 in first group of waveform 210 corresponding to OUT_P 104 to rail input signal IN_P 2.Contrast
The 6th group of waveform of the signal in the 5th group of waveform 216 and Fig. 5 of the signal on output line on expression output line is represented in Fig. 4
220, it can be seen that two groups of waveforms are similar, except in the τ of delay period 208 and 209, the level of signal is enhanced
50mv, as illustrated in the drawing the 950mv from 276 bring up to 332 1000mv；Or 50mv is lowered by, as illustrated in the drawing
350mv from 284 brings up to 352 300mv.Circuit has phase to small-signal differential output signal OUT_N 102 and OUT_P 104
Same exercising result.
One embodiment of one differential clocks drive circuit for being applied to differential clocks tree：Differential clocks drive circuit
Input signal is rail-to-rail differential input signal, and output signal is small-signal differential clock signal.Small-signal differential clock signal
It is exaggerated in signal saltus step, passes through the signal quality after interconnection line when receiving terminal is received to improve signal.Difference
Clock driver circuit includes：Current mirroring circuit with reference current source input, the first stage drive circuit, second level driving electricity
Road, output are connected to the delay circuit of the second stage drive circuit input, third level drive circuit, and output is connected to third level driving
The pulse signal generator circuit of circuit input, third level drive circuit are produced corresponding by the control of pulse signal generator circuit
Pulse signal, and an adder, adder by the first stage drive circuit, the second stage drive circuit and third level drive circuit
Output signal is added together, and forms small-signal differential output signal.
Claims (4)
1. differential clocks drive circuit, it is characterised in that including following part：
First stage drive circuit (10), it inputs termination differential voltage input, and it exports termination adder；
Adder (100), its output end is as final output end；
Delay circuit (15), it inputs termination differential voltage input；
Second stage drive circuit (20), it inputs the output end of termination delay circuit (15), and it exports termination adder；
Impulse generator (25), its first input interface connect the output end of delay circuit (15), and its second input interface connects difference
Voltage input end, it exports the input of termination third level drive circuit (30)；
Third level drive circuit (30), it exports termination adder；
First stage drive circuit (10), the second stage drive circuit (20) and third level drive circuit (30) are all used to amplify difference letter
Number.
2. differential clocks drive circuit as claimed in claim 1, it is characterised in that the first stage drive circuit (10) bag
Include：
The first PMOS (T1) and the second NMOS tube (T2) of series connection, being connected in series for the two a little connect the first driving output line
(110), the grid of the two connects the first input point as the first stage drive circuit (10) input；
The 3rd PMOS (T3) and the 5th NMOS tube (T5) of series connection, being connected in series for the two a little connect the second driving output line
(108), the grid of the two connects the second input point as the first stage drive circuit (10) input；
The source electrode of first PMOS (T1) and the source electrode of the 3rd PMOS (T3) connect, the source electrode and the 5th of the second NMOS tube (T2)
The source electrode of NMOS tube (T5) connects.
3. differential clocks drive circuit as claimed in claim 1, it is characterised in that the second stage drive circuit (20) bag
Include：
The tenth PMOS (T10) and the 11st NMOS tube (T11) of series connection, being connected in series for the two a little connect the first driving output line
(110), the grid of the two connects the second input point as the second stage drive circuit (20) input；
The 12nd PMOS (T12) and the 13rd NMOS tube (T13) of series connection, being connected in series for the two a little connect the second driving output
Line (108), the first input point that the grid of the two connects as the second stage drive circuit (20) input；
The source electrode of tenth PMOS (T10) and the source electrode of the 12nd PMOS (T12) connect, the source of the 11st NMOS tube (T11)
The source electrode of pole and the 13rd NMOS tube (T13) connects.
4. differential clocks drive circuit as claimed in claim 1, it is characterised in that
The third level drive circuit (30) includes：
20th PMOS (T20), it is arranged between high level end and the second driving output line (108)；
32nd PMOS (T32), it is arranged between high level end and the first driving output line (110)；
30th NMOS tube (T30), it is arranged between ground level end and the second driving output line (108)；
22nd NMOS tube (T22), it is arranged between ground level end and the first driving output line (110)；
First input point of the grid of 30th NMOS tube (T30) as third level drive circuit (30) input, passes through one
Phase inverter is connected with the grid of the 32nd PMOS (T32)；
Second input point of the grid of 22nd NMOS tube (T22) as third level drive circuit (30) input, passes through one
Individual phase inverter is connected with the grid of the 20th PMOS (T20).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710574979.7A CN107612527A (en) | 2017-07-14 | 2017-07-14 | Differential clocks drive circuit |
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| CN201710574979.7A CN107612527A (en) | 2017-07-14 | 2017-07-14 | Differential clocks drive circuit |
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| CN107612527A true CN107612527A (en) | 2018-01-19 |
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| CN112399662A (en) * | 2019-08-13 | 2021-02-23 | 联咏科技股份有限公司 | LED driving device and LED driver |
| CN112571964A (en) * | 2019-09-30 | 2021-03-30 | 精工爱普生株式会社 | Liquid ejecting apparatus and driving circuit |
| CN118316402A (en) * | 2024-06-06 | 2024-07-09 | 厦门元顺微电子技术有限公司 | High-side current detection amplifier with positive and negative common mode input range |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112399662A (en) * | 2019-08-13 | 2021-02-23 | 联咏科技股份有限公司 | LED driving device and LED driver |
| CN112399662B (en) * | 2019-08-13 | 2023-03-24 | 联咏科技股份有限公司 | Light emitting diode driving device and light emitting diode driver |
| CN112571964A (en) * | 2019-09-30 | 2021-03-30 | 精工爱普生株式会社 | Liquid ejecting apparatus and driving circuit |
| CN112571964B (en) * | 2019-09-30 | 2022-07-22 | 精工爱普生株式会社 | Liquid ejecting apparatus and driving circuit |
| CN118316402A (en) * | 2024-06-06 | 2024-07-09 | 厦门元顺微电子技术有限公司 | High-side current detection amplifier with positive and negative common mode input range |
| CN118316402B (en) * | 2024-06-06 | 2024-09-03 | 厦门元顺微电子技术有限公司 | High-side current detection amplifier with positive and negative common mode input range |
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Application publication date: 20180119 |