本揭露提供了數個不同的實施方法或實施例，可用於實現本發明的不同特徵。為簡化說明起見，本揭露也同時描述了特定零組件與佈置的範例。請注意提供這些特定範例的目的僅在於示範，而非予以任何限制。舉例而言，在以下說明第一特徵如何在第二特徵上或上方的敘述中，可能會包括某些實施例，其中第一特徵與第二特徵為直接接觸，而敘述中也可能包括其他不同實施例，其中第一特徵與第二特徵中間另有其他特徵，以致於第一特徵與第二特徵並不直接接觸。此外，本揭露中的各種範例可能使用重複的參考數字和/或文字註記，以使文件更加簡單化和明確，這些重複的參考數字與註記不代表不同的實施例與配置之間的關聯性。 另外，本揭露在使用與空間相關的敘述詞彙，如“在...之下”、“低”、“下”、“上方”、"上"、“在…之上”及類似詞彙時，為便於敘述，其用法均在於描述圖示中一個元件或特徵與另一個（或多個）元件或特徵的相對關係。除了圖示中所顯示的角度方向外，這些空間相對詞彙也用來描述該裝置在使用中以及操作時的可能角度和方向。該裝置的角度方向可能不同（旋轉90度或其它方位），而在本揭露所使用的這些空間相關敘述可以同樣方式加以解釋。 在本文中所使用的“第一”、“第二”、“第三”以及“第四”語詞係描述各種元件、組件、區域、層、以及/或區段，這些元件、組件、區域、層、以及/或區段應不受限於這些語詞。這些語詞可僅用於一元件、組件、區域、層、或區段與另一元件、組件、區域、層、或區段。除非內文中清楚指明，否則當於本文中使用例如“第一”、“第二”、“第三”以及“第四”語詞時，並非意指序列或順序。。 本揭露所描述的晶片測試基座可以降低晶片在進行測試時受損的風險，進而提升測試製程的良率。 參閱第1圖與第2圖。第1圖繪示本揭露之一實施例之晶片測試基座的分解示意圖，第2圖繪示本實施例之晶片測試基座的剖面示意圖，其中受限於繪示方向及便於說明起見，部分元件未繪示於部分圖式中。如第1圖與第2圖所示，本實施例之晶片測試基座1包括本體部10、容置部20、複數個通孔12、複數個探針30以及至少一彈性元件32。本體部10之上表面10U具有一凹槽10C，經配置用以放置容置部20。本體部10係由一第一絕緣材料例如塑膠材料所形成。在一或多個實施例中，凹槽10C之形狀與尺寸實質上與容置部20的形狀與尺寸相對應，藉此當容置部20置放於凹槽10C時可與凹槽10C的內壁緊密接合。在一或多個實施例中，凹槽10的內壁與上表面10U實質上垂直，但不以此為限。容置部20可設置於本體部10之凹槽10C內，且容置部20具有一底部20B，以及一容置空間20A位於底部20B之上方且經配置用以容置一待測晶片50。容置部20係由一第二絕緣材料例如塑膠材料所形成，且本體部10的第一絕緣材料與容置部20的第二絕緣材料可使用相同或不同的絕緣材料所形成。此外，在選擇容置部20及/或本體部10的材料時，除了考量絕緣特性之外，還需考量其靜電消散能力，以避免待測晶片50在電性測試的過程中被晶片測試基座1內部累積的靜電荷所破壞。在一或多個實施例中，容置部20及/或本體部10的靜電消散能力可藉由本揭露之另一實施例所揭示之判定方法所量測出。 在一或多個實施例中，容置空間20A可具有一導向側壁20L經配置用以引導待測晶片50，以及一定位側壁20M經配置用以固定待測晶片50。舉例而言，導向側壁20L可與容置部20的上表面20U連接並為向外傾斜之側壁，藉此可將待測晶片50引導至待測位置的上方。定位側壁20M位於導向側壁20L下方並可與導向側壁20L連接。定位側壁20M的角度可較導向側壁20L的傾斜角度更大，例如定位側壁20M可與容置部20的上表面20U實質上垂直，藉此待測晶片50在經由導向測壁20L引導至定位側壁20M後可被定位側壁20M定位在容置空間20A內並位於容置部20的底部20B上。 各通孔12分別貫穿本體部10與容置部20。通孔12的數目及位置係與待測晶片50的電性端點(例如錫球)52的數目及位置對應，且各通孔12於容置部20之開口處具有一定位槽12A，經配置用以定位電性端點52。在一或多個實施例中，定位槽12A具有導向側壁，例如向外傾斜的側壁，用以引導電性端點52以與對應之探針30對準。在本實施例中，容置部20的底部20B實質上為平坦部，且所有的定位槽12A實質上係位於同一平面上。探針30分別設置於對應的通孔12內，其中探針30之一端點301係突出至本體部10的凹槽10C內，而其另一端點302則突出於本體部10的下表面10B。在一或多個實施例中，探針30包括彈簧探針(pogo pin)，但不以此為限。彈性元件32設置於本體部10與容置部20之間，以提供彈性支撐。在一或多個實施例中，彈性元件32包括彈簧(spring)，但不以此為限。容置部20可藉由第一固定元件22固定於本體部10之上，其中第一固定元件22係限制容置部20自凹槽10C的上部脫離，但允許容置部20下壓而接近凹槽10C的底部。舉例而言，第一固定元件22可為螺栓(bolt)或螺絲(screw)，可鎖固於本體部10之螺孔10X內，且螺栓頭延伸至容置部20上方以限制容置部20向上移動。 本實施例之晶片測試基座1可進一步另包括一底座40，連接於本體部10之下表面10B，且通孔12可進一步貫穿底座40。在一或多個實施例中，底座40可藉由第二固定元件42固定於本體部10之上，其中第二固定元件42可為例如螺栓、螺絲或其它類似元件。 在一或多個實施例中，晶片測試基座1可固定於一測試電路板(圖未示)上，其中測試電路板係設置於底座40之下方並與探針30之另一端點302電性連接。在一或多個實施例中，晶片測試基座1可藉由第三固定元件44固定於測試電路板上，其中第三固定元件44可為例如螺栓、螺絲或其它類似元件。 參閱第3A圖、第3B圖與第3C圖，並一併參考第1圖與第2圖。第3A圖、第3B圖與第3C圖為第2圖之區域X的局部放大示意圖，其中第3A圖繪示於一預備模式下之晶片測試基座的示意圖，第3B圖繪示於一待測模式下之晶片測試基座的示意圖，且第3C圖繪示於一待測模式下之晶片測試基座的示意圖。如第3A圖所示，在預備模式下，當將待測晶片50放置在容置空間20A內時，會受到導向側壁20L的引導至待測位置的上方，接著待測晶片50會沿著定位側壁20M下移而定位在容置空間20A內並位於底部20B上方。如第3B圖所示，當待測晶片50下移至容置空間20A內後，電性端點52會位於定位槽12A的開口處，此時電性端點52會沿著定位槽12A的導向側壁滑入定位槽12A內，以與對應之探針30對準，且此時探針30之端點301與電性端點52未接觸。在電性端點52接觸定位槽12A時，彈性元件32可以提供彈性緩衝作用，以減少電性端點52受損風險。如第3C圖所示，在測試模式下，可對容置部20提供一下壓力以使容置部20朝向本體部10的凹槽10C的底部移動，此時待測晶片50會隨著容置部20向下移動而使得電性端點52與對應的探針30的端點301接觸，藉此測試電路板所送出的測試訊號可經由探針30傳送至待測晶片50的電性端點52以進行電性測試，判定待測晶片50是否為電性正常的良品。電性測試結束之後，移除對容置部20的下壓力，此時彈性元件32的彈力會將容置部20上移而使得電性端點52與探針30的端點301分離，接著可載出待測晶片50並再載入另一待測晶片50進行電性測試。 參閱第4圖至第6圖。第4圖繪示本揭露之另一實施例之晶片測試基座的示意圖，第5圖繪示本揭露之另一實施例之晶片測試基座之容置部的上視示意圖，第6圖為第5圖之區域Y的局部放大示意圖。如第4圖至第6圖所示，在本實施例中，晶片測試基座2之容置部20的底部20B具有第一區域201與第二區域202，且第一區域201內之定位槽12A係向上突出於第二區域202內之定位槽12A。在本實施例中，第二區域202係環繞第一區域201，例如第一區域201為一矩形區域，而第二區域202為一環形區域，但不以此為限。第一區域201相對該第二區域的設置位置可視定位效果而改變，且第一區域201與第二區域202的形狀、面積、數目及其涵蓋的定位槽12A的數量亦可視定位效果或其它因素加以變更。 由於第一區域201內之定位槽12A係向上突出於第二區域202內之定位槽12A，因此在待測模式下，待測晶片50的一部分的電性端點52會位於第一區域201的定位槽12A內並抵接定位槽12A的導向側壁，而待測晶片50的另一部分的電性端點52不會與位於第二區域202的定位槽12A接觸。也就是說，位於第一區域201的定位槽12A會實際發揮定位功能，而位於第二區域202的定位槽12A則作為緩衝空間。在本實施例中，第一區域201內之定位槽12A向上突出於第二區域202內之定位槽12A的配置可使得在待測模式下僅有一部分的電性端點52與容置部20接觸，因此可以降低電性端點52受損的風險。在測試模式下，當容置部20受下壓力而向下移動後，位於第一區域201與第二區域202的電性端點52均可與對應的探針30的端點301接觸而進行電性測試。 參閱第7圖。第7圖繪示本揭露之另一實施例之晶片測試基座的示意圖。如第7圖所示，在本實施例之晶片測試基座3，容置部20的底部20B的第一區域201內之定位槽12A係向上突出於第二區域202內之定位槽12A。與第4圖至第6圖之實施例不同之處在於，本實施例之第一區域201係環繞第二區域202。 參閱第8圖。第8圖為本揭露之一實施例之晶片測試基座的靜電消散能力的判定方法。本實施例之晶片測試基座包括主體部及設置於主體部上的容置部，其詳述元件及相關特徵如前述第1圖至第7圖之實施例所揭示，在此不再贅述。如第8圖所示，本實施例之晶片測試基座的靜電消散能力的判定方法100包括下列步驟： 步驟102：對晶片測試基座之容置部施加一饋入電壓； 步驟104：量測晶片測試基座在施加饋入電壓後之一第一電壓； 步驟106：量測晶片測試基座在施加饋入電壓後之一預定時間的一第二電壓； 步驟108：計算第二電壓與第一電壓之一比值； 步驟110：比較該比值是否小於一預定比值； 步驟112：當該比值小於預定比值，判定晶片測試基座具有靜電消散能力；以及 步驟114：當該比值不小於預定比值，判定晶片測試基座不具有靜電消散能力。 在一或多個實施例中，對晶片測試基座施加的饋入直流電壓介於約-1 KV至約+1 KV之間；預定時間介於約3秒至約5秒；預定比值介於約10%至約15%之間。舉例而言，由於晶片測試基座的電阻值約在10^10 ohm至10^13 ohm之間，因此當+1KV的饋入電壓饋入晶片測試基座後因該電阻值而產生壓降(約降至350V至550V之間，此電壓值即第一電壓)，且在預定時間約3秒內，該第一電壓降至50V(即第二電壓)以下，使該預定比值約介於10%至約15%之間。換言之，當對晶片測試基座施加的饋入電壓為+1KV時，且此時量測到晶片測試基座的第一電壓若在+350V至+550V之間，則在經過3秒之後，若對晶片測試基座所量測出的第二電壓(放電電壓)小於+50V，則可判定晶片測試基座具有良好的靜電消散能力，反之若對晶片測試基座所量測出的放電電壓大於+50V，則可判定晶片測試基座具有不良的靜電消散能力。本揭露之靜電消散能力的判定方法除了應用在晶片測試基座或其組件例如容置部及/或本體部之外，可應用在其它需考量靜電消散能力之裝置、治具或周邊產品上。 值得說明的是，上述晶片測試基座的靜電消散能力的判定方法所設定的饋入電壓、預定時間及預定比值等參數可視待測晶片的抗靜電能力、晶片測試基座的電阻值及其它考量而加以調整，而不以上述實施例所揭示的數值為限。 如本文中所使用，詞語「近似地」、「實質上」、「實質的」及「約」用以描述及說明小變化。當與事件或情形結合使用時，該等詞語可指事件或情形明確發生之情況及事件或情形極近似於發生之情況。舉例而言，當結合數值使用時，該等詞語可指小於或等於彼數值之±10%的變化範圍，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%。舉另一例來說，「實質正交」可指一變化範圍小於或等於90°的±10% (諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%)。 另外，有時在本文中按範圍格式呈現量、比率及其他數值。應理解，此類範圍格式係為便利及簡潔起見而使用，且應靈活地理解為不僅包括明確指定為範圍極限之數值，且亦包括涵蓋體於彼範圍內之所有個別數值或子範圍，就如同明確指定每一數值及子範圍一般。 儘管已參考本發明之特定實施例描述並說明本發明，但此等描述及說明並不限制本發明。熟習此項技術者應理解，在不脫離如由所附申請專利範圍界定的本發明之真實精神及範疇的情況下，可作出各種改變且可用等效物取代。說明可不一定按比例繪製。歸因於製程及容限，本發明中之藝術再現與實際裝置之間可存在區別。可存在並未特定說明的本發明之其他實施例。應將本說明書及圖式視為說明性而非限制性的。可作出修改，以使特定情形、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有該等修改均意欲處於此處隨附之申請專利範圍之範疇內。儘管已參看按特定次序執行之特定操作描述本文中所揭示之方法，但應理解，在不脫離本發明之教示的情況下，可組合、再分或重新定序此等操作以形成等效方法。因此，除非本文中具體指示，否則操作之次序及分組並非對本發明之限制。The disclosure provides several different implementations or embodiments that can be used to implement different features of the invention. For simplicity of explanation, the present disclosure also describes examples of specific components and arrangements. Please note that these specific examples are provided for demonstration purposes only and are not intended to be limiting. For example, in the following description of how the first feature is on or above the second feature, certain embodiments may be included, where the first feature is in direct contact with the second feature, and the description may include other differences Embodiments wherein there are other features in between the first feature and the second feature such that the first feature is not in direct contact with the second feature. In addition, various examples in the disclosure may use repeated reference numerals and/or text annotations to make the document more simplistic and clear, and such repeated reference numerals and annotations do not represent an association between different embodiments and configurations. In addition, the present disclosure uses spatially related narrative vocabulary, such as "under", "low", "lower", "above", "upper", "above", and the like, For ease of description, the usage is to describe the relative relationship of one element or feature to another element or feature. In addition to the angular orientations shown in the figures, these spatial relative terms are also used to describe the possible angles and directions of the device in use and during operation. The angular orientation of the device may vary (rotating 90 degrees or other orientations), and the spatially related descriptions used in this disclosure may be interpreted in the same manner. The terms "first", "second", "third", and "fourth" as used herein are used to describe various elements, components, regions, layers, and/or sections, such elements, components, regions, Layers and/or sections should not be limited to these terms. The words may be used in a single element, component, region, layer, or section and another element, component, region, layer, or section. The terms "first," "second," "third," and "fourth" are used herein to mean a sequence or order unless the context clearly dictates otherwise. . The wafer test pedestal described in the present disclosure can reduce the risk of damage to the wafer during testing, thereby increasing the yield of the test process. See Figures 1 and 2. 1 is a schematic exploded view of a wafer test pedestal according to an embodiment of the present disclosure, and FIG. 2 is a cross-sectional view showing the wafer test pedestal of the embodiment, which is limited by the direction of the drawing and is convenient for explanation. Some of the elements are not shown in the partial drawings. As shown in FIGS. 1 and 2, the wafer test susceptor 1 of the present embodiment includes a body portion 10, a accommodating portion 20, a plurality of through holes 12, a plurality of probes 30, and at least one elastic member 32. The upper surface 10U of the body portion 10 has a recess 10C configured to place the receiving portion 20. The body portion 10 is formed of a first insulating material such as a plastic material. In one or more embodiments, the shape and size of the recess 10C substantially corresponds to the shape and size of the accommodating portion 20, thereby being compatible with the recess 10C when the accommodating portion 20 is placed in the recess 10C. The inner wall is tightly joined. In one or more embodiments, the inner wall of the recess 10 is substantially perpendicular to the upper surface 10U, but is not limited thereto. The accommodating portion 20 is disposed in the recess 10C of the body portion 10, and the accommodating portion 20 has a bottom portion 20B, and an accommodating space 20A is located above the bottom portion 20B and configured to receive a wafer 50 to be tested. The accommodating portion 20 is formed of a second insulating material such as a plastic material, and the first insulating material of the body portion 10 and the second insulating material of the accommodating portion 20 may be formed using the same or different insulating materials. In addition, in selecting the material of the accommodating portion 20 and/or the body portion 10, in addition to considering the insulating properties, the static dissipating capability of the immersed portion 20 is also considered to prevent the wafer 50 to be tested from being tested by the wafer during the electrical testing process. The static charge accumulated inside the seat 1 is destroyed. In one or more embodiments, the electrostatic dissipation capability of the housing portion 20 and/or the body portion 10 can be measured by a determination method disclosed in another embodiment of the present disclosure. In one or more embodiments, the accommodating space 20A can have a guiding sidewall 20L configured to guide the wafer 50 to be tested, and a positioning sidewall 20M configured to fix the wafer 50 to be tested. For example, the guiding sidewall 20L can be connected to the upper surface 20U of the accommodating portion 20 and be an outwardly inclined side wall, whereby the wafer to be tested 50 can be guided above the position to be tested. The positioning side wall 20M is located below the guide side wall 20L and is connectable to the guide side wall 20L. The angle of the positioning side wall 20M may be larger than the inclination angle of the guiding side wall 20L. For example, the positioning side wall 20M may be substantially perpendicular to the upper surface 20U of the accommodating portion 20, whereby the wafer to be tested 50 is guided to the positioning side wall via the guiding wall 20L. After 20M, the positioning side wall 20M can be positioned in the accommodating space 20A and located on the bottom portion 20B of the accommodating portion 20. Each of the through holes 12 penetrates through the body portion 10 and the receiving portion 20 , respectively. The number and position of the through holes 12 correspond to the number and position of the electrical end points (for example, the solder balls) 52 of the wafer 50 to be tested, and each of the through holes 12 has a positioning groove 12A at the opening of the receiving portion 20, The configuration is used to locate the electrical endpoint 52. In one or more embodiments, the locating slot 12A has a guiding sidewall, such as an outwardly sloping sidewall, for guiding the electrical end point 52 to align with the corresponding probe 30. In this embodiment, the bottom portion 20B of the accommodating portion 20 is substantially a flat portion, and all of the positioning grooves 12A are substantially in the same plane. The probes 30 are respectively disposed in the corresponding through holes 12, wherein one end 301 of the probe 30 protrudes into the recess 10C of the body portion 10, and the other end point 302 protrudes from the lower surface 10B of the body portion 10. In one or more embodiments, the probe 30 includes a pogo pin, but is not limited thereto. The elastic member 32 is disposed between the body portion 10 and the receiving portion 20 to provide elastic support. In one or more embodiments, the elastic member 32 includes a spring, but is not limited thereto. The accommodating portion 20 can be fixed on the body portion 10 by the first fixing member 22, wherein the first fixing member 22 restricts the accommodating portion 20 from being detached from the upper portion of the groove 10C, but allows the accommodating portion 20 to be pressed down and close to The bottom of the groove 10C. For example, the first fixing component 22 can be a bolt or a screw, can be locked in the screw hole 10X of the body portion 10, and the bolt head extends above the accommodating portion 20 to limit the accommodating portion 20 Move up. The wafer test pedestal 1 of the present embodiment may further include a base 40 connected to the lower surface 10B of the body portion 10, and the through hole 12 may further penetrate the base 40. In one or more embodiments, the base 40 can be secured to the body portion 10 by a second securing member 42, wherein the second securing member 42 can be, for example, a bolt, a screw, or the like. In one or more embodiments, the wafer test pedestal 1 can be mounted on a test circuit board (not shown), wherein the test circuit board is disposed below the base 40 and electrically coupled to the other end 302 of the probe 30. Sexual connection. In one or more embodiments, the wafer test pedestal 1 can be secured to the test circuit board by a third securing element 44, which can be, for example, a bolt, a screw, or the like. Refer to Figures 3A, 3B, and 3C, and refer to Figures 1 and 2 together. 3A, 3B, and 3C are partial enlarged views of the region X of FIG. 2, wherein FIG. 3A is a schematic view of the wafer test pedestal in a standby mode, and FIG. 3B is shown in FIG. A schematic diagram of a wafer test susceptor in a test mode, and FIG. 3C is a schematic view of a wafer test pedestal in a mode to be tested. As shown in FIG. 3A, in the standby mode, when the wafer to be tested 50 is placed in the accommodating space 20A, it is guided by the guiding sidewall 20L to the position to be tested, and then the wafer 50 to be tested is positioned along the positioning. The side wall 20M is moved down and positioned in the accommodating space 20A and above the bottom portion 20B. As shown in FIG. 3B, after the wafer 50 to be tested is moved down into the accommodating space 20A, the electrical end point 52 is located at the opening of the positioning slot 12A, and the electrical end point 52 is along the positioning slot 12A. The guide side wall slides into the positioning groove 12A to align with the corresponding probe 30, and at this time the end point 301 of the probe 30 is not in contact with the electrical end point 52. When the electrical end point 52 contacts the positioning slot 12A, the resilient member 32 can provide an elastic cushioning action to reduce the risk of damage to the electrical end point 52. As shown in FIG. 3C, in the test mode, the accommodating portion 20 can be biased to move the accommodating portion 20 toward the bottom of the recess 10C of the body portion 10, and the wafer 50 to be tested is accommodated. The portion 20 moves downward to bring the electrical end point 52 into contact with the end point 301 of the corresponding probe 30, whereby the test signal sent by the test circuit board can be transmitted via the probe 30 to the electrical end point of the wafer 50 to be tested. 52 to perform an electrical test to determine whether the wafer 50 to be tested is a good electrical product. After the end of the electrical test, the downward pressure on the accommodating portion 20 is removed, at which time the elastic force of the elastic member 32 moves the accommodating portion 20 upward to separate the electrical end point 52 from the end point 301 of the probe 30, and then The wafer to be tested 50 can be loaded and loaded into another wafer 50 to be tested for electrical testing. See Figures 4 through 6. 4 is a schematic view of a wafer test pedestal according to another embodiment of the present disclosure, and FIG. 5 is a top view of the accommodating portion of the wafer test pedestal according to another embodiment of the present disclosure. FIG. A partially enlarged schematic view of a region Y of Fig. 5. As shown in FIG. 4 to FIG. 6, in the present embodiment, the bottom portion 20B of the receiving portion 20 of the wafer test susceptor 2 has a first region 201 and a second region 202, and a positioning groove in the first region 201 The 12A protrudes upward from the positioning groove 12A in the second region 202. In this embodiment, the second area 202 is surrounded by the first area 201. For example, the first area 201 is a rectangular area, and the second area 202 is an annular area, but is not limited thereto. The position of the first region 201 relative to the second region may be changed according to the positioning effect, and the shape, the area, the number of the first region 201 and the second region 202, and the number of the positioning slots 12A covered therein may also be visually positioned or other factors. Change it. Since the positioning slot 12A in the first region 201 protrudes upwardly from the positioning slot 12A in the second region 202, in the mode to be tested, the electrical end point 52 of a portion of the wafer 50 to be tested may be located in the first region 201. The positioning end wall of the positioning groove 12A is abutted in the positioning groove 12A, and the electrical end point 52 of the other portion of the wafer 50 to be tested is not in contact with the positioning groove 12A located in the second area 202. That is to say, the positioning groove 12A located in the first area 201 actually functions as a positioning function, and the positioning groove 12A located in the second area 202 serves as a buffer space. In this embodiment, the positioning slot 12A in the first region 201 protrudes upwardly from the positioning slot 12A in the second region 202, so that only a part of the electrical end point 52 and the receiving portion 20 are in the mode to be tested. Contact, thus reducing the risk of damage to the electrical end point 52. In the test mode, after the accommodating portion 20 is moved downward by the downward pressure, the electrical end points 52 of the first region 201 and the second region 202 can be contacted with the end points 301 of the corresponding probes 30. Electrical test. See Figure 7. FIG. 7 is a schematic diagram of a wafer test pedestal according to another embodiment of the present disclosure. As shown in FIG. 7, in the wafer test susceptor 3 of the present embodiment, the positioning groove 12A in the first region 201 of the bottom portion 20B of the accommodating portion 20 protrudes upwardly from the positioning groove 12A in the second region 202. The difference from the embodiment of FIGS. 4 to 6 is that the first region 201 of the present embodiment surrounds the second region 202. See Figure 8. FIG. 8 is a method for determining the static dissipative capability of the wafer test pedestal according to an embodiment of the present disclosure. The wafer test pedestal of the present embodiment includes a main body portion and a accommodating portion disposed on the main body portion. The detailed description of the components and related features are disclosed in the foregoing embodiments of FIGS. 1 to 7 and will not be further described herein. As shown in FIG. 8, the method 100 for determining the static dissipative capability of the wafer test pedestal of the present embodiment includes the following steps: Step 102: Apply a feed voltage to the receiving portion of the wafer test pedestal; Step 104: Measure The wafer test pedestal is applied to the first voltage after the voltage is applied; Step 106: Measure the second voltage of the wafer test pedestal at a predetermined time after the application of the voltage is applied; Step 108: Calculate the second voltage and the first voltage a ratio of a voltage; step 110: comparing whether the ratio is less than a predetermined ratio; step 112: determining that the wafer test pedestal has a static dissipative capability when the ratio is less than a predetermined ratio; and step 114: when the ratio is not less than a predetermined ratio, It is determined that the wafer test pedestal does not have static dissipative capability. In one or more embodiments, the feed DC voltage applied to the wafer test pedestal is between about -1 KV and about +1 KV; the predetermined time is between about 3 seconds and about 5 seconds; the predetermined ratio is between Between about 10% and about 15%. For example, since the resistance value of the wafer test pedestal is between about 10^10 ohms and 10^13 ohms, a voltage drop occurs due to the resistance value when the +1KV feed voltage is fed into the wafer test pedestal ( Between approximately 350V and 550V, the voltage value is the first voltage), and within about 3 seconds of the predetermined time, the first voltage drops below 50V (ie, the second voltage), so that the predetermined ratio is about 10 % to about 15%. In other words, when the feed voltage applied to the wafer test pedestal is +1 KV, and the first voltage of the wafer test pedestal is measured to be between +350 V and +550 V, then after 3 seconds, If the second voltage (discharge voltage) measured by the wafer test pedestal is less than +50V, it can be determined that the wafer test pedestal has good static dissipating capability, and if the measured discharge voltage of the wafer test pedestal is greater than +50V, it can be determined that the wafer test pedestal has poor static dissipative capability. The method for determining the static dissipative capability of the present disclosure can be applied to other devices, jigs, or peripheral products that require electrostatic dissipative capabilities in addition to the wafer test pedestal or components thereof such as the accommodating portion and/or the body portion. It should be noted that the parameters such as the feed voltage, the predetermined time, and the predetermined ratio set by the method for determining the static dissipative capability of the wafer test pedestal may be determined by the antistatic capability of the wafer to be tested, the resistance value of the wafer test pedestal, and other considerations. The adjustment is not limited to the numerical values disclosed in the above embodiments. As used herein, the terms "approximately", "substantially", "substantial" and "about" are used to describe and describe minor variations. When used in connection with an event or circumstance, the terms may refer to the circumstances in which the event or circumstance occurs explicitly and the event or circumstance is very similar to the occurrence. For example, when used in connection with a value, the terms may mean a range of variation less than or equal to ±10% of the value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, Less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For another example, "substantially orthogonal" may mean ±10% of a range of variation less than or equal to 90° (such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than Or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%). In addition, quantities, ratios, and other values are sometimes presented in a range format herein. It is to be understood that the scope of the present invention is to be construed as being inclusive and Just as it is explicitly specified for each value and sub-range. While the invention has been described and illustrated with reference to the specific embodiments of the invention It will be understood by those skilled in the art that various changes can be made and substituted by equivalents without departing from the true spirit and scope of the invention as defined by the appended claims. The description may not necessarily be drawn to scale. Due to the process and tolerance, there may be differences between the artistic reproduction and the actual device in the present invention. There may be other embodiments of the invention that are not specifically described. The description and drawings are to be regarded as illustrative and not limiting. Modifications may be made to adapt a particular situation, material, material composition, method or process to the objectives, spirit and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to the specific operations performed in a particular order, it is understood that the operations can be combined, sub-divided, or re-sequenced to form an equivalent method without departing from the teachings of the present invention. . Therefore, the order of operations and groupings are not limiting of the invention unless specifically indicated herein.