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TW201812932A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW201812932A
TW201812932A TW105128137A TW105128137A TW201812932A TW 201812932 A TW201812932 A TW 201812932A TW 105128137 A TW105128137 A TW 105128137A TW 105128137 A TW105128137 A TW 105128137A TW 201812932 A TW201812932 A TW 201812932A
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Taiwan
Prior art keywords
substrate
electronic package
item
patent application
scope
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TW105128137A
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English (en)
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TWI601219B (zh
Inventor
林長甫
姚進財
余國華
黃富堂
Original Assignee
矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW105128137A priority Critical patent/TWI601219B/zh
Priority to CN201610836468.3A priority patent/CN107785344A/zh
Priority to US15/372,638 priority patent/US10510720B2/en
Application granted granted Critical
Publication of TWI601219B publication Critical patent/TWI601219B/zh
Publication of TW201812932A publication Critical patent/TW201812932A/zh

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Abstract

一種電子封裝件，係包括：第一基板、設於該第一基板上之第一電子元件、藉由第一與第二導電元件堆疊於該第一基板上並藉由結合層結合至該第一電子元件上之第二基板、以及形成於該第一基板與第二基板之間的第一封裝層，藉由不同構造之第一導電元件與第二導電元件支撐該第二基板，以於模壓過程中，避免該第一封裝層之模流產生向上推擠力，而造成該第二基板發生破裂。本發明復提供該電子封裝件之製法。

Description

電子封裝件及其製法
本發明係關於一種封裝結構，特別是關於一種電子封裝件及其製法。
隨著近年來可攜式電子產品的蓬勃發展，各類相關產品亦逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢發展，為因應此趨勢，半導體封裝業界遂開發各態樣的堆疊封裝(package on package，PoP)技術，以期能符合輕薄短小與高密度的要求。
如第1圖所示，係為習知堆疊式電子封裝件1的剖視示意圖。該電子封裝件1包括兩相疊之第一封裝結構1a與第二封裝結構1b、及黏固該第一封裝結構1a與第二封裝結構1b之封裝膠體13。該第一封裝結構1a係包含第一基板10、以複數導電凸塊110覆晶結合該第一基板10之第一電子元件11(如半導體晶片)、及包覆該些導電凸塊110之底膠111。該第二封裝結構1b係包含第二基板12、以複數導電凸塊140覆晶結合該第二基板12之第二電子元件14(如半導體晶片)、及包覆該些導電凸塊140之底膠 141。該第二基板12藉由銲錫球120支撐且電性連接於該第一基板10上，且該封裝膠體13形成於該第一基板10與第二基板12之間以包覆該些銲錫球120。
惟，習知電子封裝件1中，當該第一基板10與第二基板12堆疊時，經過回銲該些銲錫球120之後，溫度升降所產生的應力會導致該第二基板12局部凹凸不平，使得後續的模壓過程中，該第二基板12之表面無法有效接觸模具表面，導致形成該封裝膠體13之封裝材流入該第一基板10與第二基板12之間時，模流會產生向上推擠力，造成該些銲錫球120與該第二基板12之間發生破裂(crack)，使得電性接觸不良。
再者，該銲錫球120於回銲後之體積及高度之公差大，不僅接點容易產生缺陷，導致電性連接品質不良，而且該銲錫球120所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，導致接點應力(stress)不平衡而容易造成該第一與第二封裝結構1a,1b之間呈傾斜接置，甚至產生接點偏移之問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種電子封裝件，係包括：第一基板；第一電子元件，係設於該第一基板上；第二基板，係藉由複數第一導電元件與第二導電元件堆疊於該第一基板上並藉由結合層結合至該第一電子 元件上，其中，該第一導電元件之構造與該第二導電元件之構造不同；以及第一封裝層，係設於該第一基板與第二基板之間，且令該第一封裝層包覆該第一電子元件、該第一導電元件與該第二導電元件。
本發明復提供一種電子封裝件之製法，係包括：提供第一基板及第二基板，其中，該第一基板上設有第一電子元件；將該第二基板藉由第一導電元件與第二導電元件堆疊於該第一基板上，並使該第二基板藉由結合層結合至該第一電子元件上，且該第一導電元件之構造與該第二導電元件之構造不同；以及形成第一封裝層於該第一基板與第二基板之間，以令該第一封裝層包覆該第一電子元件、該第一導電元件與該第二導電元件。
前述之電子封裝件及其製法中，該第一導電元件與該第二導電元件的數量比例係為1：0.5~1：1.5。
前述之電子封裝件及其製法中，該第一導電元件係為金屬塊，或者，該第一導電元件係具有金屬塊與包覆該金屬塊之導電材。
前述之電子封裝件及其製法中，該第二導電元件係為銲錫凸塊。
前述之電子封裝件及其製法中，該結合層係為薄膜(film)或散熱材。
前述之電子封裝件及其製法中，該第一基板之表面係定義有一置晶區、及環繞該置晶區之第一堆疊區與第二堆疊區，該置晶區係設有該第一電子元件，且該第一堆疊區 與該第二堆疊區係設有複數電性接點，以結合該第一導電元件及/或該第二導電元件，其中，該第一堆疊區之電性接點之密度大於該第二堆疊區之電性接點之密度。
前述之電子封裝件及其製法中，該第一基板具有定位墊。
前述之電子封裝件及其製法中，該第一導電元件與該第二導電元件係交錯排列。
前述之電子封裝件及其製法中，復包括設置支撐件於該第一與第二基板之間。例如，該支撐件未電性連接該第一與第二基板。
前述之電子封裝件及其製法中，復包括設置第二電子元件於該第二基板上。又包括形成第二封裝層於該第二基板上，且該第二封裝層包覆該第二電子元件。
前述之電子封裝件及其製法中，復包括設置封裝件於該第二基板上。
由上可知，本發明之電子封裝件及其製法中，係藉由不同構造之第一導電元件(包含有金屬塊)與第二導電元件支撐該第二基板，經過回銲該些導電元件之後，能分散溫度升降所產生的應力集中，以避免該第二基板發生局部凹凸不平，故相較於習知技術，本發明於模壓過程中，該第二基板之表面可有效接觸模具表面，以避免該第一封裝層之模流產生向上推擠力，而造成該第二基板發生破裂之問題。
再者，藉由該第二基板結合至該第一電子元件上，使 該第二基板與該第一基板之間的距離得以固定，故相較於習知技術，本發明於回銲該些第一與第二導電元件後，該些第一與第二導電元件所構成之接點能維持良好之電性連接品質，且該些第一與第二導電元件所排列成之柵狀陣列之共面性良好，因而接點應力保持平衡而不會造成該第一與第二基板之間呈傾斜接置，以避免產生接點偏移之問題。
1,2,2’,2”‧‧‧電子封裝件
1a‧‧‧第一封裝結構
1b‧‧‧第二封裝結構
10,20‧‧‧第一基板
11,21‧‧‧第一電子元件
110,140,210‧‧‧導電凸塊
111,141‧‧‧底膠
12,22‧‧‧第二基板
120‧‧‧銲錫球
13‧‧‧封裝膠體
14,24‧‧‧第二電子元件
20a,20b‧‧‧第一線路層
200‧‧‧電性接觸墊
201,202,220,221‧‧‧電性接點
203‧‧‧植球墊
22a,22b‧‧‧第二線路層
23‧‧‧第一封裝層
240‧‧‧銲線
241‧‧‧黏著層
25‧‧‧第二封裝層
26‧‧‧封裝件
260‧‧‧載體
261‧‧‧第三電子元件
262‧‧‧封裝體
263,28‧‧‧銲球
27‧‧‧支撐件
270,280‧‧‧金屬塊
271,281‧‧‧導電材
28a‧‧‧第一導電元件
28b‧‧‧第二導電元件
29‧‧‧結合層
30‧‧‧定位墊
S‧‧‧切割路徑
A‧‧‧第一堆疊區
B‧‧‧第二堆疊區
C‧‧‧置晶區
第1圖係為習知堆疊式電子封裝件之剖面示意圖；第2A至2C圖係為本發明電子封裝件之製法之剖面示意圖；其中，第2B’圖係為第2B圖之另一實施例；第2D及2D’圖係為第2C圖之其它實施例之剖面示意圖；第3圖係為本發明之電子封裝件之第一基板之上視示意圖；以及第4圖係為本發明之電子封裝件之第一基板設有第一與第二導電元件之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2C圖係為本發明之電子封裝件2之製法之剖面示意圖。
如第2A圖所示，提供一第一基板20與一第二基板22。該第一基板20上設有至少一第一電子元件21，且該第二基板22下側係形成有複數第一導電元件28a、複數第二導電元件28b與一如薄膜(film)或散熱材之結合層29。
於本實施例中，該第一基板20與第二基板22係為線路板，其分別具有複數第一線路層20a,20b與複數第二線路層22a,22b，該第一線路層20a,20b包含電性接觸墊200、電性接點201,202與植球墊203，且該第二線路層22a,22b包含電性接點220,221。應可理解地，該第一基板20與第二基板22亦可為其它承載晶片之承載件，並不限於上述。
再者，該第一電子元件21係藉由複數導電凸塊210以覆晶方式設於該第一基板20上側之電性接觸墊200上。
又，該第一導電元件28a係形成於該第二基板22下側之電性接點220上，且該第一導電元件28a具有金屬塊280與包覆該金屬塊280之導電材281，亦或該第一導電元件 28a僅為金屬塊280(不含導電材)，其中，該金屬塊280係為銅球，且該導電材281係為銲錫材，如鎳錫、錫鉛或錫銀，但不限於此。
另外，該第二導電元件28b係形成於該第二基板22下側之電性接點221上，且該第二導電元件28b係為銲錫凸塊。具體地，該第一導電元件28a與該第二導電元件28b的數量比例可為1：0.5~1：1.5，較佳為1：1。有關該些導電元件之態樣不限於上述。
如第2B圖所示，將該第二基板22堆疊於該第一基板20上，其中，該第二基板22透過該結合層29結合於該第一電子元件21上，並令該些第一導電元件28a與第二導電元件28b電性連接該第一基板20之電性接點201,202，使該第二基板22藉由該些第一導電元件28a與第二導電元件28b電性連接該第一基板20。
又，如第3圖所示，該第一基板20(或該第二基板22)之表面係定義有一置晶區C、及環繞該置晶區C之第一堆疊區A與第二堆疊區B，該置晶區C係設有複數電性接觸墊200(第3圖未顯示)，且該第一堆疊區A與該第二堆疊區B係設有複數電性接點201,202，其中，該第一堆疊區A之電性接點201,202之密度大於該第二堆疊區B之電性接點202之密度。
另外，於該第一堆疊區A中，部分該電性接點201上結合該第一導電元件28a，而部分該電性接點202上結合該第二導電元件28b，且如第4圖所示，該些第一導電元 件28a與該些第二導電元件28b係交錯排列，以藉由該第一導電元件28a(例如具有金屬塊280與包覆該金屬塊280之導電材281)之結構特徵，不僅可提供支撐效果，且能避免橋接(solder ball bridge)。於該第二堆疊區B中，該些電性接點202上均結合該第二導電元件28b(例如為銲錫凸塊)，以降低成本。
應可理解地，如第2B’圖所示，亦可先將該結合層29設於該第一電子元件21上，另該第一導電元件28a與第二導電元件28b先設於該第一基板20之電性接點201,202上，再堆疊該第二基板22於該第一基板20上，以呈現第2B圖之狀態。
如第2C圖所示，形成第一封裝層23於該第一基板20上側與該第二基板22下側之間，使該第一封裝層23包覆該第一電子元件21、該些第一導電元件28a與第二導電元件28b、該結合層29與該些導電凸塊210。
接著，沿切割路徑S進行切單製程，以製成複數電子封裝件2。
於本實施例中，由於該結合層29形成於該第二基板22與該第一電子元件21之間，故該第一封裝層23不會填入該第二基板22與該第一電子元件21之間。
再者，該第一基板20下側之植球墊203上可形成有如銲球28之導電元件，以供接置如電路板或另一線路板之電子結構。
於另一實施例中，如第2D圖所示之電子封裝件2’ 中，可藉由一黏著層241設置至少一第二電子元件24於該第二基板22上側上，再形成第二封裝層25於該第二基板22上側，且該第二封裝層25包覆該第二電子元件24。例如，該第二電子元件24係藉由複數銲線240以打線方式電性連接該第二基板22上側之第二線路層22a，且該第二封裝層25復包覆該些銲線240。於其它實施例中，該第二電子元件24亦可以覆晶方式設於該第二基板22上側。
或者，如第2D’圖所示，亦可設置至少一封裝件26於該第二基板22上。例如，該封裝件26係包含一載體260、設置並電性連接至該載體260之第三電子元件261、及包覆該第三電子元件261之封裝體262。具體地，該封裝件26係藉由複數如銲球263之導電元件電性連接該第二基板22，且該第三電子元件261之封裝方式可為打線(如第2D’圖所示)、覆晶或嵌埋等，但並無特別限制。
於另一實施例中，如第2D圖所示，亦可設置至少一支撐件27於該第一與第二基板20,22之間，使該第二基板22藉由該支撐件27堆疊於該第一基板20上，且該第一封裝層23復包覆該支撐件27。
具體地，該支撐件27之構造係類似該第一導電元件28a之構造，即具有金屬塊270與包覆該金屬塊270之導電材271，其中，該金屬塊270係為銅球，且該導電材271係為銲錫材，如鎳錫、錫鉛或錫銀，但不限於此。
再者，於製程中，該支撐件27可與該第一導電元件28a一同製作，且該第一基板20與第二基板22可藉由定 位墊30之設計，以利於該支撐件27之定位。具體地，該定位墊30未電性連接該第一基板20之第一線路層20a,20b與該第二基板22之第二線路層22a,22b，致使該支撐件27未電性連接該第一基板20與第二基板22，因而該支撐件27可視為虛設金屬件(dummy metal member)。應可理解地，如第2D’圖所示，該支撐件27亦可直接設於該第一基板20之表面與該第二基板22之表面，而省略該定位墊30之製作。
又，如第3圖所示，該定位墊30(或該支撐件27)係位於該第一堆疊區A與該第二堆疊區B之交界處(或該第一基板20之表面之四個角落處)。應可理解地，該定位墊30(或該支撐件27)可位於該第一基板20之表面之任一處，並不限於上述。
另外，上述電子元件(如第一電子元件21、第二電子元件24或第三電子元件261)係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。
本發明之製法中，藉由不同構造之第一導電元件28a與第二導電元件28b支撐該第二基板22，經過回銲該些第二導電元件28b(及第一導電元件28a，視其是否含有銲錫材料)之後，能分散溫度升降所產生的應力集中，以避免該第二基板22發生局部凹凸不平，故相較於習知技術，本發明於模壓過程中，該第二基板22之表面可有效接觸模具表面，以避免該第一封裝層23之模流產生向上推擠力。因 此，本發明之製法不僅能避免該些第一導電元件28a與第二導電元件28b發生橋接之問題，且能減少應力集中以避免該第二基板22發生破裂(crack)。
再者，藉由將該第二基板22透過該結合層29結合至該第一電子元件21上，以得到較佳的支撐效果。具體地，該第二基板22與該第一基板20之間的距離得以固定，因而能控制該些第一與第二導電元件28a,28b的高度與體積，故相較於習知技術，於回銲該些第二導電元件28b(及第一導電元件28a)後，該些第一與第二導電元件28a,28b所構成之接點能維持良好之電性連接品質，且該些第一與第二導電元件28a,28b所排列成之柵狀陣列(grid array)之共面性(coplanarity)良好，致使接點應力(stress)保持平衡而不會造成該第一與第二基板20,22之間呈傾斜接置，以避免產生接點偏移之問題。因此，本發明之製法能提高產品良率。
又，藉由該結合層29之設計，以於形成該第一封裝層23之模壓過程中，於該第一封裝層23之封裝材產生向上推擠力時，該結合層29亦可吸收應力，以減少該些第一與第二導電元件28a,28b所承受的應力，故能避免該些第一與第二導電元件28a,28b發生破裂。
另外，該支撐件27亦能提供支撐的效果，以避免該第二基板22發生崩塌而導致該些第二導電元件28b(及第一導電元件28a)發生橋接之問題。
本發明提供一種電子封裝件2,2’,2”，其包括：第一 基板20、設於該第一基板20上之第一電子元件21、藉由複數第一導電元件28a與第二導電元件28b堆疊於該第一基板20上之第二基板22、以及設於該第一基板20與第二基板22之間的第一封裝層23。
所述之第一電子元件21係藉由複數導電凸塊210設於該第一基板20上。
所述之第二基板22係藉由該些第一導電元件28a與第二導電元件28b電性連接該第一基板20並藉由結合層29結合至該第一電子元件21上，且該第一導電元件28a之構造與該第二導電元件28b之構造不同。例如，該第一導電元件28a係為金屬塊、或具有金屬塊280與包覆該金屬塊280之導電材281，且該第二導電元件28b係為銲錫凸塊。
所述之第一封裝層23係包覆該第一電子元件21、該些第一導電元件28a與第二導電元件28b。
於一實施例中，該第一導電元件28a與該第二導電元件28b的數量比例係為1：0.5~1：1.5。
於一實施例中，該結合層29係為薄膜(film)或散熱材。
於一實施例中，該第一基板20之表面係定義有一置晶區C、及環繞該置晶區C之第一堆疊區A與第二堆疊區B，該置晶區C係設有該第一電子元件21，且該第一堆疊區A與該第二堆疊區B係設有複數電性接點201,202，以結合該第一導電元件28a及/或該第二導電元件28b，其中，其中，該第一堆疊區A之電性接點201,202之密度大於該第二堆疊區B之電性接點202之密度。
於一實施例中，該第一基板20具有定位墊30。
於一實施例中，該第一導電元件28a與該第二導電元件28b係交錯排列。
於一實施例中，該電子封裝件2’,2”復包括至少一支撐件27，係設於該第一與第二基板20,22之間。例如，該支撐件27未電性連接該第一與第二基板20,22。
於一實施例中，該電子封裝件2’復包括設於該第二基板22上之第二電子元件24及第二封裝層25，且該第二封裝層25係包覆該第二電子元件24。
於一實施例中，該電子封裝件2”復包括設於該第二基板22上之至少一封裝件26。
綜上所述，本發明之電子封裝件及其製法，主要藉由不同構造之第一與第二導電元件支撐該第二基板，以於模壓過程中，避免該些導電元件發生橋接之問題，且避免該第二基板發生破裂。
再者，藉由該第二基板結合至該第一電子元件上，以得到較佳的支撐效果，且能提高產品良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (28)

  1. 一種電子封裝件，係包括：第一基板；第一電子元件，係設於該第一基板上；第二基板，係藉由複數第一導電元件與第二導電元件堆疊於該第一基板上並藉由結合層結合至該第一電子元件上，其中，該第一導電元件之構造與該第二導電元件之構造不同；以及第一封裝層，係形成於該第一基板與第二基板之間，以包覆該第一電子元件、該第一導電元件與該第二導電元件。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該第一導電元件與該第二導電元件的數量比例係為1：0.5~1：1.5。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該第一導電元件係為金屬塊。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該第一導電元件係具有金屬塊與包覆該金屬塊之導電材。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該第二導電元件係為銲錫凸塊。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該結合層係為薄膜(film)或散熱材。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該第一基板之表面係定義有一置晶區、及環繞該置晶區之第 一堆疊區與第二堆疊區，該置晶區係設有該第一電子元件，且該第一堆疊區與該第二堆疊區係設有複數電性接點，以結合該第一導電元件及/或該第二導電元件，其中，該第一堆疊區之電性接點之密度大於該第二堆疊區之電性接點之密度。
  8. 如申請專利範圍第1項所述之電子封裝件，其中，該第一基板具有定位墊。
  9. 如申請專利範圍第1項所述之電子封裝件，其中，該第一導電元件與該第二導電元件係交錯排列。
  10. 如申請專利範圍第1項所述之電子封裝件，復包括設於該第一與第二基板之間之支撐件。
  11. 如申請專利範圍第10項所述之電子封裝件，其中，該支撐件未電性連接該第一與第二基板。
  12. 如申請專利範圍第1項所述之電子封裝件，復包括設於該第二基板上之第二電子元件。
  13. 如申請專利範圍第12項所述之電子封裝件，復包括形成於該第二基板上且包覆該第二電子元件之第二封裝層。
  14. 如申請專利範圍第1項所述之電子封裝件，復包括設於該第二基板上之封裝件。
  15. 一種電子封裝件之製法，係包括：提供第一基板及第二基板，該第一基板上設有第一電子元件；將該第二基板藉由第一導電元件與第二導電元件 堆疊於該第一基板上，並使該第二基板藉由結合層結合至該第一電子元件上，且該第一導電元件之構造與該第二導電元件之構造不同；以及形成第一封裝層於該第一基板與第二基板之間，以包覆該第一電子元件、該第一導電元件與該第二導電元件。
  16. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第一導電元件與該第二導電元件的數量比例係為1：0.5~1：1.5。
  17. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第一導電元件係為金屬塊。
  18. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第一導電元件係具有金屬塊與包覆該金屬塊之導電材。
  19. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第二導電元件係為銲錫凸塊。
  20. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該結合層係為薄膜(film)或散熱材。
  21. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第一基板之表面係定義有一置晶區、及環繞該置晶區之第一堆疊區與第二堆疊區，該置晶區係設有該第一電子元件，且該第一堆疊區與該第二堆疊區係設有複數電性接點，以結合該第一導電元件及/或該第二導電元件，其中，該第一堆疊區之電性接點之密度大於該第 二堆疊區之電性接點之密度。
  22. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第一基板具有定位墊。
  23. 如申請專利範圍第15項所述之電子封裝件之製法，其中，該第一導電元件與該第二導電元件係交錯排列。
  24. 如申請專利範圍第15項所述之電子封裝件之製法，復包括設置支撐件於該第一與第二基板之間。
  25. 如申請專利範圍第24項所述之電子封裝件之製法，其中，該支撐件未電性連接該第一與第二基板。
  26. 如申請專利範圍第15項所述之電子封裝件之製法，復包括設置第二電子元件於該第二基板上。
  27. 如申請專利範圍第26項所述之電子封裝件之製法，復包括形成第二封裝層於該第二基板上，以包覆該第二電子元件。
  28. 如申請專利範圍第15項所述之電子封裝件之製法，復包括設置封裝件於該第二基板上。
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