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TW201707161A - 高頻封裝結構 - Google Patents

高頻封裝結構 Download PDF

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TW201707161A
TW201707161A TW105102436A TW105102436A TW201707161A TW 201707161 A TW201707161 A TW 201707161A TW 105102436 A TW105102436 A TW 105102436A TW 105102436 A TW105102436 A TW 105102436A TW 201707161 A TW201707161 A TW 201707161A
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ground
signal
high frequency
frequency package
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TWI585909B (zh
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黃智文
陳毓喬
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穩懋半導體股份有限公司
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Abstract

一種高頻封裝，包含有一接地引腳，耦接於一晶粒之一接地部，設置於該高頻封裝之一側邊，該接地引腳佔據該側邊，該接地引腳形成有一孔槽；以及一訊號引腳，設置於該孔槽之中；其中，該接地引腳環繞該訊號引腳，該接地引腳與該訊號引腳形成一接地－訊號－接地（Ground-Signal-Ground，GSG）結構。

Description

高頻封裝結構
本發明係指一種高頻封裝結構，尤指一種可降低高頻損耗的高頻封裝結構。
行動通訊系統及衛星通訊系統常需進行高頻操作，而傳統封裝結構並未針對高頻操作進行設計，因此傳統封裝結構在高頻產生嚴重的損耗而使傳統封裝結構之高頻效能下降。詳細來說，傳統封裝結構通常透過一打線接合（Wire Bonding）製程，利用接和線（Bonding Wires）將一晶粒（Die）以及一引腳（Lead）相互接合，接著透過一模封（Molding）製程，將晶粒以及引腳以一模封塑料（Molding Compound）包覆而成。然而，模封塑料通常由高損耗之材質所製成，因此會產生電感效應而導致高頻損耗惡化。
舉例來說，請參考第1A圖至第1C圖，第1A圖至第1C圖分別為習知一封裝結構10之剖面圖、俯視圖及仰視圖。封裝結構10包含有一晶粒100，晶粒100黏著於一晶粒座（Die Pad）102，並透過接合線106連接至引腳104。封裝結構10在經過一模封製程之後，接合線106及引腳104均會由模封塑料所覆蓋，因此於接合線106及引腳104附近會產生電感效應。需注意的是，晶粒100與其周圍之引腳104具有高度差（即晶粒100之一頂面與其周圍之引腳104之一頂面之間並未相互共平面），接合線106之長度必須夠長始能連接晶粒100與引腳104，然而，接合線106的長度越長，其所造成電感效應的大，導致高頻損耗也更加嚴重。
因此，習知技術實有改善之必要。
因此，本發明之主要目的即在於提供一種可降低高頻損耗的高頻封裝結構，以改善習知技術的缺點。
本發明揭露一種高頻封裝，包含有一接地引腳，耦接於一晶粒之一接地部，設置於該高頻封裝之一側邊，該接地引腳佔據該側邊，該接地引腳形成有一孔槽；以及一訊號引腳，設置於該孔槽之中；其中，該接地引腳環繞該訊號引腳，該接地引腳與該訊號引腳形成一接地－訊號－接地（Ground-Signal-Ground，GSG）結構。
關於接合線及引腳附近所產生之電感效應請參考第2圖，第2圖為一封裝結構之一電路模型示意圖。於第2圖中，一電感L1代表接合線附近所產生之電感效應，而一電感L2代表引腳附近所產生之電感效應。無論是降低電感L1或電感L2，皆可減輕封裝結構之高頻損耗，進而提昇封裝結構之高頻效能。
為了降低引腳附近之電感L2，高頻封裝結構之引腳可經適當設計而形成為傳輸線。請參考第3A圖及第3B圖，第3A圖及第3B圖分別為本發明實施例一高頻封裝結構30之俯視圖及仰視圖。高頻封裝結構30包含有一訊號引腳346以及一接地引腳344，接地引腳344設置於高頻封裝結構30之一側邊S1，訊號引腳346及接地引腳344可經設計而形成為傳輸線（Transmission Line），訊號引腳346透過接合線306連接於一晶粒300，用來傳遞晶粒300之一訊號。接地引腳344佔據高頻封裝結構30之整個側邊S1，接地引腳344亦透過接合線306連接於晶粒300之一接地部。接地引腳344形成有一孔槽，且訊號引腳346設置於該孔槽之中，即接地引腳344環繞訊號引腳346且接地引腳344與訊號引腳346分離。透過將訊號引腳346及接地引腳344設計成傳輸線可有效降低引腳附近之電感L2，進而提昇高頻封裝結構30之高頻效能。另外，接地引腳344連接於晶粒300之接地部，即接地引腳344之電位維持在一固定接地電位，因此接地引腳344及訊號引腳346形成一接地－訊號－接地（Ground-Signal-Ground，GSG）結構，更進一步地提昇高頻封裝結構30之高頻效能。另外，連接晶粒300與訊號引腳346之接合線306設置於連接晶粒300與接地引腳344之接合線306之中，即接合線306亦形成一接地－訊號－接地結構，可更進一步地提昇高頻封裝結構30之高頻效能。
另外，接地引腳344可包含有接地引腳分段340、342，接地引腳分段340、342相隔該孔槽而彼此相互分離，同時接地引腳分段340、342環繞訊號引腳346。接地引腳分段340、342皆連接於晶粒300之接地部，如此一來，接地引腳分段340、342之電位皆維持在固定的接地電位，以形成接地－訊號－接地結構。較佳地，接地引腳344之一頂面及訊號引腳346之一頂面位於相同之水平位準（或位於相同之高度），即接地引腳344之頂面與訊號引腳346之頂面共平面（或相戶對齊），如此一來，可使訊號引腳346之訊號輻射更加穩定，進而提昇高頻封裝結構30之高頻效能。
另外，如第3B圖所示，訊號引腳346包含一上訊號引腳部3462以及一下訊號引腳部3460，下訊號引腳部3460較上訊號引腳部3462為窄，因此，經過一模封製程後，模封塑料可對訊號引腳346形成較佳之固定效果。
較佳地，高頻封裝結構30之一晶粒座302可形成有一凹槽308，晶粒300可設置於晶粒座302之凹槽308中，使得晶粒300之一頂面大致與接地引腳344及訊號引腳346之頂面相互共平面（或相互對齊），在此情形下，可縮短接合線306的長度而有效降低接合線附近的電感L1，進而提昇高頻封裝結構30之高頻效能。
由上述可知，本發明之高頻封裝結構將訊號引腳及接地引腳設計而形成傳輸線，且接地引腳環繞訊號引腳而形成接地－訊號－接地結構，以提昇高頻封裝結構之高頻效能。
另外，訊號引腳之形狀並未有所限，訊號引腳之形狀可是實際狀況而變化。舉例來說，請參考第4圖，第4圖為本發明實施例一高頻封裝結構40之俯視圖。高頻封裝結構40之一訊號引腳446可包含突出部4462、4464，突出部4462、4464突出自訊號引腳446之一中央部4460，突出部4462、4464可形成傳輸線之一電容效應，進而提昇高頻封裝結構40之高頻效能。
需注意的是，前述實施例係用以說明本發明之概念，本領域具通常知識者當可據以做不同之修飾，而不限於此。舉例來說，訊號引腳及接地引腳可利用微帶線（Microstrip Line）或是共平面波導（Coplanar Waveguide，CPW）的方式實現，而不限於此。另外，形成凹槽的方式並未有所限，凹槽可利用正面蝕刻（Topside Etching）或背面蝕刻（Backside Etching）的方式製成，而不限於此。另外，訊號引腳之突出部之一數量並未有所限，例如，訊號引腳可僅包含單一突出部，亦屬於本發明之範疇。
綜上所述，本發明之高頻封裝結構將訊號引腳及接地引腳設計而形成傳輸線，且接地引腳環繞訊號引腳而形成接地－訊號－接地結構，因此提昇高頻封裝結構之高頻效能。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10、30、40．．．高頻封裝結構
100、300．．．晶粒
102、302．．．晶粒座
104．．．引腳
106、306．．．接合線
340、342．．．接地引腳分段
344．．．接地引腳
446、346．．．訊號引腳
3460．．．下訊號引腳部
3462．．．上訊號引腳部
4460．．．中央部
4462、4464．．．突出部
L1、L2．．．電感
S1．．．側邊
第1A圖至第1C圖分別為習知一封裝結構之剖面圖、俯視圖及仰視圖。 第2圖為一電路模型之示意圖。 第3A圖及第3B圖分別為本發明實施例一高頻封裝結構之俯視圖及仰視圖。 第4圖為本發明實施例一高頻封裝結構之俯視圖。
30‧‧‧高頻封裝結構
300‧‧‧晶粒
302‧‧‧晶粒座
306‧‧‧接合線
308‧‧‧凹槽
340、342‧‧‧接地引腳分段
344‧‧‧接地引腳
346‧‧‧訊號引腳
S1‧‧‧側邊

Claims (7)

  1. 一種高頻封裝，包含有： 一接地引腳，耦接於一晶粒之一接地部，設置於該高頻封裝之一側邊，該接地引腳佔據該側邊，該接地引腳形成有一孔槽；以及 一訊號引腳，設置於該孔槽之中； 其中，該接地引腳環繞該訊號引腳，該接地引腳與該訊號引腳形成一接地－訊號－接地（Ground-Signal-Ground，GSG）結構。
  2. 如請求項1所述之高頻封裝，其中該接地引腳與該訊號引腳分離。
  3. 如請求項1所述之高頻封裝，其中該接地引腳之一頂面與該訊號引腳之一頂面位於相同之高度。
  4. 如請求項1所述之高頻封裝，其中該接地引腳包含一第一接地引腳段以及一第二接地引腳段，該第一接地引腳段及該第二接地引腳段耦接於該晶粒之該接地部，該第一接地引腳段及該第二接地引腳段環繞該訊號引腳。
  5. 如請求項1所述之高頻封裝，其中該接地引腳及該訊號引腳形成一傳輸線。
  6. 如請求項5所述之高頻封裝，其中該訊號引腳包含至少一突出部，該至少一突出部突出自該訊號引腳之一中央部，該至少一突出部形成該傳輸線之電容效應。
  7. 如請求項1所述之高頻封裝，另包含： 至少一第一接合線（Bonding Wires），連接於該晶粒與該接地引腳之間；以及 一第二接合線，連接於該晶粒與該訊號引腳之間； 其中該至少第一接合線與該一第二接合線形成一接地－訊號－接地結構。
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