[go: up one dir, main page]

TW201631716A - 一種晶片尺寸等級的感測晶片封裝模組及其製造方法 - Google Patents

一種晶片尺寸等級的感測晶片封裝模組及其製造方法 Download PDF

Info

Publication number
TW201631716A
TW201631716A TW104143066A TW104143066A TW201631716A TW 201631716 A TW201631716 A TW 201631716A TW 104143066 A TW104143066 A TW 104143066A TW 104143066 A TW104143066 A TW 104143066A TW 201631716 A TW201631716 A TW 201631716A
Authority
TW
Taiwan
Prior art keywords
wafer
wafer size
chip package
sensing chip
sensing
Prior art date
Application number
TW104143066A
Other languages
English (en)
Inventor
Shu-Ming Chang
Tsang-Yu Liu
Yen-Shih Ho
Original Assignee
Xintec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xintec Inc filed Critical Xintec Inc
Publication of TW201631716A publication Critical patent/TW201631716A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/0354—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
    • G06F3/03547—Touch pads, in which fingers can move on a surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32237—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0311—Metallic part with specific elastic properties, e.g. bent piece of metal as electrical contact
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10151—Sensor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Multimedia (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
  • Position Input By Displaying (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

本發明揭示一種具有低生產生本且具有高效率的晶片尺寸等級的感測晶片封裝模組，其特徵乃藉由晶圓級封裝製程使一薄觸板可以精確地放置在感測晶片上，且在搭配旋塗製程情況下，使得觸板晶圓與具感測元件的晶圓之間的黏著膠厚度降低，故可改用具中、低介質電容係數的材料。

Description

一種晶片尺寸等級的感測晶片封裝模組及其製造方法
本發明是關於一種感測晶片封裝模組及其製造方法，且特別是有關於一種晶片尺寸等級的感測晶片封裝模組及其製造方法。
具有感測功能之晶片封裝體的感測裝置在傳統的製作過程中容易受到汙染或破壞，造成感測裝置的效能降低，進而降低晶片封裝體的可靠度或品質。此外，為符合電子產品朝向微型化之發展趨勢，有關電子產品封裝構造中，用以承載半導體晶片的封裝基板如何降低厚度，亦為電子產品研發中一項重要的課題。有關封裝基板之製作過程中，其係於薄形晶片層上製作線路。若封裝基板為符合微型化之要求，而選用厚度過薄的封裝基板時，不但封裝基板之生產作業性不佳，封裝基板也易因厚度過薄，而於封裝製程受到環境因素影響會產生變形翹曲或損壞，造成產品不良等問題。
此外，觸控面板或具感測功能(例如生物特徵辨識)的面板是目前流行的科技趨勢，但使用者長期頻繁地按壓面板的情況下，將使位在面板底下的觸控元件故障失效。故，具有硬度9以上的材料，例如藍寶石基板，乃脫穎而出被選作觸控面板表面的觸板，藉由其僅耐刮的優點，保護面板底下的半導體元件。不過，目前市面上用以保護觸控元件或生物特徵感測元件的藍寶石基板，其厚度均大於200μm，由於電容式觸控面板或具生物特徵辨識感測功能的面板均藉由觸板的電容變化來傳遞訊號，且眾所周知平形板電容器之電容方程式如下: C=ε*A/d C：平形板電容器電容 ε：介質電容係數 A：平形板重疊的面積 d：兩平形板間的距離 如上述平形板電容器電容方程式所示，在介質電容係數與平形板重疊的面積不變的情況下，電容的大小與兩平形板間的距離成反比，故當平形板的厚度越大時，意味兩平形板間的距離越大，導致電容變小。
有鑒於此，為了改善如上所述的缺點，增加電容式觸控面板或具感測功能的面板的靈敏度，本發明乃提出一種新的晶片尺寸等級的(chip scale)感測晶片封裝模組以及其製造方法，藉由使用硬度大於七的材料作為觸板，且降低其厚度，使得電容式觸控面板或具感測功能的面板的電容值可以提高，增加其靈敏度。
此外，本發明乃藉由晶圓級封裝製程達成，不僅可以使本發明的薄觸板可以精確地放置在感測晶片上，且在搭配旋塗製程情況下，使得觸板晶圓與具感測元件的晶圓之間的黏著膠厚度降低，故可以不需要再選擇提高電容值所需要的高介質係數材料，而改用具中、低介質電容係數的材料即可，不僅降低生產成本，也進而可提供一效率更高的晶片等級的感測晶片封裝模組。此外，由於觸板係在感測晶片的半導體製程中同時結合，因此同時具有晶片尺寸等級，可避免先前技術中感測晶片與觸板不匹配的問題。
本發明之一目的是提供一種晶片尺寸等級的感測晶片封裝模組，包括：一感測晶片，具有相對的一第一上表面與一第一下表面，且鄰近該第一上表面處包括有一感測元件以及複數導電墊，而鄰近該第一下表面處則包括有一導電結構，且該導電結構藉由一重佈線層與該等導電墊電性連接；一具有著色層的觸板，包括一基部，及一位在該基部表面的間隔部，該間隔部具有一凹穴，且該凹穴具有一裸露出部分該基部的底牆及環繞該底牆的側牆；及一第一黏著層，位於該感測晶片與觸板之間，使得該感測晶片藉由該第一上表面黏貼到該凹穴的該底牆，且該感測晶片被該凹穴的該側牆所環繞；以及；一電路板，設置於該晶片尺寸等級的感測晶片封裝體下方，且該晶片尺寸等級的感測晶片封裝體藉由該導電結構電性結合至該電路板上。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該觸板的尺寸大於該感測晶片的尺寸。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該凹穴的俯視輪廓為矩形，而該觸板的俯視輪廓為圓形。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該間隔部之厚度為該基部之厚度的十倍以上。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該著色層是塗佈於該凹穴的該底牆及該側牆。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中構成該基部與該間隔部的材料包括玻璃。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該基部包括一觸板、一著色層及一夾於該觸板與該著色層間的第二黏著層，且該間隔部是形成於該著色層上。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中構成該基部的該觸板的材料包括玻璃，而構成該間隔部的材料包括玻璃或矽。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中構成該第一黏著層之材料包括中、低電容係數的介質材料。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該導電結構包括焊球及/或焊接凸塊及/或導電柱。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該感測元件包括觸控元件、生物特徵辨識元件或環境因子感測元件。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該生物特徵辨識元件包括指紋辨識元件。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，更包括一緩衝裝置，設置於該電路板的背面。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，其中該緩衝裝置包括一彈簧或一彈力鈕。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組，且更包括一觸發元件，設置於該晶片尺寸等級的感測晶片封裝體的該凹穴內，且該觸發元件與該晶片尺寸等級的感測晶片電性連接。
本發明之另一目的是提供一種晶片尺寸等級的感測晶片封裝模組的製造方法，其步驟包括：提供複數個晶片尺寸等級的感測晶片，每一該等晶片尺寸等級的感測晶片均具有相對的一第一上表面與一第一下表面，且鄰近該第一上表面處包括有一感測元件以及複數導電墊，而鄰近該第一下表面處則包括有一導電結構，且該導電結構藉由一重佈線層與該等導電墊電性連接；提供一具有一著色層的觸板晶圓，該觸板晶圓包括有複數個固晶區，且每一該等固晶區外均具有一預定的切割道，其中每一該等固晶區包括一基部，及一位在該基部上的間隔部，該間隔部具有一凹穴，且該凹穴具有一裸露出部分該基部的底牆及環繞該底牆的側牆；提供一第一黏著層，使得每一該等感測晶片藉由該第一上表面分別黏貼到各該凹穴的該底牆，且每一該等感測晶片均被該凹穴的該側牆所環繞沿該等固晶區之間的切割道，施一切割程序以獲得複數個晶片尺寸等級的感測晶片封裝體，其中每一該等晶片尺寸等級的感測晶片封裝體，包括：一該等感測晶片；一具有著色層的觸板，包括一基部，及一位在該基部上的間隔部，該間隔部具有一凹穴，且該凹穴具有一裸露出部分該基部的底牆及環繞該底牆的側牆；及一第一黏著層，位於該感測晶片與觸板之間，使得該感測晶片藉由該第一上表面黏貼到該凹穴的該底牆，且該感測晶片被該凹穴的該側牆所環繞；以及提供一電路板，使其中一該等晶片尺寸等級的感測晶片封裝體藉由該些導電結構電性結合至該電路板上。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該觸板的尺寸大於該感測晶片的尺寸。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該凹穴的俯視輪廓為矩形，而該基部的俯視輪廓為圓形。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該間隔部之厚度為該基部之厚度的十倍以上。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該著色層是塗佈於該凹穴的底牆及側牆。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中構成該基部與該間隔部的材料包括玻璃。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該具有一著色層的觸板晶圓的製造步驟包括：提供一觸板晶圓，其具有相對的正、反面；塗佈一著色層於該觸板晶圓的正面上；塗佈一第二黏著層於該著色層上；使一觸板結合至該第二黏著層上；薄化該觸板晶圓的反面；以及圖案化該薄化的觸板晶圓反面，形成複數個彼此互相間隔的固晶區，且每一該等固晶區包括一基部及一位在基部上的間隔部，其中該基部包括一觸板、一著色層及一夾於該觸板與該著色層間的第二黏著層，該間隔部是形成於該著色層上，且該間隔部具有一裸露出該著色層表面的凹穴。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中構成該基部的該觸板的材料包括玻璃，而構成該間隔部的材料包括玻璃或矽。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該第一黏著層之材料包括中、低電容係數的介質材料。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該導電結構包括焊球及/或焊接凸塊及/或導電柱。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該感測元件包括觸控元件、生物特徵辨識元件或環境因子感測元件。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該生物特徵辨識元件包括指紋辨識元件。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，更包括一緩衝裝置，設置於該電路板的背面。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該緩衝裝置包括一彈簧或一彈力鈕(spring button)。
本發明之另一目的是提供一種如上所述的晶片尺寸等級的感測晶片封裝模組的製造方法，更包括一觸發元件，設置於該晶片尺寸等級的感測晶片封裝體的該凹穴內，且該觸發元件與該晶片尺寸等級的感測晶片電性連接。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。 實施例 一
以下將配合圖式第1A圖至第1E圖及第1C’圖至第1E’圖，說明根據本發明的實施例一的晶片尺寸等級的感測晶片封裝模組以及其製造方法。
請先參照第1A圖，先提供一觸板晶圓300，其表面包括複數個固晶區30，且在各固晶區30外圍有一預定的圓形切割道SC。在本實施例中，觸板晶圓300可選自透明且硬度大於7的材料，例如玻璃。
接著，請參照第1B圖，其顯示的是沿第1A圖的剖面線I-I’所呈現的固晶區30的剖面圖。如第1B圖所示，固晶區30包括一基部310以及一個位在基部上的間隔部320，該間隔部320具有一露出基部310表面的凹穴330，其具有一底牆330a，以及環繞該底牆之側牆330b。在本實施例中，凹穴330可藉由微影蝕刻、銑削(milling)或鑄模等技術達成。其中，間隔部320的厚度為基部310的厚度的十倍以上，在本實施例之間隔部320的厚度約為500μm，而基部310的厚度約為50μm。此外，更包括一著色層350，覆蓋於各固晶區30的間隔層30表面，及凹穴330的底牆330a及側牆330b。
其次，請參照第1C圖及第1C’圖，提供複數個如第1C圖所示的晶片尺寸等級的感測晶片10，或複數個如第1C’圖所示的晶片尺寸等級的感測晶片10’。其中，每一個晶片尺寸等級的感測晶片10、10’均包括一基板100，其具有相對的一第一上表面100a與一第一下表面100b，且鄰近該第一上表面100a處包括有一感測元件150以及複數導電墊115，而鄰近該第一下表面100b處則包括有一介電層210、重佈線層(RDL)220、鈍化保護層230以及導電結構250。其中，導電結構250乃藉由一重佈線層(RDL)220與導電墊115電性連接。其中，第1C圖所示的晶片尺寸等級的感測晶片10，其導電結構250在本實施例為焊球，在根據本發明的其他實施例，其導電結構250也可為焊接凸塊或導電柱。此外，第1C’圖所示的晶片尺寸等級的感測晶片10’，其導電結構250是由導電柱250A和焊球250b所構成，且導電柱250A是溝填於一個貫穿鈍化保護層230及鈍化保護層230表面的鑄膠層245且裸露出部分重佈線層220的貫穿孔內，而焊球250B則是位在鑄膠層246表面且與導電柱250A連接。其中，鑄膠層的厚度約100μm，且其材料可選自例如環氧樹脂等。
接著，請參照第1D圖及第1D’圖，在第1C圖所示的晶片尺寸等級的感測晶片10的第一上表面100a上或第1C’圖所示的晶片尺寸等級的感測晶片10’的第一上表面100a上塗佈一第一黏著層400，或者在凹穴300的底牆330a塗佈一第一黏著層400，使得晶片尺寸等級的感測晶片10或10’分別被黏貼固定於如第1B圖所示各固晶區30內的凹穴330的底牆330a表面的著色層350上。此外，其他可觸發感測晶片10、10’啟動的電子元件，例如觸發元件(未顯示)，也可藉由第一黏著層400被固定於各固晶區30內的凹穴330的底牆330a表面的著色層350上，並與感測晶片10、10’電性連接。
然後，沿著各固晶區30外的切割道SC，切割觸板晶圓300，進而形成複數獨立的晶片尺寸等級的感測晶片封裝體A、A’。其中，每一晶片尺寸等級的感測晶片封裝體A、A’分別包括一俯視輪廓為矩形的晶片尺寸等級的感測晶片10、10’，其表面具有一感測元件150以及複數環繞感測元件150的導電墊115，以及一個由基部310和間隔部320所形成的觸板300’，其俯視輪廓為圓形，且觸板300’的尺寸大於晶片尺寸等級的感測晶片10、10’。
最後，請參照第1E圖及第1E’圖，提供一表面具有複數個導電接觸墊445的電路板450，使得上述製程所獲得的晶片尺寸等級的感測晶片封裝體A、A’可分別藉由其導電結構250與電路板450上的導電接觸墊445電性結合，並分別形成一晶片尺寸等級的感測晶片封裝體模組1000、1000’。此外，更可在電路板450的背面裝配一緩衝裝置460，例如彈簧、或彈力鈕，使得觸板300’被使用者按壓時，提供晶片尺寸等級的感測晶片封裝體A、A’與電路板450間一緩衝力，避免晶片尺寸等級的感測晶片封裝體A、A’與電路板450間的接合處被按壓的力量所破壞。 實施例二
以下將配合圖式第2A圖至第2C圖及第2B’圖至第2C’圖，說明根據本發明的實施例二的晶片尺寸等級的感測晶片封裝模組以及其製造方法。
請參照第2A圖，其所顯示的是一固晶區50的剖面示意圖。如FIG.2A所示，固晶區50包括一基部510以及一位在該基部510上且環繞該基部510周圍的間隔部545，其中間隔部545更包括一裸露出基部510表面的凹穴550。此外，本實施例的基部510包括一觸板540、一著色層520及一夾於該觸板540與該著色層520間的第二黏著層530，且該間隔部545是形成於著色層520上。
接著，請參照第2B圖及第2B’圖，藉由第一黏著層400，使如第1C圖或第1C’圖所示的晶片尺寸等級的感測晶片10或10’被固定於第2A圖所示的固晶區50的凹穴550底部所裸露的著色層520上。然後，沿著各固晶區50外的切割道SC切割觸板晶圓500’，進而獲得如第2B圖及第2B’圖所示的複數獨立的晶片尺寸等級的感測晶片封裝體B、B’。
然後，請參照第2C圖及第2C’圖，提供一如第1E圖所示的電路板450，使得上述製程所獲得的晶片尺寸等級的感測晶片封裝體B、B’，可分別藉由其導電結構250與電路板450上的導電接觸墊445電性結合，並分別形成一晶片尺寸等級的感測晶片封裝體模組2000、2000’。
此外，其他可觸發感測晶片10、10’啟動的電子元件，例如觸發元件(未顯示)，也可固定於各固晶區50內的凹穴550底部的著色層350上，並與感測晶片10、10’電性連接。
上述的固晶區50，其製程乃描述於第3A圖~第3D圖。如第3A圖所示，先提供一觸板晶圓500，其材質可選自矽或玻璃。其次如第3B圖所示般，在觸板晶圓500正面依序形成一著色層520、一第二黏著層以及一觸板540於觸板晶圓500上。其中，在本實施例中，觸板晶圓500的材料可選自透明玻璃或矽晶圓，而觸板540則可選自透明且硬度大於7的材料，例如玻璃、藍寶石或氮化矽。
然後，利用蝕刻製程、銑削(milling)製程、磨削(grinding)製程或研磨(polishing)製程，薄化觸板晶圓500的背面，形成如第3C圖所示般的較薄的觸板晶圓500’。
最後，請參照第3D圖，利用蝕刻、銑削等技術，自觸板晶圓500’的背面進行圖案化，形成複數個彼此互相間隔的固晶區50，且每一個固晶區50包括包括一基部510及一位在基部上的間隔部545，其中該基部510包括一觸板540、一著色層520及一夾於該觸板540與該著色層520間的第二黏著層530，且該間隔部545是形成於著色層520上，且該間隔部545具有一裸露出該著色層520表面的凹穴550。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
10、10’‧‧‧晶片尺寸等級的感測晶片 100‧‧‧基板 100a‧‧‧第一上表面 100b‧‧‧第一下表面 115‧‧‧導電墊 150‧‧‧感測元件 210‧‧‧絕緣層 220‧‧‧重佈線層(RDL) 230‧‧‧鈍化保護層 240‧‧‧孔洞 245‧‧‧鑄膠層 250‧‧‧導電結構 250A‧‧‧導電柱 250B‧‧‧焊球 30‧‧‧固晶區 300‧‧‧觸板晶圓 300’‧‧‧觸板 310‧‧‧基部 320‧‧‧間隔部 330‧‧‧凹穴 330a‧‧‧底牆 330b‧‧‧側牆 350‧‧‧著色層 400‧‧‧第一黏著層 445‧‧‧導電接觸墊 450‧‧‧電路板 460‧‧‧緩衝裝置 50‧‧‧固晶區 500、500’‧‧‧觸板晶圓 510‧‧‧基部 520‧‧‧著色層 530‧‧‧第二黏著層 540‧‧‧觸板 545‧‧‧間隔層 550‧‧‧凹穴 SC‧‧‧切割道 A、A’、B、B’‧‧‧晶片尺寸等級的感測晶片封裝體 1000、1000’、2000、2000’‧‧‧晶片尺寸等級的感測晶片封裝模組
FIG.1A~FIG.1E及FIG.1C’~FIG.1E’顯示根據本發明實施例一的晶片尺寸等級的感測晶片封裝模組的剖面製程。 FIG.2A~FIG.2C及FIG2B’~FIG.2C’的顯示根據本發明實施例二的晶片尺寸等級的感測晶片封裝模組的剖面製程。 FIG.3A~FIG.3D的顯示根據本發明實施例二的FIG.2A的固晶區剖面製程。
100‧‧‧基板
115‧‧‧導電墊
150‧‧‧感測元件
210‧‧‧絕緣層
220‧‧‧重佈線層(RDL)
230‧‧‧鈍化保護層
240‧‧‧孔洞
250‧‧‧導電結構
300’‧‧‧觸板
310‧‧‧基部
320‧‧‧間隔部
350‧‧‧著色層
400‧‧‧第一黏著層
445‧‧‧導電接觸墊
450‧‧‧電路板
460‧‧‧緩衝裝置
1000‧‧‧晶片尺寸等級的感測晶片封裝模組

Claims (30)

  1. 一種晶片尺寸等級的感測晶片封裝模組，包括: 一晶片尺寸等級的感測晶片封裝體，包括: 一感測晶片，具有相對的一第一上表面與一第一下表面，且鄰近該第一上表面處包括有一感測元件以及複數導電墊，而鄰近該第一下表面處則包括有一導電結構，且該導電結構藉由一重佈線層與該等導電墊電性連接； 一具有著色層的觸板，包括一基部，及一位在該基部上的間隔部，該間隔部具有一凹穴，且該凹穴具有一裸露出部分該基部的底牆及環繞該底牆的側牆；及 一第一黏著層，位於該感測晶片與觸板之間，使得該感測晶片藉由該第一上表面黏貼到該凹穴的該底牆，且該感測晶片被該凹穴的該側牆所環繞；以及 一電路板，設置於該晶片尺寸等級的感測晶片封裝體下方，且該晶片尺寸等級的感測晶片封裝體藉由該導電結構電性結合至該電路板上。
  2. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中該觸板的尺寸大於該感測晶片的尺寸。
  3. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中該凹穴的俯視輪廓為矩形，而該觸板的俯視輪廓為圓形。
  4. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中該間隔部之厚度為該基部之厚度的十倍以上。
  5. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中該著色層是塗佈於該凹穴的該底牆及該側牆。
  6. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中構成該基部與該間隔部的材料包括玻璃。
  7. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中該基部包括一觸板、一著色層及一夾於該觸板與該著色層間的第二黏著層，且該間隔部是形成於該著色層上。
  8. 如申請專利範圍第7項所述的晶片尺寸等級的感測晶片封裝模組，其中構成該觸板的材料包括玻璃，而構成該間隔部的材料包括玻璃或矽。
  9. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中構成該第一黏著層之材料包括中、低電容係數的介質材料。
  10. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中該導電結構包括焊球及/或焊接凸塊及/或導電柱。
  11. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，其中該感測元件包括觸控元件、生物特徵辨識元件或環境因子感測元件。
  12. 如申請專利範圍第11項所述的晶片尺寸等級的感測晶片封裝模組，其中該生物特徵辨識元件包括指紋辨識元件。
  13. 如申請專利範圍第1項所述的晶片尺寸等級的感測晶片封裝模組，更包括一緩衝裝置，設置於該電路板的背面。
  14. 如申請專利範圍第13項所述的晶片尺寸等級的感測晶片封裝模組，其中該緩衝裝置包括一彈簧或一彈力鈕。
  15. 如申請專利範圍第1~14項中任一項所述的晶片尺寸等級的感測晶片封裝模組，更包括一觸發元件，設置於該晶片尺寸等級的感測晶片封裝體的該凹穴內，且該觸發元件與該晶片尺寸等級的感測晶片電性連接。
  16. 一種晶片尺寸等級的感測晶片封裝模組的製造方法，其步驟包括： 提供複數個晶片尺寸等級的感測晶片，每一該等晶片尺寸等級的感測晶片均具有相對的一第一上表面與一第一下表面，且鄰近該第一上表面處包括有一感測元件以及複數導電墊，而鄰近該第一下表面處則包括有一導電結構，且該導電結構藉由一重佈線層與該等導電墊電性連接； 提供一具有一著色層的觸板晶圓，該觸板晶圓包括有複數個固晶區，且每一該等固晶區外均具有一預定的切割道，其中每一該等固晶區包括一基部，及一位在該基部上的間隔部，該間隔部具有一凹穴，且該凹穴具有一裸露出部分該基部的底牆及環繞該底牆的側牆； 提供一第一黏著層，使得每一該等感測晶片藉由該第一上表面分別黏貼到各該凹穴的該底牆，且每一該等感測晶片均被該凹穴的該側牆所環繞； 沿該切割道，施一切割程序以獲得複數個晶片尺寸等級的感測晶片封裝體，其中每一該等晶片尺寸等級的感測晶片封裝體，包括: 一該等感測晶片； 一具有著色層的觸板，包括一基部，及一位在該基部上的間隔部，該間隔部具有一凹穴，且該凹穴具有一裸露出部分該基部的底牆及環繞該底牆的側牆；及 一第一黏著層，位於該感測晶片與觸板之間，使得該感測晶片藉由該第一上表面黏貼到該凹穴的該底牆，且該感測晶片被該凹穴的該側牆所環繞；以及 提供一電路板，使其中一該等晶片尺寸等級的感測晶片封裝體藉由該些導電結構電性結合至該電路板上。
  17. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該觸板的尺寸大於該感測晶片的尺寸。
  18. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中各該固晶區內的該凹穴的俯視輪廓為矩形，而該基部的俯視輪廓為圓形。
  19. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該間隔部之厚度為該基部之厚度的十倍以上。
  20. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該著色層是塗佈於該凹穴的該底牆及該側牆。
  21. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中構成該基部與該間隔部的材料包括玻璃。
  22. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中製造該具有一著色層的觸板晶圓的步驟包括: 提供一觸板晶圓，其具有相對的正、反面； 塗佈一著色層於該觸板晶圓的正面上； 塗佈一第二黏著層於該著色層上； 使一觸板結合至該第二黏著層上； 薄化該觸板晶圓的反面；以及 圖案化該薄化的觸板晶圓反面，形成複數個彼此互相間隔的固晶區，且每一該等固晶區包括一基部及一位在基部上的間隔部，其中該基部包括一觸板、一著色層及一夾於該觸板與該著色層間的第二黏著層，該間隔部是形成於該著色層上，且該間隔部具有一裸露出該著色層表面的凹穴。
  23. 如申請專利範圍第22項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中構成該觸板的材料包括玻璃，而構成該間隔部的材料包括玻璃或矽。
  24. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中構成該第一黏著層之材料包括中、低電容係數的介質材料。
  25. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該導電結構包括焊球及/或焊接凸塊及/或導電柱。
  26. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該感測元件包括觸控元件、生物特徵辨識元件或環境因子感測元件。
  27. 如申請專利範圍第26項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該生物特徵辨識元件包括指紋辨識元件。
  28. 如申請專利範圍第16項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，更包括一緩衝裝置，設置於該電路板的背面。
  29. 如申請專利範圍第28項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，其中該緩衝裝置包括一彈簧或一彈力鈕。
  30. 如申請專利範圍第16~29項中任一項所述的晶片尺寸等級的感測晶片封裝模組的製造方法，更包括一觸發元件，設置於該晶片尺寸等級的感測晶片封裝體的該凹穴內，且該觸發元件與該晶片尺寸等級的感測晶片電性連接。
TW104143066A 2015-02-16 2015-12-22 一種晶片尺寸等級的感測晶片封裝模組及其製造方法 TW201631716A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562116909P 2015-02-16 2015-02-16
US201562165710P 2015-05-22 2015-05-22

Publications (1)

Publication Number Publication Date
TW201631716A true TW201631716A (zh) 2016-09-01

Family

ID=56621172

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104143066A TW201631716A (zh) 2015-02-16 2015-12-22 一種晶片尺寸等級的感測晶片封裝模組及其製造方法

Country Status (3)

Country Link
US (1) US20160239699A1 (zh)
CN (1) CN105895590B (zh)
TW (1) TW201631716A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI655738B (zh) * 2017-07-26 2019-04-01 台星科股份有限公司 可提升結構強度的晶圓級尺寸封裝結構及其封裝方法
TWI832952B (zh) * 2019-01-15 2024-02-21 美商豪威科技股份有限公司 半導體裝置封裝及其製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM519281U (zh) * 2015-12-28 2016-03-21 Metrics Technology Co Ltd J 指紋辨識裝置
EP3288072A4 (en) * 2016-07-15 2018-05-23 Shenzhen Goodix Technology Co., Ltd. Fingerprint recognition module and preparation method therefor
EP3422248A1 (en) * 2017-01-22 2019-01-02 Shenzhen Goodix Technology Co., Ltd. Fingerprint module
CN109037171A (zh) * 2018-08-28 2018-12-18 苏州日月新半导体有限公司 集成电路封装体及其制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6747290B2 (en) * 2000-12-12 2004-06-08 Semiconductor Energy Laboratory Co., Ltd. Information device
US7361860B2 (en) * 2001-11-20 2008-04-22 Touchsensor Technologies, Llc Integrated touch sensor and light apparatus
US6995032B2 (en) * 2002-07-19 2006-02-07 Cree, Inc. Trench cut light emitting diodes and methods of fabricating same
US7045868B2 (en) * 2003-07-31 2006-05-16 Motorola, Inc. Wafer-level sealed microdevice having trench isolation and methods for making the same
GB0319714D0 (en) * 2003-08-21 2003-09-24 Philipp Harald Anisotropic touch screen element
US7609178B2 (en) * 2006-04-20 2009-10-27 Pressure Profile Systems, Inc. Reconfigurable tactile sensor input device
JP2007305955A (ja) * 2006-04-10 2007-11-22 Toshiba Corp 半導体装置及びその製造方法
US8040321B2 (en) * 2006-07-10 2011-10-18 Cypress Semiconductor Corporation Touch-sensor with shared capacitive sensors
US8097929B2 (en) * 2008-05-23 2012-01-17 Chia-Sheng Lin Electronics device package and fabrication method thereof
JP4748257B2 (ja) * 2008-08-04 2011-08-17 ソニー株式会社 生体認証装置
TWI497658B (zh) * 2009-10-07 2015-08-21 Xintec Inc 晶片封裝體及其製造方法
TWI408437B (zh) * 2010-09-09 2013-09-11 液晶顯示器
US8901701B2 (en) * 2011-02-10 2014-12-02 Chia-Sheng Lin Chip package and fabrication method thereof
KR20130027628A (ko) * 2011-06-27 2013-03-18 삼성전자주식회사 적층형 반도체 장치
KR101906971B1 (ko) * 2012-09-27 2018-10-11 삼성전자주식회사 하이브리드 터치 패널, 하이브리드 터치 스크린 장치 및 이의 구동 방법
CN104347536B (zh) * 2013-07-24 2018-11-16 精材科技股份有限公司 晶片封装体及其制造方法
TWI585959B (zh) * 2014-08-13 2017-06-01 精材科技股份有限公司 晶片封裝體及其製造方法
TWI628723B (zh) * 2015-03-10 2018-07-01 精材科技股份有限公司 一種晶片尺寸等級的感測晶片封裝體及其製造方法
TWI603241B (zh) * 2015-06-29 2017-10-21 精材科技股份有限公司 一種觸控面板-感測晶片封裝體模組複合體及其製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI655738B (zh) * 2017-07-26 2019-04-01 台星科股份有限公司 可提升結構強度的晶圓級尺寸封裝結構及其封裝方法
TWI832952B (zh) * 2019-01-15 2024-02-21 美商豪威科技股份有限公司 半導體裝置封裝及其製造方法

Also Published As

Publication number Publication date
US20160239699A1 (en) 2016-08-18
CN105895590B (zh) 2018-08-07
CN105895590A (zh) 2016-08-24

Similar Documents

Publication Publication Date Title
TWI642174B (zh) 一種晶片尺寸等級的感測晶片封裝體及其製造方法
TW201631716A (zh) 一種晶片尺寸等級的感測晶片封裝模組及其製造方法
TWI597813B (zh) 晶片封裝體及其製造方法
US20200327214A1 (en) Fingerprint Sensor Pixel Array and Methods of Forming Same
CN104347537B (zh) 晶片封装体及其制造方法
TWI628723B (zh) 一種晶片尺寸等級的感測晶片封裝體及其製造方法
TWI482263B (zh) 發散式感測裝置及其製造方法
TWI578411B (zh) 晶片封裝體的製造方法
US20170207182A1 (en) Chip package and method for forming the same
TWI604570B (zh) 一種晶片尺寸等級的感測晶片封裝體及其製造方法
TW201543641A (zh) 晶片封裝體及其製造方法
TWM519281U (zh) 指紋辨識裝置
CN106293196B (zh) 触控面板与感测晶片封装体模组的复合体及其制造方法
TWI666743B (zh) 感測器封裝件及其製作方法
US20170186712A1 (en) Chip package and method for forming the same
TW201715662A (zh) 晶片封裝體及其製造方法
CN107039286A (zh) 感测装置及其制造方法
TW201639094A (zh) 晶片模組及其製造方法
CN106560929A (zh) 晶片尺寸等级的感测晶片封装体及其制造方法
KR20180016362A (ko) 인터포저 구조를 갖는 지문감지장치
CN106469741A (zh) 感测模组及其制造方法
TWI593069B (zh) 晶片封裝體及其製造方法
CN109585403B (zh) 传感器封装件及其制作方法
TWI632665B (zh) 晶片封裝體之製造方法
TWI612624B (zh) 封裝結構及封裝方法