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TW201614746A - A patterned pad to create a virtual solder mask for wafer-level chip-scale packages - Google Patents

A patterned pad to create a virtual solder mask for wafer-level chip-scale packages

Info

Publication number
TW201614746A
TW201614746A TW103137164A TW103137164A TW201614746A TW 201614746 A TW201614746 A TW 201614746A TW 103137164 A TW103137164 A TW 103137164A TW 103137164 A TW103137164 A TW 103137164A TW 201614746 A TW201614746 A TW 201614746A
Authority
TW
Taiwan
Prior art keywords
pad
brace
center pad
wafer
create
Prior art date
Application number
TW103137164A
Other languages
Chinese (zh)
Other versions
TWI582871B (en
Inventor
Bora Baloglu
Glenn Rinne
Christopher J Berry
Original Assignee
Amkor Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amkor Technology Inc filed Critical Amkor Technology Inc
Publication of TW201614746A publication Critical patent/TW201614746A/en
Application granted granted Critical
Publication of TWI582871B publication Critical patent/TWI582871B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/1152—Self-assembly, e.g. self-agglomeration of the bump material in a fluid
    • H01L2224/11526—Self-assembly, e.g. self-agglomeration of the bump material in a fluid involving the material of the bonding area, e.g. bonding pad or under bump metallisation [UBM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Methods and devices for a patterned pad to create a virtual solder mask for wafer-level chip-scale packages may include a contact pad formed on a semiconductor die, the contact pad including: a center pad, a trace, and a first set of spokes extending out from the center pad. A brace may surround a portion of the first spoke pattern and the center pad. A solder ball may be formed on the center pad and the first spoke pattern but not on the brace. The center pad may comprise a circular metal disc or ring. A second spoke pattern including one or more spokes may extend out from the brace. A second brace may surround the first and second spoke patterns, the brace, and the center pad. The first and second spoke patterns may have different widths and may extend at different angles with respect to the center pad.
TW103137164A 2014-10-13 2014-10-28 A patterned pad to create a virtual solder mask for wafer-level chip-scale packages TWI582871B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462063306P 2014-10-13 2014-10-13
KR1020140138302A KR20160043492A (en) 2014-10-13 2014-10-14 A patterned pad to create a virtual solder mask for wafer-level chip-scale packages

Publications (2)

Publication Number Publication Date
TW201614746A true TW201614746A (en) 2016-04-16
TWI582871B TWI582871B (en) 2017-05-11

Family

ID=55917984

Family Applications (2)

Application Number Title Priority Date Filing Date
TW106104408A TWI656583B (en) 2014-10-13 2014-10-28 Patterned liners used to create virtual solder masks in wafer level wafer size packages
TW103137164A TWI582871B (en) 2014-10-13 2014-10-28 A patterned pad to create a virtual solder mask for wafer-level chip-scale packages

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW106104408A TWI656583B (en) 2014-10-13 2014-10-28 Patterned liners used to create virtual solder masks in wafer level wafer size packages

Country Status (2)

Country Link
KR (2) KR20160043492A (en)
TW (2) TWI656583B (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61104632A (en) * 1984-10-29 1986-05-22 Nec Corp Semiconductor device
JPS6223120A (en) 1985-07-24 1987-01-31 Hitachi Ltd semiconductor equipment
KR100216839B1 (en) * 1996-04-01 1999-09-01 김규현 Solder Ball Land Metal Structure in BGA Semiconductor Package
US6201305B1 (en) * 2000-06-09 2001-03-13 Amkor Technology, Inc. Making solder ball mounting pads on substrates
TWI251923B (en) * 2004-10-21 2006-03-21 Advanced Semiconductor Eng Package substrate with NSMD pads
US20080093749A1 (en) * 2006-10-20 2008-04-24 Texas Instruments Incorporated Partial Solder Mask Defined Pad Design
US9935038B2 (en) * 2012-04-11 2018-04-03 Taiwan Semiconductor Manufacturing Company Semiconductor device packages and methods

Also Published As

Publication number Publication date
TWI582871B (en) 2017-05-11
TW201721782A (en) 2017-06-16
KR20170081581A (en) 2017-07-12
TWI656583B (en) 2019-04-11
KR20160043492A (en) 2016-04-21
KR101864659B1 (en) 2018-06-07

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