TW201527965A - System and method for detecting a BIOS test process of a computer - Google Patents

Abstract

The present invention provides a system and method for detecting a BIOS test process of a computer. The system is implemented in the computer, which includes a BMC, a PCH chip, a switch convertor, and a LED panel. The system obtains POST codes from the PCH chip when the computer is executing a POST test process, and controls each LED of the LED panel to display each of the POST codes through the switch convertor. The system obtains system state codes from the PCH chip when the computer has executed the POST test process, and controls each LED of the LED panel to display each of the system state codes through the switch convertor.

Description

BIOS debug detection system and method

The invention relates to a computer BIOS debugging system and method, in particular to a BIOS debugging detection system and method based on a substrate controller (BMC).

Based on the need for a BIOS (basic input-output system), hardware engineers generally have two ways to debug the BIOS when designing the server. One use is a COM port, and the other is a power-on self test (POST) LED indicator. In terms of product safety, the COM port is generally removed after mass production. In this case, driving the LED becomes the only way for the user to understand the BIOS operating status and the maintenance personnel to debug the BIOS. At present, the industry uses the boot detection LED indicator to debug the BIOS, mainly using an external card to display debugging information. The external card is a small integrated circuit of a programmable device and a seven-segment display tube. The design is relatively complicated, and each motherboard must be equipped with a connection port, which causes a problem of wasting electronic devices. In addition, each time there is a problem with the server booting, it is necessary to turn off the external card and then debug it. However, for some random problems, it may be difficult to copy after shutting down, which makes the debugging inconvenient.

In view of the above, it is necessary to provide a BIOS debugging detection system and method, which can automatically display the POST information code of the computer and the system status code of the computer on the LED indicator, thereby enabling the tester to intuitively understand the debugging process of the BIOS.

The BIOS debug detection system runs on a computer, and the computer includes a BMC controller, a PCH chip, a serial-parallel converter, and an LED panel. The system comprises: a BIOS startup module, which is used to start the BIOS when the computer is powered on to perform a POST process of the computer, and to use the BIOS to set the GPIO value of the GPIO on the BMC controller to a low level, and to detect the GPIO.埠 GPIO value to determine whether the computer is in the process of performing POST; POST information detection module, when the computer is in the process of performing POST, obtain the POST information code generated by the computer performing the POST process on the PCH chip, and send the POST information code To the serial-to-parallel converter, each logical digit in the POST information code is sequentially assigned a corresponding LED indicator on the LED panel, and the LED indicator on the LED panel is controlled by the serial-parallel converter to display the corresponding POST information code. Logic digits; system information detection module, configured to acquire a system status code of the computer in the PCH chip when the POST process has been executed, send the system status code to the serial-parallel converter, and each of the system status codes The logical digits specify a corresponding LED indicator on the LED panel in sequence, and the LED indicator on the LED panel is controlled by the serial-parallel converter to display the system status code corresponding Digital logic.

The BIOS debug detection method should be implemented in a computer, which includes a BMC controller, a PCH chip, a serial-parallel converter, and an LED panel. The method comprises the steps of: starting the BIOS when the computer is turned on, performing a POST process of the computer, and using the BIOS to set the GPIO value of the GPIO on the BMC controller to a low level; determining the computer by detecting the GPIO value of the GPIO埠Whether it is in the process of performing POST; when the computer is in the process of performing POST, the POST information code generated by the computer performing the POST process is acquired in the PCH chip, and the POST information code is sent to the serial-parallel converter, and each of the POST information codes is The logic digits specify a corresponding LED indicator on the LED panel in sequence, and the LED indicator on the LED panel is controlled by the serial-parallel converter to display the logical digit corresponding to the POST information code; when the POST process has been completed, the PCH chip is executed. Obtain the system status code of the computer, send the system status code to the serial-parallel converter, assign a corresponding LED indicator to the LED panel in sequence, and use a serial-parallel converter to control The LED indicator on the LED panel displays the logical digit corresponding to the system status code.

Compared with the prior art, when the debugger uses the BIOS to perform POST on the computer, the BIOS debugging detection system and method of the present invention can automatically obtain the POST information code and display it on the LED indicator; After the boot test, the system status code of the computer can be automatically obtained and displayed on the LED indicator, so that the tester can intuitively understand the BIOS debugging process.

1 is a schematic diagram of an operating environment of a preferred embodiment of the BIOS debug detection system of the present invention.

2 is a functional block diagram of the BIOS debug detection system of the present invention.

3 is a flow chart of a preferred embodiment of the BIOS debug detection method of the present invention.

Referring to FIG. 1, a schematic diagram of an operating environment of a preferred embodiment of the BIOS debug detection system 10 of the present invention is shown. In this embodiment, the BIOS debug detection system 10 is installed and runs in the computer 100. The computer includes a BMC (Base management controller) controller 1, a South Bridge (Platform controller hub (PCH) chip 2, and a serial-to-parallel conversion. Switch 3, LED panel 4, jumper setter 5, and central processing unit (CPU) 6. The BMC controller 1 is connected to the PCH chip 2 via an LPC (Low Pin Count) bus bar 21, and is connected to the serial-parallel converter 3 via a GPIO bus bar 31. The serial-to-parallel converter 3 is electrically connected to the LED panel 4, and the LED panel 4 is composed of eight LED indicators 40 for displaying a logical digit “0” and a logical digit “1”, respectively. 40 is a seven-segment LED display tube. The computer 100 can be a personal computer (PC), a workstation computer, a notebook, a server, or other electronic computing device.

The BMC controller 1 further includes a GPIO port 11, and the jumper setter 5 is configured to connect a jumper to the GPIO port 11. The PCH chip 2 includes a basic input-output system (BIOS) 20 that performs a Power On Self Test (POST) program on the computer 100 and directs the computer 100 to the operating system ( OS) completes the entire boot process.

Referring to FIG. 2, it is a functional module diagram of the BIOS debug detection system 10 of the present invention. In the embodiment, the BIOS debugging detection system 10 includes a BIOS startup module 101, a POST information detection module 102, a system information detection module 103, and a jumper detection module 104. The functional module referred to in the present invention refers to a series of program instruction segments that can be executed by the central processing unit 6 of the computer 100 and can perform fixed functions, and are stored in the flash memory of the BMC controller 1 (for example, Flash ROM). in. The respective function modules 101-104 will be described in detail in the flowchart of FIG.

Referring to FIG. 3, it is a flowchart of a preferred embodiment of the BIOS debug detection method of the present invention. In the embodiment, the method is applied to the computer 100. When the tester uses the BIOS 20 to perform a power-on self-test (POST) debugging process on the computer 100, the method can automatically obtain the POST information code and display it in the LED indicator. 40 on. After the computer 100 performs the boot self-test test, the method can automatically obtain the system status code of the computer 100 and display it on the LED indicator 40, thereby enabling the tester to intuitively understand the BIOS debugging process.

In step S31, when the computer 100 is powered on, the BIOS startup module 101 starts the BIOS 20 to execute the POST process of the computer 100, and uses the BIOS 20 to set the GPIO value of the GPIO 埠 11 to a low level. In the present embodiment, the low level is set to logic "0" and the high level is set to logic "1". When the POST process is completed, the BIOS boot module 101 automatically sets the GPIO value of GPIO 埠 11 to a high level.

In step S32, the BIOS startup module 101 determines whether the computer 100 is in the process of performing POST by detecting the GPIO value of the GPIO port 11. In this embodiment, when the GPIO value of the GPIO埠11 is low, the BIOS startup module 101 determines that the computer 100 is performing the POST process; if the GPIO value of the GPIO埠11 is high, the BIOS startup module 101 determines The computer 100 has performed the POST process. If the computer 100 is in the process of performing the POST, the flow proceeds to step S33; if the computer 100 has completed the POST process, the flow proceeds to step S36.

In step S33, the POST information detecting module 102 acquires the POST information code generated by the computer 100 to perform the POST process on the PCH chip 2 through the LPC bus bar 21. In the embodiment, the POST information code is an octal code consisting of a logical digit “0” and a logical digit “1”. For example, if the POST information code generated when the computer 100 detects the memory is “00000000” , it means that the memory detection error; if the generated POST information code is "11111111", it means that the memory detection is successful.

In step S34, the POST information detecting module 102 sends the POST information code to the serial-parallel converter 3 through the GPIO bus bar 31, and assigns a corresponding LED on the LED panel 4 in order for each logical digit in the POST information code. Indicator light 40.

In step S35, the POST information detecting module 102 controls the LED indicator 40 on the LED panel 4 to display the logical digit corresponding to the POST information code by using the serial-parallel converter 3. For example, when the POST information code generated when the computer 100 detects the memory is “11111111”, each LED indicator 40 on the LED panel 4 is displayed as a digit “1”, indicating that the memory detection of the computer 100 is normal. When the POST information code generated when the computer 100 detects the memory is “00000000”, each LED indicator 40 on the LED panel 4 is displayed as a digit “0”, indicating that the memory of the computer 100 is detected incorrectly.

In step S36, the system information detecting module 103 acquires the system status code of the computer 100 in the PCH chip 2 through the LPC bus bar 21. In this embodiment, the system status code is also an octal code consisting of a logical digit “0” and a logical digit “1”. For example, when the system state of the computer 100 is abnormal, the system information detection mode is used. The system status code obtained by the group 103 is "00000000"; when the system status of the computer 100 is normal, the system status code obtained by the system information detecting module 103 is "11111111".

In step S37, the system information detecting module 103 sends the system status code to the serial-parallel converter 3 through the GPIO bus bar 31, and assigns each corresponding logical digit in the system status code to the corresponding LED on the LED panel 4 in order. Indicator light 40.

In step S38, the system information detecting module 103 controls the LED indicator 40 on the LED panel 4 to display the logical digit corresponding to the system status code by using the serial-parallel converter 3. For example, when the system status code of the computer 100 is "11111111", each LED indicator 40 is displayed as a digit "1", indicating that the system state of the computer 100 is normal. When the system status code of the computer 100 is "00000000", each LED indicator 40 is displayed as a digit "0", indicating that the system state of the computer 100 is abnormal, and an error may occur.

In this embodiment, the tester can use the jumper setter 5 to set a jumper on the GPIO 埠 11 to automatically connect to the GPIO 埠 11 during the POST project performed by the computer 100. The jumper detection module 104 immediately detects whether the set jumper is connected to the GPIO port 11. If the jumper is connected to the GPIO port 11, the POST information detecting module 102 controls the LED indicator 40 on the LED panel 4 to display the POST information code by using the serial-parallel converter 3, thereby allowing the tester to understand the POST of the computer 100. If the jumper is not connected to the GPIO 埠 11, the system information detecting module 103 controls the LED indicator 40 on the LED panel 4 to display the system status code by using the serial-parallel converter 3, thereby allowing the tester to understand the computer. 100 system status information.

The above is only the preferred embodiment of the present invention, and has been used in a wide range of applications. Any other equivalent conversion or modification that is not in the spirit of the present invention should be included in the following patent application. Within the scope.

100‧‧‧ computer

1‧‧‧BMC controller

10‧‧‧BIOS debug detection system

101‧‧‧BIOS boot module

102‧‧‧POST Information Detection Module

103‧‧‧System Information Detection Module

104‧‧‧jumper detection module

11‧‧‧GPIO埠

2‧‧‧PCH chip

20‧‧‧BIOS

21‧‧‧LPC bus

3‧‧‧Serial Parallel Converter

31‧‧‧GPIO bus

4‧‧‧LED panel

40‧‧‧LED indicator

5‧‧‧Jumper Setter

6‧‧‧Central processor

no

100‧‧‧ computer

1‧‧‧BMC controller

10‧‧‧BIOS debug detection system

11‧‧‧GPIO埠

2‧‧‧PCH chip

20‧‧‧BIOS

21‧‧‧LPC bus

3‧‧‧Serial Parallel Converter

31‧‧‧GPIO bus

4‧‧‧LED panel

40‧‧‧LED indicator

5‧‧‧Jumper Setter

6‧‧‧Central processor

Claims (10)

A BIOS debug detection system running on a computer, the computer comprising a BMC controller, a PCH chip, a serial-parallel converter and an LED panel, wherein the BIOS debug detection system comprises:
The BIOS boot module is used to start the BIOS when the computer is powered on to perform the POST process of the computer, and to use the BIOS to set the GPIO value of the GPIO on the BMC controller to a low level, and to detect the GPIO value of the GPIO. To determine if the computer is in the process of performing POST;
The POST information detection module, when the computer is in the process of performing POST, acquires the POST information code generated by the computer performing the POST process in the PCH chip, and sends the POST information code to the serial-parallel converter, and each of the POST information codes The logic digits sequentially design a corresponding LED indicator on the LED panel, and the LED indicator on the LED panel is controlled by the serial-parallel converter to display the logical digit corresponding to the POST information code; and the system information detection module is used for After the POST process of the computer has been executed, the system status code of the computer is obtained in the PCH chip, and the system status code is sent to the serial-parallel converter, and each logical digit in the system status code is sequentially designated on the LED panel. The LED indicator and the LED indicator on the LED panel using the serial-parallel converter display the logical digits corresponding to the system status code. For example, the BIOS debug detection system described in claim 1 further includes a system information detection module, and the system information detection module is configured to detect whether a jumper is set on the GPIO port. If the GPIO port is provided with a jumper, the LED indicator on the LED panel is controlled by the serial-parallel converter to display the POST information code. If the GPIO port is not provided with a jumper, the serial parallel is used. The LED indicator on the converter control LED panel displays the system status code. The BIOS debug detection system of claim 2, wherein the jumper is set by using a jumper setter of a computer, and is automatically connected to the GPIO port during a POST project performed by the computer. The BIOS debug detection system of claim 1, wherein the BMC controller is connected to the PCH chip by an LPC bus, and the GPIO bus and the serial-to-parallel converter Connected. The BIOS debug detection system of claim 1, wherein the serial-to-parallel converter is electrically connected to an LED panel, wherein the LED panel is respectively used for displaying logic digits “0” and logic Digital "1" LED indicator. A BIOS debug detection method, which should be implemented in a computer, includes a BMC controller, a PCH chip, a serial-parallel converter, and an LED panel. The method includes the steps of:
When the computer is powered on, the BIOS is started to perform the POST process of the computer, and the GPIO value of the GPIO on the BMC controller is set to a low level by using the BIOS;
Determine whether the computer is in the process of performing POST by detecting the GPIO value of the GPIO埠;
When the computer is in the process of performing POST, the POST information code generated by the computer performing the POST process is acquired in the PCH chip, and the POST information code is sent to the serial-parallel converter, and each logical digit in the POST information code is sequentially in the LED panel. Specifying a corresponding LED indicator, and using the serial-parallel converter to control the LED indicator on the LED panel to display the logical digit corresponding to the POST information code; and when the POST process of the computer has been executed, acquiring the computer in the PCH chip The system status code sends the system status code to the serial-to-parallel converter, assigns each logical digit in the system status code to a corresponding LED indicator on the LED panel in sequence, and controls the LED panel by using a serial-parallel converter. The LED indicator shows the logical digit corresponding to the system status code. For example, the BIOS debugging detection method described in claim 6 of the patent scope further includes the steps of:
Instantly detecting whether a jumper is set on the GPIO port;
If the GPIO port is provided with a jumper, the LED indicator on the LED panel is controlled by the serial-parallel converter to display the POST information code;
If no jumper is set on the GPIO port, the LED status indicator on the LED panel is controlled by the serial-parallel converter to display the system status code. The BIOS debugging detection method according to claim 7, wherein the jumper is set by using a jumper setter of a computer, and is automatically connected to the GPIO port during a POST project performed by the computer. The BIOS debug detection method of claim 6, wherein the BMC controller is connected to the PCH chip by an LPC bus, and the GPIO bus and the serial-to-parallel converter Connected. The BIOS debug detection method according to claim 6, wherein the serial-to-parallel converter is electrically connected to an LED panel, wherein the LED panel is respectively used for displaying logic digits “0” and logic Digital "1" LED indicator.