CN104679626A - System and method for debugging and detecting BIOS (Basic Input / Output System) - Google Patents

Abstract

The invention provides a system and a method for debugging and detecting a BIOS (Basic Input / Output System). The system and the method for debugging and detecting the BIOS are applied to a computer, wherein the computer comprises a BMC (block multiplexer channel) controller, a PCH (Platform Controller Hub) chip, a serial-parallel converter and an LED panel; when the computer performs the POST process, a POST information code generated by the computer performing the POST process is obtained from the PCH chip and the sent to the serial-parallel converter to control an LED indicator light on the LED panel to be displayed; after the computer performs the POST process, a system state code of the computer is obtained from the PCH chip and then sent to the serial-parallel converter to control the LED indicator light on the LED panel to be displayed. With the adoption of the system and the method, testers can directly know the BIOS debugging process.

Description

BIOS debugging detection system and method

technical field

The invention relates to a computer BIOS debugging system and method, in particular to a BMC-based BIOS debugging detection system and method.

Background technique

Based on the needs of debugging BIOS (basic input-output system, basic input and output system), hardware engineers use two methods to debug BIOS when designing servers. One is the COM port, and the other is the power-on self test (POST) LED indicator. In consideration of product safety, the COM port will generally be removed after the product is mass-produced. In this case, driving the LED becomes the only way for the user to understand the operating status of the BIOS and for the maintenance personnel to debug the BIOS. However, at present, the industry mainly uses an external card to display the BIOS by using the power-on detection LED indicator light to debug the BIOS. The external card is a small circuit with a programmable device and a seven-segment rainbow display tube. The design is relatively complicated. Each motherboard must be equipped with a connector, which causes a waste of electronic components. In addition, every time there is a problem with the server startup, it must be shut down and then connected to an external card for debugging. However, for some random problems, it may be difficult to reproduce after shutdown, causing inconvenience in debugging.

Contents of the invention

In view of the above, it is necessary to provide a BIOS debugging detection system and method, which can automatically display the POST information code of the computer and the system status code of the computer on the LED indicator light, so that testers can intuitively understand the BIOS debugging process .

The described BIOS debugging detection system runs in a computer, and the computer includes a BMC controller, a PCH chip, a serial-parallel converter and an LED panel. The system includes: a BIOS startup module, which is used to start the BIOS to perform the POST process of the computer when the computer is turned on, utilize the BIOS to set the GIPO value of the GIPO port on the BMC controller to a low level, and detect the GIPO port The GIPO value is used to judge whether the computer is in the process of executing POST; the POST information detection module, when the computer is in the process of executing POST, obtains the POST information code generated by the computer executing the POST process from the PCH chip, and sends the POST information code to the serial and parallel The converter assigns each logical number in the POST information code to a corresponding LED indicator on the LED panel in order, and uses the serial-parallel converter to control the LED indicator on the LED panel to display the logical number corresponding to the POST information code; The system information detection module is used to obtain the system status code of the computer from the PCH chip when the POST process of the computer has been executed, send the system status code to the serial-parallel converter, and convert each logical number in the system status code Specify a corresponding LED indicator on the LED panel in order, and use the serial-parallel converter to control the LED indicator on the LED panel to display the logic number corresponding to the system status code.

The described BIOS debugging detection method should be implemented in a computer, and the computer includes a BMC controller, a PCH chip, a serial-parallel converter and an LED panel. The method comprises steps: when the computer is turned on, the BIOS is started to perform the POST process of the computer, and the GIPO value of the GIPO port on the BMC controller is set to a low level by using the BIOS; by detecting the GIPO value of the GIPO port, it is judged whether the computer is In the process of executing POST; when the computer is in the process of executing POST, obtain the POST information code generated by the computer executing the POST process from the PCH chip, send the POST information code to the serial-parallel converter, and convert each logic in the POST information code Numbers specify a corresponding LED indicator on the LED panel in order, and use the serial-parallel converter to control the LED indicator on the LED panel to display the logical number corresponding to the POST information code; The chip obtains the system status code of the computer, sends the system status code to the serial-parallel converter, assigns each logical number in the system status code to a corresponding LED indicator on the LED panel in sequence, and uses the serial-parallel converter The LED indicators on the control LED panel display the logical numbers corresponding to the system status codes.

Compared with the prior art, the BIOS debugging detection system and method described in the present invention, when utilizing the BIOS to carry out the POST process to the computer, the method can automatically obtain the POST information code and display it on the LED indicator light; when the computer After the power-on self-test test is completed, the system status code of the computer can be automatically obtained and displayed on the LED indicator light, so that the tester can intuitively understand the BIOS debugging process.

Description of drawings

FIG. 1 is a schematic diagram of the operating environment of a preferred embodiment of the BIOS debugging and detection system of the present invention.

FIG. 2 is a functional block diagram of the BIOS debugging detection system of the present invention.

FIG. 3 is a flow chart of a preferred embodiment of the BIOS debugging detection method of the present invention.

Description of main component symbols

computer 100

BIOS debugging detection system 10

BIOS boot module 101

POST information detection module 102

System information detection module 103

Jumper detection module 104

GIPO port 11

PCH chip 2

BIOS 20

LPC bus 21

Series Parallel Converter 3

GPIO bus 31

LED panel 4

LED Indicator 40

Jumper Setter 5

CPU 6

Detailed ways

Referring to FIG. 1 , it is a schematic view of the operating environment of a preferred embodiment of the BIOS debugging and detection system 10 of the present invention. In the present embodiment, the BIOS debugging detection system 10 is installed and operated in a computer 100, which includes a BMC (Base management controller) controller 1, a south bridge (Platform controller hub, PCH) chip 2, series-parallel Converter (Switch) 3, LED panel 4, jumper setting device 5, and central processing unit (CPU) 6. The BMC controller 1 is connected with the PCH chip 2 through the LPC (Low Pin Count) bus 21, and connected with the serial-parallel converter 3 through the GPIO bus 31. The series-parallel converter 3 is electrically connected to the LED panel 4, the LED panel 4 is composed of eight LED indicator lights 40 respectively used to display the logic number "0" and the logic number "1", each LED indicator light 40 is a seven-segment LED display tube. In this embodiment, the computer 100 may be a personal computer (PC), a workstation computer (Workstation computer), a notebook computer (Notebook), a server (Server) or other electronic computing devices.

The BMC controller 1 also includes a GIPO port 11 , and the jumper setter 5 is used to set a jumper to connect to the GIPO port 11 . The PCH chip 2 includes a basic input-output system (basic input-output system, BIOS) 20, and the BIOS 20 performs a Power On Self Test (POST) program on the computer 100 and guides the computer 100 to normally import the operating system (OS ) to complete the entire boot process.

Referring to FIG. 2 , it is a functional block diagram of the BIOS debugging detection system 10 of the present invention. In this embodiment, the BIOS debugging detection system 10 includes a BIOS startup module 101 , a POST information detection module 102 , a system information detection module 103 and a jumper wire detection module 104 . The functional module referred to in the present invention refers to a series of program instruction segments that can be executed by the central processing unit 6 of the computer 100 and can complete fixed functions, which are stored in the Flash memory (such as Flash ROM) of the BMC controller 1 . Each functional module 201-204 will be described in detail in the flowchart of FIG. 3 .

Referring to FIG. 3 , it is a flow chart of a preferred embodiment of the BIOS debugging detection method of the present invention. In this embodiment, the method is applied to the computer 100 , and the method can automatically obtain the POST information code and display it on the LED indicator 40 when the BIOS 20 is used to perform the POST debugging on the computer 100 . After the computer 100 completes the POST test, the method can automatically obtain the system status code of the computer 100 and display it on the LED indicator light 40, so that testers can intuitively understand the BIOS debugging process.

Step S31 , when the computer 100 is turned on, the BIOS startup module 101 starts the BIOS 20 to execute the POST process of the computer 100 , and uses the BIOS 20 to set the GIPO value of the GIPO port 11 to a low level. In this embodiment, the low level is set to logic "0", and the high level is set to logic "1". After the POST process is completed, the BIOS startup module 101 automatically sets the GIPO value of the GIPO port 11 to a high level.

Step S32 , the BIOS startup module 101 judges whether the computer 100 is in the process of executing POST by detecting the GIPO value of the GIPO port 11 . In this embodiment, when the GIPO value of the GIPO port 11 is low, the BIOS startup module 101 determines that the computer 100 is executing the POST process; if the GIPO value of the GIPO port 11 is high, the BIOS startup module 101 determines that the computer 100 The POST process has been executed. If the computer 100 is executing the POST process, then the process turns to step S33; if the computer 100 has finished executing the POST process, then the process turns to step S36.

Step S33 , the POST information detection module 102 obtains the POST information code generated by the computer 100 executing the POST process from the PCH chip 2 through the LPC bus 21 . In this embodiment, the POST information code is an octal code composed of a logical number "0" and a logical number "1". For example, if the POST information code generated when the computer 100 detects the memory is "00000000", It means that the memory detection error; if the generated POST information code is "11111111", it means that the memory detection is successful.

Step S34, the POST information detection module 102 sends the POST information code to the serial-parallel converter 3 through the GIPO bus 31, and assigns each logical number in the POST information code to a corresponding LED indicator light on the LED panel 4 in sequence 40.

In step S35 , the POST information detection module 102 controls the LED indicator 40 on the LED panel 4 to display the logical number corresponding to the POST information code by using the serial-to-parallel converter 3 . For example, when the POST information code generated when the computer 100 detects the internal memory is "11111111", each LED indicator 40 on the LED panel 4 displays a number "1", indicating that the internal memory of the computer 100 is detected normally. When the computer 100 detects the internal memory, the POST information code is "00000000", and each LED indicator light 40 on the LED panel 4 displays a number "0", indicating that the internal memory of the computer 100 is detected incorrectly.

Step S36 , the system information detection module 103 obtains the system status code of the computer 100 from the PCH chip 2 through the LPC bus 21 . In this embodiment, the system status code is also an octal code composed of a logic number "0" and a logic number "1". For example, when the system status of the computer 100 is abnormal, the system information detection module The system status code acquired by 103 is "00000000"; when the system status of the computer 100 is normal, the system status code acquired by the system information detection module 103 is "11111111".

Step S37, the system information detection module 103 sends the system status code to the serial-parallel converter 3 through the GIPO bus 31, and assigns each logical number in the system status code to a corresponding LED indicator light on the LED panel 4 in sequence 40.

Step S38 , the system information detection module 103 uses the serial-to-parallel converter 3 to control the LED indicator 40 on the LED panel 4 to display the logical number corresponding to the system status code. For example, when the system status code of the computer 100 is "11111111", each LED indicator light 40 displays a number "1", indicating that the system status of the computer 100 is normal. When the system status code of the computer 100 is "00000000", each LED indicator light 40 displays the number "0", indicating that the system status of the computer 100 is not normal and an error may occur.

In this embodiment, the tester can use the jumper setter 5 to set a jumper on the GIPO port 11, and automatically connect to the GIPO port 11 when the computer 100 executes the POST project. The jumper detection module 104 detects in real time whether the set jumper is connected to the GIPO port 11 . If the jumper is connected to the GIPO port 11, the POST information detection module 102 utilizes the serial-parallel converter 3 to control the LED indicator light 40 on the LED panel 4 to display the POST information code, thereby allowing testers to understand the POST information of the computer 100 ; If the jumper is not connected to the GIPO port 11, the system information detection module 103 utilizes the serial-parallel converter 3 to control the LED indicator light 40 on the LED panel 4 to display the system status code, thereby allowing testers to understand the status of the computer 100 System status information.

The above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the above preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced All should not deviate from the spirit and scope of the technical solution of the present invention.

Claims (10)

1. BIOS debugs a detecting system, and run in computing machine, this computing machine comprises BMC controller, PCH chip, serial parallel converter and LED panel, it is characterized in that, described BIOS debugs detecting system and comprises:

BIOS starts module, opening computer self-inspection POST process is performed for starting BIOS when computer booting, utilize BIOS that the GIPO value of the GIPO port on BMC controller is set to low level, and judge whether computing machine is in execution POST process by the GIPO value detecting GIPO port;

POST information detecting module, perform in POST process when computing machine is in, the POST information code that computing machine execution POST process produces is obtained from PCH chip, POST information code is sent to serial parallel converter, each logic numeral in POST information code is specified in order in LED panel the LED light that corresponding, and utilize the serial parallel converter LED light controlled in LED panel to show logic numeral corresponding to POST information code; And

System information detecting module, for when the POST process of computing machine is finished, system for computer status code is obtained from PCH chip, system state code is sent to serial parallel converter, each logic numeral in system state code is specified in order in LED panel the LED light that is corresponding, and the logic numeral utilizing the LED light display system status code in serial parallel converter control LED panel corresponding.

2. BIOS as claimed in claim 1 debugs detecting system, it is characterized in that, this system also comprises system information detecting module, whether this system information detecting module is provided with wire jumper on GIPO port described in detecting real-time, if described GIPO port is provided with wire jumper, the LED light then utilizing serial parallel converter to control in LED panel shows described POST information code, if described GIPO port does not arrange wire jumper, then the LED light utilizing serial parallel converter to control in LED panel shows described system state code.

3. BIOS as claimed in claim 2 debugs detecting system, it is characterized in that, described wire jumper utilizes the wire jumper of computing machine to arrange device to arrange, and be automatically connected on described GIPO port in computing machine execution POST engineering.

4. BIOS as claimed in claim 1 debugs detecting system, and it is characterized in that, described BMC controller is connected with described PCH chip by lpc bus, and is connected with described serial parallel converter by GPIO bus.

5. BIOS as claimed in claim 1 debugs detecting system, and it is characterized in that, described serial parallel converter is electrically connected in LED panel, and this LED panel is made up of the LED light that eight are respectively used to display logic digital " 0 " and logic numeral " 1 ".

6. BIOS debugs a method for detecting, and should go in computing machine, this computing machine comprises BMC controller, PCH chip, serial parallel converter and LED panel, and it is characterized in that, the method comprising the steps of:

Start BIOS when computer booting and perform opening computer self-inspection POST process, utilize BIOS that the GIPO value of the GIPO port on BMC controller is set to low level;

Judging whether computing machine is in by the GIPO value detecting GIPO port performs in POST process;

Perform in POST process when computing machine is in, the POST information code that computing machine execution POST process produces is obtained from PCH chip, POST information code is sent to serial parallel converter, each logic numeral in POST information code is specified in order in LED panel the LED light that corresponding, and utilize the serial parallel converter LED light controlled in LED panel to show logic numeral corresponding to POST information code; And

When the POST process of computing machine is finished, system for computer status code is obtained from PCH chip, system state code is sent to serial parallel converter, each logic numeral in system state code is specified in order in LED panel the LED light that is corresponding, and the logic numeral utilizing the LED light display system status code in serial parallel converter control LED panel corresponding.

7. BIOS as claimed in claim 6 debugs method for detecting, and it is characterized in that, the method also comprises step:

Whether GIPO port described in detecting real-time is provided with wire jumper;

If described GIPO port is provided with wire jumper, then the LED light utilizing serial parallel converter to control in LED panel shows described POST information code;

If described GIPO port does not arrange wire jumper, then the LED light utilizing serial parallel converter to control in LED panel shows described system state code.

8. BIOS as claimed in claim 7 debugs method for detecting, it is characterized in that, described wire jumper utilizes the wire jumper of computing machine to arrange device to arrange, and be automatically connected on described GIPO port in computing machine execution POST engineering.

9. BIOS as claimed in claim 6 debugs method for detecting, and it is characterized in that, described BMC controller is connected with described PCH chip by lpc bus, and is connected with described serial parallel converter by GPIO bus.

10. BIOS as claimed in claim 6 debugs method for detecting, it is characterized in that, described serial parallel converter is electrically connected in LED panel, and this LED panel is made up of the LED light that eight are respectively used to display logic digital " 0 " and logic numeral " 1 ".