TW201517338A - Resistive memory device and fabrication thereof - Google Patents

Abstract

A resistive memory device is disclosed. A substrate is provided. A bottom electrode is disposed over the substrate. A bottom resistive switching layer is on the bottom electrode layer. An interfacial layer is between the bottom electrode layer and the bottom electrode. A top resistive switching layer is on the bottom resistive switching layer. A top electrode is on the top resistive switching layer.

Description

Resistive memory device and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a resistive memory and a method of fabricating the same.

In recent years, flash memory has faced problems such as miniature physical limit and excessive operating voltage. Therefore, a resistive memory device with simple structure, small area, fast operation speed and low power consumption (Resistive random access) Memory, or RRAM for short, is very likely to replace traditional flash memory and become the mainstream of next generation non-volatile memory.

The resistive memory system uses the change of resistance value to achieve the memory effect. The transition mechanism of the resistive memory is to use oxygen vacancies or oxygen ions to form a conductive filament, using external application. Voltage polarity and current values cause the conduction path to break and regenerate, resulting in a difference in resistance values.

Resistive memory has excellent memory operation characteristics such as low voltage operation, low power consumption, and high density stacked structure. However, resistive memory performs endurance or repeated write/erase (program/Erase) When the high and low resistance states are changed, the high and low resistance resistance values of the resistive memory cannot be maintained in a stable state, and the memory state interpretation error is likely to occur, and the resistance type is changed. Recall that the body is hindered by mass production.

According to the above, the industry needs a resistive memory and related manufacturing method that can solve the above problems.

According to the above, the present invention provides a resistive memory device comprising: a substrate; a lower electrode located above the substrate; a lower resistance transition layer on the lower electrode; and an interface layer between the lower resistance transition layer and the lower electrode An upper resistive layer is disposed on the lower resistive transition layer; and an upper electrode is disposed on the upper resistive transition layer.

The invention provides a method for manufacturing a resistive memory device, comprising: providing a substrate; forming a lower electrode on the substrate; forming a resistive transition layer on the lower electrode; performing an annealing process on the lower electrode and the lower resistance state Forming an interface layer between the layers; forming an upper resistance transition layer on the lower resistance transition layer; and forming an upper electrode on the upper resistance transition layer.

102‧‧‧Substrate

104‧‧‧Insulation

106‧‧‧Adhesive layer

108‧‧‧ Conductive layer

110‧‧‧ lower electrode

112‧‧‧resistive transition layer

114‧‧‧Upper electrode

115‧‧‧Oxygen vacancies

116‧‧‧Interfacial layer

118‧‧‧ Lower resistance transition layer

120‧‧‧Upper resistance transition layer

122‧‧‧ conductive path

124‧‧‧ conductive path

Figure 1 shows a cross-sectional view of a resistive memory.

Fig. 2 is a graph showing the relationship between the endurance test current and the number of cycles of the write and erase voltages of the resistive memory of Fig. 1.

Fig. 3 is a cross-sectional view showing a resistive memory according to an embodiment of the present invention.

4A to 4C are views showing the transition mechanism of the resistive memory according to an embodiment of the present invention.

Fig. 5 is a view showing a voltage-current relationship diagram of a resistive memory according to an embodiment of the present invention.

Fig. 6 is a graph showing the voltage-current relationship of a resistive memory of a comparative example.

Fig. 7 is a view showing a voltage-current relationship diagram of a resistive memory in which a bias voltage is continuously applied for 100 times in an embodiment of the present invention.

Figure 8 is a graph showing the durability test distribution of a resistive memory structure according to an embodiment of the present invention for applying a DC write and erase voltage.

FIG. 9 is a diagram showing the relationship between the endurance test current and the number of cycles of the alternating current writing and erasing voltages applied to the resistive memory structure according to an embodiment of the present invention.

Fig. 10 is a graph showing the durability test of the resistive memory according to an embodiment of the present invention.

Figure 11 is a non-destructive read test curve diagram of a resistive memory structure according to an embodiment of the present invention.

Embodiments embodying the invention are discussed in detail below. It will be appreciated that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of variations. The specific embodiments discussed are merely illustrative of specific ways to use the embodiments and are not intended to limit the scope of the invention. In order to make the features of the present invention more comprehensible, the following detailed description of the embodiments, together with the accompanying drawings, will be described in detail below. The following describes a method of fabricating a resistive memory according to FIG. Referring to FIG. 1, a substrate 102 is provided to form an insulating layer 104 of germanium dioxide on the substrate 102. Next, an adhesion layer 106 of titanium is formed on the insulating layer 104 to form a conductive layer 108 of platinum on the adhesion layer 106. The titanium nitride lower electrode 110 is formed on the conductive layer 108. Formation of erbium oxide resistance The layer is on the lower electrode 110. An upper surface of the tantalum nitride electrode 114 is formed on the resistive transition layer 112. Figure 2 shows the endurance test of the write and erase voltages of the resistive memory of Figure 1. As shown in Fig. 2, the resistance values of the high resistance and low resistance states of the resistive memory device are too large, and the interval between the high resistance and the low resistance is not obvious, indicating that the durability test is not satisfactory.

In accordance with the above, the present invention provides a resistive memory device having two layers of resistive transition layers and annealed the lower resistive transition layer to form an interfacial layer between the lower electrode and the lower resistive transition layer.

Hereinafter, a method of fabricating a resistive memory according to an embodiment of the present invention will be described based on FIG. Referring to FIG. 3, a substrate 102 is provided. Any desired semiconductor device, such as a transistor, a resistor, a logic device, etc., can be formed over the substrate 102. However, for the sake of simplicity of the drawing, only the planar substrate 102 is shown. In the context of the present invention, the term "substrate" includes both formed devices on a semiconductor wafer and various coatings overlying the wafer; the term "substrate surface" includes the exposed uppermost layer of the semiconductor wafer. For example, wafer surface, insulating layer, metal wire, and the like. The substrate may be a germanium substrate, germanium, gallium arsenide, gallium nitride, strain enthalpy, germanium, tantalum carbide, diamond, and/or other materials on the insulating layer.

An insulating layer 104 is formed on the substrate 102. In some embodiments, the insulating layer 104 is hafnium oxide or tantalum nitride. In some examples, the insulating layer 104 is hafnium oxide. The insulating layer 104 may be formed in the furnace tube by thermal oxidation, and the insulating layer 104 may have a thickness of 100 nm to 300 nm. Thereafter, an adhesion layer 106 and a conductive layer 108 are formed on the insulating layer 104. The adhesion layer 106 may include titanium, titanium nitride, tantalum or tantalum nitride, and the conductive layer 108 may include platinum, titanium, nitrogen. Titanium, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium, indium tin oxide or aluminum beryllium copper alloy. In some examples, the adhesion layer 106 is titanium and the conductive layer 108 is platinum. The adhesion layer 106 and the conductive layer 108 may be formed by an alternating current magnetron sputtering method, a direct current sputtering method, an atomic layer deposition system, or an electron beam evaporation method.

Thereafter, the lower electrode 110 is formed on the conductive layer 108. The lower electrode 110 may be titanium, titanium nitride, aluminum, tungsten, tantalum, hafnium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium, indium tin oxide or heavily doped germanium semiconductor. The lower electrode 110 can be formed by an alternating current magnetron sputtering method, an atomic layer deposition system, or an electron beam evaporation method. The thickness of the lower electrode 110 may be from 1 nm to 500 nm, preferably from 10 nm to 50 nm. In some embodiments, the lower electrode 110 is titanium nitride. In some examples, the lower electrode 110 can be formed using an atomic layer deposition system using tetramethylammonium titanium (TDMAT) as a precursor and a nitrogen plasma to react with tetramethylammonium.

Subsequently, a resistive transition layer 118 is formed over the lower electrode 110. In some embodiments, the lower resistive transition layer 118 is hafnium oxide, aluminum oxide, titanium dioxide, zirconium dioxide, tin oxide or zinc oxide. The lower resistance transition layer 118 can be formed by alternating current sputtering deposition, and the temperature can be from 100 ° C to 500 ° C. The lower resistance transition layer 118 may have a thickness of 1 nm to 100 nm.

Subsequently, the lower resistance transition layer 118 is subjected to an annealing treatment under an oxygen atmosphere to form an interface layer 116 between the lower electrode 110 and the lower resistance transition layer 118. The thickness of the interface layer 116 can be from 1 nm to 10 nm. The annealing temperature may be from 200 ° C to 600 ° C. Annealing can be carried out using a furnace tube, a rapid thermal annealing device or a temperature-increasing sputtering machine. The oxygen flow rate can range from about 10 sccm to about 50 sccm, the pressure can range from about 0.1 Torr to about 0.5 Torr, and the process time can range from about 10 minutes to about 60 minutes. The interface layer 116 may be a layer formed by the reaction of oxygen with the lower electrode 110 in the annealing process. In another embodiment, the interface layer 116 may be a layer formed by the reaction of the lower resistance transition layer 118 and the lower electrode 110 in the annealing process. In the example where the lower electrode is titanium nitride, the interface layer 116 may be titanium oxynitride.

The present invention is not particularly limited to the step of performing an annealing treatment after the lower resistance transition layer 118. In one embodiment, the annealing treatment may be performed after the formation of the lower electrode 110 before the formation of the lower resistance transition layer 118. An additional annealing step can be performed after forming the lower resistance transition layer 118. Furthermore, the present invention is not limited to the above annealing step in an oxygen atmosphere, and in another embodiment, the present invention can be carried out under an atmosphere of nitrogen or another gas such as ammonia or nitrous oxide gas.

Thereafter, an upper resistive transition layer 120 is formed on the lower resistive transition layer 118. In some embodiments, the upper resistive transition layer 120 is ceria, alumina, titania, zirconia, tin oxide or zinc oxide. The upper resistive transition layer 120 can be formed by alternating current sputtering deposition, and the temperature can be from 100 ° C to 500 ° C. In some embodiments, the upper resistive transition layer 120 is zirconium dioxide (ZrO ₂ ). The upper resistance transition layer 120 may have a thickness of 1 nm to 100 nm.

Next, an upper electrode 114 is formed on the upper resistance transition layer 120. The upper electrode 114 may be titanium, titanium nitride, aluminum, tungsten, tantalum, hafnium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium or indium tin oxide. The upper electrode 114 can be formed by an alternating current magnetron sputtering method, a direct current sputtering method, an atomic layer deposition system, or an electron beam evaporation method. The thickness of the upper electrode 114 may be 1 nm to 1000 nm. It is preferably 10 nm to 50 nm. The upper electrode 114 can be patterned using a lithography process.

Hereinafter, the transition mechanism of the resistive memory according to an embodiment of the present invention will be described based on the voltage current relationship diagrams of FIGS. 4A-4C and FIG. First, referring to FIG. 4A, after the lower resistance transition layer 118 and the upper resistance transition layer 120 are formed, and before the voltage is applied, the lower resistance transition layer 118 and the upper resistance transition layer 120 include oxygen vacancies 115, but No conductive path (or known as a conductive filament) is formed. Subsequently, referring to FIG. 4B and FIG. 5, when a negative DC bias is applied to the lower electrode 110, and the upper electrode 114 is grounded, the current rises as the voltage increases, and when the current rises to a compliance current (compliance current) At 1 mA), the bias voltage is the first forming voltage, and the device resistance value is switched from the original high resistance initial state to the high resistance state (HRS). This is the first formation process, the conductive path 122 is formed in the upper resistance transition layer 120, and since the interface layer 116 is relatively dense, no conductive path is formed therein, thereby causing the device not to reach a low resistance state (low resistance state, referred to as LRS).

Next, referring to FIG. 4C and FIG. 5, the device is subjected to a positive bias operation (ie, a positive DC bias is applied to the lower electrode 110 and the upper electrode 114 is grounded), and the current rises as the voltage increases. When rising to a compliance current (1 mA), the bias voltage is the second time the voltage is formed. At this time, the conductive path 124 is generated in the interface layer 116 of the device, so that the resistance value of the device is switched from the high resistance state to the high resistance state. Low resistance state.

After the negative bias operation, the bias is applied to the lower electrode from 0. V continuously changes to -1 V. When the applied bias voltage reaches -1 V, the current value starts to decrease, indicating that the resistance value of the device rises as the negative bias voltage increases. After continuously applying a negative bias voltage to -1.8V, the device has a higher resistance value, and then the applied bias voltage is changed from -2V to 0V, and a voltage-current when a bias voltage is applied from 0V to -1.8V is obtained. The curve differs from -1.8V to 0V, indicating that the device transitions from a low resistance state to a high resistance state.

Fig. 6 is a graph showing the voltage-current relationship of a resistive memory in a comparative example (without annealing the lower resistance transition layer). Referring to FIG. 6, if the lower resistance transition layer 118 is not annealed, an interface layer (ie, the interface layer 116 of FIG. 3) is formed. When a voltage (-2V) is applied to turn the device into a low resistance state, The device will crash, so the device cannot perform subsequent transitions.

Fig. 7 is a result of applying a bias voltage continuous cycle of 0V~1.5V~0V~-2V~0V for 100 times in the resistive memory structure of the embodiment of Fig. 2, which shows that when the read voltage is 0.3V, It has two different resistance states: high current value (0.6mA) and low current value (20μA). Therefore, the size of the bias can be controlled to cause the device to generate a resistance conversion for memory purposes, and the high and low resistance states can maintain a stable memory state without an external power supply.

Fig. 8 is a graph showing the relationship between the endurance test current and the number of cycles of the resistive memory structure of the embodiment of Fig. 2 when the DC write and erase voltages are applied. The measurement condition is that a bias is applied to the upper electrode of the device, and the lower electrode of the device is grounded, wherein the high resistance state and the low resistance state both read the high and low resistance state current values under the bias voltage of 0.3V, and the root value is obtained. According to Fig. 8, in the continuous transition operation of more than 10,000 times, the resistance ratio of the high resistance state to the low resistance state is still more than 10 times.

Fig. 9 is a graph showing the relationship between the endurance test current and the number of cycles of the alternating current writing and erasing voltages applied to the resistive memory structure of the second embodiment. The measurement condition is that a bias is applied to the electrode on the device, and the lower electrode of the device is grounded, wherein the high resistance state and the low resistance state are both read at a bias voltage of 0.3 V, and the current value of the high and low resistance states is read. The pulse voltage values were 3 V and -3.3 V, respectively, and the pulse width was 40 nm-second. Apparatus of the present embodiment operate in a continuous transient more than ¹⁰⁷ times, the resistance of the high resistance state and a low resistance state ratio is still more than 10 times, and high and low resistance current state no significant changes.

Figure 10 is a retention test of the resistive memory of the embodiment of Fig. 2, the device is respectively switched to a low resistance and high resistance memory state, and then in a low resistance and high resistance memory state, every other segment The time reads the current values of the two memory states at a voltage of 0.3 V. The result shows that the data can be read correctly after being placed at 850 ° C for 10,000 seconds without any deterioration of memory characteristics, and the memory states have more than 10 times. Resistance ratio.

Figure 11 is a non-destructive read test of the resistive memory structure of the embodiment of Figure 2, after the device is switched to a low resistance and high resistance memory state, in a low resistance and high resistance memory state. Continuously applying a bias voltage of 0.3V to the upper electrode, and reading the current values of the two memory states at a voltage of 0.3 V every 10 seconds, and the result shows that the data can be correctly read after being placed for 10000 seconds at a temperature of 85 ° C and No deterioration of memory characteristics occurs, and there is a resistance ratio greater than 10 times between the low resistance and high resistance memory states.

According to the above, the resistive memory structure of the embodiment of the present invention has less variation in high resistance and low resistance state, and can effectively improve the durability of the resistive memory.

Although the preferred embodiments of the present invention are described above, it is not intended to limit the present invention, and any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

102‧‧‧Substrate

104‧‧‧Insulation

106‧‧‧Adhesive layer

108‧‧‧ Conductive layer

110‧‧‧ lower electrode

114‧‧‧Upper electrode

116‧‧‧Interfacial layer

118‧‧‧ Lower resistance transition layer

120‧‧‧Upper resistance transition layer

Claims (13)

A resistive memory device comprising: a substrate; a lower electrode located above the substrate; a lower resistance transition layer on the lower electrode; an interface layer between the lower resistance transition layer and the lower electrode; An upper resistive transition layer is disposed on the lower resistive transition layer; and an upper electrode is disposed on the upper resistive transition layer. The resistive memory device of claim 1, wherein the interface layer is titanium oxynitride or hafnium oxynitride. The resistive memory device of claim 1, wherein the interface layer has a thickness of between 1 nm and 10 nm. The resistive memory device of claim 1, wherein the lower electrode comprises titanium, titanium nitride, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium, Indium tin oxide or heavily doped germanium semiconductor. The resistive memory device of claim 1, wherein the lower resistance layer comprises cerium oxide, aluminum oxide, titanium dioxide, zirconium dioxide, tin oxide or zinc oxide. The resistive memory device of claim 1, wherein the lower resistance layer is cerium oxide, and the upper resistance layer is zirconium dioxide. The resistive memory device of claim 1, wherein the lower resistance layer has a thickness of 1 nm to 100 nm. The resistive memory device of claim 1, wherein the lower electrode has a thickness of between 1 nm and 500 nm. A method for fabricating a resistive memory device includes: providing a substrate; forming a lower electrode over the substrate; forming a resistive transition layer on the lower electrode; performing an annealing process on the lower electrode and the lower resistor Forming an interface layer between the layers; forming an upper resistance transition layer on the lower resistance transition layer; and forming an upper electrode on the upper resistance transition layer. The method for fabricating a resistive memory device according to claim 9, wherein the annealing process has a temperature of 200 ° C to 600 ° C. The method for fabricating a resistive memory device according to claim 9, wherein the annealing process is performed under an atmosphere of oxygen, ammonia or nitrous oxide. The method for fabricating a resistive memory device according to claim 9, wherein the annealing process is performed under an oxygen atmosphere, and the oxygen flow rate is 10 sccm to 50 sccm. The method of fabricating a resistive memory device according to claim 9, wherein the annealing process has a pressure of between 0.1 Torr and 0.5 Torr.