TW201445644A - Method for manufacturing semiconductor package - Google Patents
Method for manufacturing semiconductor package Download PDFInfo
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- TW201445644A TW201445644A TW102118395A TW102118395A TW201445644A TW 201445644 A TW201445644 A TW 201445644A TW 102118395 A TW102118395 A TW 102118395A TW 102118395 A TW102118395 A TW 102118395A TW 201445644 A TW201445644 A TW 201445644A
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- Prior art keywords
- carrier
- semiconductor package
- reinforcing structure
- disposed
- adhesive layer
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims description 13
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 9
- 238000005728 strengthening Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 44
- 239000012790 adhesive layer Substances 0.000 claims description 41
- 230000003014 reinforcing effect Effects 0.000 claims description 41
- 239000005022 packaging material Substances 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 6
- 239000005001 laminate film Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 230000008569 process Effects 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Manufacturing & Machinery (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Wire Bonding (AREA)
Abstract
Description
本發明係關於一種半導體封裝件之製法，特別是指一種具有強化結構之半導體封裝件之製法。 The present invention relates to a method of fabricating a semiconductor package, and more particularly to a method of fabricating a semiconductor package having a reinforced structure.
隨著半導體技術之日新月異與半導體製程之快速演進，對於形成有封裝膠體之半導體封裝件而言，其在通過烘烤製程後容易產生翹曲(warpage)之情形，使得後續之線路重佈及切單製程難以進行，導致降低該半導體封裝件之良率，因此如何避免該半導體封裝件發生翹曲，以提升該半導體封裝件之良率實為重要的課題。 With the rapid development of semiconductor technology and the rapid evolution of semiconductor processes, for the formation of semiconductor packages with encapsulants, it is prone to warpage after the baking process, so that the subsequent lines are redeployed and cut. The single process is difficult to perform, resulting in a reduction in the yield of the semiconductor package. Therefore, how to avoid warpage of the semiconductor package to improve the yield of the semiconductor package is an important issue.
第1A圖至第1D圖係繪示習知技術之半導體封裝件之製法之剖視示意圖。 1A to 1D are cross-sectional views showing a method of fabricating a semiconductor package of the prior art.
如第1A圖所示，先依序形成剝離層(release layer)11與黏著層(adhesive layer)12於載體10上。 As shown in FIG. 1A, a release layer 11 and an adhesive layer 12 are sequentially formed on the carrier 10.
如第1B圖所示，設置具有銲墊131之晶片13於該黏著層12上。 As shown in FIG. 1B, a wafer 13 having a pad 131 is provided on the adhesive layer 12.
如第1C圖所示，形成封裝膠體14於該黏著層12上，以包覆該晶片13。 As shown in FIG. 1C, an encapsulant 14 is formed on the adhesive layer 12 to coat the wafer 13.
如第1D圖所示，對該載體10、剝離層11、黏著層12與封裝膠體14等進行烘烤。 The carrier 10, the peeling layer 11, the adhesive layer 12, the encapsulant 14 and the like are baked as shown in Fig. 1D.
上述製法之缺點，在於第1D圖之烘烤製程後，該載體10、剝離層11、黏著層12與封裝膠體14等容易產生翹曲之情形，使得後續難以進行線路重佈及切單製程，導致降低該半導體封裝件之良率。 The disadvantage of the above method is that after the baking process of FIG. 1D, the carrier 10, the peeling layer 11, the adhesive layer 12 and the encapsulant 14 are easily warped, so that it is difficult to carry out the line redistribution and the singulation process. This results in a reduction in the yield of the semiconductor package.
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件之製法，其包括：提供具有第一表面之第一承載件、具有作用面之半導體元件與第一強化結構，該半導體元件係以該作用面設置於該第一承載件之第一表面上，該第一強化結構係設置於該第一承載件之第一表面上；形成封裝材料於該第一承載件之第一表面上，以包覆該半導體元件並外露出該第一強化結構；以及對該第一承載件、封裝材料與第一強化結構進行烘烤。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a method of fabricating a semiconductor package, comprising: providing a first carrier having a first surface, a semiconductor component having an active surface, and a first reinforced structure, the semiconductor component The first reinforcing structure is disposed on the first surface of the first carrier; the encapsulating material is formed on the first surface of the first carrier And covering the semiconductor element and exposing the first reinforcing structure; and baking the first carrier, the encapsulating material and the first reinforcing structure.
該第一承載件可具有第一載體、第一剝離層與第一黏著層，該第一剝離層與該第一黏著層係依序形成於該第一載體上，該半導體元件與該第一強化結構係設置於該第一黏著層上，該封裝材料係形成於部分該第一黏著層上。 The first carrier may have a first carrier, a first release layer and a first adhesive layer, and the first adhesive layer and the first adhesive layer are sequentially formed on the first carrier, the semiconductor component and the first The reinforcing structure is disposed on the first adhesive layer, and the encapsulating material is formed on a portion of the first adhesive layer.
該第一強化結構可為金屬框，並設置於該第一承載件之第一表面之周圍上。該封裝材料可為封裝膠體或層壓膜。 The first reinforcing structure may be a metal frame and disposed on a periphery of the first surface of the first carrier. The encapsulating material can be an encapsulant or a laminate film.
該半導體封裝件之製法可包括：提供具有第二表面之 第二承載件與第二強化結構，該第二強化結構係設置於該第二承載件之第二表面上；以及以該第二表面將該第二承載件設置於該封裝材料之頂面上。 The method of fabricating the semiconductor package may include: providing a second surface a second carrier and a second reinforcing structure, the second reinforcing structure is disposed on the second surface of the second carrier; and the second carrier is disposed on the top surface of the packaging material by the second surface .
該第二承載件可具有第二載體、第二剝離層與第二黏著層，該第二剝離層與該第二黏著層係依序形成於該第二載體上，該第二強化結構係設置於該第二黏著層上，該第二承載件係以該第二黏著層設置於該封裝材料之頂面上。 The second carrier may have a second carrier, a second release layer and a second adhesive layer, and the second adhesive layer and the second adhesive layer are sequentially formed on the second carrier, and the second reinforcing structure is disposed The second carrier is disposed on the top surface of the encapsulation material with the second adhesive layer on the second adhesive layer.
該第二強化結構可為金屬框，並設置於該第二承載件之第二表面之周圍上。 The second reinforcing structure may be a metal frame and disposed on a circumference of the second surface of the second carrier.
該半導體封裝件之製法可包括：移除該第一承載件與該第一強化結構，以外露出該封裝材料之底面與複數設置於該半導體元件之作用面上之銲墊。 The method of fabricating the semiconductor package may include: removing the first carrier and the first reinforcing structure, and exposing a bottom surface of the packaging material and a plurality of pads disposed on an active surface of the semiconductor component.
該半導體封裝件之製法可包括：形成線路層於該封裝材料之底面上並電性連接該半導體元件之銲墊；形成具有複數開口之拒銲層於該封裝材料之底面上，以包覆該線路層與該銲墊，並藉由該些開口外露出部分該線路層；以及接置複數銲球於該些開口中以電性連接該線路層。 The method of manufacturing the semiconductor package may include: forming a wiring layer on the bottom surface of the packaging material and electrically connecting the bonding pads of the semiconductor component; forming a solder resist layer having a plurality of openings on a bottom surface of the packaging material to cover the a circuit layer and the bonding pad, and exposing a portion of the circuit layer through the openings; and connecting a plurality of solder balls to the openings to electrically connect the circuit layer.
該半導體封裝件之製法可包括：移除該第二承載件與該第二強化結構，以外露出該封裝材料之頂面；以及進行切單作業以形成半導體封裝件。 The method of fabricating the semiconductor package may include: removing the second carrier and the second reinforcing structure to expose a top surface of the packaging material; and performing a singulation operation to form a semiconductor package.
由上可知，本發明之半導體封裝件之製法，主要係將第一強化結構先設置於第一承載件上，再對該第一承載件、封裝材料與第一強化結構等進行烘烤，可避免該第一承載件與該封裝材料等產生翹曲之情形，以利後續進行線 路重佈及切單製程。同時，將第二強化結構設置於第二承載件上，再將該第二承載件設置於封裝材料之頂面，可使該封裝材料之頂面維持平整，並使線路層及拒銲層等易於形成在該封裝材料之底面上。藉此，本發明能提升該半導體封裝件之良率。 It can be seen that the manufacturing method of the semiconductor package of the present invention mainly comprises first placing the first reinforcing structure on the first carrier, and then baking the first carrier, the packaging material and the first reinforcing structure. Avoiding the situation that the first carrier and the packaging material and the like are warped, so as to facilitate the subsequent line Road redistribution and cutting process. At the same time, the second reinforcing structure is disposed on the second carrier, and the second carrier is disposed on the top surface of the packaging material, so that the top surface of the packaging material can be kept flat, and the circuit layer and the solder resist layer are It is easy to form on the bottom surface of the encapsulating material. Thereby, the present invention can improve the yield of the semiconductor package.
10‧‧‧載體 10‧‧‧ Carrier
11‧‧‧剝離層 11‧‧‧ peeling layer
12‧‧‧黏著層 12‧‧‧Adhesive layer
13‧‧‧晶片 13‧‧‧ wafer
131‧‧‧銲墊 131‧‧‧ solder pads
14‧‧‧封裝膠體 14‧‧‧Package colloid
2‧‧‧半導體封裝件 2‧‧‧Semiconductor package
21‧‧‧第一承載件 21‧‧‧First carrier
211‧‧‧第一載體 211‧‧‧ first carrier
212‧‧‧第一剝離層 212‧‧‧First peeling layer
213‧‧‧第一黏著層 213‧‧‧First adhesive layer
214‧‧‧第一表面 214‧‧‧ first surface
22‧‧‧第一強化結構 22‧‧‧First strengthened structure
23‧‧‧半導體元件 23‧‧‧Semiconductor components
23a‧‧‧作用面 23a‧‧‧Action surface
23b‧‧‧非作用面 23b‧‧‧Non-active surface
231‧‧‧銲墊 231‧‧‧ solder pads
24‧‧‧封裝材料 24‧‧‧Packaging materials
24a‧‧‧底面 24a‧‧‧ bottom
24b‧‧‧頂面 24b‧‧‧ top surface
25‧‧‧第二承載件 25‧‧‧Second carrier
251‧‧‧第二載體 251‧‧‧second carrier
252‧‧‧第二剝離層 252‧‧‧Second stripping layer
253‧‧‧第二黏著層 253‧‧‧Second Adhesive Layer
254‧‧‧第二表面 254‧‧‧ second surface
26‧‧‧第二強化結構 26‧‧‧Second strengthening structure
27‧‧‧線路層 27‧‧‧Line layer
28‧‧‧拒銲層 28‧‧‧Replacement layer
281‧‧‧開口 281‧‧‧ openings
29‧‧‧銲球 29‧‧‧ solder balls
SS‧‧‧切割線 SS‧‧‧ cutting line
第1A圖至第1D圖係繪示習知技術之半導體封裝件之製法之剖視示意圖；以及第2A圖至第2I圖係繪示本發明之半導體封裝件之製法之剖視示意圖，其中，第2B'圖為第2B圖之俯視示意圖。 1A to 1D are schematic cross-sectional views showing a method of fabricating a semiconductor package of the prior art; and FIGS. 2A to 2I are schematic cross-sectional views showing a method of fabricating the semiconductor package of the present invention, wherein Figure 2B' is a top plan view of Figure 2B.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered.
同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」、「表面」、「底面」及「頂面」等用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相 對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 At the same time, the terms "upper", "one", "first", "second", "surface", "bottom" and "top" as quoted in this manual are for convenience only. Rather than limiting the scope of the invention, the Changes or adjustments to the relationship are considered to be within the scope of the invention without departing from the scope of the invention.
第2A圖至第2I圖係繪示本發明之半導體封裝件之製法之剖視示意圖，其中，第2B'圖為第2B圖之俯視示意圖。 2A to 2I are schematic cross-sectional views showing a method of fabricating the semiconductor package of the present invention, wherein FIG. 2B' is a top plan view of FIG. 2B.
如第2A圖所示，先提供具有第一表面214之第一承載件21。 As shown in FIG. 2A, a first carrier 21 having a first surface 214 is provided first.
在本實施例中，該第一承載件21可為晶圓形式(wafer form)或面板形式(panel form)，並具有第一載體211、第一剝離層212與第一黏著層213，但不以此為限。在其他實施例中，該第一承載件21亦可具有各種不同的結構。 In this embodiment, the first carrier 21 may be in a wafer form or a panel form, and has a first carrier 211, a first peeling layer 212 and a first adhesive layer 213, but This is limited to this. In other embodiments, the first carrier 21 can also have a variety of different configurations.
該第一剝離層212與該第一黏著層213係依序形成於該第一載體211上，亦即該第一剝離層212係先以塗佈(coating)或化學氣相沈積(Chemical Vapor Deposition；CVD)等方式形成於該第一載體211上，該第一黏著層213再以塗佈等方式形成於該第一剝離層212上。該第一表面214即為該第一黏著層213之表面。 The first peeling layer 212 and the first adhesive layer 213 are sequentially formed on the first carrier 211, that is, the first peeling layer 212 is first coated or chemical vapor deposited (Chemical Vapor Deposition). CVD) or the like is formed on the first carrier 211, and the first adhesive layer 213 is formed on the first peeling layer 212 by coating or the like. The first surface 214 is the surface of the first adhesive layer 213.
如第2B圖與第2B'圖所示，提供例如方形或環狀之第一強化結構22，並將其設置於該第一承載件21之第一表面214或其周圍上。 As shown in Figures 2B and 2B', a first reinforcing structure 22, for example square or annular, is provided and placed over or around the first surface 214 of the first carrier 21.
在本實施例中，該第一強化結構22可為金屬框或其他強化件(stiffener)，係設置於該第一黏著層213之表面或其周圍上。 In this embodiment, the first reinforcing structure 22 may be a metal frame or other stiffener disposed on the surface of the first adhesive layer 213 or around the surface.
如第2C圖所示，提供具有複數銲墊231、相對之作用面23a與非作用面23b之半導體元件23，該銲墊231係設 置於該作用面23a上，該半導體元件23係為一個以上。同時，以該作用面23a將該半導體元件23設置於該第一承載件21之第一表面214上。 As shown in FIG. 2C, a semiconductor element 23 having a plurality of pads 231, an opposite active surface 23a and an inactive surface 23b is provided, and the pad 231 is provided. The active surface 23a is placed on the active surface 23a, and the semiconductor element 23 is one or more. At the same time, the semiconductor element 23 is disposed on the first surface 214 of the first carrier 21 with the active surface 23a.
在本實施例中，該半導體元件23係為二個或複數個，並以該作用面23a設置於該第一黏著層213之表面上。 In the embodiment, the semiconductor elements 23 are two or more, and the active surface 23a is disposed on the surface of the first adhesive layer 213.
此外，在其他實施例中，可將上述第2B圖與第2C圖之製程加以對調，亦即先將第2C圖之半導體元件23設置於該第一承載件21之第一表面214上，再將第2B圖之第一強化結構22設置於該第一承載件21之第一表面214或其周圍上。 In addition, in other embodiments, the processes of FIG. 2B and FIG. 2C can be reversed, that is, the semiconductor component 23 of FIG. 2C is first disposed on the first surface 214 of the first carrier 21, and then The first reinforcing structure 22 of FIG. 2B is disposed on or around the first surface 214 of the first carrier 21.
如第2D圖所示，形成封裝材料24於該第一承載件21之部分第一表面214上，以包覆該半導體元件23並外露出該第一強化結構22，使該第一強化結構22環繞於該封裝材料24之周圍。接著，對該第一承載件21、封裝材料24與第一強化結構22等進行烘烤。 As shown in FIG. 2D, a package material 24 is formed on a portion of the first surface 214 of the first carrier 21 to encapsulate the semiconductor component 23 and expose the first reinforcement structure 22 such that the first reinforcement structure 22 Surrounding the periphery of the encapsulating material 24. Next, the first carrier 21, the encapsulating material 24, the first reinforcing structure 22, and the like are baked.
在本實施例中，該封裝材料24可為封裝膠體或層壓膜(lamination film)等，係形成於該第一黏著層213之部分表面上，用以包覆該半導體元件23，但不包覆該第一強化結構22。 In this embodiment, the encapsulating material 24 may be an encapsulant or a lamination film or the like formed on a portion of the surface of the first adhesive layer 213 for covering the semiconductor component 23, but not including The first reinforcing structure 22 is covered.
如第2E圖所示，提供具有第二表面254之第二承載件25與例如方形或環狀之第二強化結構26，該第二承載件25可為晶圓形式或面板形式，該第二強化結構26可設置於該第二承載件25之第二表面254或其周圍上。同時，以該第二表面254將該第二承載件25設置於該封裝材料24 之頂面24b上。 As shown in FIG. 2E, a second carrier 25 having a second surface 254 and a second reinforcing structure 26, such as a square or ring, are provided. The second carrier 25 can be in the form of a wafer or a panel, the second The reinforcing structure 26 can be disposed on or around the second surface 254 of the second carrier 25. At the same time, the second carrier 25 is disposed on the encapsulation material 24 by the second surface 254. On the top surface 24b.
在本實施例中，該第二承載件25係具有第二載體251、第二剝離層252與第二黏著層253，但不以此為限。在其他實施例中，該第二承載件25亦可具有各種不同的結構。 In this embodiment, the second carrier 25 has a second carrier 251, a second peeling layer 252 and a second adhesive layer 253, but is not limited thereto. In other embodiments, the second carrier 25 can also have a variety of different configurations.
該第二剝離層252與該第二黏著層253係依序形成於該第二載體251上，亦即該第二剝離層252係先以塗佈或化學氣相沈積(CVD)等方式形成於該第二載體251上，該第二黏著層253再以塗佈等方式形成於該第二剝離層252上。該第二表面254即為該第二黏著層253之表面。 The second peeling layer 252 and the second adhesive layer 253 are sequentially formed on the second carrier 251, that is, the second peeling layer 252 is formed by coating or chemical vapor deposition (CVD). On the second carrier 251, the second adhesive layer 253 is formed on the second release layer 252 by coating or the like. The second surface 254 is the surface of the second adhesive layer 253.
該第二強化結構26可為金屬框或其他強化件，係設置於該第二黏著層253之表面或其周圍上。該第二承載件25係以該第二黏著層253設置於該封裝材料24之頂面24b上。 The second reinforcing structure 26 can be a metal frame or other reinforcing member disposed on the surface of the second adhesive layer 253 or on the periphery thereof. The second carrier 25 is disposed on the top surface 24b of the encapsulation material 24 with the second adhesive layer 253.
如第2F圖所示，移除該第一承載件21與該第一強化結構22，以外露出該封裝材料24之底面24a與該半導體元件23之銲墊231，該銲墊231係設置於該半導體元件23之作用面23a上。 As shown in FIG. 2F, the first carrier 21 and the first reinforcing structure 22 are removed, and the bottom surface 24a of the encapsulating material 24 and the bonding pad 231 of the semiconductor component 23 are exposed, and the bonding pad 231 is disposed on the bonding pad 231. On the active surface 23a of the semiconductor element 23.
如第2G圖所示，形成線路層27或線路重佈層(Redistribution Layer；RDL)於該封裝材料24之底面24a上，並電性連接該半導體元件23之銲墊231。接著，形成具有複數開口281之拒銲層28於該封裝材料24之底面24a上，以包覆該線路層27、該半導體元件23之銲墊231與作用面23a，並藉由該些開口281外露出部分該線路層27。 然後，接置複數銲球29於該些開口281中以電性連接該線路層27。 As shown in FIG. 2G, a wiring layer 27 or a redistribution layer (RDL) is formed on the bottom surface 24a of the encapsulation material 24, and is electrically connected to the pad 231 of the semiconductor element 23. Next, a solder resist layer 28 having a plurality of openings 281 is formed on the bottom surface 24a of the encapsulation material 24 to cover the wiring layer 27, the pad 231 and the active surface 23a of the semiconductor device 23, and through the openings 281. A portion of the wiring layer 27 is exposed. Then, a plurality of solder balls 29 are connected to the openings 281 to electrically connect the circuit layer 27.
如第2H圖所示，移除該第二承載件25與該第二強化結構26，以外露出該封裝材料24之頂面24b。之後，沿著切割線SS進行切單(singulation)作業，以形成複數半導體封裝件。 As shown in FIG. 2H, the second carrier 25 and the second reinforcing structure 26 are removed to expose the top surface 24b of the encapsulating material 24. Thereafter, a singulation operation is performed along the dicing line SS to form a plurality of semiconductor packages.
如第2I圖所示，係顯示切單後之半導體封裝件2。 As shown in Fig. 2I, the semiconductor package 2 after singulation is shown.
由上可知，本發明之半導體封裝件之製法，主要係將第一強化結構先設置於第一承載件上，再對該第一承載件、封裝材料與第一強化結構等進行烘烤，可避免該第一承載件與該封裝材料等產生翹曲之情形，以利後續進行線路重佈及切單製程。同時，將第二強化結構設置於第二承載件上，再將該第二承載件設置於封裝材料之頂面，可使該封裝材料之頂面維持平整，並使線路層及拒銲層等易於形成在該封裝材料之底面上。藉此，本發明能提升該半導體封裝件之良率。 It can be seen that the manufacturing method of the semiconductor package of the present invention mainly comprises first placing the first reinforcing structure on the first carrier, and then baking the first carrier, the packaging material and the first reinforcing structure. The situation that the first carrier and the packaging material and the like are warped is avoided, so as to facilitate the subsequent line redistribution and singulation process. At the same time, the second reinforcing structure is disposed on the second carrier, and the second carrier is disposed on the top surface of the packaging material, so that the top surface of the packaging material can be kept flat, and the circuit layer and the solder resist layer are It is easy to form on the bottom surface of the encapsulating material. Thereby, the present invention can improve the yield of the semiconductor package.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
21‧‧‧第一承載件 21‧‧‧First carrier
211‧‧‧第一載體 211‧‧‧ first carrier
212‧‧‧第一剝離層 212‧‧‧First peeling layer
213‧‧‧第一黏著層 213‧‧‧First adhesive layer
214‧‧‧第一表面 214‧‧‧ first surface
22‧‧‧第一強化結構 22‧‧‧First strengthened structure
23‧‧‧半導體元件 23‧‧‧Semiconductor components
23a‧‧‧作用面 23a‧‧‧Action surface
23b‧‧‧非作用面 23b‧‧‧Non-active surface
231‧‧‧銲墊 231‧‧‧ solder pads
24‧‧‧封裝材料 24‧‧‧Packaging materials
24a‧‧‧底面 24a‧‧‧ bottom
24b‧‧‧頂面 24b‧‧‧ top surface
25‧‧‧第二承載件 25‧‧‧Second carrier
251‧‧‧第二載體 251‧‧‧second carrier
252‧‧‧第二剝離層 252‧‧‧Second stripping layer
253‧‧‧第二黏著層 253‧‧‧Second Adhesive Layer
254‧‧‧第二表面 254‧‧‧ second surface
26‧‧‧第二強化結構 26‧‧‧Second strengthening structure
Claims (15)
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| Application Number | Priority Date | Filing Date | Title |
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| TW102118395A TW201445644A (en) | 2013-05-24 | 2013-05-24 | Method for manufacturing semiconductor package |
| CN201310222505.8A CN104183509B (en) | 2013-05-24 | 2013-06-06 | Method for manufacturing semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| TW102118395A TW201445644A (en) | 2013-05-24 | 2013-05-24 | Method for manufacturing semiconductor package |
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| TW201445644A true TW201445644A (en) | 2014-12-01 |
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| TWI622151B (en) * | 2016-12-07 | 2018-04-21 | 矽品精密工業股份有限公司 | Carrier substrate for semiconductor packaging and package structure thereof, and method for fabricating semiconductor package |
| CN108242404A (en) * | 2016-12-27 | 2018-07-03 | 冠宝科技股份有限公司 | Substrate-free semiconductor package manufacturing method |
| US20180350708A1 (en) * | 2017-06-06 | 2018-12-06 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
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| JPH10178145A (en) * | 1996-12-19 | 1998-06-30 | Texas Instr Japan Ltd | Semiconductor device and its manufacturing method and insulation substrate for semiconductor device |
| JP3032964B2 (en) * | 1996-12-30 | 2000-04-17 | アナムインダストリアル株式会社 | Ball grid array semiconductor package and manufacturing method |
| JP3738176B2 (en) * | 2000-08-03 | 2006-01-25 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| TWI339865B (en) * | 2007-08-17 | 2011-04-01 | Chipmos Technologies Inc | A dice rearrangement package method |
| US8400774B2 (en) * | 2009-05-06 | 2013-03-19 | Marvell World Trade Ltd. | Packaging techniques and configurations |
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| CN104183509A (en) | 2014-12-03 |
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