[go: up one dir, main page]

TW201248800A - Wiring substrate, method for manufacturing same, and semiconductor device - Google Patents

Wiring substrate, method for manufacturing same, and semiconductor device Download PDF

Info

Publication number
TW201248800A
TW201248800A TW101105250A TW101105250A TW201248800A TW 201248800 A TW201248800 A TW 201248800A TW 101105250 A TW101105250 A TW 101105250A TW 101105250 A TW101105250 A TW 101105250A TW 201248800 A TW201248800 A TW 201248800A
Authority
TW
Taiwan
Prior art keywords
layer
substrate
metal
insulating layer
wiring
Prior art date
Application number
TW101105250A
Other languages
Chinese (zh)
Inventor
Kazuhito Hikasa
Toshiaki Amano
Masato Watanabe
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2011033489A external-priority patent/JP2012174791A/en
Priority claimed from JP2011068642A external-priority patent/JP2012204662A/en
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Publication of TW201248800A publication Critical patent/TW201248800A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention suppresses the generation of reflow cracking and the generation of electromigration. Provided is a wiring substrate which enables impedance matching due to flatness, a high degree of design freedom, and high-density installation, and also provided are a method for manufacturing the wiring substrate, and a semiconductor device. An interposer (30) comprises: a substrate (32) made of resin and constituting a base; a wiring pattern (50) formed on the substrate (32); and an insulating layer (40) that covers part of the wiring pattern (50). Posts (60) that are connected with the semiconductor chip and are formed of metal the chief constituent of which is copper are erected in prescribed locations on the wiring pattern (50). The posts (60) are erected on the wiring pattern (50) in a state in which the posts (60) pass through the substrate (32).

Description

201248800 六、發明說明 【發明所屬之技術領域】 本發明係關於配線基板及其製造方法以及半導體裝 置，尤其係關於特化成配線基板之構造的技術。 【先前技術】 伴隨著近年來的電子機器的高密度化，已開發出一種 層積複數枚半導體晶片而實現3次元構裝構造的高密度半 導體裝置（半導體封裝體）。如上所示之半導體裝置係例 如在板狀或薄膜狀基板的表面固定積體電路、電阻器、電 容器等多數電子零件，以配線連接該零件間而構成電子電 路。 以形成如上所示之半導體裝置的多層配線基板而言， 利用按每層反覆進行層積、鑽孔加工、電路形成等的工法 所製作的積層（Build-up )基板正在普及中。在積層基板 中的電路形成過程中，係有將絕緣層層疊薄膜狀樹脂而形 成者（參照專利文獻1 )。 此外，例如，以上述半導體裝置之一形態而言，係進 行：使複數枚半導體晶片分別以引線接合連接於1個基板 且作層積來進行封裝體化（參照專利文獻2 )。但是，若 使用在中央具有電極（焊墊）的半導體晶片時，若欲將各 半導體晶片與基板進行引線接合時，藉由用以接著各半導 體晶片的接著劑層，會有線材本身被擠壞而使電特性變差 的問題。 -5- 201248800 因此，在如上所示之情形下，由於由半導體晶片的中 央焊墊至外側進行再配線（供半導體晶片的電極間距擴張 之用）而使用一種被稱爲「中介層（Interposer)」的配 線基板。 最近，中介層亦被使用在用以使半導體封裝體本身的 電氣特性或耐久性提升，其例揭示於專利文獻2、3等。 藉由專利文獻2的技術，在半導體晶片（1 )間插入中介 層（1 1 )，欲解決電源雜訊的問題（參照段落 0027〜 0033、第3圖等）。藉由專利文獻3的技術，使中介層 (6 )介在於半導體晶片（5，8 )間來評估耐久性能（參 照段落0058、段落0065、表3、表4、第2圖等）。 [先前技術文獻] [專利文獻] [專利文獻1]日本特開2010-34247號公報 [專利文獻2]日本特開2002-151644號公報 [專利文獻3]日本特開2008-4853號公報 [專利文獻4]日本特開2008-177504號公報 【發明內容】 (發明所欲解決之課題） 但是’半導體晶片與中介層的電性連接，一般而言係 藉由對半導體晶片或中介層的至少—方外部連接電極，僅 設置焊料凸塊而將其進行熔融（迴焊）來進行。在如上所 示之連接構造中’焊料流動而無法確保絕緣層的厚度，會 -6- 201248800 有發生迴焊裂痕的可能性。此外，伴隨著上述半導體晶片 的多段化或精密間距化，亦會有發生電子遷移、且在半導 體晶片與中介層的連接部分，電阻上升的可能性。 此外’在近年來曰益薄型化的多層配線基板中，在構 裝電子零件時的處理上，維持基板的剛性已成爲課題，在 上述文獻中的多層配線基板中，亦以高剛性且處理容易爲 目標。但是，在上述習知技術中，會造成當在基板的絕緣 層層疊薄膜狀樹脂時發生配向、且在配線基板發生翹曲的 原因。 本發明係爲了解決如以上所示之習知技術的課題所硏 創者，其目的在提供可抑制迴焊裂痕發生或電子遷移發生 之配線基板及其製造方法以及利用如上所示之配線基板的 半導體裝置。 此外，本發明之其他目的在提供因平坦性所致之阻抗 整合及設計自由度高、且可進行高密度構裝的多層配線基 板及其製造方法以及半導體裝置。 (解決課題之手段） 爲解決上述課題，在本發明之多層配線基板之較佳態 樣中，其具有：作爲基底的樹脂製基板；形成在前述基板 上的配線圖案；及被覆前述配線圖案之一部分的絕緣層， 在前述配線圖案上的預定位置立設有由以銅爲主成分的金 屬所構成且與半導體晶片相連接的支柱，前述支柱係在貫 穿前述基板的狀態下立設於前述配線圖案上。 201248800 在本發明之多層配線基板之其他較佳態樣中，其具 有：作爲基底的樹脂製基板；形成在前述基板上的配線圖 案；及一面被覆前述配線圖案，一面在前述基板的兩面對 稱積層所形成的絕緣層，前述絕緣層係在MD方向及TD 方向中，強度相同。 在以上態樣中，在絕緣層中，將屬於基板流動方向的 MD( Machine Direction)方向、及屬於基板垂直方向的 TD方向（Transverse Direction )設定爲相同強度。藉 此，即使在基板積層絕緣層，亦可提供翹曲少且具平坦性 的多層配線基板。此外，在基板的上面及下面，藉由形成 爲上下對稱構造，不會有基板翹曲的情形，同時可實現低 熱膨脹，即使爲較大尺寸的基板，亦不會發生構裝偏移。 較佳爲，在上述態樣中，前述絕緣層係藉由澆鑄所形 成爲其特徵。在該態樣中，當積層絕緣層時，藉由澆鑄 (溶液湊鑄法（solution casting))來進行，藉此由於對 薄膜未施加物理性的壓力，因此不會發生高分子的配向， 且在強度或光學特性等不會產生方向性。此外，作爲薄膜 而在市面上販售的絕緣層係規格品，厚度一定，但是如上 述態樣所示，藉由將絕緣層進行澆鑄，可形成任意厚度， 且亦可製作例如傾斜構造。因此，亦可防止因不需要的絕 緣層厚度所造成的製品肥大化。此外，可使用任意設定考 慮到訊號延遲的厚度、或作爲絕緣層而符合電路密度或目 的的CTE (線膨脹係數）的材料，設計自由度高。 201248800 (發明之效果） 藉由本發明，可抑制迴焊裂痕發生或電子遷移發生。 此外’可提供因平坦性所致之阻抗整合及設計自由度高、 且可進行高密度構裝之多層配線基板及其製造方法以及半 導體裝置。 【實施方式】 以下一面參照圖示，一面說明本發明之較佳實施形 態。如上所述，本發明係可掌握爲多層配線基板之發明， 並且亦可掌握爲製作該多層配線基板的製造方法、半導體 裝置。因此’以下連同實施形態，首先說明半導體裝置之 構成，然後具體說明多層配線基板之構成，此外說明多層 配線基板之製造方法。 〔1 ·第1實施形態〕 半導體裝置（100 )係具有所謂 TSV ( Through Silicon Via，直通矽穿孔）構造的半導體封裝體，如第1 圖所示，主要由半導體晶片層積體1 0、控制器20及中介 層3 0所構成。 如第2圖所示，半導體晶片層積體10係層積複數枚 Si製半導體晶片12所構成。各半導體晶片12係發揮作 爲 DRAM ( Dynamic Random Access Memory，動態隨機存 取記憶體）的功能。在各半導體晶片1 2形成有貫穿孔14 (Via)，通過貫穿孔14而形成貫穿電極16。各半導體 201248800 晶片1 2係通過貫穿電極1 6而與其他半導體晶片1 2或控 制器2 0作電性連接。 控制器20係具有Si製半導體晶片22。在半導體晶 片22亦形成有貫穿孔24 ( Via)，通過貫穿孔24而形成 貫穿電極26。半導體晶片22係藉由底層塡充材料28予 以封裝。控制器20係通過貫穿電極26而與半導體晶片層 積體1〇或中介層30作電性連接。 中介層30係供半導體晶片22之電極間距擴張之用的 配線基板。中介層30係在可撓性的可撓性基板形成有凸 塊的所謂附焊料凸塊的中介層。 如第3圖所示，中介層30係具有作爲基底的樹脂製 基板32。基板32係由例如聚亞醯胺樹脂、酚醛樹脂、環 氧樹脂、聚酯樹脂、氟樹脂等所構成，較佳爲由聚亞醯胺 樹脂所構成。 在基板32的下部形成有絕緣層34。絕緣層34係由 接著劑層36及補強膜38所構成。接著劑層36係由例如 環氧系接著劑或聚亞醯胺系接著劑等所構成，較佳爲由環 氧系接著劑所構成。補強膜3 8係由例如聚亞醯胺樹脂製 薄膜所構成。 在絕緣層3 4的下部形成有絕緣層40。絕緣層40係 由抗焊劑所形成的層。 在基板32上形成有由絕緣層34的接著劑層36至絕 緣層40具有3次元構造的配線圖案50。配線圖案50係 由以銅爲主成分的金劂所構成。 -10- 201248800 「以銅爲主成分的金屬」係指可爲銅單體，亦可爲 銅添加鎳、鈷、鐵等的合金。若爲以銅爲主成分的金屬 合金的情形，相對銅的鎳等的添加量較佳爲20%以下。 配線圖案50主要係由下部配線部52、連結配線部 及上部配線部56所構成。爲易於瞭解之後的說明，將 線圖案5 0劃分爲該等部位，但是該等部位實際上係— 形成。 下部配線部52係被絕緣層40所被覆。絕緣層40 被圖案化成預定圖案，下部配線部52的一部分由絕緣 40的開口部42露出。下部配線部5 2的露出部係作爲 部連接電極而發揮功能，在該露出部形成焊球等，半導 裝置1〇〇被構裝在主機板等電路基板。 連結配線部54係以貫穿補強膜38的方式所形成。 結配線部54係連接於下部配線部52與上部配線部56 將該等配線部相連結。 上部配線部56係形成在接著劑層36中。在上部配 部56形成有支柱60。支柱60係在貫穿基板32的狀態 立設於配線圖案50上。支柱60的前端部（頂部64 ) 由基板32稍微露出。基板32係在使支柱的前端部（頂 64 )突出的狀態下被覆支柱60的側面，作爲保護支柱 的保護層來發揮功能。 在支柱60上形成有焊料凸塊62。焊料凸塊62係 以與半導體晶片等電子元件作電性覆晶連接的突起電極 由例如錫-銀合金所構成。 對 爲 54 配 體 係 層 外 體 連 而 線 下 係 部 60 用 -11 - 201248800 如第3圖擴大部所示，支柱60係呈由頂部64朝向基 部66爲尖端細的形狀（倒錐狀）。頂部64係透過焊料凸 塊62而與控制器20的半導體晶片22相連接的部位。基 部66係與配線圖案50的上部配線部56相連接的部位。 例如，頂部64的直徑係相對半導體晶片22的電極29 (第2圖，參照後述）的直徑爲+10〜20 μηι，基部66的 直徑係相對半導體晶片22的電極29的直徑爲±10μιη。 支柱60呈如上所示之形狀，因此支柱60的頂部64 係由基部66俯視時的面積大，可防止與半導體晶片22連 接時的電極間的位置偏移。另一方面，支柱60的基部66 係由頂部64俯視時的面積小，可防止在支柱60形成時， 與上部配線部56之間的位置偏移、或支柱60誤連接於所 希望的上部配線部56的相鄰的上部配線部56。 其中，在第3圖中雖省略，基板32、絕緣層34及絕 緣層40與配線圖案50的界面、或基板32與支柱60的界 面係形成有基底金屬層，配線圖案50或支柱60對基板 32等的接著性被提高。該基底金屬層係由例如鎳鉻合金 或銅等所構成。 具有以上構成的半導體裝置100的各種尺寸係例如設 計成如下所示（參照第1圖〜第3圖）。 封裝體尺寸（中介層30)爲llmmxl5mm。 晶片尺寸（半轉體晶片12)爲7mmx8mni。 貫穿電極16的直徑a爲20μηι。 貫穿電極1 6問的間距b爲3 5 μη!。 -12- 201248800 貫穿電極26的直徑c爲20μηι。 貫穿電極2 6間的間距d爲7 0 μ m。 支柱60的直徑e大約爲20μιη。 焊料凸塊6 2間的間距f爲7 0 μ m。 外部連接電極（焊球）間的間距g爲800μιη。 焊料凸塊62的高度h爲5μπι。 支柱60的高度i爲35μηι。 基板32的厚度j爲25μπι。 配線圖案50的連結配線部54的高度k爲38μιη。 如上所示藉由半導體裝置100，半導體晶片12之貫 穿電極1 6間的間距b藉由控制器2 0 (半導體晶片2 2 )而 由35μιη擴張至70μηι，半導體晶片22之貫穿電極26間 的間距d藉由中介層30而由70μηι大幅擴張至800μηι。 在此’在半導體裝置100中，在控制器20(半導體 晶片22)形成有由底面朝向中介層30側突出的電極29。 該半導體晶片22的電極29的高度與中介層30的支柱60 的高度的合計Η (參照第2圖）較佳爲3 5μίη以上，更佳 爲5 0 μ m以上。 此時’在半導體晶片22的電極29與中介層30的支 柱60中任一者較高均可’但是較佳爲提高支柱6〇而將支 柱60的闻度確保3 5 μηι以上。此係基於（i)若欲在半導 體晶片2 2側確保高度時’必須按每個半導體晶片2 2 (每 —枚）製造電極29’較耗費勞力，相對於此，以欲在中 介層3〇側確保咼度者’以r〇n-to_r〇n (輥-輥）方式可較 -13- 22 201248800 爲容易製造支柱60之故’ （ii)若考慮到半導體晶片 與中介層30的良率時，以在中介層30側確保高度者， 良率較佳之故。 因此，較佳爲半導體晶片22的電極29僅由焊墊電 所構成，在電極29以未形成凸塊等爲佳。 接著，說明中介層30之製造方法。 中介層30係藉由以被捲繞在預定滾筒的長形基板 被捲繞在其他滾筒的方式予以搬送，在該搬送過程中形 配線圖案30等的roll-to-roll方式來進行製造。 具體而言，首先如第4圖所示，在基板32層疊樹 製乾膜70，進行曝光而使乾膜70硬化（S1)。之後， 用雷射而在基板32及乾膜70的預定位置形成貫穿 72，將其膠渣（削屑）去除（S2 )。 之後，在基板32及乾膜70將金屬進行濺鍍而形成 屬基底層74 ( S3 )。之後，在基板32的下面側的金屬 底層74層疊樹脂製乾膜76，使用與上部配線部56相 應的圖案的遮罩來將乾膜76進行曝光/顯影，且以預 圖案的樹脂層（乾膜76)被覆金屬基底層74(S4)。 之後，將以銅爲主成分的金屬鍍敷在由乾膜76所 出的金屬基底層74，在金屬基底層74形成金屬層78, 且在貫穿孔72亦塡充金屬層79(S5)。之後，在基板 的下面側的金屬層78及乾膜76上黏貼樹脂製乾膜80 將乾膜70的上面側的金屬基底層74及金屬層78進行 刻而予以去除（S6 )。結果，形成由金屬層79所構成 總 極 32 成 脂 使 孔 金 基 對 定 露 並 32 ， 蝕 的 -14- 201248800 支柱60。 其中’在S2的處理中，調整雷射的輸出而由上方 下方慢慢降低，將貫穿孔72形成爲尖端細狀（倒 狀）。結果，可形成尖端細狀的支柱60 (參照第3圖 大部）。 之後，在支柱 60鍍敷焊料而形成焊料凸塊 (S7 )，將形成在基板32的乾膜 70、76、80剝 (S 8 )。之後，如第5圖所示，在基板32黏貼樹脂製 膜82’並且將以乾膜76予以被覆的部分的金屬基底層 進行蝕刻而去除（S9 )。結果，形成由金屬層78所構 的配線圖案5 0的上部配線部5 6 » 之後，在基板3 2的下面側塗佈接著劑而形成接著 層3 6，另外在接著劑層3 6上層疊補強膜3 8，以絕緣 3 4被覆上部配線部5 6 ( S 1 0 )。之後，進行加熱而使接 劑層36硬化，並且將乾膜82剝離（S1 1 )。之後，使 雷射，在絕緣層34的預定位置至露出上部配線部56爲 形成貫穿孔84，將其膠渣（削屑）去除（S 12 )。 之後，在絕緣層34、貫穿孔84及上部配線部56 金屬進行濺鍍而形成金屬基底層86 (S13)。之後，在 板32層疊樹脂製乾膜88，並且在金屬基底層86亦層 樹脂製乾膜90，使用與下部配線部52及連結配線部 相對應的圖案的遮罩來將乾膜90進行曝光/顯影，以 定圖案的樹脂層（乾膜90)被覆金屬基底層86(S14) 之後，如第6圖所示，在由乾膜90露出的金屬基 至 錐 擴 62 離 乾 74 成 劑 層 著 用 止 將 基 疊 54 預 〇 底 -15- 201248800 層86鍍敷以銅爲主成分的金屬，在金屬基 孔84及上部配線部56形成金屬層92 ( S1: 乾膜90剝離（S 1 6 )。之後，將以乾膜90 底層86進行蝕刻而去除。結果，形成由金j 的配線圖案50的下部配線部52及連結配線 之後，將乾膜8 8剝離。之後，在絕緣 線部52及連結配線部54層疊樹脂製抗焊齊丨 40，使用預定圖案的遮罩而將絕緣層40進 (S 1 7 )。結果，在絕緣層40形成開口部 部 52的一部分由開口部 42露出（形丨 極。）。 可經由以上S1〜S17的處理來製造中介 藉由以上的半導體裝置100，在中介層 6〇，該形成部分以基板32或底層塡充材料 塡滿，因此在欲將半導體裝置100構裝在主 板時，應力獲得緩和而可抑制迴焊裂痕發生 此外，在中介層30形成支柱60，在β 導體晶片22與中介層30的配線圖案50之 隔，因此亦可抑制電子遷移發生。 〔2 ·第2實施形態〕 第2實施形態係在中介層之構成中與第 同，關於其他構成，係與第】實施形態相同 如第7圖所示，在本實施形態之中介層 底層86、貫穿 5 )。之後，將 被覆的金屬基 覊層92所構成 部54。 層34 '下部配 丨而形成絕緣層 ;行曝光/顯影 42，下部配線 戎外部連接電 層30。 3 0形成支柱 2 8等樹脂予以 :機板等電路基 〇 爸制器20的半 .間確保預定間 1實施形態不 〇 200中，係在 c -16- 201248800 基板3 2的上部形成絕緣層3 4，在基板3 2的下部形成絕 緣層40。 支柱6 0係在貫穿絕緣層3 4 (尤其補強膜3 8 )的狀態 下立設在配線圖案50的上部配線部56。 在中介層200中，絕緣層34在使支柱60的前端部 (頂部64 )突出的狀態下被覆支柱60的側面，絕緣層34 係作爲保護支柱60的保護層而發揮功能。 接著，說明中介層200之製造方法。 首先，如第8圖所示，使用雷射，在基板32的預定 位置形成貫穿孔2 1 0，將其膠渣（削屑）去除（S21 )。 之後，在基板 32濺鍍金屬而形成金屬基底層 212 (S22 )。 之後，在金屬基底層212的預定位置鍍敷以銅爲主成 分的金屬，在金屬基底層形成金屬層214，並且在貫穿孔 210亦塡充金屬層2:16(S23)。之後，將由金屬層214露 出的金屬基底層2 1 2進行蝕刻而去除（S 24 )。結果，形 成由金屬層214及金屬層216所構成的配線圖案50。 之後，在基板3 2的上面側塗佈接著劑而形成接著劑 層3 6，另外在接著劑層3 6上層疊補強膜3 8，以絕緣層 34被覆配線圖案50的上部配線部56。同時’在基板32 的下面側層疊樹脂製抗焊劑而形成絕緣層40 ’以絕緣層 40被覆配線圖案50的下部配線部52 ( S25 )。 之後，在絕緣層3 4上黏貼樹脂製乾膜2 1 8 ’進行曝 光而使乾膜21 8硬化（S26 )。之後’使用雷射’在乾膜 -17- 201248800 2 1 8及絕緣層34的預定位置，至露出上部配線部56爲止 形成貫穿孔220 ’並且使用雷射，在絕緣層40的預定位 置亦至露出下部配線部52爲止形成貫穿孔（開口部 42)，將該等膠渣（削屑）去除（S27)。 之後，如第9圖所示，在乾膜218及貫穿孔220濺鍍 金屬而形成金屬基底層2 22，並且在絕緣層40及開口部 42亦濺鍍金屬而形成金屬基底層224(S28)。之後，在 金屬基底層224黏貼樹脂製乾膜22 6，並且在金屬基底層 222鍍敷以銅爲主成分的金屬，在金屬基底層222形成金 屬層228，並且在貫穿孔220亦塡充金屬層230 (S29)。 之後，將乾膜218上的金屬基底層222及金屬層228進行 蝕刻而去除（S30 )。結果，形成由金屬層230所構成的 支柱6 0。 之後，在支柱60鍍敷焊料而形成焊料凸塊62，在焊 料凸塊62及乾膜218上層疊乾膜232，進行曝光而使乾 膜232硬化（S31)。之後，將形成在金屬基底層224的 乾膜226剝離（S32 )。之後，將金屬基底層224進行蝕 刻而去除，且將絕緣層3 4上的乾膜2 1 8、2 3 2同時剝離 (S33 )。 可經由以上S21〜S33處理來製造中介層200。 其中，亦可使用第10圖之中介層240或第11圖之中 介層25〇來取代中介層200。在第10圖之中介層240 中’係形成有絕緣層242，來取代中介層200的接著劑層 3 6及補強膜3 8。絕緣屑242係由例如聚亞醯胺樹脂所構 201248800 成。 在製造中介層240時’亦可在基板32及上部 56上澆鑄液狀樹脂而使其硬化，來取代在S25中 著劑層3 6而黏貼補強膜3 8。 在第11圖之中介層250中，並沒有相當於 200的接著劑層36及補強膜38的構件。 在製造中介層250時，並未進行在S25中形成 層36來黏貼補強膜38，而是在S26中在基板32 配線部26上直接黏貼乾膜2 1 8即可。 〔3.第3實施形態〕 第3實施形態主要在F列與第1實施形態不同 構成係具有與第1實施形態相同的構成。 如第1 2圖所示，半導體裝置3 0 0係具有所言I (Double Die Package)構造的半導體封裝體，將 同種類的半導體晶片310層積而進行封裝者。 半導體裝置3 00係具有尺寸大於半導體晶片31 刷基板3 2 0。在印刷基板3 20的表面形成有接合墊 在印刷基板32〇的背面形成有電極焊墊3 24，在電 324形成有焊球326。 在印刷基板320上透過接著劑層3 3 0構裝有半 片310。在半導體晶片310形成有電極312。電極 由例如銅或金、焊料等所構成。半導體晶片3 1 0係 極3 1 2朝向上方的狀態下與中介層400作覆晶連接 配線部 形成接 中介層 接著劑 及上部 ，其他 | DDP 2枚相 0的印 3 22 〇 極焊墊 導體晶 3 12係 在將電 。在中 -19- 201248800 介層400上係透過接著劑層340而另外層積有半導體晶片 310及中介層400。 在各中介層400的外側形成有外部連接電極4〇2。各 外部連接電極402係藉由接合導線3 50而與印刷基板320 的接合墊322作電性連接。 在半導體裝置30〇中，如上所述所層積的半導體晶片 310係連同接合導線3 50 —起藉由封裝樹脂3 60予以封 裝。 如第13圖所示，在中介層400亦以基板32形成爲基 底。在基板32上形成有絕緣層410。絕緣層410係由例 如環氧樹脂所構成。 支柱60係在貫穿絕緣層4 1 0的狀態下立設在配線圖 案50的上部配線部56。 在中介層400中亦由絕緣層410被覆支柱60的側 面，絕緣層410係作爲保護支柱60的保護層而發揮功 能。 配線圖案5 0的下部配線部5 2係以金屬層4 1 2被覆而 構成外部連接電極402。金屬層412係具有層積有例如鎳 或金等的構成。 接著，說明中介層400之製造方法。 首先，如第14圖所示，準備基板32(S41)，對基 板3 2的側緣部，藉由衝孔，以預定間隔穿開用以扣止在 搬送用滾筒的孔420 ( S42 )。 之後，使用雷射而在基板3 2的預定位置形成貫穿孔 -20- 201248800 422，去除其膠渣（削屑）而進行洗淨（S43 )。之後，在 基板32濺鍍金屬而形成金屬基底層42 4(S44)。 之後，在基板32的兩面層疊樹脂製乾膜426、428 (S45 )，使用與配線圖案50的上部配線部56及下部配 線部52相對應的形狀的遮罩來進行曝光、顯影（S46 )。 之後，在由乾膜426、428露出的金屬基底層424鍍敷以 銅爲主成分的金屬，在金屬基底層424形成金屬層430, 並且在貫穿孔422亦塡充金屬層432 ( S47 )。 之後，如第 1 5圖所示，將乾膜 4 2 6、4 2 8剝離 (S48 )，將被乾膜426、428所被覆的金屬基底層424進 行蝕刻而去除（S49)。結果，形成由金屬層430及金屬 層432所構成的配線圖案50 (上部配線部56、下部配線 部5 2及連結配線部5 4 )。 之後，在基板3 2的上面側黏貼樹脂製接著劑（或絕 緣層）而形成絕緣層4 1 0 ( S 5 0 )。之後，在下部配線部 52鍍敷金屬而形成金屬層412(S51)。之後，在基板32 的下面側黏貼樹脂製乾膜434，並且使用雷射而在絕緣層 410的預定位置至露出上部配線部56爲止形成貫穿孔 436，而將其膠渣（削屑）去除（S52 )。之後，在由貫穿 孔43 6露出的上部配線部56鍍敷以銅爲主成分的金屬而 形成支柱60，另外在支柱60鍍敷焊料而形成焊料凸塊 62，最後將乾膜434剝離（S53 )。 可經由以上S41〜S53的處理來製造中介層400。 -21 - 201248800 〔試樣例〕 (1 )試樣的製作 製造具有與第2圖相同構成的半導體裝置（ 造）、及具有與第〗2圖相同構成的半導體裝置（ 造），將該等作爲試樣。 以半導體裝置而言’準備封裝體尺寸爲5mm 及10mm見方者面適當變更半導體晶片的電稻 或其高度、中介層的支柱的高度等，一面按照其糸ί 別爲試樣1〜1 2 (參照表1 )，試樣1 3〜2 2 ( 2)。 在表1及表2中，試樣2、4、6、8、10、1 1 6的「（註）」係表示在半導體晶片側使用焊璧 該焊墊電極由半導體晶片的突出長度。 (2 )試樣的評估 (2.1 )迴焊裂痕試驗 將各試樣進行迴焊處理，來觀察有無迴焊處理 痕。 將觀察結果顯示於表1及表2。 表1及表2中，〇、△' X的基準如以下所述 「〇」…5mm見方、10mm見方均沒有裂痕 「△」…5mm見方沒有裂痕，但是l〇mm見尤 以上的封裝體發生裂痕 「X」…5 m m見方、1 0 m m見方均在1個以_t TSV構 DPP構 見方者 的態樣 合，區 參照表 2、14、 電極， 後的裂 在1個 的封裝 -22- 201248800 體發生裂痕 (2.2 )長期可靠性試驗（電子遷移） 在各試樣中，以初期狀態及放置在一定環境（1 1 0 °C，85%RH，1 .95V，5 00小時）後，來測定電阻値。若 電阻値的增加爲1 〇%以內，即評估爲「〇」，若超過 1 0 % ’則g平估爲「X」。 將評估結果顯示於表1及表2。 [表1] 試樣 1 2 3 4 5 6 特性 封裝體構造 TSV D] DP TSV 晶片側電極高度 (μηι) 15 溯凸塊) 1 (註） 15 (銅凸塊) 1 (註） 15 (銅凸塊) 1 (註） 中介層側支柱高度 (μηι) 35 49 35 49 34 48 合計 (μηι) 50 50 50 50 49 49 評估 迴焊裂痕 〇 〇 〇 〇 〇 〇 電子遷移 〇 〇 〇 〇 〇 〇 試樣 7 8 9 10 11 12 特性 封裝體構造 D] DP TSV D1 DP 晶片側電極高度 (μηι) 1.5 (銅凸塊) 1 (註） 15 (銅凸塊) 1 (註） 15 (銅凸塊) 1 (註） 中介層側支柱高度 (μιη) 34 48 20 34 20 34 合計 (μηι) 49 49 35 35 35 35 評估 迴焊裂痕 〇 〇 Δ Δ Δ Δ 電子遷移 〇 〇 〇 〇 〇 〇 -23- 201248800 [表2][Technical Field] The present invention relates to a wiring board, a method of manufacturing the same, and a semiconductor device, and more particularly to a technique for constructing a wiring board. [Prior Art] With the recent increase in the density of electronic devices, a high-density semiconductor device (semiconductor package) in which a plurality of semiconductor wafers are stacked to realize a three-dimensional structure has been developed. In the semiconductor device as described above, for example, a plurality of electronic components such as an integrated circuit, a resistor, and a capacitor are fixed on the surface of a plate-shaped or film-form substrate, and an electronic circuit is formed by wiring the components. In the multilayer wiring board in which the semiconductor device shown above is formed, a build-up substrate produced by a method of laminating, drilling, circuit formation, or the like for each layer is widely used. In the circuit formation process of the laminated substrate, a film-like resin is formed by laminating an insulating layer (see Patent Document 1). Further, for example, in the form of one of the above-described semiconductor devices, a plurality of semiconductor wafers are connected by wire bonding to one substrate and laminated to form a package (see Patent Document 2). However, when a semiconductor wafer having electrodes (pads) in the center is used, if each semiconductor wafer and the substrate are to be wire-bonded, the wire material itself is crushed by the adhesive layer for the subsequent semiconductor wafers. And the problem of making electrical characteristics worse. -5- 201248800 Therefore, in the case shown above, a re-wiring from the center pad of the semiconductor wafer to the outside (for the electrode pitch expansion of the semiconductor wafer) is used as an "interposer". Wiring board. Recently, an interposer has also been used to improve the electrical characteristics or durability of the semiconductor package itself, and examples thereof are disclosed in Patent Documents 2 and 3. According to the technique of Patent Document 2, the interposer (1 1 ) is inserted between the semiconductor wafers (1) to solve the problem of power supply noise (see paragraphs 0027 to 0033, Fig. 3, etc.). According to the technique of Patent Document 3, the interposer (6) is interposed between the semiconductor wafers (5, 8) to evaluate the durability (refer to paragraphs 0056, 5065, 3, 4, 2, etc.). [PRIOR ART DOCUMENT] [Patent Document 1] Japanese Laid-Open Patent Publication No. JP-A-2002-153644 [Patent Document 3] JP-A-2008-153644 [Patent Document 3] JP-A-2008-4853 [Document 4] Japanese Laid-Open Patent Publication No. 2008-177504 [Draft of the Invention] (The problem to be solved by the invention) However, the electrical connection between the semiconductor wafer and the interposer is generally performed by at least the semiconductor wafer or the interposer. The square external connection electrode is formed by merely providing a solder bump and melting (reflowing) it. In the connection structure as described above, the solder flows and the thickness of the insulating layer cannot be ensured, and there is a possibility that reflow cracking may occur in -6-201248800. Further, as the semiconductor wafer is multi-staged or precisely pitched, there is a possibility that electron migration occurs and the resistance increases at the connection portion between the semiconductor wafer and the interposer. In addition, in the multilayer wiring board which has been thinned in recent years, it has been a problem to maintain the rigidity of the substrate in the process of arranging electronic components, and the multilayer wiring board in the above-mentioned document also has high rigidity and is easy to handle. For the goal. However, in the above-mentioned conventional technique, alignment occurs when the film-like resin is laminated on the insulating layer of the substrate, and the wiring substrate is warped. The present invention has been made to solve the problems of the above-described conventional techniques, and an object thereof is to provide a wiring board capable of suppressing generation of reflow cracks or electron migration, a method of manufacturing the same, and a wiring board as described above. Semiconductor device. Further, another object of the present invention is to provide a multilayer wiring board which is excellent in impedance integration due to flatness and high in design freedom, and which can be mounted at a high density, a method of manufacturing the same, and a semiconductor device. (Means for Solving the Problems) In order to solve the above problems, in a preferred aspect of the multilayer wiring board of the present invention, the substrate includes a resin substrate as a base, a wiring pattern formed on the substrate, and a wiring pattern covering the wiring pattern. a part of the insulating layer is provided with a pillar made of a metal mainly composed of copper and connected to the semiconductor wafer at a predetermined position on the wiring pattern, and the pillar is erected on the wiring in a state of penetrating the substrate. On the pattern. Other preferred aspects of the multilayer wiring board of the present invention include: a resin substrate as a base; a wiring pattern formed on the substrate; and a wiring pattern on one surface of the substrate while covering the wiring pattern In the insulating layer formed, the insulating layer has the same strength in the MD direction and the TD direction. In the above aspect, in the insulating layer, the MD (machine direction) direction belonging to the substrate flow direction and the TD direction (Transverse Direction) belonging to the substrate vertical direction are set to the same intensity. As a result, a multilayer wiring board having less warpage and flatness can be provided even in the case where the insulating layer is laminated on the substrate. Further, by forming the upper and lower symmetrical structures on the upper and lower sides of the substrate, there is no possibility of warpage of the substrate, and low thermal expansion can be achieved, and even if the substrate is a large-sized substrate, the mounting deviation does not occur. Preferably, in the above aspect, the insulating layer is characterized by casting. In this aspect, when the insulating layer is laminated, it is carried out by casting (solution casting), whereby no physical alignment is applied to the film, so that alignment of the polymer does not occur, and There is no directionality in strength or optical properties. Further, the insulating layer type product which is commercially available as a film has a constant thickness. However, as described above, the insulating layer can be cast to have an arbitrary thickness, and for example, an inclined structure can be produced. Therefore, it is also possible to prevent the product from being enlarged due to the thickness of the insulating layer which is not required. Further, it is possible to use a material having a thickness which is arbitrarily set in consideration of a signal delay or a CTE (linear expansion coefficient) which is an insulating layer and conforms to a circuit density or a target, and has a high degree of design freedom. 201248800 (Effects of the Invention) According to the present invention, occurrence of reflow cracking or electron migration can be suppressed. Further, it is possible to provide a multilayer wiring board which is excellent in impedance integration due to flatness and high in design freedom, and which can be mounted at a high density, a method of manufacturing the same, and a semiconductor device. [Embodiment] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. As described above, the present invention can be grasped as an invention of a multilayer wiring board, and can also be understood as a method of manufacturing the multilayer wiring board and a semiconductor device. Therefore, the configuration of the semiconductor device will be described below with reference to the embodiment, and then the configuration of the multilayer wiring substrate will be specifically described, and a method of manufacturing the multilayer wiring substrate will be described. [1. First Embodiment] A semiconductor device (100) is a semiconductor package having a structure of a TSV (through-silicon via). As shown in Fig. 1, it is mainly controlled by a semiconductor wafer laminate 10. The device 20 and the interposer 30 are formed. As shown in Fig. 2, the semiconductor wafer laminate 10 is formed by laminating a plurality of Si semiconductor wafers 12. Each of the semiconductor wafers 12 functions as a DRAM (Dynamic Random Access Memory). A through hole 14 (Via) is formed in each semiconductor wafer 12, and a through electrode 16 is formed through the through hole 14. Each of the semiconductors 201248800 wafers 12 is electrically connected to the other semiconductor wafers 12 or the controller 20 through the through electrodes 16. The controller 20 has a semiconductor wafer 22 made of Si. A through hole 24 ( Via) is also formed in the semiconductor wafer 22, and a through electrode 26 is formed through the through hole 24. The semiconductor wafer 22 is packaged by the underlying chelating material 28. The controller 20 is electrically connected to the semiconductor wafer laminate 1 or the interposer 30 via the through electrodes 26. The interposer 30 is a wiring substrate for expanding the electrode pitch of the semiconductor wafer 22. The interposer 30 is an interposer of a so-called solder bump in which a bump is formed on a flexible flexible substrate. As shown in Fig. 3, the interposer 30 has a resin substrate 32 as a base. The substrate 32 is made of, for example, a polyimide resin, a phenol resin, an epoxy resin, a polyester resin, a fluororesin or the like, and is preferably made of a polyimide resin. An insulating layer 34 is formed on the lower portion of the substrate 32. The insulating layer 34 is composed of a subsequent agent layer 36 and a reinforcing film 38. The adhesive layer 36 is made of, for example, an epoxy-based adhesive or a polyimide-based adhesive, and is preferably composed of an epoxy-based adhesive. The reinforced film 38 is composed of, for example, a film made of a polyimide resin. An insulating layer 40 is formed on the lower portion of the insulating layer 34. The insulating layer 40 is a layer formed of a solder resist. A wiring pattern 50 having a three-dimensional structure from the adhesive layer 36 of the insulating layer 34 to the insulating layer 40 is formed on the substrate 32. The wiring pattern 50 is composed of a metal crucible containing copper as a main component. -10- 201248800 "Metal based on copper" means an alloy which may be a copper monomer or may be added with nickel, cobalt or iron. In the case of a metal alloy containing copper as a main component, the amount of nickel or the like added to copper is preferably 20% or less. The wiring pattern 50 is mainly composed of a lower wiring portion 52, a connection wiring portion, and an upper wiring portion 56. For easy understanding of the following description, the line pattern 50 is divided into such parts, but the parts are actually formed. The lower wiring portion 52 is covered by the insulating layer 40. The insulating layer 40 is patterned into a predetermined pattern, and a part of the lower wiring portion 52 is exposed by the opening portion 42 of the insulating layer 40. The exposed portion of the lower wiring portion 5 2 functions as a portion connecting electrode, and a solder ball or the like is formed on the exposed portion, and the semiconductor device 1 is mounted on a circuit board such as a motherboard. The connection wiring portion 54 is formed to penetrate the reinforcing film 38. The junction wiring portion 54 is connected to the lower wiring portion 52 and the upper wiring portion 56 to connect the wiring portions. The upper wiring portion 56 is formed in the adhesive layer 36. A pillar 60 is formed in the upper fitting portion 56. The pillar 60 is erected on the wiring pattern 50 in a state of penetrating the substrate 32. The front end portion (top portion 64) of the pillar 60 is slightly exposed by the substrate 32. The substrate 32 covers the side surface of the pillar 60 in a state where the tip end portion (top portion 64) of the pillar is protruded, and functions as a protective layer for protecting the pillar. Solder bumps 62 are formed on the pillars 60. The solder bump 62 is formed of, for example, a tin-silver alloy by a bump electrode electrically connected to an electronic component such as a semiconductor wafer. For the 54-linkage layer, the outer body is connected to the lower thread portion 60. -11 - 201248800 As shown in the enlarged portion of Fig. 3, the pillar 60 has a shape in which the tip portion 64 is tapered toward the base portion 66 (inverted tapered shape). The top portion 64 is a portion that is connected to the semiconductor wafer 22 of the controller 20 through the solder bumps 62. The base portion 66 is a portion that is connected to the upper wiring portion 56 of the wiring pattern 50. For example, the diameter of the top portion 64 is +10 to 20 μm with respect to the electrode 29 of the semiconductor wafer 22 (see Fig. 2, referred to later), and the diameter of the base portion 66 is ±10 μm with respect to the diameter of the electrode 29 of the semiconductor wafer 22. Since the pillar 60 has the shape as described above, the top portion 64 of the pillar 60 has a large area when viewed from the base portion 66, and the positional displacement between the electrodes when the semiconductor wafer 22 is connected can be prevented. On the other hand, the base portion 66 of the pillar 60 has a small area when viewed from the top portion 64, and prevents a positional shift from the upper wiring portion 56 when the pillar 60 is formed, or the pillar 60 is erroneously connected to the desired upper wiring. The adjacent upper wiring portion 56 of the portion 56. However, although omitted in FIG. 3, the interface between the substrate 32, the insulating layer 34, the insulating layer 40 and the wiring pattern 50, or the interface between the substrate 32 and the pillar 60 is formed with a base metal layer, and the wiring pattern 50 or the pillar 60 is opposed to the substrate. The adhesion of 32 is improved. The underlying metal layer is composed of, for example, a nickel-chromium alloy or copper. The various dimensions of the semiconductor device 100 having the above configuration are, for example, as follows (see Figs. 1 to 3). The package size (interposer 30) is llmm x l5 mm. The wafer size (half-turn wafer 12) is 7 mm x 8 mni. The diameter a of the through electrode 16 is 20 μm. The pitch b of the through electrode 1 6 is 3 5 μη!. -12- 201248800 The diameter c of the through electrode 26 is 20 μm. The pitch d between the through electrodes 26 is 70 μm. The diameter e of the strut 60 is approximately 20 μm. The pitch f between the solder bumps 6 2 is 70 μm. The pitch g between the external connection electrodes (solder balls) was 800 μm. The height h of the solder bump 62 is 5 μm. The height i of the pillar 60 is 35 μm. The thickness j of the substrate 32 is 25 μm. The height k of the connection wiring portion 54 of the wiring pattern 50 is 38 μm. As described above, with the semiconductor device 100, the pitch b between the through electrodes 16 of the semiconductor wafer 12 is expanded from 35 μm to 70 μm by the controller 20 (semiconductor wafer 2 2 ), and the pitch between the through electrodes 26 of the semiconductor wafer 22 d is greatly expanded from 70μηι to 800μηι by the interposer 30. Here, in the semiconductor device 100, the controller 20 (semiconductor wafer 22) is formed with an electrode 29 projecting from the bottom surface toward the interposer 30 side. The total height of the electrode 29 of the semiconductor wafer 22 and the height of the pillar 60 of the interposer 30 (see Fig. 2) is preferably 3 5 μίη or more, more preferably 50 μm or more. At this time, either the electrode 29 of the semiconductor wafer 22 and the pillar 60 of the interposer 30 may be higher, but it is preferable to raise the pillar 6〇 to ensure the sensibility of the pillar 60 to be 3 5 μm or more. This is based on (i) if it is desired to ensure the height on the side of the semiconductor wafer 2 2, it is necessary to manufacture the electrode 29' for each semiconductor wafer 2 2 (each), and it is relatively labor intensive to do so. The side ensures that the twister 'in the r〇n-to_r〇n (roller-roller) manner can be compared with the -13-22 201248800 for the easy manufacture of the pillar 60' (ii) if the yield of the semiconductor wafer and the interposer 30 is taken into consideration In the case where the height is secured on the side of the interposer 30, the yield is better. Therefore, it is preferable that the electrode 29 of the semiconductor wafer 22 is composed only of a pad electrode, and it is preferable that the electrode 29 is not formed with a bump or the like. Next, a method of manufacturing the interposer 30 will be described. The interposer 30 is transported by winding an elongated substrate wound around a predetermined roll around another roll, and is manufactured by a roll-to-roll method in which the wiring pattern 30 or the like is formed during the transfer. Specifically, first, as shown in Fig. 4, the dry film 70 is laminated on the substrate 32, and exposure is performed to cure the dry film 70 (S1). Thereafter, a penetration 72 is formed at a predetermined position of the substrate 32 and the dry film 70 by laser, and the slag (shaving) is removed (S2). Thereafter, the metal is sputter-plated on the substrate 32 and the dry film 70 to form a basal layer 74 (S3). Thereafter, a resin dry film 76 is laminated on the metal underlayer 74 on the lower surface side of the substrate 32, and the dry film 76 is exposed/developed using a mask corresponding to the pattern of the upper wiring portion 56, and a resin layer (pre-patterned) is used. The film 76) is coated with the metal base layer 74 (S4). Thereafter, a metal containing copper as a main component is plated on the metal base layer 74 formed by the dry film 76, a metal layer 78 is formed on the metal base layer 74, and the metal layer 79 is also filled in the through hole 72 (S5). Thereafter, a resin dry film 80 is adhered to the metal layer 78 and the dry film 76 on the lower surface side of the substrate, and the metal base layer 74 and the metal layer 78 on the upper surface side of the dry film 70 are removed and removed (S6). As a result, a -60-201248800 pillar 60 is formed which is formed by the metal layer 79 which is formed by the total thickness of the metal layer 79 to cause the pores to be condensed and 32 etched. In the process of S2, the output of the laser is adjusted to be gradually lowered from the upper side to the lower side, and the through hole 72 is formed into a thin tip shape (inverted shape). As a result, the pillar 60 having a fine tip shape can be formed (refer to the majority of Fig. 3). Thereafter, solder is applied to the pillars 60 to form solder bumps (S7), and the dry films 70, 76, and 80 formed on the substrate 32 are stripped (S8). Thereafter, as shown in Fig. 5, the resin film 82' is adhered to the substrate 32, and the metal base layer of the portion covered with the dry film 76 is etched and removed (S9). As a result, the upper wiring portion 5 6 » of the wiring pattern 50 formed of the metal layer 78 is formed, and then an adhesive is applied on the lower surface side of the substrate 3 2 to form the bonding layer 3 6 and laminated on the adhesive layer 36. The reinforced film 38 is covered with the insulating portion 34 with the upper wiring portion 5 6 (S 1 0 ). Thereafter, heating is performed to harden the adhesive layer 36, and the dry film 82 is peeled off (S1 1 ). Thereafter, the laser is formed so as to form the through hole 84 at a predetermined position of the insulating layer 34 to the exposed upper wiring portion 56, and the slag (shaving) is removed (S12). Thereafter, the metal layer 86 is formed by sputtering on the insulating layer 34, the through hole 84, and the upper wiring portion 56 (S13). Thereafter, a resin-made dry film 88 is laminated on the plate 32, and a resin-made dry film 90 is also formed on the metal base layer 86, and the dry film 90 is exposed by using a mask corresponding to the lower wiring portion 52 and the connection wiring portion. / Developing, after coating the metal base layer 86 (S14) with the patterned resin layer (dry film 90), as shown in Fig. 6, the metal base exposed from the dry film 90 is tapered to 62 to form a coating layer The metal layer 92 is formed on the metal base hole 84 and the upper wiring portion 56 by plating the base layer 54 - 201248800 layer 86 with a copper-based metal as the main component (S1: dry film 90 peeling (S 1 6) After that, the underlayer 86 of the dry film 90 is etched and removed. As a result, the lower wiring portion 52 of the wiring pattern 50 of the gold j and the connection wiring are formed, and then the dry film 886 is peeled off. 52 and the connection wiring portion 54 are laminated with a resin solder resist 40, and the insulating layer 40 is formed by using a mask of a predetermined pattern (S 17). As a result, a part of the opening portion 52 is formed in the insulating layer 40 by the opening portion 42. Exposed (shaped bungee.) Can be manufactured by the above processing of S1 to S17 According to the semiconductor device 100 described above, in the interposer 6 〇, the formed portion is filled with the substrate 32 or the underlying susceptor. Therefore, when the semiconductor device 100 is to be mounted on the main board, stress is relieved and reflow can be suppressed. In addition, cracks are formed in the interposer 30, and the β-conductor wafer 22 is separated from the wiring pattern 50 of the interposer 30, so that electron migration can be suppressed. [2. Second embodiment] The second embodiment is The configuration of the interposer is the same as that of the first embodiment, and the other configuration is the same as that of the first embodiment. As shown in Fig. 7, the interposer layer 86 of the present embodiment is penetrated 5). Thereafter, the coated metal base layer 92 constitutes a portion 54. The lower portion of the layer 34' is patterned to form an insulating layer; line exposure/development 42, lower wiring 戎 externally connected to the electrical layer 30. 30. The resin such as the pillars 2 8 is formed: the circuit board and the like are used as the base of the daemon 20, and the predetermined interval 1 is ensured. In the case of the c-16-201248800 substrate 32, an insulating layer is formed. 3 4, an insulating layer 40 is formed on the lower portion of the substrate 32. The pillar 60 is erected on the upper wiring portion 56 of the wiring pattern 50 in a state of penetrating the insulating layer 34 (especially, the reinforcing film 38). In the interposer 200, the insulating layer 34 covers the side surface of the pillar 60 in a state where the tip end portion (top portion 64) of the pillar 60 is protruded, and the insulating layer 34 functions as a protective layer for protecting the pillar 60. Next, a method of manufacturing the interposer 200 will be described. First, as shown in Fig. 8, a through hole 2 1 0 is formed at a predetermined position of the substrate 32 by using a laser, and the slag (shaving) is removed (S21). Thereafter, metal is sputtered on the substrate 32 to form a metal base layer 212 (S22). Thereafter, a metal mainly composed of copper is plated at a predetermined position of the metal base layer 212, a metal layer 214 is formed on the metal base layer, and a metal layer 2: 16 is also filled in the through hole 210 (S23). Thereafter, the metal base layer 2 1 2 exposed by the metal layer 214 is etched and removed (S 24 ). As a result, the wiring pattern 50 composed of the metal layer 214 and the metal layer 216 is formed. Thereafter, an adhesive is applied to the upper surface side of the substrate 3 2 to form an adhesive layer 3 6, and a reinforcing film 38 is laminated on the adhesive layer 36, and the upper wiring portion 56 of the wiring pattern 50 is covered with an insulating layer 34. At the same time, a resin solder resist is laminated on the lower surface side of the substrate 32 to form the insulating layer 40', and the lower wiring portion 52 of the wiring pattern 50 is covered with the insulating layer 40 (S25). Thereafter, the resin-made dry film 2 1 8 ' is adhered to the insulating layer 34 to be exposed, and the dry film 21 8 is cured (S26). Then, 'through the laser', at the predetermined position of the dry film -17-201248800 2 1 8 and the insulating layer 34, the through hole 220' is formed until the upper wiring portion 56 is exposed, and the laser is used, and the predetermined position of the insulating layer 40 is also A through hole (opening 42) is formed until the lower wiring portion 52 is exposed, and the dross (shaving) is removed (S27). Thereafter, as shown in FIG. 9, a metal base layer 22 is formed by sputtering a metal on the dry film 218 and the through hole 220, and a metal base layer 224 is formed by sputtering a metal on the insulating layer 40 and the opening 42 (S28). . Thereafter, a resin-made dry film 22 6 is adhered to the metal base layer 224, and a metal mainly composed of copper is plated on the metal base layer 222, a metal layer 228 is formed on the metal base layer 222, and a metal is also filled in the through hole 220. Layer 230 (S29). Thereafter, the metal base layer 222 and the metal layer 228 on the dry film 218 are etched and removed (S30). As a result, the pillar 60 composed of the metal layer 230 is formed. Thereafter, the solder bumps 62 are formed by plating the solder on the pillars 60, and the dry film 232 is laminated on the solder bumps 62 and the dry film 218, and exposure is performed to cure the dry film 232 (S31). Thereafter, the dry film 226 formed on the metal base layer 224 is peeled off (S32). Thereafter, the metal base layer 224 is etched and removed, and the dry films 2 18 and 2 3 2 on the insulating layer 34 are simultaneously peeled off (S33). The interposer 200 can be manufactured through the above processes S21 to S33. Here, the interposer 240 of Fig. 10 or the interposer 25 of Fig. 11 may be used instead of the interposer 200. In the interposer 240 of Fig. 10, an insulating layer 242 is formed instead of the adhesive layer 36 and the reinforcing film 38 of the interposer 200. The insulating chips 242 are made of, for example, a polyamine resin. When the interposer 240 is produced, a liquid resin may be cast on the substrate 32 and the upper portion 56 to be cured, and the reinforcing film 38 may be adhered instead of the primer layer 36 in S25. In the interposer 250 of Fig. 11, there is no member corresponding to the adhesive layer 36 of the 200 and the reinforcing film 38. When the interposer 250 is formed, the layer 36 is not formed in S25 to adhere the reinforcing film 38, but the dry film 2 1 8 may be directly adhered to the wiring portion 26 of the substrate 32 in S26. [3. Third embodiment] The third embodiment is mainly different from the first embodiment in the F column. The configuration has the same configuration as that of the first embodiment. As shown in Fig. 2, the semiconductor device 300 is a semiconductor package having a structure of the first (I) (Double Die Package) structure, and a semiconductor wafer 310 of the same type is laminated and packaged. The semiconductor device 300 has a larger size than the semiconductor wafer 31 of the brush substrate 3 20 . A bonding pad is formed on the surface of the printed circuit board 306. An electrode pad 3 24 is formed on the back surface of the printed circuit board 32, and a solder ball 326 is formed on the battery 324. A half piece 310 is placed on the printed substrate 320 through the adhesive layer 3 30. An electrode 312 is formed on the semiconductor wafer 310. The electrode is composed of, for example, copper or gold, solder, or the like. The semiconductor wafer 3 10 0 pole 3 1 2 is in a state of being upward, and the interposer 400 is connected to the interposer 400. The wiring portion is formed with an interposer and an upper portion, and the other | DDP 2 phase 0 is printed with a 3b gate pad conductor. The crystal 3 12 series is electrically charged. The semiconductor wafer 310 and the interposer 400 are additionally laminated on the interlayer 340 through the adhesive layer 340 on the interlayer 190-201248800. An external connection electrode 4〇2 is formed on the outer side of each interposer 400. Each of the external connection electrodes 402 is electrically connected to the bonding pad 322 of the printed circuit board 320 by bonding the wires 350. In the semiconductor device 30, the semiconductor wafer 310 laminated as described above is packaged by the encapsulating resin 366 together with the bonding wires 350. As shown in Fig. 13, the interposer 400 is also formed with the substrate 32 as a base. An insulating layer 410 is formed on the substrate 32. The insulating layer 410 is composed of, for example, an epoxy resin. The pillar 60 is erected on the upper wiring portion 56 of the wiring pattern 50 in a state of penetrating the insulating layer 410. In the interposer 400, the side surface of the pillar 60 is also covered by the insulating layer 410, and the insulating layer 410 functions as a protective layer for the protective pillar 60. The lower wiring portion 52 of the wiring pattern 50 is covered with the metal layer 412 to constitute the external connection electrode 402. The metal layer 412 has a structure in which, for example, nickel or gold is laminated. Next, a method of manufacturing the interposer 400 will be described. First, as shown in Fig. 14, the substrate 32 is prepared (S41), and the side edge portion of the substrate 3 2 is punched to pierce the hole 420 for holding the transfer roller at a predetermined interval (S42). Thereafter, a through hole -20-201248800 422 is formed at a predetermined position of the substrate 3 2 by using a laser, and the slag (shaving) is removed and washed (S43). Thereafter, metal is sputtered on the substrate 32 to form a metal base layer 42 4 (S44). Thereafter, resin dry films 426 and 428 are laminated on both surfaces of the substrate 32 (S45), and exposure and development are performed using a mask having a shape corresponding to the upper wiring portion 56 and the lower wiring portion 52 of the wiring pattern 50 (S46). Thereafter, the metal base layer 424 exposed by the dry films 426, 428 is plated with a metal mainly composed of copper, a metal layer 430 is formed on the metal base layer 424, and the metal layer 432 is also filled in the through holes 422 (S47). Thereafter, as shown in Fig. 15, the dry film 4 2 6 and 4 2 8 are peeled off (S48), and the metal base layer 424 covered by the dry films 426 and 428 is etched and removed (S49). As a result, the wiring pattern 50 (the upper wiring portion 56, the lower wiring portion 52, and the connection wiring portion 5 4) composed of the metal layer 430 and the metal layer 432 is formed. Thereafter, a resin-made adhesive (or insulating layer) is adhered to the upper surface side of the substrate 3 2 to form an insulating layer 4 1 0 (S 5 0 ). Thereafter, metal is plated on the lower wiring portion 52 to form a metal layer 412 (S51). Thereafter, a resin-made dry film 434 is adhered to the lower surface side of the substrate 32, and a through hole 436 is formed at a predetermined position of the insulating layer 410 to expose the upper wiring portion 56 by using a laser, and the slag (shaving) is removed ( S52). After that, the upper wiring portion 56 exposed by the through hole 436 is plated with a metal containing copper as a main component to form the pillar 60, and the pillar 60 is plated with solder to form the solder bump 62, and finally the dry film 434 is peeled off (S53). ). The interposer 400 can be manufactured through the processes of S41 to S53 described above. -21 - 201248800 [Sample Example] (1) Production and manufacture of a semiconductor device having the same configuration as that of Fig. 2 and a semiconductor device having the same configuration as that of Fig. 2, and the like As a sample. In the semiconductor device, 'the size of the package is 5 mm and 10 mm square, and the height of the rice of the semiconductor wafer or the height of the pillar of the interposer is appropriately changed, and the sample 1 to 1 2 is used. Refer to Table 1), Sample 1 3~2 2 (2). In Tables 1 and 2, "(Note)" of the samples 2, 4, 6, 8, 10, and 1 16 indicates that the solder pad is used on the side of the semiconductor wafer, and the length of the pad electrode is extended from the semiconductor wafer. (2) Evaluation of the sample (2.1) Reflow crack test Each sample was subjected to reflow treatment to observe the presence or absence of reflow treatment marks. The observation results are shown in Tables 1 and 2. In Tables 1 and 2, the reference for 〇 and △' X is as follows: “〇”...5mm square, 10mm square without cracks “△”...5mm square without cracks, but l〇mm sees more than the package The crack "X"...5 mm square, 10 mm square are combined in a pattern of _t TSV structure DPP, the area is referred to Table 2, 14, electrode, and the crack is in one package-22 - 201248800 Body crack (2.2) Long-term reliability test (electron migration) In each sample, after initial state and after being placed in a certain environment (1 10 °C, 85% RH, 1.95V, 500 hours) To determine the resistance 値. If the increase in resistance 为 is within 1 〇%, it is evaluated as “〇”, and if it exceeds 10% ’, g is estimated to be “X”. The evaluation results are shown in Tables 1 and 2. [Table 1] Sample 1 2 3 4 5 6 Characteristic package structure TSV D] DP TSV Wafer side electrode height (μηι) 15 Retrograde bump 1 (Note) 15 (Copper bump) 1 (Note) 15 (Copper Bump) 1 (Note) Interposer side strut height (μηι) 35 49 35 49 34 48 Total (μηι) 50 50 50 50 49 49 Evaluation of reflow cracks 〇〇〇〇〇〇 Electron migration test Sample 7 8 9 10 11 12 Characteristic package construction D] DP TSV D1 DP Wafer side electrode height (μηι) 1.5 (copper bump) 1 (Note) 15 (copper bump) 1 (Note) 15 (copper bump) 1 (Note) Intermediary side pillar height (μιη) 34 48 20 34 20 34 Total (μηι) 49 49 35 35 35 35 Evaluation of reflow crack 〇〇 Δ Δ Δ 电子 Electron migration 〇〇〇〇〇〇-23- 201248800 [Table 2]

試樣 13 14 15 16 17 18 特 性 封裝體構造 TSV DDP TSV 晶片側電極高度 (μηι) 15 (銅凸塊） 1 (註） 15 (銅凸塊） 1 (註) 35 (金柱凸塊） 50 (金柱凸塊） 中介層側支柱高度 (μηι) 19 33 19 33 (僅焊料凸塊) (僅焊料凸塊) 合計 (μη) 34 34 34 34 35 50 評 估 迴焊裂痕 X X X X 〇 〇 電子遷移 〇 〇 〇 〇 X XSample 13 14 15 16 17 18 Characteristic Package Construction TSV DDP TSV Wafer Side Electrode Height (μηι) 15 (Copper Bump) 1 (Note) 15 (Copper Bump) 1 (Note) 35 (Gold Stud) 50 (gold stud bump) Interposer side strut height (μηι) 19 33 19 33 (solder bump only) (solder bump only) Total (μη) 34 34 34 34 35 50 Evaluation of reflow cracks XXXX 〇〇 Electron migration〇 〇〇〇XX

試樣 19 20 21 22 特 性 封裝體構造 TSV DDP TSV 晶片側電極高度 (μηι) (焊料凸塊） 35 (金柱凸塊） 50 (金柱凸塊） (焊料凸塊） 中介層側支柱高度 (μη) (僅焊料凸塊） (僅焊料凸塊） (僅焊料凸塊） (僅焊料凸塊） 合計 (μηι) - 35 50 - 評 估 迴焊裂痕 X 〇 〇 X 電子遷移 X X X X (3 )結論 如表1及表2所示，若將試樣1〜1 6與試樣1 7〜22 作比較，可知在中介層側形成有支柱的試樣1〜〗6中，在 長期可靠性試驗中獲得良好的結果，爲了提升長期可靠 性，以在中介層形成支柱較爲有用。 尤其若將各試樣1〜1 6作比較，可知在中介層側的支 柱的高度爲35μηΊ以上的試樣1〜8屮，既不會發生迴焊 -24- 201248800 裂痕，在防止迴焊裂痕發生方面，以將支柱的高度形成爲 35μηι以上較爲有用。 〔4 .第4實施形態〕 〔4-1.半導體裝置之構成〕 本實施形態之半導體裝置500係具有所謂 TSV (Through Silicon Via )構造的半導體封裝體，如第16 圖所示’由多層配線基板510、半導體晶片層積體S、及 被配置在多層配線基板510與半導體晶片層積體S之間的 控制器C所構成。 如第16圖所示，半導體晶片層積體S係層積複數枚 S i製的半導體晶片S1所構成。各半導體晶片S 1係作爲 DRAM (Dynamic Random Access Memory)而發揮功能。 在各半導體晶片SI形成有貫穿孔S2( Via)，通過貫穿 孔S2而形成有貫穿電極S3。各半導體晶片si係通過貫 穿電極S3而與其他半導體晶片si或控制器C作電性連 接。 控制器C係由Si製的半導體晶片C1所構成。在半導 體晶片C1亦形成有貫穿孔C2 ( Via )，通過貫穿孔C2 (Via)而形成有貫穿電極C3。半導體晶片C1係藉由底 層塡充材料C4予以封裝。控制器C係通過貫穿電極C3 而與半導體晶片層積體S或多層配線基板5 1 0作電性連 接。 -25- 201248800 〔4-2.多層配線基板之構成〕 多層配線基板5 1 0係供半導體晶片C 1的電極間距擴 張之用的配線基板。多層配線基板510係在可撓性的可撓 性基板形成有凸塊之所謂附焊料凸塊的多層配線基板。 如第1 6圖及第1 7圖所示，多層配線基板5 1 0係具有 作爲基底的樹脂製基板5 1 1。基板5 1 1亦可藉由例如玻 璃、矽氧樹脂、聚亞醯胺樹脂、酚醛樹脂、環氧樹脂、聚 酯樹脂、氟樹脂等任何樹脂來形成。在本實施形態中，以 藉由玻璃、矽氧樹脂或聚亞醯胺樹脂來形成爲佳。 多層配線基板510係在基板511的上部具備絕緣層 512，與此對稱在基板511的下部具備絕緣層513。該等 絕緣層係藉由聚亞醯胺樹脂所形成，對基板5 1 1，藉由澆 鑄（溶液澆鑄法（solution casting))進行積層而形成。 藉此所積層的絕緣層5 1 2、5 1 3之任一者或二者係在 屬於基板流動方向的MD( Machine Direction)方向、及 屬於基板垂直方向的TD方向（Transverse Direction)， 使強度爲相同。 在此，在本實施形態之絕緣層之澆鑄中，爲了防止孔 隙（層積孔隙，亦即在通常應該有的區域沒有樹脂或接著 劑）發生，將屬於聚亞醯胺樹脂之前驅物的黏度低的清漆 塡充在電路間且在乾燥後，將黏度高的清漆進行澆鑄。該 清漆的澆鑄（塗佈、硬化）係進行複數次，俾以展現平坦 性。其中，各清漆的黏度、澆鑄次數係按照L/ S (電路 密度）或電路厚度、CTE的傾斜情況來作適當設定。藉由 -26- 201248800 如上所示之澆鑄所形成的絕緣層係維持與配線圖案的密接 性，不會發生孔隙。 在基板5 1 1上形成有由絕緣層5 1 2至絕緣層5 1 3具有 3次元構造的配線圖案5 1 4。配線圖案5 1 4係由以銅爲主 成分的金屬所構成。「以銅爲主成分的金屬」係指可爲銅 單體，亦可爲對銅添加有鎳、鈷、鐵等的合金。若爲將以 銅爲主成分的金屬形成爲合金時，相對銅的鎳等的添加量 較佳爲20%以下。 配線圖案514主要由下部配線部514a、連結配線部 514b、及上部配線部514c所構成。爲了易於瞭解之後的 說明，將配線圖案5 1 4劃分爲該等部位，但是該等部位在 實際上爲一體形成。 下部配線部514a係被絕緣層513所被覆。絕緣層 513係被圖案化成預定圖案，下部配線部514a的一部分 由絕緣層5 1 3的開口部5 1 3 a露出。下部配線部5 1 4 a的露 出部作爲外部連接電極而發揮功能，在該露出部形成焊球 等，半導體裝置500被構裝在主機板等的電路基板。 連結配線部5 1 4b係以貫穿絕緣層5 1 3及基板5 1 1的 方式形成，在上下端部中連接於下部配線部514a與上部 配線部514c而將該等配線部相連結。 上部配線部514c係形成在絕緣層512中。在上部配 線部5 1 4c形成有支柱5 1 5。支柱5 1 5係在貫穿絕緣層5 1 2 的狀態下立設於配線圖案5 1 4上。支柱5 1 5的前端部（頂 部515b)係由絕緣層512露出。絕緣層512係在使支柱 -27- 201248800 的前端部（頂部515b)突出的狀態下被覆支柱515的側 面，作爲保護支柱515的保護層而發揮功能。 在支柱515上形成有焊料凸塊515a。焊料凸塊515a 係用以與半導體晶片等電子元件作電性覆晶連接的突起電 極，由例如錫-銀-銅合金所構成。 如第1 7圖之擴大部所示，支柱5 1 5係呈由頂部5 1 5b 朝向基部5 1 5 c爲尖端細形狀（倒錐狀）。頂部5 1 5b係透 過焊料凸塊5 1 5 a而與控制器C的半導體晶片C 1相連接 的部位。基部5 1 5c係與配線圖案5 1 4的上部配線部5 1 4c 相連接的部位。例如，頂部5 1 5b的直徑係相對半導體晶 片C1的電極C5(第16圖）的直徑爲+10〜520μηι，基部 515c的直徑係相對半導體晶片C1的電極C5的直徑爲± 1 0 μ m。 支柱515呈如上所示之形狀，因此支柱515的頂部 5 1 5b係由基部5 1 5 c俯視時的面積大，可防止與半導體晶 片C1連接時的電極間的位置偏移。另一方面，支柱515 的基部5 1 5 c係由頂部5 1 5 b俯視時的面積小，可防止在支 柱5 1 5形成時與上部配線部5 1 4 c的位置偏移、或支柱 5 1 5誤連接於所希望的上部配線部5 1 4c的相鄰的上部配 線部514c。 其中，在第17圖中雖省略，在基板511、絕緣層512 及絕緣層5 1 3與配線圖案5 1 4的界面、或絕緣層5 1 2與支 柱515的界面形成有基底金屬層。藉由如上所示之基底金 屬層，提高配線圖案5 1 4或支柱5 1 5對基板5 1 1等的接著 -28- 201248800 性。該基底金屬層係由例如鎳鉻合金或銅等所構成。 具有以上構成的半導體裝置500的各種尺寸係例如設 計成如下所示（參照第1 6圖〜第1 7圖）。 封裝體尺寸（多層配線基板510)爲1 lmmx5 1 5 mm ° 晶片尺寸（半導體晶片Cl)爲7mmx8mm。 貫穿電極C3的直徑a爲20μηι。 貫穿電極C3間的間距b爲35μιη。 貫穿電極C3的直徑c爲20μιη。 貫穿電極C3間的間距d爲70μηι。 支柱515的直徑e大約爲20μηι。 焊料凸塊515a間的間距f爲70 μηι。 外部連接電極（焊球）間的間距g爲800μηι。 焊料凸塊515a的高度h爲5μηι。 支柱515的高度i爲35μηι。 基板51 1的厚度j爲38μπα。 配線圖案514的連結配線部514b的高度k爲38μηι。 在此’在半導體裝置500中，在控制器C (半導體晶 片C 1 )係形成有由底面朝向多層配線基板5 1 0側突出的 電極C5。該半導體晶片C1的電極C5的高度與多層配線 基板51〇的支柱515的高度的合計Η(參照第16圖）較 佳爲53 5 μηι以上，更佳爲50μπι以上。 此時，在半導體晶片C1的電極C5與多層配線基板 510的支柱515中任一者較高均可，但是較佳爲提高支柱 515而將支柱515的高度確保35μηι以上。此係基於（i) -29- 201248800 若欲在半導體晶片c1側確保高度時，必須按每個半導體 晶片C1 (每一枚）製造電極C5，較耗費勞力，相對於 此，以欲在多層配線基板510側確保高度者，以r〇ll-t〇-r〇U (輥-輥）方式可較爲容易製造支柱515之故。此外， (ii)若考慮到半導體晶片C1與多層配線基板510的良 率時，以在多層配線基板5 1 0側確保高度者，總良率較佳 之故。因此，較佳爲半導體晶片C1的電極C5係僅由焊 墊電極所構成，在電極C5未形成凸塊等爲佳。 〔4_ 3.多層配線基板之製造方法〕 接著，說明多層配線基板5 1 0之製造方法。 如第18圖所示，使用雷射而在基板511的預定位置 形成貫穿孔A1，去除其膠渣（削屑）（SI)。之後，在 基板5Π濺鍍金屬而形成金屬基底層B1(S2)。 之後，在金屬基底層B1的預定位置鍍敷以銅爲主成 分的金屬，在金屬基底層形成金屬層ML1，並且在貫穿孔 A1亦塡充金屬層ML2(S3)。之後，將由金屬層ML1露 出的金屬基底層B1進行蝕刻而去除（S4)。結果，形成 由金屬層ML 1及金屬層M L2所構成的配線圖案514 (下 部配線部5 1 4a、連結配線部5 1 4b及上部配線部5〗4c )。 之後，在基板5 1 1的上面側的配線圖案5 1 4 (上部配 線部5 1 4c )上，藉由澆鑄，形成由聚亞醯胺樹脂所構成 的絕緣層5 1 2，以絕緣層5 1 2被覆配線圖案5 1 4的上部配 線部5 1 4c。同時，在基板5 1 1的下面側亦在配線圖案 -30 - 201248800 上，藉由澆鑄，形成由聚亞醯胺樹脂所構成的絕緣層 5 1 3，以絕緣層5 1 3被覆配線圖案5 1 4的下部配線部5 1 4a (S5 ) 〇 在此，在本實施形態之絕緣層的澆鑄中，如上所述’ 爲了防止孔隙發生，將屬於聚亞醯胺樹脂之前驅物的黏度 低的清漆塡充在電路間，乾燥後，將黏度高的清漆進行澆 鑄。該澆鑄係進行複數次，俾以展現平坦性。 之後，在絕緣層5 1 2上黏貼樹脂製乾膜D 1，進行曝 光而使乾膜D1硬化（S6)。之後，使用雷射，在乾膜D1 及絕緣層512的預定位置至露出上部配線部514c爲止形 成貫穿孔A2。與此同時，使用雷射，在絕緣層513的預 定位置亦至露出下部配線部5 1 4 a爲止形成貫穿孔（開口 部5 1 3 a )，且將該等膠渣（削屑）去除（S7 )。 之後’如第19圖所示，在乾膜Di及貫穿孔A2濺鍍 金屬而形成金屬基底層B2，並且在絕緣層513及開口部 513a亦濺鍍金屬而形成金屬基底層B3(S8)。之後，在 金屬基底層B3黏貼樹脂製乾膜〇2，並且在金屬基底層 B2鍍敷以銅爲主成分的金屬，在金屬基底層B2形成金屬 層ML3 ’此外，在貫穿孔A2亦塡充金屬層ML4 ( S9 )。 之後’將乾膜D1上的金屬基底層B2及金屬層ML3進行 鈾刻而去除（S10)。結果，形成由金屬層ML4所構成的 支柱5 1 5。 之後’在支柱5 1 5鑛敷焊料而形成焊料凸塊5 1 5 a， 在焊料凸塊515a及乾膜D1上層疊乾膜D3,進行曝光而 -31 · 201248800 使乾膜D3硬化（S11)。之後’將形成在金屬基底f 的乾膜D2剝離（S12)。之後，將金屬基底層Β3進 刻而去除，將絕緣層512上的乾膜D1、D3同時 (S13 )。 可經由以上s 1〜S 1 3的處理來製造多層配線 5 10° 〔4-4.效果〕 (基板的翹曲減低效果） 藉由以上的多層配線基板510及具備此之半導體 5 00，藉由進行澆鑄，在絕緣層512、513中，在屬於 511之流動方向的MD方向、及屣於基板511之垂直 的TD方向，可使強度爲相同。因此，即使在基板5 兩面，藉由積層來形成絕緣層5 1 2、5 1 3，亦可減低 所造成之基板511的翹曲。尤其，藉由相同材料來構 含基板511的絕緣層的全部，藉此可更加有效地減低 5 1 1的翹曲。 此外，藉由將上下絕緣層512及513形成爲對 造，不會有基板511翹曲的情形，同時可實現低熱膨 因此，即使爲較大尺寸的基板，亦不會發生構裝偏移 (使用聚亞醯胺樹脂的效果） 將包含基板5 1 ]的絕緣層5 1 2、5 1 3的任一者或 形成爲聚亞醯胺樹脂，藉此可提供由良好的耐熱性與 I B3 行蝕 剝離 基板 裝置 基板 方向 11的 因此 成包 基板 稱構 脹。 全部 低介 -32- 201248800 電係數、低線膨脹係數所構成的多層配線基板5 i 〇。此 外，使用聚亞醯胺樹脂’而不使用環氧系絕緣材料及抗焊 劑’可實現良好的耐熱性、低介電係數及低線膨脹率，即 使在基板511爲較大的情形下，亦不會發生構裝偏移。 藉由如上所示之聚亞醯胺樹脂所製作的多層配線基板 5 1 0係剛性高’且可進行與玻璃環氧基板同樣的處理，成 爲不需要載體的可撓性基板。因此，可以習知的搬送設備 來對應，亦可對應迴焊方式。此外，與環氧系絕緣材料相 比較，可製作廉價的多層配線基板5 1 0。 (在配線圖案上以澆鑄形成絕緣層的效果） 在積層絕緣層5 1 2、5 1 3時，藉由澆鑄（溶液澆鑄法 (solution casting ))來進行，藉此由於對薄膜不會施加 物理性的壓力，因此不會發生高分子的配向，在強度或光 學特性等不會產生方向性。 此外，作爲薄膜而在市面上販售的絕緣層爲規格品， 厚度一定，但是如本實施形態般，藉由將絕緣層5 1 2、 5 1 3進行澆鑄，可形成任意厚度，而且亦可製作例如傾斜 構造。因此，亦可防止因不需要的絕緣層厚度所造成的製 品肥大化。此外，可使用任意設定考慮到訊號延遲的厚 度、或作爲絕緣層而符合電路密度或目的的CTE (線膨脹 係數）的材料，設計自由度高。 半導體封裝體構裝構造係如上所述，以LSI晶片/ NCP ( Non Conductive Paste) /中介層/底層填充材料/ -33- 201248800 主機板的順序予以層積。其中’在LSI晶片中，CTE小 (3〜5ppm)，在主機板中則大。因此’在本實施形態 中，例如在半導體封裝體中’在多層配線基板5 1 0中，在 絕緣層5 1 2側（LSI晶片側）選擇CTE小的材料，在絕緣 層513側（主機板側）選擇CTE大的材料。藉此，可減 輕對1次（與LSI晶片的連接）、2次（與主機板的連 接）連接端子的負荷。如上所示可提供設計自由度極高的 多層配線基板5 1 0。 此外，在澆鑄中，與熔融押出成型法相比，施加於樹 脂的熱量較低（亦不需要如薄膜狀樹脂般的熔融），可減 低熱安定劑等的添加量。此外，藉由澆鑄時的熔融溫度的 設定，可調整捲曲情形。 此外，藉由如上所示之澆鑄，由於可設置將溶液過濾 的工程，因此不會發生樹脂塊（fisheye)，亦不易造成損 傷，因此可成型出用以使用在絕緣層5 1 2、5 1 3之透明性 高的薄膜。 如上所示，藉由在絕緣層5 1 2、5 1 3的成形使用澆 鑄，具有可形成厚度精度高、平滑性、透明性、光澤性優 異的絕緣層512、513的優點。其中，如上所示藉由使用 澆鑄，可輕易地藉由熔點高且押出成形不易的聚亞醯胺薄 膜來形成絕緣層5 1 2、5 1 3。 〔5 ·第5實施形態〕 第5實施形態係在多層配線基板之構成中與第4實施 -34- 201248800 形態不同，關於其他構成，由於與第4實施形態相同，故 以下僅說明與第4實施形態不同之處。此外，即使爲多層 配線基板之構成，關於未特別提及之處，係沿用第4實施 形態中的說明。 〔5 -1 .多層配線基板之構成〕 如第20圖所示，本實施形態之多層配線基板5 20係 在基板521的上部具備有絕緣層522，與其對稱在基板 52 1的下部具備有絕緣層523。該等絕緣層係與第4實施 形態相同，藉由聚亞醯胺樹脂所形成，對基板52 1使用澆 鑄進行積層而形成。如上所示所積層的絕緣層522、523 的任一者或二者係可在屬於基板流動方向的MD方向、及 屬於基板垂直方向的TD方向中，使強度爲相同。 在基板521上形成有由絕緣層522至絕緣層523具有 3次元構造的配線圖案524。配線圖案524主要由最上部 配線部524a、上部配線部5 24b、連結配線部524c、下部 配線部524d及最下部配線部524e所構成。在此，與第4 實施形態同樣地，爲方便說明起見，將配線圖案524劃分 爲該等部位，但是該等部位實際上係一體形成。 下部配線部5 24d及最下部配線部5 24e係被絕緣層 523所被覆’最下部配線部524e的一部分由絕緣層523 的開口部523 a露出》最下部配線部524e的露出部作爲外 部連接電極而發揮功能，在該露出部形成焊球等，半導體 裝置500被構裝在主機板等電路基板。 -35- 201248800 連結配線部5 2 4 c係以貫穿基板5 2 1的方式形成，在 上下端部中連接於上部配線部5 24b與下部配線部524tJ而 將該等配線部相連結。 上部配線部524b係被絕緣層522所被覆，與上部配 線部524b相連接的最上部配線部524a係露出於絕緣層 522的上部來作配置。絕緣層522係形成爲使最上部配線 部5 2 4 a突出的狀態。 在最上部配線部5 24a上形成焊料凸塊5 2 5，最上部 配線部524a係透過焊料凸塊5 25而與控制器C的半導體 晶片C 1相連接的部位。焊料凸塊5 2 5係用以與半導體晶 片等電子元件作電性覆晶連接的突起電極，由例如錫-銀· 銅合金所構成。 其中，與第4實施形態相同地，形成有基板521、絕 緣層522及絕緣層523與配線圖案524的界面、或基底金 屬層。藉由如上所示之基底金屬層，配線圖案5 24對基板 521等的接著性被提高。該基底金屬層係由例如鎳鉻合金 或銅等所構成。 具有以上構成的多層配線基板520的各種尺寸係例如 設計成如下所示（參照第2 0圖）。 (a)形成在絕緣層5 22的通孔的直徑係在15μηι〜 ΙΟΟμηι的範圍內進行設計。 (b )通孔連接盤（via land )的寬度係設計爲大於 1 6 0 μ m 〇 (C )最上部配線部524a間的空間係設計爲大於 -36- 201248800 1 5 μ m。 (d )線的寬度係設計爲大於1 5 μ m。 (e )最上部配線部5 24a的厚度係設計爲小於 1 8 μ m。 (f)焊料凸塊525的厚度係在2〜8μπι的範圍進行 設計。 (g )最下部配線部524e中的開口部523 a間的間距 係設計爲小於2 5 0 μ m。 (h )最下部配線部 524e的厚度係設計爲小於 1 8 μ m。 (i)基板521的厚度係藉由12.5、5、25、38、40、 5 0 μ m的任一者來進行設計。 〔5 -2 .多層配線基板之製造方法〕 接著，說明多層配線基板520之製造方法。 如第21圖所示，使用雷射而在基板521的預定位置 形成貫穿孔A1，將其膠渣（削屑）去除（S 1 )»之後， 在基板521濺鍍金屬而形成金屬基底層B1(S2)。 之後，在基板52 1的下面側的金屬基底層B1層疊樹 脂製乾膜D1，使用與上部配線部524b、連結配線部524c 及下部配線部524d相對應的圖案的遮罩，將乾膜D 1進 行曝光/顯影而形成。藉此，以預定圖案的樹脂層（乾膜 D1)被覆金屬基底層B1(S3)。 之後，在由乾膜D1露出的金屬基底層B1的預定位Sample 19 20 21 22 Characteristic package structure TSV DDP TSV Wafer side electrode height (μηι) (solder bump) 35 (gold stud bump) 50 (gold stud bump) (solder bump) Interposer side pillar height ( Ηη) (solder bump only) (solder bump only) (solder bump only) (solder bump only) Total (μηι) - 35 50 - Evaluation of reflow cracks X 〇〇X Electron migration XXXX (3) Conclusion As shown in Tables 1 and 2, when the samples 1 to 16 were compared with the samples 17 to 22, it was found that the samples 1 to 6 in which the pillars were formed on the interposer side were obtained in the long-term reliability test. Good results, in order to improve long-term reliability, it is useful to form pillars in the interposer. In particular, when the samples 1 to 16 were compared, it was found that the samples 1 to 8 高度 in which the height of the pillars on the interposer side was 35 μηΊ or more did not cause reflow -24 - 201248800 cracks, and prevented reflow cracks. In terms of occurrence, it is useful to form the height of the pillars to be 35 μm or more. [4. Fourth Embodiment] [4-1. Configuration of Semiconductor Device] The semiconductor device 500 of the present embodiment has a semiconductor package having a so-called TSV (Through Silicon Via) structure, as shown in Fig. 16 The substrate 510, the semiconductor wafer laminate S, and the controller C disposed between the multilayer wiring substrate 510 and the semiconductor wafer laminate S are formed. As shown in Fig. 16, the semiconductor wafer laminate S is formed by laminating a plurality of semiconductor wafers S1 made of Si. Each of the semiconductor wafers S 1 functions as a DRAM (Dynamic Random Access Memory). A through hole S2 ( Via) is formed in each semiconductor wafer SI, and a through electrode S3 is formed through the through hole S2. Each of the semiconductor wafers si is electrically connected to the other semiconductor wafers si or the controller C by penetrating the electrodes S3. The controller C is composed of a semiconductor wafer C1 made of Si. A through hole C2 ( Via ) is also formed in the semiconductor wafer C1, and a through electrode C3 is formed through the through hole C2 (Via). The semiconductor wafer C1 is packaged by the underlying chelating material C4. The controller C is electrically connected to the semiconductor wafer laminate S or the multilayer wiring substrate 5 10 through the through electrode C3. -25-201248800 [4-2. Configuration of multilayer wiring board] The multilayer wiring board 5 10 is a wiring board for expanding the electrode pitch of the semiconductor wafer C 1 . The multilayer wiring board 510 is a so-called solder bump-based multilayer wiring board in which bumps are formed on a flexible flexible substrate. As shown in Fig. 16 and Fig. 17, the multilayer wiring board 510 has a resin substrate 511 as a base. The substrate 51 1 may also be formed of any resin such as glass, epoxy resin, polyamido resin, phenol resin, epoxy resin, polyester resin, fluororesin or the like. In the present embodiment, it is preferably formed of glass, a silicone resin or a polyimide resin. The multilayer wiring board 510 is provided with an insulating layer 512 on the upper portion of the substrate 511, and is provided with an insulating layer 513 at a lower portion of the substrate 511. These insulating layers are formed of a polyimide resin, and are formed by laminating a substrate 51 1 by casting (solution casting). Either one or both of the insulating layers 5 1 2, 5 1 3 which are laminated are in the MD (Machine Direction) direction belonging to the substrate flow direction and the TD direction (Transverse Direction) belonging to the vertical direction of the substrate, so that the strength For the same. Here, in the casting of the insulating layer of the present embodiment, in order to prevent voids (layered pores, that is, no resin or an adhesive agent in a region which should normally be present), the viscosity of the precursor of the polyamidamide resin will be maintained. The low varnish is filled between the circuits and after drying, the viscous varnish with high viscosity is cast. The casting (coating, hardening) of the varnish is carried out a plurality of times to exhibit flatness. Here, the viscosity and the number of castings of each varnish are appropriately set in accordance with L/S (circuit density), circuit thickness, and inclination of CTE. The insulating layer formed by the casting as described above by -26-201248800 maintains the adhesion to the wiring pattern, and voids do not occur. A wiring pattern 5 1 4 having a three-dimensional structure from the insulating layer 51 to the insulating layer 51 1 is formed on the substrate 51 1 . The wiring pattern 5 1 4 is made of a metal mainly composed of copper. The "metal containing copper as a main component" means an alloy which may be a copper monomer or a nickel, cobalt or iron added to copper. When a metal containing copper as a main component is formed into an alloy, the amount of nickel or the like added to copper is preferably 20% or less. The wiring pattern 514 is mainly composed of a lower wiring portion 514a, a connection wiring portion 514b, and an upper wiring portion 514c. In order to facilitate the understanding of the following description, the wiring pattern 5 1 4 is divided into such portions, but the portions are actually formed integrally. The lower wiring portion 514a is covered by the insulating layer 513. The insulating layer 513 is patterned into a predetermined pattern, and a part of the lower wiring portion 514a is exposed by the opening 5 1 3 a of the insulating layer 513. The exposed portion of the lower wiring portion 5 1 4 a functions as an external connection electrode, and a solder ball or the like is formed in the exposed portion, and the semiconductor device 500 is mounted on a circuit board such as a motherboard. The connection wiring portion 5 1 4b is formed to penetrate the insulating layer 513 and the substrate 51 1 , and is connected to the lower wiring portion 514 a and the upper wiring portion 514 c at the upper and lower ends to connect the wiring portions. The upper wiring portion 514c is formed in the insulating layer 512. A pillar 5 15 is formed in the upper wiring portion 5 1 4c. The pillars 5 1 5 are erected on the wiring pattern 5 1 4 in a state of penetrating the insulating layer 5 1 2 . The front end portion (top portion 515b) of the pillar 5 15 is exposed by the insulating layer 512. The insulating layer 512 covers the side surface of the pillar 515 in a state in which the front end portion (the top portion 515b) of the pillar -27-201248800 is protruded, and functions as a protective layer for the protective pillar 515. Solder bumps 515a are formed on the pillars 515. The solder bump 515a is a bump electrode for electrically flip-chip bonding with an electronic component such as a semiconductor wafer, and is made of, for example, a tin-silver-copper alloy. As shown in the enlarged portion of Fig. 7, the pillar 5 15 is formed into a thin tip shape (inverted tapered shape) from the top portion 5 1 5b toward the base portion 5 1 5 c. The top portion 5 1 5b is a portion that is connected to the semiconductor wafer C 1 of the controller C through the solder bumps 5 1 5 a. The base portion 5 1 5c is a portion that is connected to the upper wiring portion 5 1 4c of the wiring pattern 516. For example, the diameter of the top portion 5 1 5b is +10 520 520 μm with respect to the electrode C5 (Fig. 16) of the semiconductor wafer C1, and the diameter of the base portion 515c is ± 10 μm with respect to the diameter of the electrode C5 of the semiconductor wafer C1. Since the pillars 515 have the shape shown above, the top portion 5 15b of the pillars 515 has a large area when viewed from the base portion 5 15 c, and the positional displacement between the electrodes when the semiconductor wafer C1 is connected can be prevented. On the other hand, the base portion 5 1 5 c of the stay 515 is small in plan view from the top portion 5 1 5 b, and can prevent the position of the upper wiring portion 5 1 4 c from being displaced when the pillar 5 15 is formed, or the pillar 5 15 is erroneously connected to the adjacent upper wiring portion 514c of the desired upper wiring portion 5 1 4c. However, although not shown in Fig. 17, a base metal layer is formed on the interface between the substrate 511, the insulating layer 512, the insulating layer 513 and the wiring pattern 516, or the interface between the insulating layer 511 and the pillar 515. The 280-201248800 property of the wiring pattern 5 1 4 or the pillar 5 15 to the substrate 5 1 1 or the like is improved by the underlying metal layer as shown above. The underlying metal layer is composed of, for example, a nickel-chromium alloy or copper. The various dimensions of the semiconductor device 500 having the above configuration are, for example, as follows (see Figs. 6 to 17). The package size (multilayer wiring substrate 510) was 1 mm x 5 1 5 mm ° and the wafer size (semiconductor wafer C1) was 7 mm x 8 mm. The diameter a of the through electrode C3 is 20 μm. The pitch b between the through electrodes C3 was 35 μm. The diameter c of the through electrode C3 is 20 μm. The pitch d between the through electrodes C3 is 70 μm. The diameter e of the pillar 515 is approximately 20 μm. The pitch f between the solder bumps 515a is 70 μm. The pitch g between the external connection electrodes (solder balls) is 800 μm. The height h of the solder bump 515a is 5 μm. The height i of the pillar 515 is 35 μm. The thickness j of the substrate 51 1 is 38 μπα. The height k of the connection wiring portion 514b of the wiring pattern 514 is 38 μm. Here, in the semiconductor device 500, the controller C (semiconductor wafer C1) is formed with an electrode C5 projecting from the bottom surface toward the multilayer wiring substrate 5 1 0 side. The total height 电极 (see Fig. 16) of the height of the electrode C5 of the semiconductor wafer C1 and the height of the pillar 515 of the multilayer wiring substrate 51 is preferably 53 5 μη or more, more preferably 50 μm or more. In this case, either the electrode C5 of the semiconductor wafer C1 or the pillar 515 of the multilayer wiring board 510 may be higher. However, it is preferable to increase the height of the pillar 515 by 35 μm or more by raising the pillar 515. This is based on (i) -29-201248800. If it is desired to ensure the height on the side of the semiconductor wafer c1, it is necessary to manufacture the electrode C5 for each semiconductor wafer C1 (each), which is labor-intensive. The height of the substrate 510 is ensured, and the pillar 515 can be easily manufactured by the method of r〇ll-t〇-r〇U (roller-roller). Further, (ii) in consideration of the yield of the semiconductor wafer C1 and the multilayer wiring substrate 510, the total yield is preferably ensured by ensuring the height on the multilayer wiring substrate 5 10 side. Therefore, it is preferable that the electrode C5 of the semiconductor wafer C1 is composed only of the pad electrode, and it is preferable that the electrode C5 is not formed with a bump or the like. [4_ 3. Method of Manufacturing Multilayer Wiring Substrate] Next, a method of manufacturing the multilayer wiring substrate 510 will be described. As shown in Fig. 18, the through hole A1 is formed at a predetermined position of the substrate 511 by using a laser to remove the slag (swarf) (SI). Thereafter, metal is sputtered on the substrate 5 to form a metal base layer B1 (S2). Thereafter, a metal mainly composed of copper is plated at a predetermined position of the metal base layer B1, a metal layer ML1 is formed on the metal base layer, and a metal layer ML2 is also filled in the through hole A1 (S3). Thereafter, the metal base layer B1 exposed by the metal layer ML1 is etched and removed (S4). As a result, the wiring pattern 514 (the lower wiring portion 5 1 4a, the connection wiring portion 5 1 4b, and the upper wiring portion 5 4c) composed of the metal layer ML 1 and the metal layer M L2 is formed. Thereafter, on the wiring pattern 5 1 4 (upper wiring portion 5 1 4c) on the upper surface side of the substrate 51 1 , an insulating layer 5 1 2 made of a polyimide resin is formed by casting, and the insulating layer 5 is formed. The upper wiring portion 5 1 4c of the wiring pattern 5 1 4 is covered by 1 2 . At the same time, on the lower surface side of the substrate 51 1 , on the wiring pattern -30 - 201248800, an insulating layer 5 1 3 made of a polyimide resin is formed by casting, and the wiring pattern 5 is covered with an insulating layer 5 1 3 . In the casting of the insulating layer of the present embodiment, as described above, in order to prevent the occurrence of voids, the viscosity of the precursor of the polyamidamide resin is low. The varnish is filled between the circuits, and after drying, the varnish having a high viscosity is cast. The casting system is performed a plurality of times to exhibit flatness. Thereafter, the resin-made dry film D1 is adhered to the insulating layer 51 and exposed to light to cure the dry film D1 (S6). Thereafter, the through hole A2 is formed by a predetermined position of the dry film D1 and the insulating layer 512 to the exposed upper wiring portion 514c by using a laser. At the same time, a through hole (opening 5 1 3 a ) is formed at a predetermined position of the insulating layer 513 until the lower wiring portion 5 1 4 a is exposed by using a laser, and the slag (shaving) is removed ( S7). Thereafter, as shown in Fig. 19, a metal base layer B2 is formed by sputtering a metal on the dry film Di and the through hole A2, and a metal base layer B3 is formed by sputtering a metal on the insulating layer 513 and the opening 513a (S8). Thereafter, the resin-made dry film crucible 2 is adhered to the metal base layer B3, and a metal containing copper as a main component is plated on the metal base layer B2, and a metal layer ML3' is formed on the metal base layer B2. Further, the through hole A2 is also filled. Metal layer ML4 (S9). Thereafter, the metal base layer B2 and the metal layer ML3 on the dry film D1 are uranium-etched and removed (S10). As a result, the pillars 5 15 composed of the metal layer ML4 are formed. Then, the solder bumps 5 1 5 a are formed by depositing solder on the pillars 5 1 5 , and the dry film D 3 is laminated on the solder bumps 515 a and the dry film D 1 to expose the film to dry the film D3 (S11). . Thereafter, the dry film D2 formed on the metal substrate f is peeled off (S12). Thereafter, the metal base layer Β3 is removed and removed, and the dry films D1 and D3 on the insulating layer 512 are simultaneously (S13). The multilayer wiring 5 can be manufactured by the above processing of s 1 to S 1 3 [4-4. Effect] (warpage reduction effect of the substrate) The multilayer wiring board 510 and the semiconductor 510 having the above are borrowed from the above. By casting, in the insulating layers 512 and 513, the intensity in the MD direction belonging to the flow direction of 511 and the vertical direction in the TD direction of the substrate 511 can be made the same. Therefore, even if the insulating layers 5 1 2, 5 1 3 are formed by lamination on both sides of the substrate 5, the warpage of the substrate 511 caused by the reduction can be reduced. In particular, all of the insulating layers of the substrate 511 are formed by the same material, whereby the warpage of 51 can be more effectively reduced. In addition, by forming the upper and lower insulating layers 512 and 513 as a pair, the substrate 511 is not warped, and at the same time, low thermal expansion can be achieved, so that even a large-sized substrate does not undergo a structural offset ( Effect of using a polyimide resin) Any one of the insulating layers 5 1 2, 5 1 3 including the substrate 5 1 ] or formed into a polyimide resin, thereby providing good heat resistance and I B3 The etched and peeled substrate device substrate direction 11 is thus bulged. All low dielectric -32- 201248800 multilayer wiring board 5 i 构成 composed of electric coefficient and low linear expansion coefficient. In addition, the use of a polyimide resin 'without an epoxy-based insulating material and a solder resist' can achieve good heat resistance, a low dielectric constant, and a low coefficient of linear expansion, even in the case where the substrate 511 is large. The configuration offset does not occur. The multilayer wiring board 5 10 made of the polyamidene resin as described above has a high rigidity and can be treated in the same manner as the glass epoxy substrate to form a flexible substrate which does not require a carrier. Therefore, it is possible to correspond to a conventional conveying device, and it is also possible to correspond to a reflow method. Further, an inexpensive multilayer wiring substrate 510 can be produced as compared with an epoxy-based insulating material. (Effect of forming an insulating layer by casting on a wiring pattern) When the insulating layer 5 1 2, 5 1 3 is laminated, it is performed by casting (solution casting), whereby no physical force is applied to the film. The pressure of the property does not cause the alignment of the polymer, and the directionality does not occur in terms of strength or optical properties. Further, the insulating layer which is commercially available as a film is a standard product and has a constant thickness. However, as in the present embodiment, the insulating layer 5 1 2, 5 1 3 can be cast to form an arbitrary thickness, and it is also possible to form an arbitrary thickness. For example, a slanted structure is produced. Therefore, it is also possible to prevent the product from being enlarged due to the thickness of the insulating layer which is not required. Further, it is possible to use a material which is arbitrarily set in consideration of the thickness of the signal delay or a CTE (linear expansion coefficient) which is an insulating layer and conforms to the circuit density or purpose, and has a high degree of design freedom. The semiconductor package structure is laminated as described above in the order of LSI wafer / NCP (Non Conductive Paste) / Interposer / Underfill material / -33 - 201248800 motherboard. Among them, in the LSI wafer, the CTE is small (3 to 5 ppm), which is large in the motherboard. Therefore, in the present embodiment, for example, in the semiconductor package, a material having a small CTE is selected on the side of the insulating layer 5 1 2 (on the LSI wafer side) in the multilayer wiring substrate 5 10 , and on the side of the insulating layer 513 (the motherboard) Side) Select a material with a large CTE. Thereby, the load on the connection terminal for one time (connection to the LSI chip) and the second time (connection to the motherboard) can be reduced. As described above, the multilayer wiring substrate 5 10 having an extremely high degree of design freedom can be provided. Further, in the casting, the amount of heat applied to the resin is lower than that of the melt extrusion molding method (the film resin is not required to be melted), and the amount of addition of the thermal stabilizer or the like can be reduced. Further, the curling condition can be adjusted by setting the melting temperature at the time of casting. Further, by the casting as shown above, since the process of filtering the solution can be provided, the fisheye does not occur and is not easily damaged, so that it can be molded for use in the insulating layer 5 1 2, 5 1 3 high transparency film. As described above, by using the casting of the insulating layers 5 1 2, 5 1 3 for casting, there is an advantage that the insulating layers 512 and 513 having high thickness precision, smoothness, transparency, and gloss can be formed. Here, as described above, by using casting, the insulating layers 5 1 2, 5 1 3 can be easily formed by a polyimide film having a high melting point and being formed by extrusion. [5. Fifth embodiment] The fifth embodiment is different from the fourth embodiment-34-201248800 in the configuration of the multilayer wiring board, and the other configuration is the same as that of the fourth embodiment. Differences in implementation. Further, even in the case of the configuration of the multilayer wiring board, the description of the fourth embodiment will be used unless otherwise specified. [5 -1. Configuration of Multilayer Wiring Substrate] As shown in Fig. 20, the multilayer wiring board 520 of the present embodiment is provided with an insulating layer 522 on the upper portion of the substrate 521, and is insulated from the lower portion of the substrate 52 1 . Layer 523. These insulating layers are formed of a polyimide resin and formed by laminating the substrate 52 1 by casting, similarly to the fourth embodiment. Either or both of the insulating layers 522 and 523 laminated as described above may have the same intensity in the MD direction belonging to the substrate flow direction and the TD direction belonging to the substrate vertical direction. A wiring pattern 524 having a three-dimensional structure from the insulating layer 522 to the insulating layer 523 is formed on the substrate 521. The wiring pattern 524 is mainly composed of an uppermost wiring portion 524a, an upper wiring portion 524b, a connecting wiring portion 524c, a lower wiring portion 524d, and a lowermost wiring portion 524e. Here, as in the fourth embodiment, the wiring pattern 524 is divided into the portions for convenience of explanation, but the portions are actually integrally formed. The lower wiring portion 5 24d and the lowermost wiring portion 5 24e are covered by the insulating layer 523. A part of the lowermost wiring portion 524e is exposed by the opening 523a of the insulating layer 523. The exposed portion of the lowermost wiring portion 524e serves as an external connection electrode. In order to form a solder ball or the like on the exposed portion, the semiconductor device 500 is mounted on a circuit board such as a motherboard. -35- 201248800 The connection wiring portion 5 2 4 c is formed so as to penetrate the substrate 511, and is connected to the upper wiring portion 524b and the lower wiring portion 524tJ at the upper and lower ends to connect the wiring portions. The upper wiring portion 524b is covered by the insulating layer 522, and the uppermost wiring portion 524a connected to the upper wiring portion 524b is exposed on the upper portion of the insulating layer 522. The insulating layer 522 is formed in a state in which the uppermost wiring portion 5 2 4 a is protruded. Solder bumps 520 are formed on the uppermost wiring portion 5 24a, and the uppermost wiring portion 524a is a portion that is connected to the semiconductor wafer C 1 of the controller C through the solder bumps 525. The solder bumps 525 are projection electrodes for electrically flip-chip bonding with electronic components such as semiconductor wafers, and are made of, for example, tin-silver-copper alloy. In the same manner as in the fourth embodiment, the substrate 521, the insulating layer 522, the interface between the insulating layer 523 and the wiring pattern 524, or the underlying metal layer are formed. The adhesion of the wiring pattern 524 to the substrate 521 and the like is improved by the underlying metal layer as described above. The underlying metal layer is composed of, for example, a nickel-chromium alloy or copper. The various dimensions of the multilayer wiring board 520 having the above configuration are designed, for example, as follows (see Fig. 20). (a) The diameter of the through hole formed in the insulating layer 522 is designed to be in the range of 15 μm to ΙΟΟμηι. (b) The width of the via land is designed to be larger than 160 μm 〇 (C) The space between the uppermost wiring portions 524a is designed to be larger than -36 - 201248800 1 5 μ m. The width of the (d) line is designed to be greater than 15 μm. (e) The thickness of the uppermost wiring portion 5 24a is designed to be less than 18 μm. (f) The thickness of the solder bump 525 is designed in the range of 2 to 8 μm. (g) The pitch between the opening portions 523a in the lowermost wiring portion 524e is designed to be less than 250 μm. (h) The thickness of the lowermost wiring portion 524e is designed to be less than 18 μm. (i) The thickness of the substrate 521 is designed by any of 12.5, 5, 25, 38, 40, and 50 μm. [5-2. Method of Manufacturing Multilayer Wiring Substrate] Next, a method of manufacturing the multilayer wiring substrate 520 will be described. As shown in FIG. 21, a through hole A1 is formed at a predetermined position of the substrate 521 by laser, and after the slag (swarf) is removed (S 1 )», metal is sputtered on the substrate 521 to form a metal base layer B1. (S2). After that, the resin-made dry film D1 is laminated on the metal base layer B1 on the lower surface side of the substrate 52 1 , and the dry film D 1 is formed by using a mask corresponding to the upper wiring portion 524 b and the connection wiring portion 524 c and the lower wiring portion 524 d. It is formed by exposure/development. Thereby, the metal base layer B1 (S3) is coated with the resin layer (dry film D1) of a predetermined pattern. Thereafter, the predetermined position of the metal base layer B1 exposed by the dry film D1

S -37- 201248800 置鍍敷以銅爲主成分的金屬，在金屬基底層B1形成金屬 層ML1及ML2(S4)。之後，將乾膜D1及位於乾膜D1 的位置的金屬基底層B1進行蝕刻而去除（S5)。結果， 形成由金屬層ML1及金屬層ML2所構成的配線圖案524 的一部分（上部配線部5 2 4b、連結配線部5 24c及下部配 線部524d )。 之後，在基板521的上面側與下面側之雙方，將聚亞 醯胺樹脂形成爲絕緣層5 22及523來進行澆鑄。此外，使 用雷射而在絕緣層522及523的預定位置，至露出配線圖 案5 24爲止形成貫穿孔 A2而將其膠渣（削屑）去除 (S6)。之後，在絕緣層5 22及52 3濺鏟金屬而形成金屬 基底層B2 ( S7 )。 之後，在絕緣層522及523上黏貼樹脂製乾膜D2， 進行曝光而使乾膜D2硬化（S8 )。之後，如第22圖所 示，在絕緣層522及523的預定位置鍍敷以銅爲主成分的 金屬，在絕緣層522及523形成金屬層ML3及ML4 (S9 )。之後，將乾膜D2、及位於乾膜D2的位置的金屬 基底層B2進行蝕刻而去除（S10)。藉此，由金屬層 ML3形成最上部配線部524a，由金屬層ML4形成最下部 配線部524e » 之後，在基板521的上面及下面側、及配線部層疊樹 脂製乾膜D3，將與焊料凸塊525相對應的圖案，使用遮 罩進行曝光而使乾膜D3硬化。之後，在設於絕緣層522 上的配線圖案524的最上部配線部524a上形成由錫-銀-S -37- 201248800 A metal mainly composed of copper is plated, and metal layers ML1 and ML2 (S4) are formed on the metal base layer B1. Thereafter, the dry film D1 and the metal base layer B1 located at the position of the dry film D1 are etched and removed (S5). As a result, a part of the wiring pattern 524 composed of the metal layer ML1 and the metal layer ML2 (the upper wiring portion 5 2 4b, the connection wiring portion 524c, and the lower wiring portion 524d) is formed. Thereafter, on the upper surface side and the lower surface side of the substrate 521, a polyimide resin is formed into the insulating layers 5 22 and 523 to be cast. Further, the through hole A2 is formed at a predetermined position of the insulating layers 522 and 523 to the exposed wiring pattern 524 by using a laser to remove the slag (swarf) (S6). Thereafter, metal is sputtered on the insulating layers 5 22 and 52 3 to form a metal base layer B2 (S7). Thereafter, the resin-made dry film D2 is adhered to the insulating layers 522 and 523, and exposure is performed to cure the dry film D2 (S8). Thereafter, as shown in Fig. 22, a metal mainly composed of copper is plated at predetermined positions of the insulating layers 522 and 523, and metal layers ML3 and ML4 are formed in the insulating layers 522 and 523 (S9). Thereafter, the dry film D2 and the metal base layer B2 located at the position of the dry film D2 are etched and removed (S10). Thereby, the uppermost wiring portion 524a is formed by the metal layer ML3, and the lowermost wiring portion 524e is formed by the metal layer ML4. Then, the resin dry film D3 is laminated on the upper surface and the lower surface side of the substrate 521 and the wiring portion, and the solder bump is formed. The pattern corresponding to the block 525 is exposed using a mask to harden the dry film D3. Thereafter, tin-silver is formed on the uppermost wiring portion 524a of the wiring pattern 524 provided on the insulating layer 522.

C -38- 201248800 銅合金所構成的焊料凸塊525 (sn)。焊料凸塊52 5係 用以與半導體晶片等電子元件作電性覆晶連接的突起電 極。之後，將形成在基板521的乾膜D3剝離（S1 2 )。 之後，在基板下面側澆鑄聚亞醯胺樹脂（絕緣層523 的殘存部分的形成）。另外在絕緣層523的預定位置’使 用雷射至露出最下部配線層524e爲止形成貫穿孔5 23 a ’ 將其膠渣（削肩）去除（S1 3 )。 可經由以上S1〜S13的處理來製造多層配線基板 520 ° 〔5 - 3 .效果〕 藉由如以上所示之本實施形態中的多層配線基板 520，當對基板521積層絕緣層5 22及523時，在配線圖 案5 24上藉由澆鑄形成絕緣層。藉此，由於絕緣層的厚度 等、設計自由度高，因此可輕易地進行多層基板的製作。 因此，Via on Via或塡孔的設計自由度 '高密度構裝、層 間可靠性、層厚安定高，亦可得因平坦性所致之阻抗整 合。此外，在本實施形態之多層配線基板中，係藉由使用 塡孔，可使連接強度更爲良好。 〔6.第6實施形態〕 第6實施形態係在多層配線基板之構成中與第4及第 5實施形態不同，但是關於其他構成，由於與第4及第5 實施形態相同，因此在以下僅針對與第4及第5實施形態 -39- 201248800 不同之處加以說明。此外，關於多層配線基板之構成’針 對未特別提及之處，亦沿用第4及第5實施形態中的說 明。 〔6 -1 .多層配線基板之構成〕 如第2 3圖所示，本實施形態之多層配線基板5 3 0係 在作爲基底的樹脂製基板531的下部形成絕緣層5 32，在 該絕緣層5 3 2的下部另外形成有絕緣層533。該等絕緣層 係藉由聚亞醯胺樹脂所形成，對基板531，使用澆鑄進行 積層而形成。 與在第4實施形態中之說明同樣地，藉由如上所示積 層絕緣層532、513之任一者或二者，可在屬於基板流動 方向的MD( Machine Direction)方向、及屬於基板垂直 方向的 TD方向（Transverse Direction )，使強度爲相 同。 在基板531上形成有由絕緣層532至絕緣層533具有 3次元構造的配線圖案534。配線圖案534主要由上部配 線部53 4a、連結配線部5 34b、及下部配線部5 3 4c所構 成。在此，與第4及第5實施形態同樣地，爲方便說明起 見’將配線圖案534劃分爲該等部位，但是該等部位實際 上係一體形成。 上部配線部534a係形成在絕緣層532中。在上部配 線部534a形成有支柱535。支柱535係在貫穿基板531 的狀態下立設在配線圖案5 3 4上。支柱5 3 5的前端部（頂C -38- 201248800 Solder bump 525 (sn) made of copper alloy. The solder bumps 52 5 are bump electrodes for electrically flip-chip bonding with electronic components such as semiconductor wafers. Thereafter, the dry film D3 formed on the substrate 521 is peeled off (S1 2 ). Thereafter, a polyimide resin (formation of a remaining portion of the insulating layer 523) is cast on the lower surface side of the substrate. Further, a through hole 5 23 a ' is formed at a predetermined position of the insulating layer 523 to expose the lowermost wiring layer 524e, and the slag (sharp) is removed (S1 3 ). The multilayer wiring board 520 ° [5 - 3 . effect] can be produced by the above-described processes of S1 to S13. By the multilayer wiring substrate 520 of the present embodiment as described above, the insulating layer 5 22 and 523 are laminated on the substrate 521. At this time, an insulating layer is formed by casting on the wiring pattern 5 24. Thereby, the thickness of the insulating layer is high, and the degree of freedom in design is high, so that the multilayer substrate can be easily fabricated. Therefore, the design freedom of Via on Via or the pupil is 'high-density construction, interlayer reliability, high layer thickness stability, and impedance integration due to flatness. Further, in the multilayer wiring board of the present embodiment, the connection strength can be further improved by using the pupil. [6th embodiment] The sixth embodiment differs from the fourth and fifth embodiments in the configuration of the multilayer wiring board. However, the other configurations are the same as those of the fourth and fifth embodiments, and therefore only the following. The differences from the fourth and fifth embodiments -39 to 201248800 will be described. Further, the description of the fourth and fifth embodiments is also used in the case where the configuration of the multilayer wiring board is not particularly mentioned. [6-1. Configuration of Multilayer Wiring Substrate] As shown in Fig. 2, the multilayer wiring board 530 of the present embodiment is formed with an insulating layer 532 on the lower portion of the resin substrate 531 as a base. An insulating layer 533 is additionally formed on the lower portion of the 5 3 2 . These insulating layers are formed of a polyimide resin, and the substrate 531 is formed by lamination using casting. As described in the fourth embodiment, either or both of the laminated insulating layers 532 and 513 as described above can be in the MD (Machine Direction) direction belonging to the substrate flow direction and belonging to the substrate vertical direction. The TD direction (Transverse Direction) makes the intensity the same. A wiring pattern 534 having a three-dimensional structure from the insulating layer 532 to the insulating layer 533 is formed on the substrate 531. The wiring pattern 534 is mainly composed of an upper wiring portion 534a, a connecting wiring portion 534b, and a lower wiring portion 553c. Here, in the same manner as in the fourth and fifth embodiments, the wiring pattern 534 is divided into the portions for convenience of explanation, but the portions are actually integrally formed. The upper wiring portion 534a is formed in the insulating layer 532. A pillar 535 is formed in the upper wiring portion 534a. The pillar 535 is erected on the wiring pattern 543 in a state of penetrating the substrate 531. The front end of the pillar 5 3 5 (top

.C -40- 201248800 部53 5b )係由基板53 1稍微露出。基板 的前端部（頂部535b)突出的狀態下被I 面，作爲保護支柱.5 35的保護層來發揮功 連結配線部534b係以貫穿基板531 方式所形成。連結配線部534b係連接於. 與下部配線部5 34c而將該等配線部相連糸Ϊ 下部配線部5 34c係被絕緣層533 53 3係被圖案化成預定圖案，下部配線部 由絕緣層533的開口部533a露出。下部@ 出部作爲外部連接電極而發揮功能，在該 等，半導體裝置500被構裝在主機板等電 在支柱53 5上形成有焊料凸塊53 5a 係用以與半導體晶片等電子元件作電性覆 極，由例如錫-銀-銅合金所構成。 其中，與第4實施形態同樣地，在基 532及絕緣層533與配線圖案534的界面 支柱535的界面形成有基底金屬層。藉由 金屬層，配線圖案5 34或支柱5 3 5對基板 被提高。該基底金屬層係由例如鎳鉻合金 具有以上構成的多層配線基板53 0的 設計成如下所示（參照第23圖及第24圖 封裝體尺寸（多層配線基板530)爲 支柱535的直徑e大約爲20μπι。 焊料凸塊535a間的間距f爲70μιη。 5 3 1係在使支柱 g支柱5 3 5的側 能。 及絕緣層5 3 2的 上部配線部534a 所被覆。絕緣層 534c的一部分 β線部534c的露 露出部形成焊球 路基板。 。焊料凸塊5 3 5 a 晶連接的突起電 板5 3 1、絕緣層 、或基板531與 如上所示之基底 5 3 1等的接著性 或銅等所構成。 各種尺寸係例如 )° 1 1 mmx5 1 5mm。 -41 - 201248800 外部連接電極（焊球）間的間距g爲800μηι 焊料凸塊535a的高度h爲5μηι。 支柱5 3 5的高度i爲35μηι。 基板531的厚度j爲25μηι。 配線圖案5 3 4的連結配線部5 3 4b的高度k i 在此，在半導體裝置500中，在控制器C( 片C 1 )形成有由底面朝向多層配線基板5 3 0側 極C5。該半導體晶片C1的電極C5的高度與多 板530的支柱535的高度的合計Η (參照第16 爲35μηι以上，更佳爲50μπι以上。 〔6-2.多層配線基板之製造方法〕 接著，說明多層配線基板530之製造方法。 多層配線基板530係藉由以被捲繞在預定滾 基板531被捲繞在其他滾筒的方式予以搬送且在 程中形成配線圖案534等的roll-to-roll方式 造。 具體而言，首先，如第24圖所示，在基板 樹脂製乾膜D1，進行曝光而使乾膜D1硬化（ 後，使用雷射，在基板531及乾膜D1的預定位 穿孔A1，且將其膠渣（削屑）去除（S2)。 之後，在基板53 1及乾膜D1濺鍍金屬而形 底層B1(S3)。之後，在基板531的下面側的 層B 1層疊樹脂製乾膜D2。接著，以與上部配,1 '·, 3 8 μ m ° 半導體晶 突出的電 層配線基 圖）較佳 筒的長形 其搬送過 來進行製 531層疊 S1 )。之 置形成貫 成金屬基 金屬基底 良部534a_ -42- 201248800 相對應的圖案將乾膜D2進行曝光/顯影，以預定圖案的 樹脂層（乾膜D2)被覆金屬基底層B1(S4)。 之後，在乾膜D1上的金屬基底層B1與由乾膜D2露 出的金屬基底層BI鍍敷以銅爲主成分的金屬，在金屬基 底層B1上形成金屬層ML1，並且在貫穿孔A1亦塡充金 屬層ML2 ( S5 )。之後，在基板531的下面側的金屬層 ML1及乾膜D2上黏貼樹脂製乾膜D3，將乾膜D1的上面 側的金屬基底層B1及金屬層 ML1進行蝕刻而去除 (S6 )。結果，形成由金屬層ML1所構成的支柱5 3 5。 其中，在S2的處理中，係調整雷射的輸出而由上方 至下方慢慢降低，將貫穿孔A1形成爲尖端細形狀（倒錐 狀）。結果，可形成尖端細形狀的支柱53 5 (參照第23 圖擴大部）。 之後，在支柱53 5鍍敷焊料而形成焊料凸塊5 3 5 a (S7 )，將形成在基板 531的乾膜 Dl、D2、D3剝離 (S8 ) 〇 之後，如第2 5圖所示，在基板5 3 1黏貼樹脂製乾膜 D4，並且將在基板5 31的下面以乾膜D2所被覆的部分的 金屬基底層B 1進行蝕刻而去除（S 9 )。結果’形成由金 屬層ML2所構成的配線圖案5 3 4的上部配線部5 3 4a。之 後，在基板53 1的下面側藉由澆鑄來積層絕緣層5 3 2 ’以 絕緣層 53 2被覆配線圖案 5 34的上部配線部 5 34a (S10 ) » 之後，將乾膜D4剝離（S 1 1 )。接著，使用雷射而 -43- 201248800 在絕緣層53 2的預定位置至露出上部配線部534a爲止形 成貫穿孔A2，且將其膠渣（削屑）去除（S12)。 之後，在絕緣層532、貫穿孔A2及上部配線部534a 濺鍍金屬而形成金屬基底層B2(S13)。之後，在基板 531層疊樹脂製乾膜D5。與此同時，在金屬基底層B2亦 層疊樹脂製乾膜D6。接著，使用與下部配線部5 34c及連 結配線部5 34b相對應的圖案的遮罩，將乾膜D6進行曝 光/顯影，且以預定圖案的樹脂層（乾膜D6)被覆金屬 基底層B2 ( S14 )。 之後，如第26圖所示，在由乾膜D6露出的金屬基 底層B2鍍敷以銅爲主成分的金屬，在金屬基底層B2、貫 穿孔A2及上部配線部5 34a形成金屬層ML2 ( S15 )。之 後，將乾膜D6剝離（S16)。之後，將以乾膜D6所被覆 的金屬基底層B2進行蝕刻而去除。結果，形成由金屬層 ML2所構成的配線圖案534的下部配線部534c及連結配 線部534b。 之後，將乾膜D5剝離，在絕緣層53 2、下部配線部 534c及連結配線部534b，未使用抗焊劑而藉由聚亞醯胺 樹脂，使用澆鑄來形成絕緣層53 3，使用雷射，在絕緣層 53 3形成開口部5 3 3 a，藉此，下部配線部534c的一部分 由開口部53 3 a露出（形成外部連接電極）（S17)。 可經由以上 S1〜S17的處理來製造多層配線基板 53 0。 -44 - 201248800 〔6_3 ·效果〕 藉由如以上所示之本實施形態之多層配線基板5 3 0， 與第4實施形態同樣地，藉由在基板5 3 1上積層絕緣層 532、533，可在屬於基板531之流動方向的MD方向、及 屬於基板5 3 1之垂直方向的TD方向，使強度形成爲相 同。藉此，可減低基板531的翹曲。尤其，藉由相同的材 料來構成包含基板531的絕緣層的全部，藉此可更加有效 地減低基板5 3 1的翹曲。 將包含基板531的絕緣層53 2、5 3 3的任一者或全部 形成爲聚亞醯胺樹脂，藉此可提供由良好的耐熱性、及低 介電係數、低線膨脹係數所構成的基板5 3 1。此外，使用 聚亞醯胺樹脂，而不使用環氧系絕緣材料及抗焊劑，藉此 可實現良好的耐熱性、低介電係數及低線膨脹率，即使基 板531爲較大的尺寸，亦不會有構裝偏移的情形。 此外，在積層絕緣層532、53 3時，藉由澆鑄來進 行，由於不會對薄膜施加物理性的壓力，因此不會發生高 分子的配向，在強度或光學特性等不會產生方向性。 〔7 ·本發明之實施形態的結論〕 本發明之第1態樣係提供一種配線基板，其特徵爲具 有：作爲基底的樹脂製基板；形成在前述基板上的配線圖 案；及被覆前述配線圖案之一部分的絕緣層，在前述配線 圖案上的預定位置立設有由以銅爲主成分的金屬所構成且 與半導體晶片相連接的支柱，前述支柱係在貫穿前述基板 -45- 201248800 的狀態下立設於前述配線圖案上。 藉由本發明之第2態樣，提供一種配線基板’其特徵 爲具有：作爲基底的樹脂製基板；形成在前述基板上的配 線圖案；及被覆前述配線圖案之一部分的絕緣層’在前述 配線圖案上的預定位置立設有由以銅爲主成分的金屬所構 成且與半導體晶片相連接的支柱，前述支柱係在貫穿前述 絕緣層的狀態下立設於前述配線圖案上。 藉由本發明之第3態樣，提供一種配線基板之製造方 法，其特徵爲具有：在樹脂製基板的預定位置形成第1貫 穿孔的工程；在前述基板形成第1金屬基底層的工程；以 預定圖案的第1樹脂層被覆前述基板的一面側的前述第1 金屬基底層的工程；在由前述第1樹脂層露出的前述第1 金屬基底層形成以銅爲主成分的第1金屬層，並且在前述 第1貫穿孔塡充以銅爲主成分的第2金屬層的工程；去除 前述基板之形成有前述第1樹脂層的面的相反面所形成的 前述第1金屬基底層及前述第1金屬層，形成由前述第2 金屬層所構成的支柱的工程；去除前述第1樹脂層的工 程：去除以前述第〗樹脂層所被覆的部分的前述第1金屬 基底層，形成由前述第1金屬層所構成的配線圖案的一部 分的工程；形成被覆前述配線圖案之一部分的第1絕緣層 的工程；在前述第1絕緣層的預定位置，至露出前述配線 圖案的一部分爲止形成第2貫穿孔的工程；在前述第1絕 緣層形成第2金屬基底層的工程；以預定圖案的第2樹脂 層被覆前述第2金屣蕋底層的工程；在由前述第2樹脂層.C - 40 - 201248800 Part 53 5b ) is slightly exposed by the substrate 53 1 . When the front end portion (the top portion 535b) of the substrate protrudes, the surface is formed on the I surface, and the protective layer of the protective pillar .5 35 functions as the through-substrate 534b. The connection wiring portion 534b is connected to the lower wiring portion 534b and is connected to the wiring portion. The lower wiring portion 534c is patterned into a predetermined pattern by the insulating layer 53353 3, and the lower wiring portion is made of the insulating layer 533. The opening 533a is exposed. The lower portion of the lower portion functions as an external connection electrode. In this case, the semiconductor device 500 is mounted on the main board, and the solder bumps 53 5a are formed on the pillars 53 5 to electrically connect the electronic components such as the semiconductor wafer. The polarity is covered by, for example, a tin-silver-copper alloy. In the same manner as in the fourth embodiment, the base metal layer is formed at the interface between the base 532 and the insulating layer 533 and the interface post 535 of the wiring pattern 534. The substrate is improved by the metal layer, the wiring pattern 534 or the pillars 535. The base metal layer is designed by, for example, a nickel-chromium alloy having the above-described multilayer wiring substrate 530 as follows (see the package size (multilayer wiring substrate 530) of FIGS. 23 and 24 as the diameter e of the pillar 535. The pitch f between the solder bumps 535a is 70 μm. The 5 3 1 is coated on the side of the pillar g 535 and the upper wiring portion 534a of the insulating layer 533. A part of the insulating layer 534c is β. The exposed portion of the line portion 534c forms a solder ball substrate. The bumps of the solder bumps 5 3 5 a are electrically connected, the insulating layer, or the substrate 531 is bonded to the substrate 531 as shown above. Or copper or the like. Various sizes are, for example, 1 1 mm x 5 1 5 mm. -41 - 201248800 The pitch g between the external connection electrodes (solder balls) is 800 μm. The height h of the solder bumps 535a is 5 μm. The height i of the pillar 5 3 5 is 35 μm. The thickness j of the substrate 531 is 25 μm. The height k i of the connection wiring portion 5 3 4b of the wiring pattern 5 3 4 Here, in the semiconductor device 500, the controller C (plate C 1 ) is formed with the bottom surface toward the multilayer wiring substrate 5 3 0 side electrode C5. The total height of the electrode C5 of the semiconductor wafer C1 and the height of the pillars 535 of the multi-plate 530 (refer to 16 is 35 μm or more, more preferably 50 μm or more. [6-2. Method of Manufacturing Multilayer Wiring Substrate] Next, a description will be given A method of manufacturing the multilayer wiring board 530. The multilayer wiring board 530 is a roll-to-roll method in which a wiring pattern 534 is formed by being wound around a predetermined roller substrate 531 and wound around another cylinder. Specifically, first, as shown in Fig. 24, the dry film D1 of the substrate resin is exposed, and the dry film D1 is cured (after the laser is used, the hole A1 is pre-positioned on the substrate 531 and the dry film D1). Then, the slag (swarf) is removed (S2). Thereafter, the substrate 53 1 and the dry film D1 are sputtered with a metal to form the underlayer B1 (S3). Thereafter, the resin is laminated on the layer B 1 on the lower surface side of the substrate 531. The dry film D2 is formed, and then an electric layer wiring pattern which is protruded from the upper portion and has a semiconductor crystal protrusion of 1 '·, 3 8 μ m °) is preferably formed by elongating the length of the tube and performing 531 lamination S1). The formation of the through-metal-based metal substrate 534a_-42-201248800 corresponding pattern exposes/develops the dry film D2, and coats the metal base layer B1 with a predetermined pattern of the resin layer (dry film D2) (S4). Thereafter, the metal base layer B1 on the dry film D1 and the metal base layer BI exposed by the dry film D2 are plated with a metal mainly composed of copper, a metal layer ML1 is formed on the metal base layer B1, and the through hole A1 is also formed. Fill the metal layer ML2 (S5). After that, the resin-made dry film D3 is adhered to the metal layer ML1 and the dry film D2 on the lower surface side of the substrate 531, and the metal base layer B1 and the metal layer ML1 on the upper surface side of the dry film D1 are etched and removed (S6). As a result, the pillars 535 composed of the metal layer ML1 are formed. In the process of S2, the output of the laser is adjusted to gradually decrease from the upper side to the lower side, and the through hole A1 is formed into a tapered shape (inverted tapered shape). As a result, the pillar 53 5 having a thin tip shape can be formed (refer to the enlarged portion of Fig. 23). Thereafter, solder is plated on the pillars 53 5 to form solder bumps 5 3 5 a (S7 ), and after the dry films D1, D2, and D3 formed on the substrate 531 are peeled off (S8), as shown in FIG. The resin-made dry film D4 is adhered to the substrate 531, and the metal base layer B1 of the portion covered with the dry film D2 under the substrate 531 is etched and removed (S9). As a result, the upper wiring portion 5 3 4a of the wiring pattern 533 composed of the metal layer ML2 is formed. Thereafter, the insulating layer 5 3 2 ' is deposited on the lower surface side of the substrate 53 1 by the insulating layer 53 2 to cover the upper wiring portion 5 34a (S10) » of the wiring pattern 534, and then the dry film D4 is peeled off (S 1 1 ). Next, the through hole A2 is formed at a predetermined position of the insulating layer 53 2 to expose the upper wiring portion 534a by using a laser, and the slag (shaving) is removed (S12). Thereafter, metal is sputtered on the insulating layer 532, the through hole A2, and the upper wiring portion 534a to form the metal base layer B2 (S13). Thereafter, a resin-made dry film D5 is laminated on the substrate 531. At the same time, a resin-made dry film D6 is laminated on the metal base layer B2. Next, the dry film D6 is exposed/developed using a mask corresponding to the pattern of the lower wiring portion 534c and the connection wiring portion 534b, and the metal base layer B2 is coated with the resin layer (dry film D6) of a predetermined pattern ( S14). Then, as shown in Fig. 26, a metal containing copper as a main component is plated on the metal base layer B2 exposed by the dry film D6, and a metal layer ML2 is formed in the metal base layer B2, the through hole A2, and the upper wiring portion 534a ( S15). Thereafter, the dry film D6 is peeled off (S16). Thereafter, the metal base layer B2 covered with the dry film D6 is removed by etching. As a result, the lower wiring portion 534c and the connection wiring portion 534b of the wiring pattern 534 composed of the metal layer ML2 are formed. After that, the dry film D5 is peeled off, and the insulating layer 53 2, the lower wiring portion 534c, and the connection wiring portion 534b are formed of a polyimide layer by using a polyamine resin without using a solder resist, and a laser is used. The opening portion 53 3 a is formed in the insulating layer 53 3 , whereby a part of the lower wiring portion 534c is exposed by the opening portion 53 3 a (the external connection electrode is formed) (S17). The multilayer wiring substrate 530 can be manufactured through the processes of S1 to S17 described above. -44 - 201248800 [6_3 Effect] The multilayer wiring board 530 of the present embodiment as described above is formed by laminating insulating layers 532 and 533 on the substrate 531 as in the fourth embodiment. The intensity can be made the same in the MD direction belonging to the flow direction of the substrate 531 and the TD direction belonging to the vertical direction of the substrate 531. Thereby, the warpage of the substrate 531 can be reduced. In particular, all of the insulating layers including the substrate 531 are formed by the same material, whereby the warpage of the substrate 531 can be more effectively reduced. Any one or all of the insulating layers 53 2, 5 3 3 including the substrate 531 are formed into a polyimide resin, thereby providing a heat resistance, a low dielectric constant, and a low coefficient of linear expansion. Substrate 5 3 1. Further, a polyimide resin is used instead of an epoxy-based insulating material and a solder resist, whereby good heat resistance, low dielectric constant, and low linear expansion ratio can be achieved, even if the substrate 531 has a large size. There will be no configuration offsets. Further, when the insulating layers 532 and 53 are laminated, by casting, since no physical pressure is applied to the film, high molecular alignment does not occur, and directionality is not generated in terms of strength and optical characteristics. [7] The first aspect of the present invention provides a wiring board comprising: a resin substrate as a base; a wiring pattern formed on the substrate; and a wiring pattern covering the substrate a part of the insulating layer is provided with a pillar made of a metal mainly composed of copper and connected to the semiconductor wafer at a predetermined position on the wiring pattern, and the pillar is inserted through the substrate -45-201248800 It is erected on the aforementioned wiring pattern. According to a second aspect of the present invention, a wiring board having a resin substrate as a base, a wiring pattern formed on the substrate, and an insulating layer covering a portion of the wiring pattern in the wiring pattern are provided. A pillar formed of a metal mainly composed of copper and connected to the semiconductor wafer is erected at a predetermined position, and the pillar is erected on the wiring pattern in a state of penetrating the insulating layer. According to a third aspect of the present invention, a method of manufacturing a wiring board, comprising: forming a first through hole at a predetermined position of a resin substrate; and forming a first metal base layer on the substrate; a first resin layer of a predetermined pattern covers a first metal base layer on one surface side of the substrate, and a first metal layer containing copper as a main component is formed on the first metal base layer exposed by the first resin layer. And the first through hole is filled with a second metal layer containing copper as a main component; and the first metal base layer and the first surface formed by the opposite surface of the surface of the substrate on which the first resin layer is formed are removed a metal layer forming a pillar formed of the second metal layer; and a step of removing the first resin layer: removing the first metal base layer in a portion covered by the first resin layer, and forming the first metal base layer a part of a wiring pattern formed of a metal layer; a process of forming a first insulating layer covering a portion of the wiring pattern; at a predetermined position of the first insulating layer, a process of forming a second through hole in a part of the wiring pattern; a process of forming a second metal base layer in the first insulating layer; and a process of covering the second metal base layer in a second resin layer having a predetermined pattern; From the aforementioned second resin layer

C 46- 201248800 露出的前述第2金屬基底層形成以銅爲主成分的第3金 層的工程；去除前述第2樹脂層的工程；去除以前述第 樹脂層所被覆的部分的前述第2金屬基底層’形成由前 第3金屬層所構成的配線圖案的剩餘部分的工程；及以 2絕緣層被覆前述配線圖案的剩餘部分的工程。 藉由本發明之第4態樣，提供一種配線基板之製造 法，其特徵爲具有：在樹脂製基板的預定位置形成第1 穿孔的工程；在前述基板形成第1金屬基底層的工程； 前述第1金屬基底層形成以銅爲主成分的預定圖案的第 金屬層的工程；去除由前述第1金屬層露出的前述第1 屬基底層，形成由前述第1金屬層所構成的配線圖案的 程；在前述基板的兩面分別形成絕緣層，以第1絕緣層 第2絕緣層被覆前述配線圖案的工程；在前述第1絕緣 的預定位置，至露出前述配線圖案爲止形成第2貫穿孔 工程；在前述第1絕緣層與前述第2貫穿孔形成第2金 基底層的工程；在前述第2金屬基底層形成以銅爲主成 的第2金屬層，並且在前述第2貫穿孔塡充以銅爲主成 的第3金屬層的工程；及去除前述第1絕緣層上的前述 2金屬基底層及第2金屬層，形成由前述第3金屬層所 成的支柱的工程。 藉由本發明之第5態樣，提供一種半導體裝置，其 將具有貫穿電極的複數枚半導體晶片層積在上述第1態 或上述第2態樣之配線基板上的半導體裝置，其特徵爲 在前述半導體晶片形成與前述配線基板相連接的電極， 屬 2 述 第 方 貫 在 1 金 工 與 層 的 屬 分 分 第 構 係 樣 刖 -47- 201248800 述配線基板的支柱的高度與前述半導體晶片的電極 的合計爲35μηι以上。 藉由本發明之第6態樣，提供一種半導體裝置 將複數枚半導體晶片，按每1枚構裝在上述第1態 述第2態樣之配線基板的半導體裝置，其特徵爲： 半導體晶片形成與前述配線基板相連接的電極’前 基板的支柱的高度與前述半導體晶片的電極的高度 爲3 5 μ m以上。 藉由本發明之第7態樣，提供一種多層配線蕋 特徵爲具有：作爲基底的樹脂製基板；形成在前述 的配線圖案；及一面被覆前述配線圖案，一面對稱 在前述基板的兩面所形成的絕緣層，前述絕緣層係 方向及TD方向，強度爲相同。 本發明之第8態樣係上述第7態樣的多層配線 製造方法，其特徵爲具有：在樹脂製基板的預定位 第1貫穿孔的工程：在前述基板的上面及下面形成 屬基底層的工程；在前述第1金屬基底層的預定位 以銅爲主成分的第1金屬層，並且在前述第1貫穿 以銅爲主成分的第2金屬層的工程；去除由前述第 層露出的前述第〗金屬基底層，形成由前述第1及 屬層所構成的配線圖案的一部分的工程；在前述基 面側及下面側，且爲前述一部分配線圖案上，藉由 成由聚亞醯胺樹脂所構成的絕緣層，被覆前述第1 的工程；在前述絕緣層的預定位置，至露出前述配 的高度 ，其係 樣或上 在前述 述配線 的合計 板，其 基板上 地積層 在 MD 基板之 置形成 第1金 置形成 孔塡充 1金屬 第2金 板的上 澆鑄形 金屬層 線圖案 -48- 201248800 的一部分爲止形成第2貫穿孔的工程；在前述第2貫穿孔 形成第2金屬基底層，並且在前述絕緣層形成第3金屬基 底層的工程；在形成有前述第2金屬基底層的前述第2貫 穿孔，塡充以銅爲主成分的第3金屬層，並且在前述第3 金屬基底層形成第4金屬層的工程；去除由前述第4金屬 層露出的前述第3金屬基底層的工程；及形成由前述第2 及第3金屬層所構成的配線圖案的剩餘部分的工程。 在以上態樣中，在絕緣層中，將屬於基板流動方向的 MD( Machine Direction)方向、及屬於基板垂直方向的 TD方向（Transverse Direction)設定爲相同強度。藉 此，即使在基板積層絕緣層，亦可提供翹曲少且具平坦性 的多層配線基板。此外，藉由在基板的上面與下面形成爲 上下對稱構造，不會有基板翹曲的情形，同時可實現低熱 膨脹，即使爲大尺寸的基板，亦不會發生構裝偏移。 本發明之第9態樣係在上述第7態樣中，前述絕緣層 係藉由澆鑄所形成爲其特徵。 在以上態樣中，係當積層絕緣層時，藉由澆鑄（溶液 澆鑄法（solution casting))來進行，藉此不會對薄膜施 加物理性的壓力，因此不會發生高分子的配向，在強度或 光學特性等不會產生方向性。此外，作爲薄膜而在市面上 販售的絕緣層爲規格品，厚度一定，但是如上述態樣所 示，可藉由將絕緣層進行澆鑄，來形成任意厚度，而且亦 可製作例如傾斜構造。因此，亦可防止因不需要的絕緣層 厚度所造成的製品肥大化。此外，可使用任意設定考慮到 -49- 201248800 訊號延遲的厚度、或作爲絕緣層而符合電路密度或目的的 CTE (線膨脹係數）的材料，設計自由度高。 本發明之第1 〇態樣係在上述第7或第8態樣中’前 述基板及前述絕緣層的任一者係藉由聚亞醯胺樹脂所構成 爲其特徵。 以聚亞醯胺樹脂形成包含基板的絕緣層的任一者或全 部’藉此可提供由良好的耐熱性、及低介電係數、低線膨 脹係數所構成的多層配線基板。此外，使用聚亞醯胺樹 脂，而不使用環氧系絕緣材料及抗焊劑，藉此可實現良好 的耐熱性、低介電係數及低線膨脹率，即使爲較大的基 板，亦不會有構裝偏移的情形。如上所示之藉由聚亞醯胺 樹脂所製作的多層配線基板係剛性高，且可進行與習知的 玻璃環氧基板相同的處理，成爲不需要載體的可撓性基 板。因此，以習知的搬送設備即可對應，亦可對應迴焊方 式。此外，與環氧系絕緣材料相比較，可製作廉價的多層 配線基板。 本發明之第11態樣係在上述第7或第8態樣中，係 具備有多層配線基板的半導體裝置，其特徵爲：由半導體 晶片層積體、上述第7或第8態樣所記載之多層配線基 板、前述多層配線基板、及半導體晶片層積體所構成。 【圖式簡單說明】 第1圖係顯示第1圖之半導體裝置之槪略性全體構成 的平面圖 -50- 201248800 第2圖係顯示第1實施形態之半導體裝置之槪略構成 的剖面圖。 第3圖係顯示第1實施形態之中介層之槪略構成的剖 面圖。 第4圖係槪略顯示第3圖之中介層之製造方法的圖 不 ° 第5圖係槪略顯示第3圖之中介層之製造方法的圖 示，槪略顯示第4圖之後續工程的圖示。 第6圖係槪略顯示第3圖之中介層之製造方法的圖 示，槪略顯示第5圖之後續工程的圖示。 第7圖係顯示第2實施形態之中介層之槪略構成的剖 面圖。 第8圖係槪略顯示第7圖之中介層之製造方法的圖 不 。 第9圖係槪略顯示第7圖之中介層之製造方法的圖 示，槪略顯示第8圖之後續工程的圖示。 第10圖係顯示第7圖之中介層之變形例的剖面圖。 第1 1圖係顯示第7圖之中介層之變形例的剖面圖。 第12圖係顯示第3實施形態之半導體裝置之槪略構 成的剖面圖。 第13圖係顯示第3實施形態之中介層之槪略構成的 剖面圖。 第14圖係槪略顯示第13圖之中介層之製造方法的圖 示。 -51 - 201248800 第15圖係槪略顯示第丨3圖之中介層之製造方法的圖 示，槪略顯示第14圖之後續工程的圖示。 第16圖係顯示第4實施形態之半導體裝置之構成的 剖面圖。 第1 7圖係顯示第4實施形態之多層配線基板之構成 的剖面圖。 第18圖係顯示第4實施形態之多層配線基板之製造 方法的圖示。 第19圖係顯示第4實施形態之多層配線基板之製造 方法的圖示，顯示第1 8圖之後續工程的圖示。 第20圖係顯示第5實施形態之多層配線基板之構成 的剖面圖。 第2 1圖係顯示第5實施形態之多層配線基板之製造 方法的圖示。 第22圖係顯示第5實施形態之多層配線基板之製造 方法的圖示，顯示第21圖之後續工程的圖示。 第23圖係顯示第6實施形態之多層配線基板之構成 的剖面圖。 第24圖係顯示第6實施形態之多層配線基板之製造 方法的剖面圖。 第25圖係顯示第6實施形態之多層配線基板之製造 方法的圖示，顯示第24圖之後續工程的圖示。 第26圖係顯示第6實施形態之多層配線基板之製造 方法的圖示，顯示第2 5圖之後續工程的圖示。 -52 - 201248800 【主要元件符號說明】 1 〇:半導體晶片層積體 1 2 :半導體晶片 1 4 :貫穿孔 16 :貫穿電極 2 0 :控制器 22 :半導體晶片 24 :貫穿孔 26 :貫穿電極 2 8 :底層塡充材料 30 :中介層 3 2 :基板 3 4 :絕緣層 3 6 :接著劑層 3 8 :補強膜 4 0 :絕緣層 42 :開口部 5 0 :配線圖案 52 :下部配線部 54 :連結配線部 56 :上部配線部 6 0 :支柱 62 :焊料凸塊 -53- 201248800 64 :頂部 6 6 :基部 70 :乾膜 72 :貫穿孔 74 :金屬基底層 76 :乾膜 78、79 :金屬層 8 0、8 2 :乾膜 8 4 :貫穿孔 86 :金屬基底層 8 8、9 0 :乾膜 92 :金屬層 100 :半導體裝置 200 :中介層 2 1 0 :貫穿孔 212 :金屬基底層 2 1 4、2 1 6 :金屬層 218 :乾膜 2 2 0 :貫穿孔 222、224 :金屬基底層 226 :乾膜 22 8、2 3 0 ：金屬層 232 :乾膜 2 4 0 :中介層 -54 201248800 242 :絕緣層 25 0 :中介層 3 00 :半導體裝置 3 1 0 :半導體晶片 3 1 2 :電極 3 2 0 :印刷基板 3 22 :接合墊 3 2 4 :電極焊墊 3 2 6 :焊球 3 30、3 40 :接著劑層 3 5 0 :接合導線 3 60 :封裝樹脂 400 :中介層 4 1 0 :絕緣層 412 :金屬層 420 :孔 422 :貫穿孔 424 :金屬基底層 426、428 :乾膜 430 、 432 :金屬層 434 :乾膜 500 :半導體裝置 5 1 0 :多層配線基板 511 :基板 -55 201248800 5 1 2、5 1 3 :絕緣層 5 1 3 a :開口部 5 1 4 :配線圖案 5 14a :下部配線部 5 1 4 b :連結配線部 5 1 4 c :上部配線部 5 1 5 :支柱 5 1 5 a :焊料凸塊 5 1 5 b :頂部 515c :基部 520:多層配線基板 5 2 1 :基板 5 2 2、5 2 3 :絕緣層 5 2 3 a :開口部 524 :配線圖案 5 2 4 a :最上部配線部 5 2 4b :上部配線部 524c :連結配線部 524d :下部配線部 5 24e :最下部配線部 5 2 5 :焊料凸塊 53 0 :多層配線基板 5 3 1 :基板 5 3 2、5 3 3 :絕緣屑 201248800 5 3 3 a ：開口部 5 3 4 :配線圖案 5 3 4 a :上部配線部 5 3 4b :連結配線部 534c :下部配線部 5 3 5 :支柱 5 3 5 a :焊料凸塊 535b :頂部 A1、A 2 :貫穿孔 B 1〜B 3 :金屬基底層 C :控制器 C 1 : 晶片 C 2 :貫穿孔 C3 :貫穿電極 C 4 :底層塡充材料 C 5 :電極 D 1〜D 6 :乾膜 ML1〜ML4 :金屬層 S :半導體晶片層積體 S 1 :半導體晶片 S 2 :貫穿孔 S3 :貫穿電極C 46-201248800 The exposed second metal base layer forms a third gold layer containing copper as a main component; the second resin layer is removed; and the second metal is removed from the portion covered by the first resin layer The underlayer 'forms the remaining portion of the wiring pattern composed of the front third metal layer; and the other portion of the wiring pattern is covered with the second insulating layer. According to a fourth aspect of the present invention, a method of manufacturing a wiring board, comprising: forming a first through hole at a predetermined position of a resin substrate; and forming a first metal base layer on the substrate; 1 a process in which a metal base layer forms a metal layer of a predetermined pattern containing copper as a main component; and a process of forming a wiring pattern composed of the first metal layer by removing the first base layer exposed by the first metal layer; An insulating layer is formed on both surfaces of the substrate, and the wiring pattern is covered by the first insulating layer second insulating layer; and the second through hole is formed at a predetermined position of the first insulating layer until the wiring pattern is exposed; The first insulating layer and the second through hole form a second gold base layer; the second metal base layer forms a second metal layer mainly composed of copper, and the second through hole is filled with copper a process of forming a third metal layer as a main component; and removing the two metal base layers and the second metal layer on the first insulating layer to form a pillar formed of the third metal layer. According to a fifth aspect of the present invention, a semiconductor device including a plurality of semiconductor wafers having a through electrode stacked on a wiring substrate of the first state or the second aspect is characterized in that The semiconductor wafer is formed with an electrode connected to the wiring substrate, and the height of the pillar of the wiring substrate and the electrode of the semiconductor wafer are the same as those of the metal structure and the layer. The total is 35 μηι or more. According to a sixth aspect of the present invention, a semiconductor device in which a plurality of semiconductor wafers are mounted on a wiring substrate of the second aspect of the first aspect is provided in a semiconductor device, and the semiconductor wafer is formed and formed. The height of the pillar of the front substrate of the electrode connected to the wiring substrate and the height of the electrode of the semiconductor wafer are 35 μm or more. According to a seventh aspect of the present invention, there is provided a multilayer wiring board characterized by comprising: a resin substrate as a base; a wiring pattern formed thereon; and an insulating layer formed on both surfaces of the substrate while being covered with the wiring pattern The layer has the same strength in the direction of the insulating layer and the TD direction. According to a ninth aspect of the present invention, there is provided a method of manufacturing a multilayer wiring according to the seventh aspect of the present invention, characterized in that: the first through hole in a predetermined position of the resin substrate: the base layer is formed on the upper surface and the lower surface of the substrate The first metal layer containing copper as a main component in the predetermined position of the first metal base layer, and the second metal layer mainly containing copper as a main component; and the removal of the first layer exposed by the first layer a metal base layer forming a part of the wiring pattern composed of the first and the genus layers; and the base surface side and the lower surface side, and the partial wiring pattern is formed of a polyimide resin The insulating layer is formed to cover the first step; at a predetermined position of the insulating layer, to expose the height of the arrangement, a pattern or a total plate on the wiring is laminated on the substrate on the substrate. a second through hole is formed in a part of the upper casting metal layer line pattern -48 - 201248800 in which the first gold forming hole is formed in the first metal gold plate; and the second through hole is formed in the second through hole a second metal base layer is formed, and a third metal base layer is formed on the insulating layer; and the second through hole formed in the second metal base layer is filled with a third metal layer containing copper as a main component. And forming a fourth metal layer on the third metal base layer; removing the third metal base layer exposed by the fourth metal layer; and forming a wiring pattern formed of the second and third metal layers The rest of the project. In the above aspect, in the insulating layer, the MD (machine direction) direction belonging to the substrate flow direction and the TD direction (Transverse Direction) belonging to the substrate vertical direction are set to the same intensity. As a result, a multilayer wiring board having less warpage and flatness can be provided even in the case where the insulating layer is laminated on the substrate. Further, by forming the upper and lower symmetrical structures on the upper surface and the lower surface of the substrate, there is no possibility of warpage of the substrate, and low thermal expansion can be achieved, and even a large-sized substrate does not cause a structural offset. According to a ninth aspect of the invention, in the seventh aspect, the insulating layer is characterized by being formed by casting. In the above aspect, when the insulating layer is laminated, it is carried out by casting (solution casting), whereby no physical pressure is applied to the film, so that alignment of the polymer does not occur. Intensity or optical characteristics, etc. do not produce directionality. Further, the insulating layer which is commercially available as a film is a product having a constant thickness. However, as shown in the above aspect, the insulating layer can be cast to have an arbitrary thickness, and for example, an inclined structure can be produced. Therefore, it is possible to prevent the product from being enlarged due to the thickness of the unnecessary insulating layer. In addition, it is possible to use any material which has a thickness of -49 - 201248800 signal delay or a CTE (linear expansion coefficient) which is an insulating layer and meets the circuit density or purpose, and has a high degree of design freedom. The first aspect of the present invention is characterized in that in the seventh or eighth aspect, the substrate and the insulating layer are characterized by being composed of a polyimide resin. Any one or all of the insulating layers including the substrate can be formed of a polyimide resin to provide a multilayer wiring board composed of good heat resistance, low dielectric constant, and low linear expansion coefficient. In addition, polyimide resin is used instead of epoxy-based insulating material and solder resist, thereby achieving good heat resistance, low dielectric constant, and low linear expansion ratio, even for larger substrates. There are cases where the configuration is offset. The multilayer wiring board produced by the polyimide resin as described above is highly rigid and can be processed in the same manner as the conventional glass epoxy substrate, and becomes a flexible substrate which does not require a carrier. Therefore, it is possible to correspond to a conventional conveying device, and it is also possible to correspond to a reflow method. Further, an inexpensive multilayer wiring board can be produced as compared with an epoxy-based insulating material. According to an eleventh aspect of the present invention, in the seventh aspect or the eighth aspect, the present invention provides a semiconductor device including a multilayer wiring substrate, characterized in that the semiconductor wafer laminate is described in the seventh or eighth aspect. The multilayer wiring board, the multilayer wiring board, and the semiconductor wafer laminate are configured. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a schematic overall configuration of a semiconductor device of Fig. 1 -50-201248800 Fig. 2 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment. Fig. 3 is a cross-sectional view showing a schematic configuration of an interposer of the first embodiment. Fig. 4 is a view showing a method of manufacturing the interposer of Fig. 3, and Fig. 5 is a schematic view showing a method of manufacturing the interposer of Fig. 3, showing the subsequent work of Fig. 4 Illustration. Fig. 6 is a view schematically showing the manufacturing method of the interposer of Fig. 3, showing a schematic diagram of the subsequent work of Fig. 5. Fig. 7 is a cross-sectional view showing a schematic configuration of an interposer of the second embodiment. Fig. 8 is a view schematically showing the manufacturing method of the interposer of Fig. 7. Fig. 9 is a view schematically showing the manufacturing method of the interposer of Fig. 7, showing a schematic diagram of the subsequent work of Fig. 8. Fig. 10 is a cross-sectional view showing a modification of the interposer of Fig. 7. Fig. 1 is a cross-sectional view showing a modification of the interposer of Fig. 7. Fig. 12 is a cross-sectional view showing the schematic configuration of the semiconductor device of the third embodiment. Fig. 13 is a cross-sectional view showing the schematic configuration of the interposer of the third embodiment. Fig. 14 is a view schematically showing the manufacturing method of the interposer of Fig. 13. -51 - 201248800 Fig. 15 is a diagram showing a method of manufacturing the interposer of Fig. 3, and shows a schematic diagram of the subsequent work of Fig. 14. Fig. 16 is a cross-sectional view showing the configuration of a semiconductor device of a fourth embodiment. Fig. 17 is a cross-sectional view showing the configuration of a multilayer wiring board of a fourth embodiment. Fig. 18 is a view showing a method of manufacturing the multilayer wiring board of the fourth embodiment. Fig. 19 is a view showing a method of manufacturing the multilayer wiring board of the fourth embodiment, and showing a subsequent process of Fig. 18. Fig. 20 is a cross-sectional view showing the configuration of a multilayer wiring board of a fifth embodiment. Fig. 2 is a view showing a method of manufacturing the multilayer wiring board of the fifth embodiment. Fig. 22 is a view showing a method of manufacturing the multilayer wiring board of the fifth embodiment, and shows an illustration of the subsequent work of Fig. 21. Figure 23 is a cross-sectional view showing the configuration of a multilayer wiring board of a sixth embodiment. Fig. 24 is a cross-sectional view showing a method of manufacturing the multilayer wiring board of the sixth embodiment. Fig. 25 is a view showing a method of manufacturing the multilayer wiring board of the sixth embodiment, and shows a drawing of the subsequent work of Fig. 24. Fig. 26 is a view showing a method of manufacturing the multilayer wiring board of the sixth embodiment, and shows an illustration of the subsequent process of Fig. 25. -52 - 201248800 [Description of main component symbols] 1 〇: semiconductor wafer laminate 1 2 : semiconductor wafer 14 : through hole 16 : through electrode 2 0 : controller 22 : semiconductor wafer 24 : through hole 26 : through electrode 2 8 : underlying chelating material 30 : interposer 3 2 : substrate 3 4 : insulating layer 3 6 : adhesive layer 3 8 : reinforcing film 40 : insulating layer 42 : opening portion 50 : wiring pattern 52 : lower wiring portion 54 : connection wiring portion 56 : upper wiring portion 60 : pillar 62 : solder bump - 53 - 201248800 64 : top portion 6 6 : base portion 70 : dry film 72 : through hole 74 : metal base layer 76 : dry film 78 , 79 : Metal layer 80, 8 2 : dry film 8 4 : through hole 86 : metal base layer 8 8 , 90 : dry film 92 : metal layer 100 : semiconductor device 200 : interposer 2 1 0 : through hole 212 : metal substrate Layer 2 1 4, 2 1 6 : Metal layer 218 : Dry film 2 2 0 : Through hole 222, 224 : Metal base layer 226 : Dry film 22 8 , 2 3 0 : Metal layer 232 : Dry film 2 4 0 : Intermediary Layer-54 201248800 242: Insulation layer 25 0 : Interposer 3 00 : Semiconductor device 3 1 0 : Semiconductor wafer 3 1 2 : Electrode 3 2 0 : Printed substrate 3 22 : Bond pad 3 2 4 : Polar pad 3 2 6 : solder ball 3 30, 3 40 : adhesive layer 3 50 : bonding wire 3 60 : encapsulating resin 400 : interposer 4 1 0 : insulating layer 412 : metal layer 420 : hole 422 : through hole 424: metal base layer 426, 428: dry film 430, 432: metal layer 434: dry film 500: semiconductor device 5 1 0: multilayer wiring substrate 511: substrate - 55 201248800 5 1 2, 5 1 3 : insulating layer 5 1 3 a : opening 5 1 4 : wiring pattern 5 14a : lower wiring portion 5 1 4 b : connection wiring portion 5 1 4 c : upper wiring portion 5 1 5 : pillar 5 1 5 a : solder bump 5 1 5 b Top 515c: Base 520: Multilayer wiring substrate 5 2 1 : Substrate 5 2 2, 5 2 3 : Insulation layer 5 2 3 a : Opening portion 524 : Wiring pattern 5 2 4 a : Uppermost wiring portion 5 2 4b : Upper portion Wiring portion 524c: connection wiring portion 524d: lower wiring portion 5 24e: lowermost wiring portion 5 2 5 : solder bump 53 0 : multilayer wiring substrate 5 3 1 : substrate 5 3 2, 5 3 3 : insulating dust 201248800 5 3 3 a : opening 5 3 4 : wiring pattern 5 3 4 a : upper wiring portion 5 3 4b : connection wiring portion 534c : lower wiring portion 5 3 5 : pillar 5 3 5 a : solder bump 535b : top A1, A 2: Holes B 1 to B 3 : Metal base layer C : Controller C 1 : Wafer C 2 : Through hole C3 : Through electrode C 4 : Underlayer charge material C 5 : Electrodes D 1 to D 6 : Dry film ML1 to ML4 : Metal layer S: semiconductor wafer laminate S 1 : semiconductor wafer S 2 : through hole S3 : through electrode

Claims (1)

201248800 七、申請專利範園 1.一種配線基板，其特徵爲具有： 作爲基底的樹脂製基板； 形成在前述基板上的配線圖案；及 被覆前述配線圖案之一部分的絕緣層， 在前述配線圖案上的預定位置立設有由以銅爲主成分 的金屬所構成且與半導體晶片相連接的支柱， 前述支柱係在貫穿前述基板的狀態下立設於前述配線 圖案上。 2 .—種配線基板，其特徵爲具有： 作爲基底的樹脂製基板； 形成在前述基板上的配線圖案：及 被覆前述配線圖案之一部分的絕緣層， 在前述配線圖案上的預定位置立設有由以銅爲主成分 的金屬所構成且與半導體晶片相連接的支柱， 前述支柱係在貫穿前述絕緣層的狀態下立設於前述配 線圖案上。 3. 如申請專利範圍第1項或第2項之配線基板，其 中，前述支柱係高度爲3 5 μπι以上》 4. 如申請專利範圍第1項或第2項之配線基板，其 中，前述支柱係呈由與半導體晶片相連接的頂部朝向與前 述配線圖案相連接的基部呈尖端細的倒錐狀。 5 ·如申請專利範圍第1項或第2項之配線基板，其 中’前述基板作爲被覆前述支柱的側面的保護層而發揮功 -58- 201248800 能。 6.如申請專利範圍第2項之配線基板，其中，前述絕 緣層作爲被覆前述支柱的側面的保護層而發揮功能。 7 ·如申請專利範圍第1項或第2項之配線基板，其 中’在前述支柱的頂部設有焊料凸塊。 8 · —種配線基板之製造方法，其特徵爲具有： 在樹脂製基板的預定位置形成第1貫穿孔的工程； 在前述基板形成第1金屬基底層的工程； 以預定圖案的第1樹脂層被覆前述基板的一面側的前 述第1金屬基底層的工程： 在由前述第1樹脂層露出的前述第1金屬基底層形成 以銅爲主成分的第1金屬層，並且在前述第1貫穿孔塡充 以銅爲主成分的第2金屬層的工程； 去除前述基板之形成有前述第1樹脂層的面的相反面 所形成的前述第1金屬基底層及前述第1金屬層，形成由 前述第2金屬層所構成的支柱的工程； 去除前述第1樹脂層的工程； 去除以前述第1樹脂層所被覆的部分的前述第1金屬 基底層，形成由前述第1金屬層所構成的配線圖案的一部 分的工程； 形成被覆前述配線圖案之一部分的第1絕緣層的工 程； 在前述第1絕緣層的預定位置，至露出前述配線圖案 的一部分爲止形成第2貫穿孔的工程； -59- 201248800 在前述第1絕緣層形成第2金屬基底層的工 以預定圖案的第2樹脂層被覆前述第2金屬 工程： 在由前述第2樹脂層露出的前述第2金屬基 以銅爲主成分的第3金屬層的工程； 去除前述第2樹脂層的工程； 去除以前述第2樹脂層所被覆的部分的前述 基底層，形成由前述第3金屬層所構成的配線圖 部分的工程；及 以第2絕緣層被覆前述配線圖案的剩餘部分 9.一種配線基板之製造方法，其特徵爲具有 在樹脂製基板的預定位置形成第1貫穿孔的 在前述基板形成第1金屬基底層的工程； 在前述第1金屬基底層形成以銅爲主成分的 的第1金屬層的工程； 去除由前述第1金屬層露出的前述第1金屬 形成由前述第1金屬層所構成的配線圖案的工程 在前述基板的兩面分別形成絕緣層，以第1 第2絕緣層被覆前述配線圖案的工程； 在前述第1絕緣層的預定位置，至露出前述 爲止形成第2貫穿孔的工程； 在前述第1絕緣層與前述第2貫穿孔形成第 底層的工程； 在前述第2金厠基底層形成以銅爲主成分的 程； 基底層的 底層形成 第2金屬 案的剩餘 的工程。 工程； 預定圖案 基底層， t 絕緣層與 配線圖案 2金屬基 第2金屬 -60 - 201248800 層，並且在前述第2貫穿孔塡充以銅爲主成分的第3金屬 層的工程；及 去除前述第1絕緣層上的前述第2金屬基底層及第2 金屬層’形成由前述第3金屬層所構成的支柱的工程。 1 〇·如申請專利範圍第9項之配線基板之製造方法， 其中’在形成由前述第3金屬層所構成的支柱的工程之 後’具有將前述第〖絕緣層剝離的工程。 11. 一種半導體裝置，其係將具有貫穿電極的複數枚 半導體晶片層積在如申請專利範圍第1項或第2項之配線 基板上的半導體裝置，其特徵爲： 在則述半導體晶片形成與前述配線基板相連接的電 極， 前述配線基板的支柱的高度與前述半導體晶片的電極 的高度的合計爲3 5 μ m以上。 12. —種半導體裝置，其係將複數枚半導體晶片，按 每1枚構裝在如申請專利範圍第1項或第2項之配線基板 的半導體裝置，其特徵爲： 在前述半導體晶片形成與前述配線基板相連接的電 極， 前述配線基板的支柱的高度與前述半導體晶片的電極 的高度的合計爲35μπι以上。 13. —種多層配線基板，其特徵爲具有： 作爲基底的樹脂製基板； 形成在前述基板上的配線圖案；及 -61 - 201248800 積層前述配線圖案的一部分所形成的絕緣層， 前述絕緣層係在MD方向及TD方向，強度爲相同。 1 4.如申請專利範圍第1 3項之多層配線基板，其中， 前述絕緣層係藉由澆鑄所形成。 15. 如申請專利範圍第13項或第14項之多層配線基 板，其中，前述基板及前述絕緣層的任一者均藉由聚亞醯 胺樹脂所構成。 16. —種配線基板之製造方法，其特徵爲具有： 在樹脂製基板的預定位置形成第1貫穿孔的工程； 在前述基板的上面及下面形成第1金屬基底層的工 程； 在前述第1金屬基底層的預定位置形成以銅爲主成分 的第1金屬層，並且在前述第1貫穿孔塡充以銅爲主成分 的第2金屬層的工程； 去除由前述第1金屬層露出的前述第1金屬基底層， 形成由前述第1及第2金屬層所構成的配線圖案的一部分 的工程； 在前述基板的上面側及下面側，且爲前述一部分配線 圖案上，藉由澆鑄形成由聚亞醯胺樹脂所構成的絕緣層， 被覆前述第1金屬層的工程； 在前述絕緣層的預定位置，至露出前述配線圖案的一 部分爲止形成第2貫穿孔的工程； 在前述第2貫穿孔形成第2金厫基底層，並且在前述 絕緣層形成第3金劂基底層的工程； -62- 201248800 在形成有前述第2金屬基底層的 充以銅爲主成分的第3金屬層，並且 層形成第4金屬層的工程； 去除由前述第4金屬層露出的前 工程；及 形成由前述第.2及第3金屬層所 餘部分的工程。 17. —種半導體裝置，其特徵爲 體、如申請專利範圍第1 3項或第1 4 前述多層配線基板、及半導體晶片層 前述第2貫穿孔，塡 在前述第3金屬基底 述第3金屬基底層的 構成的配線圖案的剩 :由半導體晶片層積 項之多層配線基板、 積體所構成。 -63-201248800 VII. Patent application 1. A wiring board comprising: a resin substrate as a base; a wiring pattern formed on the substrate; and an insulating layer covering a portion of the wiring pattern on the wiring pattern A pillar formed of a metal mainly composed of copper and connected to the semiconductor wafer is provided at a predetermined position, and the pillar is erected on the wiring pattern in a state of penetrating the substrate. A wiring board comprising: a resin substrate as a base; a wiring pattern formed on the substrate; and an insulating layer covering a portion of the wiring pattern, which is provided at a predetermined position on the wiring pattern A pillar formed of a metal containing copper as a main component and connected to a semiconductor wafer, the pillar is erected on the wiring pattern in a state of penetrating the insulating layer. 3. The wiring substrate of claim 1 or 2, wherein the height of the pillar is 35 5 π or more. 4. The wiring substrate of claim 1 or 2, wherein the pillar The base portion connected to the semiconductor wafer has an inverted tapered shape with a tip end that is connected to the wiring pattern. 5. The wiring board according to the first or second aspect of the patent application, wherein the substrate is capable of functioning as a protective layer covering a side surface of the pillar. -58-201248800. 6. The wiring board according to the second aspect of the invention, wherein the insulating layer functions as a protective layer covering a side surface of the pillar. 7. The wiring board of claim 1 or 2, wherein the solder bump is provided on the top of the pillar. A method of manufacturing a wiring board, comprising: forming a first through hole at a predetermined position of a resin substrate; forming a first metal base layer on the substrate; and forming a first resin layer in a predetermined pattern A process of covering the first metal base layer on one surface side of the substrate: forming a first metal layer containing copper as a main component in the first metal base layer exposed from the first resin layer, and forming the first through hole a process of filling a second metal layer containing copper as a main component; removing the first metal base layer and the first metal layer formed on the opposite surface of the surface of the substrate on which the first resin layer is formed, and forming the first metal layer The work of removing the pillars of the second metal layer; the process of removing the first resin layer; removing the first metal base layer in the portion covered by the first resin layer, and forming the wiring formed of the first metal layer a part of the pattern; a process of forming a first insulating layer covering a portion of the wiring pattern; and exposing the wiring pattern at a predetermined position of the first insulating layer a part of the second through hole is formed in the first insulating layer. -59 - 201248800 The second metal layer is formed in the first insulating layer to cover the second metal layer in a predetermined pattern. a process of removing the second metal layer containing copper as a main component in the second metal base exposed; a process of removing the second resin layer; and removing the underlying layer in a portion covered by the second resin layer to form the first layer a process of the wiring pattern portion formed of the metal layer; and a remaining portion of the wiring pattern covered with the second insulating layer. 9. A method of manufacturing a wiring board, characterized in that the first through hole is formed at a predetermined position of the resin substrate. a process of forming a first metal base layer on the substrate; a process of forming a first metal layer containing copper as a main component in the first metal base layer; and removing the first metal formed by the first metal layer The wiring pattern of the first metal layer is formed by forming an insulating layer on both surfaces of the substrate, and coating the wiring pattern with the first and second insulating layers. a process of forming a second through hole at a predetermined position of the first insulating layer until the exposure; forming a second underlayer in the first insulating layer and the second through hole; and forming a second underlayer in the second gold enamel base layer The process of copper as the main component; the bottom layer of the base layer forms the remaining project of the second metal case. Engineering; predetermined pattern base layer, t insulating layer and wiring pattern 2 metal-based second metal-60 - 201248800 layer, and the second through-hole is filled with a third metal layer containing copper as a main component; and the foregoing The second metal base layer and the second metal layer 'on the first insulating layer form a pillar formed of the third metal layer. In the method of manufacturing a wiring board according to the ninth aspect of the invention, the method of peeling off the insulating layer is performed after the step of forming the pillar formed of the third metal layer. A semiconductor device in which a plurality of semiconductor wafers having a through-electrode are stacked on a wiring substrate as in the first or second aspect of the patent application, characterized in that the semiconductor wafer is formed and In the electrode to which the wiring board is connected, the total height of the pillar of the wiring board and the height of the electrode of the semiconductor wafer is 35 μm or more. 12. A semiconductor device comprising: a semiconductor device in which a plurality of semiconductor wafers are mounted on a wiring substrate according to claim 1 or 2 of the patent application, wherein: the semiconductor wafer is formed and formed In the electrode to which the wiring board is connected, the total height of the pillar of the wiring board and the height of the electrode of the semiconductor wafer is 35 μm or more. 13. A multilayer wiring board comprising: a resin substrate as a base; a wiring pattern formed on the substrate; and -61 - 201248800 an insulating layer formed by laminating a part of the wiring pattern, wherein the insulating layer is The intensity is the same in the MD direction and the TD direction. 1. The multilayer wiring board of claim 13, wherein the insulating layer is formed by casting. 15. The multilayer wiring board of claim 13 or 14, wherein the substrate and the insulating layer are each formed of a polyimide resin. 16. A method of manufacturing a wiring board, comprising: forming a first through hole at a predetermined position of a resin substrate; forming a first metal base layer on an upper surface and a lower surface of the substrate; a predetermined position of the metal base layer forms a first metal layer containing copper as a main component, and the first through hole is filled with a second metal layer containing copper as a main component; and the foregoing exposed by the first metal layer is removed a first metal base layer is formed by forming a part of the wiring pattern composed of the first and second metal layers; and the upper surface side and the lower surface side of the substrate are formed by casting on the part of the wiring pattern The insulating layer formed of the melamine resin covers the first metal layer; the second through hole is formed at a predetermined position of the insulating layer until a part of the wiring pattern is exposed; and the second through hole is formed. a second metal ruthenium base layer, and a third gold ruthenium base layer is formed on the insulating layer; -62- 201248800 in the formation of the second metal base layer Copper as a main component of the third metal layer, and a fourth layer forming step of metal layer; exposed by removing the fourth metal layer of the front Engineering; Engineering formed by said first and third .2 remainder of the metal layer. A semiconductor device characterized by being the body of the first or third multilayer wiring substrate of the first or third aspect of the invention, and the second through hole of the semiconductor wafer layer, and the third metal of the third metal substrate The remaining wiring pattern of the underlying layer structure is composed of a multilayer wiring board and an integrated body of a semiconductor wafer laminate. -63-
TW101105250A 2011-02-18 2012-02-17 Wiring substrate, method for manufacturing same, and semiconductor device TW201248800A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011033489A JP2012174791A (en) 2011-02-18 2011-02-18 Wiring board, manufacturing method of wiring board, and semiconductor device
JP2011068642A JP2012204662A (en) 2011-03-25 2011-03-25 Wiring board and method for manufacturing the same, and semiconductor device

Publications (1)

Publication Number Publication Date
TW201248800A true TW201248800A (en) 2012-12-01

Family

ID=46672725

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101105250A TW201248800A (en) 2011-02-18 2012-02-17 Wiring substrate, method for manufacturing same, and semiconductor device

Country Status (2)

Country Link
TW (1) TW201248800A (en)
WO (1) WO2012111814A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI620293B (en) * 2016-09-09 2018-04-01 Toshiba Memory Corp Manufacturing method of semiconductor device
TWI721912B (en) * 2019-12-24 2021-03-11 日商鈴木股份有限公司 Manufacturing method of semiconductor device and manufacturing device of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9515035B2 (en) 2014-12-19 2016-12-06 International Business Machines Corporation Three-dimensional integrated circuit integration

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3378334B2 (en) * 1994-01-26 2003-02-17 株式会社東芝 Semiconductor device mounting structure
JP2001274277A (en) * 2000-03-27 2001-10-05 Taiyo Ink Mfg Ltd Printed wiring substrate with projection electrode and its manufacturing method
JP2001308542A (en) * 2000-04-20 2001-11-02 Nippon Shokubai Co Ltd Multilayer wiring board
JP4345705B2 (en) * 2005-04-19 2009-10-14 エルピーダメモリ株式会社 Memory module
JP5173651B2 (en) * 2008-07-29 2013-04-03 京セラ株式会社 Wiring board manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI620293B (en) * 2016-09-09 2018-04-01 Toshiba Memory Corp Manufacturing method of semiconductor device
TWI721912B (en) * 2019-12-24 2021-03-11 日商鈴木股份有限公司 Manufacturing method of semiconductor device and manufacturing device of semiconductor device

Also Published As

Publication number Publication date
WO2012111814A1 (en) 2012-08-23

Similar Documents

Publication Publication Date Title
US20240266321A1 (en) Semiconductor device and manufacturing method thereof
TWI710072B (en) Semiconductor device package and method of forming the same
US12218020B2 (en) Semiconductor packages
US10163802B2 (en) Fan-out package having a main die and a dummy die, and method of forming
TWI809012B (en) Methods and apparatus for wafer-level die bridge
US8703539B2 (en) Multiple die packaging interposer structure and method
US9013037B2 (en) Semiconductor package with improved pillar bump process and structure
TWI556400B (en) Stacked fan-out semiconductor chip
JP5588620B2 (en) Wafer level package and method of forming the same
US11355428B2 (en) Semiconductor package
US9338886B2 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
US12159822B2 (en) Method of manufacturing a semiconductor package having conductive pillars
TW201133743A (en) Semiconductor structure and method forming semiconductor device
TWI622107B (en) Semiconductor device having a semiconductor die embedded between an extension substrate and a bottom substrate
US11145614B2 (en) Semiconductor device and method of manufacture
TWI692839B (en) Semiconductor device and method for manufacturing same
TW201248800A (en) Wiring substrate, method for manufacturing same, and semiconductor device
TWI876486B (en) Package structure and methods of forming the package structure
TWI757864B (en) Package structure and method of forming the same
KR20130042938A (en) Semiconductor chip, semiconductor package having the same, and method of fabricating stack type semiconductor package
TW202439557A (en) Package structure and methods of forming the package structure
CN117276243A (en) Semiconductor package and method of forming same
JP2012221975A (en) Interposer and method of manufacturing the same
JP2004200238A (en) Semiconductor device, manufacturing method therefor, method for mounting the same and mounting structure thereof