KR20130042938A - Semiconductor chip, semiconductor package having the same, and method of fabricating stack type semiconductor package - Google Patents

Abstract

Disclosed is a semiconductor chip having a structure that enables a bonding process of a semiconductor chip at a low temperature, excluding a high temperature process that impairs the reliability of a package or a semiconductor chip.
According to the present invention, a semiconductor chip includes a substrate including first and second surfaces that are opposite to each other, conductive through vias penetrating the substrate, and through vias on the first surface of the substrate. A bump disposed to be electrically connected, an auxiliary bump disposed on the first surface of the substrate to be spaced apart from the bump, and an auxiliary solder disposed on an area corresponding to the auxiliary bump on the second surface of the substrate. do.

Description

Semiconductor chip, Semiconductor Package having the same, and Method of fabricating stack type semiconductor package

The present invention relates to a semiconductor chip, a semiconductor package including the same, and a method of manufacturing a stacked semiconductor package.

Packaging technology for integrated circuits has been continuously developed to meet the requirements for miniaturization and mounting reliability. Recently, as miniaturization of electric and electronic products and high performance is required, chips are stacked and various technologies related to the stack have been developed. Stacked packages have advantages in terms of increased memory capacity as well as efficiency in mounting density and footprint area, which has accelerated the research and development of stacked packages.

As an example of such a laminated package, a structure using a through silicon via (TSV) has been proposed. A stacked package using through silicon vias (TSV) is a technique of forming through vias through a chip and using the through vias as electrodes, which provides various advantages as the use of conventional wires is unnecessary.

In general, a semiconductor package is mounted on a package substrate after dicing a semiconductor substrate on which a semiconductor element is formed, and electrically connects a bonding pad formed on the semiconductor chip to a lead frame of the package substrate using wire bonding and epoxy It is manufactured through the process of sealing with sealing materials, such as. The semiconductor package manufactured as described above is mounted on a printed circuit board using a solder. However, bump electrodes are formed on the back surface of the chip to improve the fine-pitch, trend of heat dissipation, and shorten the signal path for improving the mounting density, and the chip is inverted to form a printed circuit board (PCB). Flip chip packaging technology for mounting on a substrate has been introduced.

In the case of flip chip packaging for a stacked package, solder is used to electrically connect the chip to the chip.In the process of mounting the semiconductor chip, the chip and the chip are subjected to a high temperature treatment process such as solder reflow. Since the chip and the substrate are bonded, the bonding is performed in a state where deformation such as bending or warping by heat occurs. Therefore, in the process of restoring to the original state while being cooled to room temperature, there is a problem in that a defect such as breakage of electrical and mechanical joints occurs and the reliability of the package is reduced. In addition, the high temperature bonding process also adversely affects the reliability of the semiconductor device mounted on the chip, which has a disadvantage of limiting the material used in the process.

Disclosure of Invention Problems to be Solved by the Invention The present invention is to provide a semiconductor package and a semiconductor package including the same, which excludes a high temperature process that impairs the reliability of the package or the semiconductor chip and enables the bonding process of the semiconductor chip at a low temperature.

Another object of the present invention is to provide a method of forming a highly reliable stacked semiconductor package at low temperature or room temperature.

In order to solve the above problems, a semiconductor chip according to the present invention includes a substrate including first and second surfaces opposite to each other, a conductive through via penetrating the substrate, and a first surface of the substrate. A bump disposed to be electrically connected to the through via, an auxiliary bump disposed to be spaced apart from the bump on the first surface of the substrate, and an auxiliary solder disposed on a region corresponding to the auxiliary bump on the second surface of the substrate; Characterized in that it comprises a.

The semiconductor package according to the present invention includes a package substrate, a plurality of semiconductor chips stacked vertically on the package substrate, and a sealing material injected into a space between the semiconductor chips. In this case, the semiconductor chip is electrically connected to a substrate having a first surface and a second surface opposite to each other, a conductive through via penetrating the substrate, and a through via to the first surface of the substrate. And bumps disposed to be spaced apart from each other, auxiliary bumps spaced apart from the bumps on the first surface of the substrate, and auxiliary solders disposed in regions corresponding to the auxiliary bumps on the second surface of the substrate.

In order to solve the above problems, a method of manufacturing a stacked semiconductor package according to the present invention may include a bump including a solder on a surface of the semiconductor substrate on which a through via is formed and connected to the through via on a first surface of the semiconductor substrate. Forming an auxiliary bump, forming an auxiliary solder layer in an area corresponding to the auxiliary bump of the second surface, and cutting individual semiconductor chips on which the bump, the auxiliary bump and the auxiliary solder layer are formed, to form individual semiconductor chips And arranging the plurality of semiconductor chips on the package substrate, and bonding the aligned semiconductor chips.

According to the present invention, the process of stacking and bonding semiconductor chips can be performed at a low temperature of 100 ° C. to 150 ° C., thereby preventing warpage or breakage of bumps due to high temperatures, thereby improving package reliability. Can be.

1 is a cross-sectional view schematically illustrating a semiconductor chip according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
3 to 9 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor package according to an embodiment of the present invention.

Hereinafter, an embodiment of a semiconductor package and a method of manufacturing the same according to an aspect of the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, and a duplicate description thereof will be omitted.

1 is a cross-sectional view schematically illustrating a semiconductor chip according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor chip 300 of the present invention includes a substrate 100, a through via 110, a bump 140, an auxiliary bump 150, and an auxiliary solder 150 ′. .

The substrate 100 has a first side 101 and a second side 102 opposing each other. In the substrate 100, a semiconductor device such as a memory device or a logic device is formed.

The through via 110 penetrates the substrate and consists of a conductive layer such as metal. The bump 140 is disposed on the first surface of the substrate to be electrically connected to the through via 110. The bump 140 ′ may also be disposed on the second surface of the substrate so as to be connected to the through via 110 to correspond to the bump 140, and the bump 140 ′ of the second surface may be omitted in some cases. . The bumps 140 and 140 ′ may include conductive pillars 142 and 142 ′ that connect to the through vias 110 and solders 145 and 145 ′ formed on the conductive pillars. The conductive pillars 142 and 142 ′ may be made of copper (Cu), for example. The solders 145 and 145 'have a lower melting point than the materials constituting the conductive pillars 142 and 142', such as tin, so that they can be melted by pressure at relatively low temperatures, such as 100 to 150 degrees C or room temperature. It is preferable to comprise at least any one of (Sn) and silver (Ag).

An under bump metallurgy layer 120 and 120 ′ may be interposed between the through via 110 and the conductive pillars 142 and 142 ′. In one example, the UBM layers 120 and 120 'have an adhesion between the seed layer 124. 124' and the substrate 100 and the seed layers 124 and 124 'for forming a metal layer through electroplating. Adhesive layers 122 and 122 'for improvement. In one example, the seed layers 124 and 124 'may be formed of a conductive layer including copper (Cu), and the adhesive layers 122 and 122' may be formed of a metal layer including titanium (Ti).

An auxiliary bump 150 is disposed on the first surface 101 of the substrate to be spaced apart from the bump 140. In one example, the auxiliary bump 150 includes a first pillar 152 disposed on the first surface 102 of the substrate and a second pillar 154 disposed over the first pillar 152. A seed layer 124 is formed between the substrate and the auxiliary bump 150 to form a metal layer through electrolytic plating, and an adhesive layer 122 is formed to improve adhesion between the substrate 100 and the seed layer 124. The UBM layer 120 may be interposed.

On the second surface 102 of the substrate, an auxiliary solder layer 150 ′ is disposed in a region corresponding to the auxiliary bump 150. The auxiliary solder layer 150 ′ may be buried below the second surface 102 of the substrate. The auxiliary solder layer 150 ′ is a material constituting the pillar 154 of the auxiliary bump 150 such that the auxiliary solder layer 150 ′ is melted by a pressure at a relatively low temperature, for example, 100 ° C. to 150 ° C. or at room temperature to bond with the auxiliary bump 150. It is preferred to comprise at least one of a lower melting point material, such as tin (Sn) and silver (Ag).

When stacking two substrates including the auxiliary bumps 150 and the auxiliary solder layers 150 'disposed on the opposing first and second surfaces, the auxiliary bumps 150 of the substrate 100 and the other substrates are stacked. After the auxiliary solder layers 150 'are aligned to face each other and a predetermined pressure is applied, a part of the auxiliary solder layer 150' is melted, and the auxiliary bumps 150 are inserted into the auxiliary solder layer 150 'to insert the two substrates. Bonding is made between. Therefore, the adhesive force between the two substrates may be further improved by further including the auxiliary bumps 150 and the auxiliary solder layer 150 ′ in addition to the bumps 140.

2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor package of the present invention has a structure in which a plurality of semiconductor chips 300 and 301 illustrated in FIG. 1 are stacked on a package substrate 400. In the drawings, only two semiconductor chips 300 and 301 are shown for convenience of description. Since the semiconductor chips 300 and 301 have the same structure as the semiconductor chip 300 described with reference to FIG. 1, a redundant description of the structure of the semiconductor chips 300 and 301 will be omitted.

The semiconductor chips 300 and 301 stacked on the package substrate 400 may have a plurality of through vias 110 penetrating therein and connected to the lower bumps 140 and stacked in a plurality of vertical directions. That is, the through via 110 of the upper chip 301 is electrically interconnected through the through via 110 and the bump 140 of the lower chip 300, and the lower chip 300 is bump 410. ) Is connected to the package substrate 400. A conductive solder 145 is disposed on the top of the bump 140, and the solder 145 is a conductive material, such as tin (Sn), that is melted at a lower temperature than the pillar 142, such as at room temperature or at a low temperature of about 100 ° C. to 150 ° C. ) And silver (Ag). Accordingly, when the two semiconductor chips 300 and 301 are joined, the solder 145 is melted by pressure to bond the bumps 140, and the semiconductor is connected through the through vias 110 connected to the bumps 140. Electrical connections between the chips 300 and 301 are made.

On the outside of the through via 110, the auxiliary bump 150 and the auxiliary solder 150 ′ formed in the opposing regions of the upper and lower chips are bonded to each other, thereby more physically bonding the two semiconductor chips 300 and 301. . In addition, an underfill adhesive 420 for attaching the chips 300 and 301 to each other is disposed in the space between the chips 300 and 301 adjacent to each other in the vertical direction.

As described above, according to the semiconductor chip and the semiconductor package of the present invention, the solder is formed on the upper end of the bump to be connected to the through electrode, and the auxiliary bump and the auxiliary solder disposed around the bump, thereby bonding the semiconductor chip in a low temperature process. Can be achieved. In addition, due to the auxiliary bumps and the auxiliary solder, alignment between the semiconductor chips stacked up and down may be easily achieved, and the adhesion between the semiconductor chips may be further increased.

3 to 9 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor package according to an embodiment of the present invention.

Referring to FIG. 3, a first surface of a substrate 100 on which a semiconductor device (not shown) and a blind via 111 including an active device such as a transistor and a passive device such as a resistor and a capacitor are formed. An UBM layer (Under Bump Metallurgy layer, 120) is formed in 101. The blind vias 111 are portions formed of through silicon vias through a backside grinding process to be performed later.

In one example, the UBM layer 120 may include a seed layer 124 for forming a bump metal layer through electroplating, and an adhesive layer 122 for improving adhesion between the substrate 100 and the seed layer 124. It includes. In one example, the seed layer 124 is a conductive layer containing copper (Cu), is formed by a sputtering method, the adhesive layer 122 is a metal layer containing titanium (Ti), is formed by a sputtering method .

Next, a first resist pattern 132 is formed to expose the region where the bump is to be formed and the region where the auxiliary bump is to be formed. Then, an electroplating process is performed to form the bumps 142 and the auxiliary bumps. The first pillar 152 is formed. In one example, the pillars 142 and the first pillars 152 are formed of copper (Cu).

When a plurality of semiconductor chips are stacked to form a stacked package, bonding is performed between chips stacked up and down by pressure. Accordingly, the cross-sectional area of the pillar 142 is at least the cross-sectional area of the through silicon vias, that is, in order to prevent defects such as bumps or bends of the lower semiconductor chip from being caused by the pressure applied from the bumps of the upper semiconductor chips. It is preferable to form larger than the cross-sectional area of the blind via (111).

Referring to FIG. 4, after removing the first resist pattern, a second resist pattern 134 is formed to expose a region where the second pillar of the auxiliary bump is to be formed. The electroplating process may be performed to form a second pillar 154 extending from the first pillar 152 of the auxiliary bump in the region exposed by the second resist pattern 134. The first pillar 152 and the second pillar 154 constitute an auxiliary bump. In one example, the second pillar 154 is formed of copper (Cu). Auxiliary bumps are formed for mechanical connection, unlike bumps for electrical and mechanical connection between upper and lower semiconductor chips.

The height h of the auxiliary bumps is at least equal to the gap between the chips in order to keep the gap between the two semiconductor chips stacked later. In addition, in order to prevent the bump from bending or breaking in the process of stacking the multilayer semiconductor chip and to facilitate the pressure transfer to the lower semiconductor chip, the first pillar may be larger than the cross-sectional area of the second pillar 154 of the auxiliary bump. It is desirable to form a larger cross-sectional area of 152.

Referring to FIG. 5, after removing the second resist pattern 134 of FIG. 3, a third resist pattern (not shown) exposing a region where a solder layer is to be formed is formed. The electroplating process is performed to form the solder layer 144 on the top of the pillar 142 to form the bump 140 formed of the pillar 142 and the solder layer 144. The solder layer 144 is melted when the semiconductor chips are stacked to allow electrical and mechanical bonding between the stacked semiconductor chips.

When the metal constituting the pillar 142 is exposed to air, the metal is combined with oxygen in the air to form an oxide film. When the oxide film is formed on the surface, adhesion to the solder is inferior. Therefore, before forming the solder layer 144 on the pillar 142, it is preferable to perform a process of removing the oxide film formed on the surface of the metal layer. The process of removing the oxide film may be performed using a sulfuric acid solution of a certain concentration. In addition, the solder layer 144 may be formed of a material that can be melted by pressure at a low temperature or room temperature of about 100 ° C. to 150 ° C. in the step of bonding and stacking semiconductor chips. In one example, the solder layer 144 may include at least one of tin (Sn) and silver (Ag).

Next, after removing the third resist pattern formed to form the solder 144, the exposed region of the UBM layer is removed. As a result, the UBM layer 120 remains only under the bump 140 and the UBM layer is removed in the remaining area, thereby exposing the substrate 100. As a result, the first surface 101 of the substrate includes a bump 140 including an UBM layer 120 pattern including an adhesive layer 122 and a seed layer 124, a pillar 142, and a solder layer 144. The auxiliary bump 150 including the UBM layer 120 pattern including the adhesive layer 122 and the seed layer 124, the first pillar 152, and the second pillar 154 is formed.

Referring to FIG. 6, after the adhesive 160 is applied to the first surface 101 of the substrate on which the bump 140 and the auxiliary bump 150 are formed and adhered to the carrier substrate 200, the substrate 100 is turned upside down. A backside grinding process is performed on the second surface 102 of the substrate. In the case of forming a package by stacking a substrate having a thickness of about several hundred μm, the package is thick, and therefore, a defect is likely to occur in the package due to deformation due to heat, and the number of stacking stages is limited depending on the height. Therefore, in order to overcome these limitations and defects, the back grinding process is performed by grinding the back surface of the substrate to make the thickness thinner.

The back grinding process initially performs chemical mechanical polishing (CMP) to mechanically grind the back surface of the substrate while approaching the target thickness so as to achieve the desired thickness. In the chemical mechanical polishing (CMP) process, a slurry is used. Since the etching rate of the substrate is faster than that of the metal embedded in the through silicon via 110, the metal embedded in the through silicon via 110 protrudes relatively. do. When the insulating layer is formed on the second surface 102 of the substrate in a state where a predetermined thickness of the through silicon via 110 is protruded, and then chemical mechanical polishing is performed again, the surface of the through silicon via 110 is The insulating layer 170 is exposed and has a flat surface.

Referring to FIG. 7, the planarized insulating layer 170 is patterned to form an auxiliary solder region S ′ which is a position where the auxiliary solder layer is to be formed. Subsequently, the UBM layer 120 'including the adhesive layer 122' and the seed layer 124 'is formed on the surface of the insulating layer 170 on which the auxiliary solder region S' is formed. The adhesive layer 122 ′ and the seed layer 124 may be formed in the same manner as the process of forming the UBM layer 120 on the first surface 101 of the substrate.

Referring to FIG. 8, a fourth resist pattern (not shown) is formed to expose a region corresponding to the bump 140 of the resultant UBM layer 120 ′, that is, an upper portion of the through silicon via 110. Next, an electroplating process is performed to form pillars 142 'in the exposed areas. The pillars 142 and 142 ′ formed on the first and second surfaces 101 and 102 of the substrate are electrically connected to a semiconductor circuit (not shown) formed on the substrate. In one example, the pillars 142 formed on the first side 101 of the substrate are electrically connected to the pillars 142 ′ formed on the second side through the through silicon vias. In one example, the pillar 142 ′ formed on the second surface of the substrate, like the pillar 142 formed on the first surface, prevents a defect such as bending or breaking due to pressure applied from a chip stacked on the upper side during the stacking. In order to form the cross-sectional area larger than the cross-sectional area of the through-silicon via (110). In some cases, the pillar may be formed on only one of the first and second surfaces of the substrate.

Next, after removing the fourth resist pattern, an auxiliary solder region and an upper surface of the pillar 142 'are opened to form a fifth resist pattern (not shown) that defines a region where a solder layer is to be formed. The electroplating process is performed to form solder layers 150 ′ and 144 ′ in regions exposed by the fifth resist pattern. In this case, before forming the solder layers 150 ′ and 144 ′, a natural oxide film formed on the surfaces of the pillars 142 ′ and the seed layer 124 ′ is removed, and then a solder layer is formed. In one example, the solder layers 150 ′ and 144 ′ may be formed to include any one or more of tin (Sn) and silver (Ag).

Subsequently, the fifth resist pattern is removed and then the exposed UBM layer 120 is removed.

The bump 140 formed on the first surface 101 of the substrate and the bump 140 'formed on the second surface 102 of the substrate are formed at positions corresponding to each other when the substrates are stacked. In addition, the auxiliary bump 150 formed on the first surface 101 of the substrate and the auxiliary solder 150 ′ formed on the second surface 102 of the substrate are formed at positions corresponding to each other when the substrates are stacked.

Referring to FIG. 9, substrates having bumps 140 and 140 ′, auxiliary bumps 150, and auxiliary solders 150 ′ may be diced to form individual semiconductor chips 300 and 301. After mounting the diced semiconductor chip 300 on the package substrate (not shown), the other semiconductor chip 301 is aligned thereon. In this case, the bumps 140 and 140 ′ of the semiconductor chips 300 and 301 that are stacked, the auxiliary bumps 150 of the lower semiconductor chip 300 and the auxiliary solder 150 ′ of the upper semiconductor chip 301 are mutually different. Arrange face to face.

Next, applying pressure to the aligned semiconductor chips causes melting of the solder formed on the tops of the bumps 140 and 140 ', thereby bonding the semiconductor chips 300 and 301 to each other. A part of the auxiliary solder 150 ', which is in contact with the auxiliary bump 150, is partially melted by the pressure to be bonded to each other, and the two semiconductor chips 300 are stacked together with the bonding between the bumps 140 and 140' by the solder. Improve the tightening force between the 301).

In one example, the bonding between the semiconductor chips 300 and 301 is made by melting the solder by applying pressure at room temperature. In another example, bonding is performed between the semiconductor chips 300 and 301 by melting the solder by applying pressure in a temperature range of 100 ° C to 150 ° C.

Subsequently, after the semiconductor chips 300 and 301 are bonded to each other, an under filling material is injected into the space between the two semiconductor chips and sealed. In one example, a material having a high thermal conductivity, such as a ceramic paste, may be used as the underfill material to allow the heat generated in the semiconductor chip to be easily released to the outside.

According to the present invention described above, the process of stacking and bonding semiconductor chips can be performed at low temperatures of 100 ° C to 150 ° C, thereby preventing warpage or breakage of bumps due to high temperatures, thereby improving package reliability. Can be improved.

100: substrate 101: first surface
102: second side 110: through silicon via (TSV)
111: blind via 120, 120 ': UBM layer
122: adhesive layer 124: seed layer
132 and 134: resist patterns 140 and 140 ': bump
142, 142 ': Pillar 144, 144': Solder layer
150: secondary bump 150 ': secondary solder
152, 154: Pillar 160: Adhesive
180: polymer layer 200: carrier substrate
300, 301: semiconductor chip

Claims (25)

A substrate comprising a first side and a second side opposite to each other;
Conductive through vias penetrating the substrate;
A bump disposed on the first surface of the substrate to be electrically connected to the through via;
An auxiliary bump disposed on the first surface of the substrate to be spaced apart from the bump; And
And a second solder on a second surface of the substrate, the auxiliary solder being disposed in a region corresponding to the auxiliary bump. The method of claim 1, wherein the bump,
And a conductive pillar connected to the through via and a solder formed on the conductive pillar. The method of claim 2,
And the conductive pillar has a cross-sectional area larger than that of the through via. The method of claim 2,
The solder is a semiconductor chip, characterized in that made of a material having a lower melting point than the material constituting the conductive pillar. 5. The method of claim 4,
The solder is a semiconductor chip comprising at least one of tin (Sn) and silver (Ag). The method of claim 1,
The auxiliary solder is a semiconductor chip, characterized in that made of a material having a lower melting point than the material constituting the auxiliary bump. The method according to claim 6,
The auxiliary solder comprises at least one of tin (Sn) and silver (Ag). The method of claim 1,
And the auxiliary solder is embedded below the surface of the substrate. The method of claim 1,
And the auxiliary bumps have a cross-sectional area smaller than a size of a region in which the auxiliary solder is formed. The method of claim 1,
And a bump formed on a region corresponding to the bump on the second surface of the substrate. A package substrate;
A plurality of semiconductor chips stacked vertically on the package substrate; And
Is injected into the space between the semiconductor chip comprises a sealing material, The semiconductor chip,
A substrate having a first side and a second side opposite to each other,
Conductive through vias penetrating the substrate;
A bump disposed on the first surface of the substrate to be electrically connected to the through via;
An auxiliary bump disposed on the first surface of the substrate to be spaced apart from the bump, and
And a second solder disposed on a region corresponding to the auxiliary bump on a second surface of the substrate. The method of claim 11, wherein the bump,
And a conductive pillar connected to the through via and a solder formed on an upper portion of the conductive pillar. The method of claim 12,
The solder is a semiconductor package, characterized in that made of a material having a lower melting point than the material constituting the conductive pillar. The method of claim 13,
The solder is a semiconductor package comprising at least one of tin (Sn) and silver (Ag). The method of claim 11,
The auxiliary solder is a semiconductor package, characterized in that made of a material having a lower melting point than the material constituting the auxiliary bump. The method of claim 11,
An auxiliary solder is buried below the surface of the substrate,
And the auxiliary bump is inserted into an area in which the auxiliary solder is formed. The method of claim 11,
And a bump formed in a region corresponding to the bump on the second surface of the substrate, wherein bumps formed on the first and second surfaces are bonded to each other. Forming bumps on the first surface of the semiconductor substrate having through vias formed thereon, the bumps including solder on a surface thereof, and an auxiliary bump spaced apart from the bumps;
Forming an auxiliary solder layer in an area corresponding to the auxiliary bump of the second surface;
Cutting individual semiconductor chips on which bumps, auxiliary bumps, and auxiliary solder layers are formed to form individual semiconductor chips;
Arranging a plurality of semiconductor chips on the package substrate; And
A method of manufacturing a stacked semiconductor package comprising bonding the aligned semiconductor chips. 19. The method of claim 18,
At least one of the solder and the auxiliary solder layer,
The manufacturing method of the stacked semiconductor package, characterized in that formed of a material having a lower melting point than the material constituting the bump or auxiliary bump. 19. The method of claim 18,
The auxiliary solder layer is a buried semiconductor package manufacturing method, characterized in that formed to be buried below the second surface of the semiconductor substrate. 19. The method of claim 18,
Before the step of forming the auxiliary solder layer,
In an area corresponding to the bump of the second surface,
And forming bumps connected to the through vias. 19. The method of claim 18,
In the step of forming the auxiliary bump,
And forming a height of the auxiliary bumps greater than a distance between two semiconductor chips after at least the semiconductor chips are stacked. 19. The method of claim 18,
In arranging semiconductor chips on the package substrate,
And manufacturing the auxiliary bumps and the auxiliary solder layers to face each other. 19. The method of claim 18,
In the bonding of the semiconductor chips,
The method of manufacturing a stacked semiconductor package, characterized in that for the solder of the bump to be melted and bonded by the pressure. 19. The method of claim 18,
Bonding the semiconductor chips,
Method for manufacturing a laminated semiconductor package, characterized in that carried out in a temperature range of 100 ℃ to 150 ℃.

Images