201247093 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之封裝技術，特別 於一種形成雙面電磁遮蔽層之半導體封裝方法。 【先前技術】 按，半導體晶片是一種微小型電子 v令1卞即使經過封 裝之後，仍有可能受到電磁干擾(贿)而導致晶片運算異 常或是電性功能失效，特以晶片的運算頻率越高時越 容易受到干擾。故依已知的傳統作法之其中之一，於其 内密封有晶片的封膠體之外表面覆蓋上一電磁遮蔽層 (或可稱為射頻遮蔽層）。然而，電磁遮蔽層必須有效接 地連接才能發揮良好的遮蔽效果。又，封膠體本身為電 =絕緣材料，僅能利用基板之特殊接地結構與特殊封裝 製程方可達成電磁遮蔽層之接地連接，導致封裝成本的 提南。 美國專利US 7,342,303 B1揭示一種使電磁遮蔽層接 地連接之半導體封裝技術，在封裝製程中需要多道半切 操作基板於切割道尚需要預先製作可被半切之鍍通 孔。第1圖所示者為依該習知方法製得之半導體封裝構 造’包含一具有特殊接地結構與厚度增加之基板單元 11 3 ’在基板單元113之側邊（即超過第2圖中切割道丨丨4) °又有可半切外露之鍍通孔η 7 ’晶片1 2 0設置於基板單 疋Π 3上’可利用銲線〗22電性連接該晶片】2〇至該基 板單元113，再以一封膠體130密封該晶片120。封膠體 201247093 130之表面形成有一導電塗層，作為電磁遮蔽層152。該 基板單元113之下方則設有複數個銲球16〇。如第2圖 所示，在單體化切割之前的封裝過程中，多個基板單元 n3係構成於一基板母片11〇内。在形成該電磁遮蔽層 1 52之前，必須先執行一半切割步驟，其係沿著切割道 114由上方切穿該封膠體13〇直到移除該些鍍通孔^7 之。卩分，所形成的半切溝槽140之深度超過該封膠體 130之厚度，約為整體厚度之三分之二以上並且該基 板母片110之一部份亦被切除，導致該基板母片丨⑺之 承載能力不夠。此外，該基板母片11〇厚度應增加，約 大於該封膠體230之厚度，以提供該些鍍通孔117的足 夠半切外露面積，否則可能造成該㈣通孔11?無法順 利地被該電磁遮蔽層152覆蓋連接。因此，習知的電磁 遮蔽層152為單面覆蓋型態，並且基板母片必須設計特 殊的接地連接結構並須具有能在半切割後提供足夠支撐 強度的厚度。 【發明内容】 有鑒於此，本發明之+ M , 个知/3及王要目的係在於提供一種形成雙 面電磁遮蔽層之半導體封穿方 了哀万法及構造，不需要改變基 板母片的接地連接結構與厚度，並能達到封裝製程中由 +切步驟至單體化切割步驟之過程中有效承載晶片之功 效。 201247093 遮蔽效果。 本發明的目的及解決其技術問題是採用以下技術方 案來實見的。本發明揭示一種形成雙面電磁遮蔽層之半 導體封裝方法’主要步驟如下所述。首先，提供一基板 母片°亥基板母片係具有一上表面與一下表面，該基板 母片係包含複數個基板單元以及複數個在該些基板單元 之間之切割道’該下表面於每一基板單元之角隅處係設 有一接地連接之對位標記。接著’設置複數個晶片於該 二基板單元上。然後，形成一封膠體於該基板母片之該 上表面以連續覆蓋該些基板單元與該些切割道。然後， 由該基板母片之該下表面形成複數個半切溝槽，係沿著 該些切割道而形成並至少貫穿該基板母片。然後，圖案 化形成一第一電磁遮蔽層於該基板母片之該下表面，以 覆蓋連接至該對位標記，並且該第一電磁遮蔽層係更形 成於該些半切溝槽内。然後，沿著該些切割道之位置單 體化切割該封膠體’以使該些基板單元分離為複數個半 導體封裝構造。最後，形成一第二電磁遮蔽層於單離後 半導體封裝構造之封膠體之一頂面與複數個切割側面， 並且該第二電磁遮蔽層更連接至該第一電磁遮蔽層。本 發明另揭示一種由該方法製造得到之半導體封裝構造。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在刚述的半導體封裝方法中’該對位標記係可為三角 形並且只形成於每—基板單元中複數個角隅之其中之 5 201247093 在前述的半導體封裝方法中，該第一電磁遮蔽層係 完全覆蓋該冑位標t己並在該下纟面形成有肖該對位標 相同之一致形狀。 在前述的半導體封裝方法中，該基板母片之該下表 係可設有複數個外接墊，係不被該第—電磁遮蔽層所 蓋，並且在上述圖案化形成該第一電磁遮蔽層之步驟 後與上述單體化切割該封膠體之步驟之前，該方法可 包含：設置複數個銲球於該些外接墊。 在⑴述的半導體封裝方法中，前述單體化切割之封 體切除間隙係可小於剩_座i t & 办六 』於對應+切溝槽之寬度減去該第一 磁遮蔽層之厚度值，r义仅 以保留位在該些半切溝槽之側邊 該第一電磁遮蔽層。 在前述的半導體封裝方法中，該些半切溝槽之深度 可不】於該基板母片之厚度但小於該封膠體之厚度。 由乂上技術方案可以看出，本發明之形成雙面電礤 蔽層之半導體封裝方法乃搂、皮 衣乃忐及構造’具有以下優點與功效 一、可藉由由基板母y > T i r 母片之下表面切入形成之半切溝槽 及雙面形成之第_豳故 _ t Λ 9 ^ 與第二電磁遮蔽層在半切溝槽 連接作為其中9 Τ之一技術手段，並活用基板母片所 有的對位標記，以笙 , 以第一電磁遮蔽層覆蓋之，故不 要改變基板母Η %201247093 VI. Description of the Invention: [Technical Field] The present invention relates to a packaging technology for a semiconductor device, and more particularly to a semiconductor packaging method for forming a double-sided electromagnetic shielding layer. [Prior Art] According to the semiconductor chip, a micro-small electronic device can be subjected to electromagnetic interference (bribet) after being packaged, resulting in abnormal operation of the chip or electrical function failure. The higher the time, the more susceptible it is to interference. Therefore, according to one of the known conventional methods, the surface of the sealant in which the wafer is sealed is covered with an electromagnetic shielding layer (or may be referred to as a radio frequency shielding layer). However, the electromagnetic shielding layer must be effectively grounded to provide a good shielding effect. Moreover, the encapsulant itself is electrically=insulating material, and the grounding connection of the electromagnetic shielding layer can be achieved only by using the special grounding structure of the substrate and the special packaging process, resulting in the cost of packaging. U. 1 is a semiconductor package structure prepared according to the conventional method, including a substrate unit 11 3 having a special ground structure and an increased thickness on the side of the substrate unit 113 (ie, more than the cutting line in FIG. 2)丨丨4) ° There is a plated through hole η 7 ' that is half-cut exposed. The wafer 1 2 0 is disposed on the substrate unit 3, and the wafer can be electrically connected to the substrate unit 113 by using a bonding wire 22 The wafer 120 is then sealed with a gel 130. The surface of the sealant 201247093 130 is formed with a conductive coating as the electromagnetic shielding layer 152. A plurality of solder balls 16 are disposed under the substrate unit 113. As shown in Fig. 2, in the packaging process before the singulation, a plurality of substrate units n3 are formed in a substrate mother substrate 11A. Before the formation of the electromagnetic shielding layer 152, a half-cutting step must be performed, which is cut through the sealing body 13 from above along the cutting path 114 until the plating through holes 7 are removed. The depth of the half-cut trench 140 formed exceeds the thickness of the encapsulant 130 by about two-thirds of the overall thickness and a portion of the substrate mother substrate 110 is also removed, resulting in the substrate master 丨(7) The carrying capacity is insufficient. In addition, the thickness of the substrate mother substrate 11 should be increased to be greater than the thickness of the sealing body 230 to provide a sufficient half-cut exposed area of the plated through holes 117, otherwise the (four) through holes 11 may not be smoothly penetrated by the electromagnetic The shielding layer 152 covers the connection. Therefore, the conventional electromagnetic shielding layer 152 is of a one-sided covering type, and the substrate mother substrate must be designed with a special ground connection structure and must have a thickness capable of providing sufficient supporting strength after half cutting. SUMMARY OF THE INVENTION In view of the above, the invention of the present invention is to provide a semiconductor encapsulation method for forming a double-sided electromagnetic shielding layer, and the structure does not need to be changed. The ground connection structure and thickness, and can achieve the effect of effectively carrying the wafer during the packaging process from the +-cut step to the singulation step. 201247093 Shadow effect. The object of the present invention and solving the technical problems thereof are to be realized by the following technical solutions. The present invention discloses a semiconductor package method for forming a double-sided electromagnetic shielding layer. The main steps are as follows. First, a substrate mother substrate is provided with an upper surface and a lower surface. The substrate master includes a plurality of substrate units and a plurality of dicing streets between the substrate units. An alignment mark of a ground connection is provided at a corner of a substrate unit. Next, a plurality of wafers are placed on the two substrate units. Then, a gel is formed on the upper surface of the substrate to continuously cover the substrate units and the scribe lines. Then, a plurality of half-cut grooves are formed on the lower surface of the substrate mother substrate, and are formed along the scribe lines and penetrate at least through the substrate mother substrate. Then, a first electromagnetic shielding layer is patterned on the lower surface of the substrate mother substrate to cover the alignment mark, and the first electromagnetic shielding layer is further formed in the half-cut trenches. Then, the encapsulants are monolithically cut along the locations of the dicing streets to separate the substrate units into a plurality of semiconductor package configurations. Finally, a second electromagnetic shielding layer is formed on a top surface and a plurality of cutting sides of the encapsulant of the semiconductor package structure, and the second electromagnetic shielding layer is further connected to the first electromagnetic shielding layer. A semiconductor package structure fabricated by the method is also disclosed. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the semiconductor packaging method just described, the alignment mark may be triangular and formed only in a plurality of corners of each substrate unit. 201247093 In the foregoing semiconductor packaging method, the first electromagnetic shielding layer is The target mark is completely covered and a uniform shape having the same alignment mark is formed on the lower jaw surface. In the foregoing semiconductor package method, the lower surface of the substrate mother substrate may be provided with a plurality of external pads which are not covered by the first electromagnetic shielding layer, and patterned to form the first electromagnetic shielding layer. After the step and the step of singulating the encapsulant by the singulation, the method may include: setting a plurality of solder balls to the external pads. In the semiconductor packaging method of (1), the singulation cut gap of the singulation can be smaller than the width of the corresponding + dicing groove minus the thickness of the first magnetic shielding layer. , r is only to retain the first electromagnetic shielding layer on the side of the half-cut trenches. In the foregoing semiconductor packaging method, the depth of the half-cut trenches may not be greater than the thickness of the substrate mother substrate but less than the thickness of the sealant. It can be seen from the above technical solution that the semiconductor encapsulation method for forming a double-sided electric shielding layer of the present invention has the following advantages and effects as the first embodiment, and can be used by the substrate mother y > T ir The half-cut groove formed by the lower surface of the mother piece and the double-sided groove formed by the double-sided surface are connected with the second electromagnetic shielding layer in a half-cut groove as one of the technical means of 9 Τ, and the substrate mother piece is used. All the alignment marks are covered by the first electromagnetic shielding layer, so do not change the substrate mother. %
母片的接地連接結構與厚度，並能造 封裝製程巾tb ik L 由+切步驟至單體化切割步驟之過程 有效承載晶片之功效。 玉 可 記 面 覆 之 另 膠 電 之 係 遮 以 内 具 需 到 中 6 201247093 一、可藉由基板母片之下表面切入形成之半切溝槽以及 雙面形成之第~與第二電磁遮蔽層在半切溝槽内連 接作為其中之一技術手段，能達到較佳的側面電磁 遮蔽效果。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是’該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係’圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種形成雙面電磁遮 蔽層之半導體封裝方法與構造舉例說明於第3八至η圖 各步驟形成元件之截面示意圖，各步驟的詳細說明如下。 首先，如第3A與4圖所示’提供一基板母片21〇, 該基板母片210係具有一上表面211與一下表面2丨2。 該基板母片210係可為一條狀印刷電路板或是條狀軟性 電路板，内有單層或多層之線路結構。該上表面211係 供晶片設置，該下表面2 1 2係為半導體封裝構造之對外 表面接合的表面《該下表面212係可設有複數個矩陣排 列之外接墊216。該基板母片21〇係包含複數個基板單 兀2 1 3以及複數個在該些基板單元2丨3之間之切割道 201247093 214。每一基板單元213係作為—丰導 牛導體封裝構造之晶片 載體’而該些切割道214係為在單體化切割中欲定被移 除之區域。該下表面212於每一基板單元213之角隅處 係設有-接地連接之對位標$ 215。Μ，㉟對位標記 215係用以在表面接合時確定或修正該些外接墊216的 位置。在製造上，該對位標記215是與該些外接墊216 形成在同一線路層。該對位標記215的接地連接係可依 一般基板設計以電鍍線或/與既有在基板單元内的通孔 連接至基板内的接地層或接地墊，並可以在該對位標記 215之表面上形成電鍍層，如鎳/金（圖中未繪出）。較佳 地，如第4圖所示，該對位標記215係可為三角形，並 且只形成於每一基板單元213中四個角隅之其中之一， 即每一基板單元2 1 3只會有一個對位標記2丨5並且位置 固定，便可在 或The ground connection structure and thickness of the mother piece can be used to make the package process tb ik L effectively carry the wafer during the process from the + cutting step to the singulation cutting step. The jade can be covered by another layer of glue. The inner part of the cover is required. 6 201247093 1. The half-cut groove formed by the lower surface of the substrate mother substrate and the second and second electromagnetic shielding layers formed on both sides are The half-groove inner connection is one of the technical means to achieve a better side electromagnetic shielding effect. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, in which Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to a first embodiment of the present invention, a semiconductor package method and structure for forming a double-sided electromagnetic shielding layer are schematically illustrated in a cross-sectional view of elements formed in steps 3 to η, and the detailed description of each step is as follows. First, as shown in Figs. 3A and 4, a substrate mother substrate 210 is provided which has an upper surface 211 and a lower surface 2丨2. The substrate mother substrate 210 can be a strip-shaped printed circuit board or a strip-shaped flexible circuit board having a single-layer or multi-layered line structure. The upper surface 211 is provided for a wafer, and the lower surface 221 is a surface to which the outer surface of the semiconductor package structure is bonded. The lower surface 212 may be provided with a plurality of matrix array pads 216. The substrate mother substrate 21 includes a plurality of substrate 兀2 1 3 and a plurality of dicing streets 201247093 214 between the substrate units 2丨3. Each of the substrate units 213 serves as a wafer carrier for the bovine conductor package construction and the dicing streets 214 are regions to be removed during the singulation. The lower surface 212 is provided at the corner of each of the substrate units 213 with a pair of ground contacts $215. Μ, 35 alignment mark 215 is used to determine or correct the position of the outer pads 216 when the surface is joined. In manufacturing, the alignment mark 215 is formed in the same circuit layer as the external pads 216. The ground connection of the alignment mark 215 can be connected to the ground layer or the ground pad in the substrate by a plating line or/and a via hole existing in the substrate unit according to a general substrate design, and can be on the surface of the alignment mark 215. A plating layer such as nickel/gold (not shown) is formed thereon. Preferably, as shown in FIG. 4, the alignment mark 215 is triangular, and is formed only in one of the four corners of each substrate unit 213, that is, each substrate unit 2 1 3 There is a registration mark 2丨5 and the position is fixed, you can
(Pin 1)的對位用途’可用以確定該些外接塾216(或對外 端子）的排列順序以及表面接合的方向。 接著，執行一晶片設置步驟。如第3B圖所示，設置 複數個晶片220於該些基板單元213上。可利用既有的 黏晶材料黏著該些晶片220之背面至該基板母片2 1 0之 該上表面211。本實施例中該些晶片220與該些基板單 元2 1 3之間的電性連接係為打線連接，在晶片設置步驟 之後’可利用打線形成之複數個銲線222連接該些晶片 220在其主動面之銲墊221至該些基板單元213上之接 指。在不同變化實施例中，晶片與基板單元之間的電性 201247093 連接亦可為覆晶連接或是矽通孔的導電柱連接，在晶片 S史置步驟之過程中’利用該些晶片220之凸塊或導電枝 結合至該些基板單元2丨3上之接墊。此外，該些晶片22〇 係為由一半導體晶圓切割出之晶粒，内有各式積體電路 或光主動元件，例如特殊應用積體電路（ASIC)、記憶體、 或邏輯元件。此外，每一基板單元213上不限於設置_ 個晶片，亦可設置更多相同或不同功能' 尺寸的晶片， 以達到多晶片封裝或是系統封裝。 然後，執行一封膠步驟。如第3C圖所示，形成一封 膠體230於該基板母片210之該上表面211，以連續覆 蓋該些基板單元213與該些切割道214。當該封膠體23 〇 係為模封形成，例如轉移模注或是壓縮模封，該封膠步 驟即為模封陣列製程（Mold Array Process, MAP)。而該 封膠體230之材質係可為包含無機填充材與色料之電絕 緣性熱固性樹脂，可供模封形成之封膠體一般係為環氧 模封化合物（Epoxy Molding Compound，EMC)。由模封形 成之封膠體230相對於印刷或其它方式會具有一平坦度 較高之頂面231。 然後，待該封膠體2 3 0成型之後’執行一半切割步 驟’其切割深度可不超過該封膠體230與該基板母片210 之厚度總合之二分之一。如3D圖所示，利用一切割刀 具271’由該基板母片210之該下表面212形成複數個 半切溝槽240，係沿著該些切割道2 1 4而形成並至少貫 穿該基板母片21〇。該些半切溝槽240之深度係可不小 201247093 於該基板母片210之厚度但小於該封膠體230之厚度， 約為該封膠體230與該基板母片210之厚度總合之二分 之或更夕，故在上述半切步驟之後至單體化切割之 刖該二aa片220仍以該封膠體23〇密封一起而不散離。 此外，半切步驟中形成之該些半切溝槽24〇之寬度w係 應大於該些切割道2 1 4之寬度。 …丨後如第3E與3F圖所示，圖案化形成一第一電 磁遮蔽層251於該基板母片21〇之該下表面212，以覆 蓋連接至該對位標記215，並且該第一電磁遮蔽層251 係更形成於該些半切溝槽24〇内。如第3e圖所示，可先 利用光阻層280形成於該下表面212並經曝光顯影之 後覆蓋該下表面212之該些外接墊216但顯露出該對位 標記215,或是以一遮罩直接覆蓋住該些外接墊216，使 得-又於該基板母片210之該下表面212之該些外接墊 216係不被該第一電磁遮蔽層251所覆蓋。之後，如第 3F圖所示，在該光阻層28〇或遮罩之界定下該第一電 磁遮蔽層251圖案化形成，之後再移除該光阻層2⑽戋 遮罩。該第一電磁遮蔽層25 1之材質可為抗射頻干擾之 金屬’該第一電磁遮蔽層251之形成方法可利用賤纪、 蒸鍵、化學鑛、物理氣相沉積、印刷或喷喹望 主寻方式。而 該第一電磁遮蔽層251係可更延伸覆蓋至該些半切溝槽 240之側邊241，以避免該些基板單&213^玄心層外^ 並增進側向的電磁遮蔽效果。 較佳地’如第6圖所示，該第一電磁遮蔽層251< 10 201247093 與該 215 完全覆蓋該對位標記215並在該下表面2i2形成有 對位標記215相同之一致形狀’以保留該對位標記 的對位效果。 在本實施例中，在上述圖案化形成該第一電磁遮蔽層 川之步驟之後與單體化切割步驟之前，該方法可另包 含-植球步驟。如第3G圖所示，設置複數個銲球26〇 於該些外接墊216。可利用球放置加上回焊的方式或是 銲料印刷與回焊的方式使該些銲球26〇結合在該些外接 塾2U上。該些銲球26〇係作為半導體封裝構造表面接 合時之外接端子。 -然後，執行一單體化切割步驟。如第3〇與扭圖所 不，利用-切割刀具272，其切割寬度小於前述切割刀 具之切割寬度而約等於該些切割道2"之寬度。沿著該 些切割道214 <位置單體化切割該封膠冑23〇，以使該 些基板單元213分離為複數個半導體封裝構造。較佳 地’比對第3H、3E與3F圖，前述單體化切割之封膠體 切除間隙s係可小於對應半切溝槽24〇之寬度w減去該 第一電磁遮蔽層251之厚度τ之值，以保留位在該些半 切溝槽240之側邊241之該第一電磁遮蔽層25ι。在本 步驟中，切單後的封膠體230具有複數個切割側面M2。 最後，如第31圖所示，形成一第二電磁遮蔽層252 於單離後半導體封裝構造之封膠體23〇之該頂面23丨與 該些切割側面232，並且該第二電磁遮蔽層252更連接 至該第一電磁遮蔽層251於該些半切溝槽24〇之側邊 201247093 24卜該第二電磁遮蔽層252之材質與形成方法係可與前 述的該第-電磁遮蔽層251之材質與形成方法相同。因 此，該第二電磁遮蔽層252經由該第一電磁遮蔽層 連接至該對位標記2丨5，藉以達到接地連接。該第一電 磁遮蔽層251與該第二電磁遮蔽層252之組合能提供該 些晶片220更好的電磁遮蔽效果。該基板母片21〇的接 地連接結構與厚度不需要作特別的設計或改變，並且在 封裝製程中由第3D圖的半切步驟至第3H圖的單體化切 割步驟之過程中該封膠體23〇仍能夠有效承載晶片。 如第5與6圖所示，為依上述半導體封裝方法製造得 到之半導體封裝構造，主要包含該基板單元213、該晶 片220、該封膠體23〇、該第一電磁遮蔽層251以及該第 二電磁遮蔽層252。該晶片220設置於該基板單元213 上。該封膠體230係形成於該基板母片21〇之該上表面 211，以覆蓋該基板單元213,其中由該下表面212之側 邊形成有該些半切溝槽之側彡241。肖第一電磁遮蔽層 251係圖案化形成於該下表面212,以覆蓋連接至該對位 標記215’並且該第-電磁遮蔽# 251係更形成於該些 半切溝槽之側邊241。該帛三電磁遮蔽層252係形成於 該封膠體230之該頂面231與該些切割側面232，並且 該第二電磁遮蔽層252更連接至該第一電磁遮蔽層 2^卜較佳地，該第一電磁遮蔽層251係完全覆蓋該對位 標記215並在該下表面212形成有與該對位標記川相 同之-致形狀。因此’該半導體封裝構造具有較佳的側 12 201247093 面電磁遮蔽效果。 在本發明之第二具體實施例中，揭示另一種形成雙面 電磁遮蔽層之半導體封裝構造，以第一具體實施例中相 同步驟的封裝方法製造而得。如第7圖所示，該半導體 封裝構造主要包含一基板單元213、一晶片22〇、一封膠 體23 0、一第一電磁遮蔽層251以及一第二電磁遮蔽層 252。主要元件大體與第一具體實施例相同相同圖號的 疋件不再詳細贅述》較佳地，該第二電磁遮蔽層252亦 L伸覆蓋至該第一電磁遮蔽層251位在該些半切溝槽之 側邊24 1之部位，以達到較佳連接與保護效果。藉此， 該第一電磁遮蔽層251可以不必考慮電磁遮蔽效果，可 以選用與該第一電磁遮蔽層252不相同的更便宜金屬。 在本實施例中，該第一電磁遮蔽層25丨在該下表面 212的圖案化形成區域除了覆蓋該對位標記215，更可覆 蓋該基板單元213在該下表面212之不具有對位標記之 其餘角隅，即該基板單元213在該下表面212之所有角 隅皆被該第一電磁遮蔽層25丨所覆蓋，而該第一電磁遮 蔽層25 1覆蓋在無對位標記角隅之形狀係可不相同於覆 蓋在有對位標記角隅之形狀’例如方形或圓形相對於在 對位標記上之三角形。如此，除了會有較佳的電磁遮蔽 效果；並且，在表面接合時，設於該下表面212之銲球 260接合至一外部印刷電路板31〇之球墊311，利用角隅 鲜料320亦可接合該第一電磁遮蔽層25 i至該外部印刷 電路板3 10之接地墊3 12或虛置墊，便可使該對位標記 13 201247093 2 1 5為接地連接並且提供更多接地連接至該外部印刷電 路板310之路徑，並且能夠分散該些銲球26〇承受的應 力’以達到更穩固的表面接合。 以上所述，僅是本發明的較佳實施例而已，並非對本 j作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上’然而並非用以限定本發明，任何熟悉本項技 参 在不脫離本發明之技術範圍内，所作的任何簡單 ^文等則生變化與修飾，均仍屬於本發明的技術範圍 【圖式簡單說明】 第 第 第 圖.習知電磁遮蔽層接地連接至基板半切割邊緣之 半導體封裝構造之截面示意圖。 第2圖：羽a 士隹 D +導體封裝構造在半切割之後與單離切割 第3 之前的製程中截面示意圖。 至31圖.依據本發明之第一具體實施例，繪示一 種升> 成雙面電磁遮蔽層之半導體封裝過程中各 4 步驟形成元件之截面示意圖。 依據本發明之第一具體實施例的該半導體封裝 5胃：方法所使用基板母片之下表面示意圖。 依據本發明之第—具體實施例的該半導體封裝 方去所製造得到之—半導體封裝構造之截面示The alignment use of (Pin 1) can be used to determine the order in which the external ports 216 (or external terminals) are arranged and the direction in which the surfaces are joined. Next, a wafer setting step is performed. As shown in Fig. 3B, a plurality of wafers 220 are disposed on the substrate units 213. The back surface of the wafer 220 may be adhered to the upper surface 211 of the substrate mother substrate 210 using an existing die bonding material. In this embodiment, the electrical connection between the wafers 220 and the substrate units 21 is a wire bonding. After the wafer setting step, a plurality of bonding wires 222 formed by wire bonding are connected to the wafers 220. The pads 221 of the active surface are connected to the substrates 213. In different variant embodiments, the electrical 201247093 connection between the wafer and the substrate unit may also be a flip-chip connection or a conductive pillar connection of the via via, which is utilized during the wafer S history step. A bump or a conductive branch is bonded to the pads on the substrate units 2丨3. In addition, the wafers 22 are diced by a semiconductor wafer having various integrated circuits or optical active components such as special application integrated circuits (ASICs), memories, or logic elements. In addition, each substrate unit 213 is not limited to _ one wafer, and more wafers of the same or different functional size may be disposed to achieve multi-chip packaging or system packaging. Then, perform a glue step. As shown in FIG. 3C, a colloid 230 is formed on the upper surface 211 of the substrate mother substrate 210 to continuously cover the substrate unit 213 and the dicing streets 214. When the encapsulant 23 is formed by molding, such as transfer molding or compression molding, the encapsulation step is a Mold Array Process (MAP). The material of the encapsulant 230 may be an electrically insulating thermosetting resin containing an inorganic filler and a colorant. The encapsulant formed by the molding is generally an epoxy resin compound (EMC). The encapsulant 230 formed by the molding will have a higher flat top surface 231 relative to printing or other means. Then, after the encapsulant 210 is formed, the "cutting half cutting step" may be performed to a depth not exceeding one-half of the total thickness of the encapsulant 230 and the substrate mother substrate 210. As shown in FIG. 3D, a plurality of half-cut trenches 240 are formed by the lower surface 212 of the substrate mother substrate 210 by a cutting tool 271', and are formed along the scribe lines 214 and penetrate at least through the substrate master. 21〇. The depth of the half-cut trenches 240 may be not less than the thickness of the substrate mother substrate 210 but less than the thickness of the sealant 230, which is about two or more of the thickness of the sealant 230 and the substrate mother substrate 210. In the evening, the two aa sheets 220 are still sealed together with the sealant 23 without being dispersed after the above-described half-cutting step to the singulation. In addition, the width w of the half-cut grooves 24 formed in the half-cut step should be greater than the width of the scribe lines 2 14 . a third electromagnetic shielding layer 251 is patterned on the lower surface 212 of the substrate mother substrate 21 to cover the connection to the alignment mark 215, and the first electromagnetic A shielding layer 251 is formed in the half-cut trenches 24A. As shown in FIG. 3e, the photoresist layer 280 may be formed on the lower surface 212 and exposed to the external pads 216 of the lower surface 212 after exposure and development, but the alignment mark 215 is exposed, or is covered by a mask. The cover directly covers the external pads 216 such that the external pads 216 of the lower surface 212 of the substrate mother substrate 210 are not covered by the first electromagnetic shielding layer 251. Thereafter, as shown in Fig. 3F, the first electromagnetic shielding layer 251 is patterned under the definition of the photoresist layer 28 or the mask, and then the photoresist layer 2 (10) 遮 mask is removed. The material of the first electromagnetic shielding layer 25 1 may be a metal that is resistant to radio frequency interference. The method for forming the first electromagnetic shielding layer 251 may utilize a dynasty, a steaming bond, a chemical ore, a physical vapor deposition, a printing or a smouldering. Find the way. The first electromagnetic shielding layer 251 can extend to cover the side edges 241 of the half-cut trenches 240 to avoid the substrate single layer and to enhance the lateral electromagnetic shielding effect. Preferably, as shown in FIG. 6, the first electromagnetic shielding layer 251 < 10 201247093 completely overlaps the alignment mark 215 with the 215 and forms the same uniform shape of the alignment mark 215 on the lower surface 2i2 to retain The alignment effect of the alignment mark. In this embodiment, the method may additionally include a ball implantation step after the step of patterning the first electromagnetic shielding layer and before the singulation cutting step. As shown in Fig. 3G, a plurality of solder balls 26 are disposed on the external pads 216. The solder balls 26 can be bonded to the external ports 2U by means of ball placement plus reflow or solder printing and reflow. The solder balls 26 are external terminals when the surface of the semiconductor package structure is bonded. - Then, a singulation cutting step is performed. As with the third and twisting diagrams, the cutting cutter 272 has a cutting width that is less than the cutting width of the cutting tool and is approximately equal to the width of the cutting lanes 2". The sealant 23 is singulated along the dicing streets 214 < locating locations to separate the substrate units 213 into a plurality of semiconductor package configurations. Preferably, the third embodiment of the third electromagnetic shielding layer 251 is smaller than the width w of the corresponding semi-cutting groove 24, minus the thickness of the first electromagnetic shielding layer 251. a value to retain the first electromagnetic shielding layer 25ι located at the side 241 of the half-cut trenches 240. In this step, the singulated sealant 230 has a plurality of cut side faces M2. Finally, as shown in FIG. 31, a second electromagnetic shielding layer 252 is formed on the top surface 23 of the encapsulant 23 of the semiconductor package structure and the cut side 232, and the second electromagnetic shielding layer 252 is formed. Further connected to the side of the first electromagnetic shielding layer 251 on the side of the half-cut trench 24, 201247093, the material and formation method of the second electromagnetic shielding layer 252 and the material of the first electromagnetic shielding layer 251 Same as the formation method. Therefore, the second electromagnetic shielding layer 252 is connected to the alignment mark 2丨5 via the first electromagnetic shielding layer, thereby achieving a ground connection. The combination of the first electromagnetic shielding layer 251 and the second electromagnetic shielding layer 252 can provide better electromagnetic shielding of the wafers 220. The ground connection structure and thickness of the substrate mother substrate 21〇 need not be specially designed or changed, and the encapsulant 23 is in the packaging process from the half-cut step of the 3D drawing to the singulation cutting step of the 3H drawing. The crucible is still able to carry the wafer efficiently. As shown in FIGS. 5 and 6, the semiconductor package structure manufactured by the above semiconductor package method mainly includes the substrate unit 213, the wafer 220, the sealant 23, the first electromagnetic shielding layer 251, and the second Electromagnetic shielding layer 252. The wafer 220 is disposed on the substrate unit 213. The encapsulant 230 is formed on the upper surface 211 of the substrate mother substrate 21 to cover the substrate unit 213, wherein the side 彡241 of the half-cut trench is formed by the side of the lower surface 212. A first electromagnetic shielding layer 251 is patterned on the lower surface 212 to cover the connection to the alignment mark 215' and the first electromagnetic shielding #251 is formed on the side 241 of the half-cut trench. The third electromagnetic shielding layer 252 is formed on the top surface 231 of the encapsulant 230 and the cutting side 232, and the second electromagnetic shielding layer 252 is further connected to the first electromagnetic shielding layer. The first electromagnetic shielding layer 251 completely covers the alignment mark 215 and is formed on the lower surface 212 in the same shape as the alignment mark. Therefore, the semiconductor package structure has a better side 12 201247093 surface electromagnetic shielding effect. In a second embodiment of the present invention, another semiconductor package construction for forming a double-sided electromagnetic shielding layer is disclosed, which is fabricated by the same method of packaging in the first embodiment. As shown in FIG. 7, the semiconductor package structure mainly includes a substrate unit 213, a wafer 22, a glue 203, a first electromagnetic shielding layer 251, and a second electromagnetic shielding layer 252. The main components are substantially the same as those of the first embodiment. The components of the same figure are not described in detail. Preferably, the second electromagnetic shielding layer 252 is also extended to cover the first electromagnetic shielding layer 251. The side of the side of the groove 24 1 to achieve a better connection and protection. Thereby, the first electromagnetic shielding layer 251 can be used without regard to the electromagnetic shielding effect, and a cheaper metal different from the first electromagnetic shielding layer 252 can be selected. In this embodiment, the patterned formation region of the first electromagnetic shielding layer 25 in the lower surface 212 not only covers the alignment mark 215, but also covers the substrate unit 213 without the alignment mark on the lower surface 212. The remaining corners, that is, all corners of the lower surface 212 of the substrate unit 213 are covered by the first electromagnetic shielding layer 25, and the first electromagnetic shielding layer 25 1 is covered by the alignment mark The shape system may be different from the shape that covers the shape of the alignment mark 隅, such as a square or a circle relative to the triangle on the alignment mark. In this way, in addition to the better electromagnetic shielding effect, and when the surface is bonded, the solder balls 260 disposed on the lower surface 212 are bonded to the ball pad 311 of an external printed circuit board 31, and the corner slab 320 is also used. The first electromagnetic shielding layer 25 i can be bonded to the ground pad 3 12 or the dummy pad of the external printed circuit board 3 10 to make the alignment mark 13 201247093 2 1 5 a ground connection and provide more ground connections to The outer printed circuit board 310 is routed and is capable of dispersing the stresses experienced by the solder balls 26 to achieve a more stable surface bond. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, however, it is not intended to limit the invention. Any changes and modifications made by the present invention without departing from the technical scope of the present invention are still within the technical scope of the present invention. [Simplified description of the drawings] Fig. 1 is a schematic connection of a conventional electromagnetic shielding layer. A schematic cross-sectional view of a semiconductor package structure to a half-cut edge of a substrate. Figure 2: Schematic diagram of the plume d + conductor package construction after half-cutting and single-cutting before the third process. FIG. 31 is a cross-sectional view showing the steps of forming a component in a semiconductor package process of a double-sided electromagnetic shielding layer according to a first embodiment of the present invention. The semiconductor package 5 according to the first embodiment of the present invention is a schematic view of the lower surface of the substrate used in the method. According to the semiconductor package of the first embodiment of the present invention, a cross-section of the semiconductor package structure is obtained.
意圖D 第6圖·第S圖之半導體封 第7圖：依據本發明之第二 裝構造之立體示意圖。 具體實施例的另一種半導體 14 201247093 封裝構造在表面接合至一外部印刷電路板之截 面示意圖。 【主要元件符號說明】 11 0基板母片 11 3基板單元 11 4切割道 11 7鍍通孔 120 晶片 1 3 0封膠體 140半切溝槽 1 52 電磁遮蔽層 160銲球 2 1 0基板母片 2 1 3基板單元 2 1 6 外接墊 220 晶片 230封膠體 240半切溝槽 251第一電磁遮 252 第二電磁遮 260銲球 2 8 0光阻層 3 10 外部印刷電 122銲線 1 3 1 頂面 1 4 1側邊 21 1 上表面 2 1 4切割道 221 銲墊 231 頂面 241側邊 蔽層 蔽層 271 切割刀具 路板 1 3 2 切割側面 212 下表面 2 1 5 對位標記 222銲線 232切割側面 272切割刀具 3 1 1 球墊 312接地墊 320 角隅銲料 S封膠體切除間隙 W半切溝槽之寬度 T第一電磁遮蔽層之厚度 15Intention D Fig. 6 and Fig. S is a semiconductor package Fig. 7 is a perspective view showing a second structure according to the present invention. Another semiconductor of a specific embodiment 14 201247093 A schematic cross-sectional view of a package construction bonded to an external printed circuit board. [Major component symbol description] 11 0 substrate master 11 3 substrate unit 11 4 scribe line 11 7 plated through hole 120 wafer 1 3 0 sealant 140 half-cut groove 1 52 electromagnetic shielding layer 160 solder ball 2 1 0 substrate mother 2 1 3 substrate unit 2 1 6 external pad 220 wafer 230 encapsulant 240 half-cut trench 251 first electromagnetic shielding 252 second electromagnetic shielding 260 solder ball 2 8 0 photoresist layer 3 10 external printing electricity 122 bonding wire 1 3 1 top surface 1 4 1 Side 21 1 Upper surface 2 1 4 Cutting path 221 Pad 231 Top surface 241 Side masking layer 271 Cutting tool board 1 3 2 Cutting side 212 Lower surface 2 1 5 Alignment mark 222 Bonding wire 232 Cutting side 272 cutting tool 3 1 1 ball pad 312 grounding pad 320 corner 隅 solder S sealing body cutting gap W width of half-cut groove T thickness of first electromagnetic shielding layer 15