201117327 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種免用 凸塊之覆晶封裝構造及其中介板。 【先前技術】 在早期的半導體封裝構造中，不同的元件有不同的個 別作用’例如銲線具有電性連接晶片與基板之作用，黏 B曰材料只有固定晶片與基板的黏著作用。一種習知打線 連接之半導體封裝構造如第〖圖所示，一晶片11〇係藉 由一黏晶材料130固定在一基板12〇上，黏晶材料13〇 黏附該晶片110之背面與該基板12〇之上表面m，通 常疋選用日日粒貼附膜（Die Attached Film，DAF)，可同晶 片尺寸並預先貼附至該晶片11〇’以防止污染到該基板 120上的連接墊122。打線形成之銲線150電性連接在該 晶片110之主動面111上的銲墊112與該連接墊122。 另以一,封膠體140密封該晶片11〇與該些銲線15〇。由 於該些銲線150有一線弧高度，無法降低封裝厚度。又， 該些連接墊122設於該基板120用以黏附該晶片11〇之 區域之外，無法降低封裝構造之底面積（footprint)。故整 體封裝構造之尺寸無法進一步微小化，不符合先進封裝 技術之要求。 一種習知的先進封裝技術係採用晶片上有凸塊之覆 晶接合，以縮小封裝尺寸。在第2圖中一種習知使用凸 塊之覆晶封裝構造200的放大倍數是大於第1圖的放大 201117327 倍數，當晶片210與晶片11〇的尺寸相同時，第2圖的 覆晶封裝構造2G0的厚度與底面積將比第i圖的半導體 封裝構故100的厚度與底面積更薄與更小。如第2圖所 不，將晶片210之主動面211翻覆以接合至基板22〇。 在晶片210之主動面211上必須設置複數個凸塊216， 例如錫船鲜球或是金凸塊，作為尺寸增加的晶片突出端 點。為避免ώ塊間短路與凸塊位移之電性連接失敗該 • 些凸塊216之間距應大於晶片210之銲墊212之間距， 方可接合至基板220在其上表面221之連接墊222。因 此，晶片210之主動面211除了形成有顯露銲墊212之 絕緣性第一保護層213,還會形成有至少一層的重配置 線路層（redistribution layer)214與至少一層的第二保護 層2 1 5，以保s蔓重配置線路層2丨4。以上的重配置線路層 214與第二保護層215皆是以半導體製程予以製造。因 此，晶片210的成本遠高於裸晶粒。此外，在覆晶接合 之後，晶片21 0與基板22〇之間會留下—微小的覆晶空 隙，這會造成封膠體240的模流填入的困難以及應力集 中在特定凸塊，特別是位在晶片角隅的凸塊，故尚需要 .填入一底部填充膠23〇。利用底部填充膠23〇的高流動 性產生毛細作用，以填滿覆晶空隙。然，這會增加封裝 製程步驟與複雜度，導致產出率降低。 本國專利公告編號423 132揭示一種「無凸塊型覆晶 構裝與製程方法」’使用具有複數個導電凸墊座之單（多） 層結構的連結層來取代凸塊與底部填充膠，此具導電凸 201117327 墊座結構之連接岸主 s為耐熱型、低熱膨脹係數 性及彈性結構之敕暂带双見具黏著特 的。該連接層的11 絕緣高分子聚合物材料所組配 電性絕緣高分子聚^ 為具黏著特性之同質或異質 σ物’對晶片和基板均有相洛鋥磨沾 接著強度。將晶片、、击从口 J啕相田程度的 連接層與基板組合為 運用埶壓劁恝妯化 口結構’ :壓製程技術，達到電性導通的接。 連接層的金屬連結 …、而 電性絕緣封料承栽主物矣成於連接層的核心層(即 ^ a λ 體）的表面，為浮凸的型態，隨即覆 以黏著層（即接著劑 a 嗯即稷 π * 在由核心層與金屬連結層構成之凹201117327 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a flip chip package structure free of bumps and an interposer thereof. [Prior Art] In the early semiconductor package construction, different components have different roles. For example, the bonding wires have the function of electrically connecting the wafer to the substrate, and the bonding material has only the adhesion of the fixed wafer to the substrate. A semiconductor package structure of a conventional wire bonding connection is as shown in the figure, a wafer 11 is fixed on a substrate 12 by a die bonding material 130, and the die bonding material 13 is adhered to the back surface of the wafer 110 and the substrate. The upper surface m of the upper surface of the crucible is generally selected from the surface of the wafer and is pre-attached to the wafer 11' to prevent contamination of the connection pad 122 on the substrate 120. . The wire 150 formed by the wire is electrically connected to the pad 112 on the active surface 111 of the wafer 110 and the connection pad 122. In addition, the encapsulant 140 seals the wafer 11 and the bonding wires 15A. Since the bonding wires 150 have a line arc height, the package thickness cannot be reduced. Moreover, the connection pads 122 are disposed outside the region where the substrate 120 is adhered to the wafer 11 and cannot reduce the footprint of the package structure. Therefore, the size of the overall package structure cannot be further miniaturized and does not meet the requirements of advanced packaging technology. One conventional advanced packaging technique employs a bump bond with a bump on the wafer to reduce package size. In FIG. 2, the magnification of a conventional flip chip package structure 200 using bumps is greater than the magnification of 201117327 of FIG. 1, and when the wafer 210 and the wafer 11 are the same size, the flip chip package structure of FIG. The thickness and bottom area of 2G0 will be thinner and smaller than the thickness and bottom area of the semiconductor package structure 100 of FIG. As shown in Fig. 2, the active surface 211 of the wafer 210 is flipped over to bond to the substrate 22A. A plurality of bumps 216, such as tin boat balls or gold bumps, must be provided on the active surface 211 of the wafer 210 as the wafer protruding end points of increased size. In order to avoid the failure of the electrical connection between the inter-strip short circuit and the bump displacement, the bumps 216 should be spaced apart from the pads 212 of the wafer 210 to be bonded to the connection pads 222 of the substrate 220 on the upper surface 221. Therefore, the active surface 211 of the wafer 210 is formed with an insulating first protective layer 213 exposing the solder pads 212, and at least one re-distribution layer 214 and at least one second protective layer 2 1 are formed. 5, to ensure that the circuit layer 2丨4. The above reconfiguration circuit layer 214 and the second protection layer 215 are both manufactured by a semiconductor process. Therefore, the cost of the wafer 210 is much higher than that of the bare die. In addition, after the flip chip bonding, a slight crystal-clearing void is left between the wafer 20 0 and the substrate 22 , which causes difficulty in filling the mold flow of the sealing body 240 and stress concentration on a specific bump, particularly a bit. At the corner of the wafer, it is still necessary to fill in an underfill 23 〇. The high fluidity of the underfill 23 产生 produces a capillary action to fill the flip gap. However, this increases the packaging process steps and complexity, resulting in a lower yield. National Patent Publication No. 423 132 discloses a "bumpless flip chip mounting and processing method" 'replaces bumps and underfills using a tie layer having a single (multiple) layer structure with a plurality of conductive bump pads, The conductive land of the 201117327 pedestal structure is a heat-resistant type, a low thermal expansion coefficient and an elastic structure. The electrically insulating polymer of the 11 insulating polymer material of the connecting layer is a homogenous or heterogeneous σ substance having adhesive properties, and the wafer and the substrate are both etched and then with strength. The wafer, the connection layer and the substrate which are struck from the mouth are combined with the substrate to be used to form a conductive structure. The metal bond of the connection layer, and the electrically insulating sealing material host material is formed on the surface of the core layer of the connection layer (ie, the ^ a λ body), which is in an embossed shape, and then is covered with an adhesive layer (ie, Agent a 稷 稷 π * in the concave layer composed of the core layer and the metal connecting layer
凸表面，而使金属坫耳俾取心U 表面的黏著層厚度：=嵌埋於勘著層，故形成在凹凸 容易發生晶片主動二二於：屬連結層的厚度，否則 險。因此，連接層的厚V 金屬連結層的短路風 覆晶封裝構造度將Α於既有的覆晶空隙，此一 明、、Λ社M M a 度亦無法有效降低。此外，在三 連接層的導電凸執t J町邾W日日月興基板， 不易準確對準至晶片之銲塾。 【發明内容】 受 為了解決上述之Η % 免用十番本發明之主要目的係在於一種 曰構1^及其中介板，取代習知凸塊與 日曰片上重配置線路層、 ^ ^ ^ ^ 取代I知黏晶材料、取代習知底 4填充膠與間隔維 致薄化的厘择、物並使中介板之表面黏著層有- 路的風險，並進一步nr層與晶片主動面短 ,步降低封裝厚度與晶片成本。 本發明之次—曰 的係在於提供一種免用凸塊之覆晶 r f- 201117327 封裝構造及其中介板’中介板可以達到先貼附於晶片主 動面、再貼附至基板' 後經一次迴焊之功效，避免習知 以二明治結構熱壓造成對不準晶片銲墊之問題。 本發明之再一目的係在於提供一種免用凸塊之覆晶 封裝構&及其中介板，該中介板具有結構補強之作用， 可先將貼附至晶片再作晶圓薄化，以避免在薄化時晶片 的碎裂。 • 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種免用凸塊之覆晶封裝構 化’主要包含-晶片、一基板以及一中介板。該晶片係 具有複數個在-主動面上之銲墊。該基板係具有一上表 面以及複數個在該上表面之連接塾，其中該些連接塾之 間距係大於該些輝墊之間距。該中介板設置於該晶片與 該基板之間’用以電性連接該晶片與該基板黏著讀晶 鲁片以及填充與維持在該晶片與該基板之間的間隙，該中 介板係.包含-具有導通孔之核心層、—在該核心層上之 第一圖案化金屬層、—與該第-圖案化金屬層同層之一 第一絕緣層…在該第_絕緣層與該第—圖案化金屬層 上之第-黏著層、-在該核心層下之第二圖案化金屬 層、-與該第二圖案化金屬層同層之一第二絕緣層、一 在該第二絕緣層與該第二圖案化金屬層下之第二黏著 層其中該帛冑案化金屬層與該第二圖案化金屬層係 藉由該些導通孔相互電性連接’該第—絕緣層與該第二 絕緣層之設置係避免該第—圖案化金屬層與該第二圖案 201117327 化金屬層突出地嵌入對應之該 層。装击 黏著層與該第二黏著 層其中，該第一黏著層係黏附至 者 並使該第一圄垒几八& 月之該主動面’ 二圖案化金屬層電性連接該晶片之該些輝墊， ^第一黏著層係黏附至該基板 圖案化金屬層電性連接職板之;表面，並使該第二 揭不該覆晶封裝構造之中介板。 月另 本發明的目的及解決装#&The convex surface, and the thickness of the adhesive layer on the surface of the metal 坫 俾 俾 : : : : = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Therefore, the short-circuited air-clad encapsulation structure of the thick V metal-bonding layer of the connection layer will be inconsistent with the existing flip-chip voids, and the M M a degree of the invention cannot be effectively reduced. In addition, in the three-connected layer of conductive convex t-machi, it is difficult to accurately align to the solder bump of the wafer. SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the main purpose of the present invention is to construct a structure 1^ and its interposer, instead of the conventional bump and the re-distribution circuit layer on the solar array, ^ ^ ^ ^ Substituting I for the viscous material, replacing the thinning of the underfill 4 and the spacer dimension, and the risk of the surface adhesion layer of the interposer, and further the nr layer and the active surface of the wafer are short. Reduce package thickness and wafer cost. The sub-system of the present invention is to provide a flip-chip-free flip-chip r f-201117327 package structure and its interposer 'interposer can be attached to the active surface of the wafer first, and then attached to the substrate' The effect of reflow is to avoid the problem of not being able to solder the pad by the hot pressing of the second Meiji structure. A further object of the present invention is to provide a flip-chip package and an interposer free of bumps, which have the function of structural reinforcement, and can be attached to the wafer for wafer thinning first. Avoid chip breakage during thinning. • The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a flip chip package structure that is free of bumps, which comprises a wafer, a substrate, and an interposer. The wafer has a plurality of pads on the active surface. The substrate has an upper surface and a plurality of connecting ports on the upper surface, wherein the spacing of the connecting lines is greater than the distance between the glow pads. The interposer is disposed between the wafer and the substrate to electrically connect the wafer to the substrate, and to fill and maintain a gap between the wafer and the substrate. The interposer includes - a core layer having a via hole, a first patterned metal layer on the core layer, a first insulating layer in the same layer as the first patterned metal layer, ... the first insulating layer and the first pattern a first-adhesive layer on the metal layer, a second patterned metal layer under the core layer, a second insulating layer in the same layer as the second patterned metal layer, and a second insulating layer in the second insulating layer a second adhesive layer under the second patterned metal layer, wherein the patterned metal layer and the second patterned metal layer are electrically connected to each other by the via holes, the first insulating layer and the second The insulating layer is disposed such that the first patterned metal layer and the second patterned 201117327 metal layer are protruded into the corresponding layer. Attaching the adhesive layer and the second adhesive layer, wherein the first adhesive layer adheres to the first adhesive layer and the active surface of the first barrier is electrically connected to the wafer The first adhesive layer is adhered to the patterned metal layer of the substrate to electrically connect the surface of the board; and the second adhesive layer is unmasked. Month, the object of the present invention and the solution #&
措施進-步實現問題還可採用以下技術 在前述的免用凸塊之覆晶封裝構造令，該第一圖 金屬層係可包含複數個第—轉接塾，其表面設有第 料’用以焊接該些銲塾，並且該第二圖案化金屬層係可 包含複數個第二轉接墊’其表面設有第二銲料，用以 接該些連接墊。 ^ 在前述的免用凸塊之覆晶封裝構造中’該第一銲料與 該第二銲#係可具有㈣的熔，點，其係高於該第一黏著 層與該第二黏著層之黏性活化溫度。 在前述的免用凸塊之覆晶封裝構造中，該晶片係可為 不具有凸塊與重配置線路層之裸晶粒，該晶片之主動面 係形成有一保護層，該第一黏著層係黏著至該保護層。 在前述的免用凸塊之覆晶封裝構造中，該晶片係可被 薄化，以使該晶片之厚度係略小於該中介板之厚度。 在前述的免用凸塊之覆晶封裝構造中，該第一絕緣層 與該第二絕緣層之厚度係可分別等於該第一圖案化金屬 層與該第二圖案化金屬層之厚度。 201117327 在前述的免用凸塊之覆晶封裝構造中，可另包含一封 膠體，係形成於該基板之該上表Φ， 丄Α ^ 167以进封該晶片與該 中介板》 由以上技術方案可以看出，本發明之免用凸塊之覆晶 封裝構造及其中介板，有以下優點與功效： -、可藉由令介板的多層結構作為其中—技術手段，使 圖案化金屬層不會突出地嵌入表面黏著層，取代習The method further implements the above-mentioned technology in the above-mentioned die-free package structure of the free bump, and the first metal layer may include a plurality of first-transfer turns, and the surface thereof is provided with a material The solder pads are soldered, and the second patterned metal layer may include a plurality of second transfer pads having a second solder on the surface for connecting the connection pads. In the foregoing bump-free flip-chip package structure, the first solder and the second solder may have a melting point of (4) higher than the first adhesive layer and the second adhesive layer. Viscous activation temperature. In the above-mentioned bump-free flip chip package structure, the wafer system may be a bare die having no bump and re-distribution circuit layers, and the active surface of the wafer is formed with a protective layer, the first adhesive layer Adhered to the protective layer. In the aforementioned bump-free flip-chip package construction, the wafer system can be thinned such that the thickness of the wafer is slightly less than the thickness of the interposer. In the above-mentioned bump-free flip chip package structure, the thickness of the first insulating layer and the second insulating layer may be equal to the thicknesses of the first patterned metal layer and the second patterned metal layer, respectively. 201117327 In the above-mentioned bump-free flip chip package structure, a further colloid may be further formed on the upper surface of the substrate Φ, 167 167 to seal the wafer and the interposer. It can be seen that the flip chip package structure and the interposer thereof of the present invention have the following advantages and effects: - The patterned metal layer can be made by using the multilayer structure of the interface as a technical means therein. Will not be prominently embedded in the surface adhesive layer, replacing the ha
知凸塊與晶片上重配置線路層、取代習知黏晶材 料、取代習知底部填充膠與間隔維持物，並使中介 板之表面黏著層有一致薄化的厚度且不會有其圖案 化金屬層與晶片主動面短路的風險，並進一步降低 封裝厚度與晶片成本。 二、可藉由中介板的多層結構作為其中一技術手段，使 圖案化金屬層不會突出地嵌入表面黏著層，以使表 面黏著層可-致薄化’中介板可以達到先貼附於晶 片主動面再貼附至基板、後經一次迴焊之功效， 避免習知以三明治結構熱壓造成對不準晶片銲墊之 問題 -可藉由可藉由中介板的多層結構及貼附至晶片作為 其中技術手段，該晶片係可被薄化，以使該晶片 之厚度係略小於該中介板之厚度，該中介板具有結 構補強之作用，可先將貼附至晶片再作晶圓薄化， 以避免在薄化時晶片的碎裂。 【實施方式】 201117327 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案Knowing that the bump and the wafer are reconfigured with a circuit layer, replacing the conventional die-bonding material, replacing the conventional underfill and spacer maintenance, and making the surface adhesion layer of the interposer have a uniform thickness and without patterning. The risk of shorting the metal layer to the active face of the wafer and further reducing package thickness and wafer cost. Second, the multilayer structure of the interposer can be used as one of the technical means, so that the patterned metal layer does not protrude into the surface adhesive layer so that the surface adhesive layer can be thinned. The interposer can be attached to the wafer first. The effect of attaching the active surface to the substrate and then re-welding, avoiding the problem of misaligning the solder pads with the sandwich structure hot pressing - can be performed by the multilayer structure of the interposer and attached to the wafer As a technical means, the wafer system can be thinned so that the thickness of the wafer is slightly smaller than the thickness of the interposer, and the interposer has the function of structural reinforcement, and can be attached to the wafer for wafer thinning first. To avoid chipping during thinning. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings, in which FIG. , so only show this case
有關之兀件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之一較佳具體實施例，一種免用凸塊之覆 晶封裝構造舉例說明於第3圖之截面示意圖。該覆晶封 裝構造300,主要包含一晶片31〇、一基板32〇以及一中 介板330。第4圖為該中介板33〇之截面示意圖。第5 圖為該中介330在導通1 33 ! a之局部截面放大示意 圖。第6圖為該晶片310之主動面示意圖。第7圖為該 基板320之上表面示意圖。其中，該中介板330係設置 於該晶片310與該基板32。之間，用以電性連接該晶片 310與^基板320,以取代f知凸塊與晶片上重配置線路 層、黏著該晶4 3 1〇，以取代習知黏晶材料以及填充與 維持在該晶片3 10與該基板32〇之間的間隙以取代習 知底部填充膠與間隔維持物。 包含一具有導 上之第一圖 本發明之主要特徵在於該中介& 33〇的特定多層結 構°如第4及5圖所示，該中介板330係 通孔33 1A之核心層33卜一在該核心層33 案化金屬層332 與該第一圖案化金屬層332同層 201117327 一第一絕緣層333、一 鍫廢絕緣層333上之第一黏 著層4、—在該核心| 331 33S、一與該笛-因& s下之第一圖案化金屬層 336 ' 一在；第一八化金層335同層之-第二絕緣層 以第二絕緣層336下之第二黏著層3”。該杪 〜331係為-種介電材料，例如PET或PI軟片式薄 膜’或可為弋曰地女 式溝 通孔⑶“貫穿二二纖維含浸樹脂。該些導 導電材料：孔内可電鍍銅或是填入 導電材枓。該第-圖案化金屬層332與該第二圖 屬層335係為經選擇性蝕刻或選擇性電鍍形 其他金屬層。該第一絕緣層333與該第二絕緣層3 = 材質可為聚亞醯胺⑽，可利用薄膜印刷技術形成，以 真禹子應該第-圖案化金屬$ 332與該第二圖案化金屬 層335之間的圖案空隙，以使該第一圖案化金屬層 與該第m金屬層335不為浮凸之型態，以提供黏 著層的平坦形成表面。該第-黏著層334與該第二黏著 層337係可為具有黏性之環氧樹脂。 其中，該第一圖案化金屬層332與該第二圖案化金屬 層335係藉由該些導通孔331八相互電性連接，該第一 絕緣層333與該第二絕緣層336之設置係避免該第一圖 案化金屬層332與該第二圖案化金屬層335突出地嵌入 對應之該第一黏著層334與該第二黏著層337。較佳地， 該第一絕緣層333與該第二絕緣層336之厚度係可分別 等於該第一圖案化金屬層332與該第二圖案化金屬層 335之厚度，故能以該些黏著層334與337作為該中负 10 201117327 板330之厚度一致之阻焊層，以達到薄化效果。 如第3及6圖所示，該晶片310係具有複數個在一主 動面311上之銲墊312。較佳地，利用該中介板HQ的 高效率多元件取代特性，該晶片31〇係可為不具有凸塊 與重配置線路層之裸晶粒，該晶片31〇之主動面3ιι係 形成有一保護層313❶該晶片310不需要設置凸塊、重 配置線路層及其它保護層，故具有低晶片成本之功效。 在本實施例中，該些銲墊312係為中央排列（如第6圖所 示）。較佳地，該中介板330具有結構補強之作用，該晶 片310係可被薄化，以使該晶片31〇之厚度係略小於該 中介板330之厚度，可先將該中介板33〇貼附至該晶片 3 10再作晶圓薄化，以避免在薄化時該晶片3 1〇的碎裂。 如第3及7圖所示’該基板32〇係具有一上表面321 以及複數個在該上表面321之連接墊322，其中該些連 接墊3 22之間距係大於該些銲墊312之間距。該基板320 係可為一印刷電路板，以供無凸塊之覆晶接合。 再如第3圖所示，該第一黏著層334係黏附至該晶片 310之該主動面31卜並使該第一圖案化金屬層332電性 連接該晶片310之該些銲墊312，該第二黏著層337係 黏附至該基板320之該上表面321，並使該第二圖案化 金屬層335電性連接該基板32〇之該些連接墊322。在 一較佳實施例中，由於該晶片3丨〇可為裸晶粒，該第一 黏著層334係直接黏著至該保護層313。 以下進一步說明該中介板330電性連接該晶片31p 201117327 與該基板3 20之技術手段。該第一圖案化金屬層332係 可包含複數個第一轉接墊332A，其表面設有第—銲料 338，用以焊接該些銲墊312，並且該第二圖案化金屬層 335係包含複數個第二轉接墊33SA，其表面設有第二銲 料339，用以焊接該些連接墊322。藉由該第一絕緣層 333與該第二絕緣層336之設置係更可避免銲料擴散污 染至對應圖案化金屬層332或335之空隙。尤佳地，該 第一銲料3 38與該第二銲料339係可具有相同的熔點， 其係高於該第一黏著層334與該第二黏著層337之黏性 活化溫度。藉以實現該中介板3 3 〇先貼附於該晶片3 i 〇 之主動面311、再貼附至該基板32〇之上表面321、後經 一次迴焊達到電性連接之功效，避免習知以三明治結構 熱壓造成對不準晶片銲墊之問題。 更具體地，該覆晶封裝構造300係可另包含一封膠體 340’係形成於該基板3 2〇之該上表面321，以密封該晶 片310與該中介板330。 因此’本發明之覆晶封裝構造300係可藉由該中介板 330的多層結構作為其中一技術手段，使該些圖案化金 屬層332、335不會突出地嵌入表面黏著層334、337, 取代習知凸塊與晶片上重配置線路層、取代習知黏晶材 料、取代習知底部填充膠與間隔維持物，並使該中介板 33〇之表面黏著層334、337有一致薄化的厚度且不會有 其圖案化金屬層332、335與晶片主動面311短路的風 險，並進一步降低封裝厚度與晶片成本。 12 201117327 種免用凸塊之覆晶封裝構造之細部製造流程詳細 如後。 如第8A圖所示，提供該晶片31〇，可為一裸晶粒。 在該步驟中，該晶片310係-體形成於-晶圓。如第8B 斤厂' 該中"板330往該晶片310壓合。如第sc圖 所示，該中介板330貼附至該晶片31〇，以使該中介板 33〇之第一黏著層334係黏附至該晶片gw之主動面 3 可利用尚準度之覆晶接合機實現該第一轉接墊 33 A對準該銲塾312。在該步驟中，該第—銲料Mg尚 可不需要以迴焊方式焊接至該銲墊312。另可實施一晶 圓薄化步驟，以降低該晶片31〇之厚度’在該中介板33〇 之結構補強之作用T，該晶片31G可得到滿意的薄化厚 度（約數密耳）。再經晶圓切割之後，已貼附有該中介板 330之該晶片310呈單體化分離。如第8d圖所示，該晶 片3 10往該基板320壓合。如第8E圖所示，利用該中介 板330之第二黏著層337係黏附至該基板32〇之該上表 面321可利用低準度之覆晶接合機或表面接合機實現 該第二轉接墊335A對準該連接墊322。在該步驟中，該 第二銲料339尚可不需要以迴焊方式焊接至該連接墊 322。之後’實施一迴焊步驟，以使該第二銲料339焊接 該第二轉接墊335A與該連接墊322，並使該第一銲料 338焊接該第一轉接墊332八與該銲墊312，達到該晶片 310與該基板3 20之電性連接。最後，以模封或已知封 膠技術，使封膠體形成於該基板3 2〇上，以密封該晶片 13 201117327 310與該中介板33〇, 覆晶封裝構造。 以製造如第3圖所 示之免用凸塊之 上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制’雖然本發明已以較佳實施例 揭露如上’然而並非用以限定本發明，任何熟悉本項技 術者，在不脫離本發明《技術範㈣，所作的任何簡單For the related components and combinations, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a preferred embodiment of the present invention, a flip-chip-free package structure is illustrated in cross-section in FIG. The flip chip package structure 300 mainly includes a wafer 31, a substrate 32, and a middle plate 330. Figure 4 is a schematic cross-sectional view of the interposer 33A. Fig. 5 is an enlarged schematic partial cross-sectional view of the interposer 330 in the conduction 1 33 ! a. FIG. 6 is a schematic diagram of the active surface of the wafer 310. Fig. 7 is a schematic view showing the upper surface of the substrate 320. The interposer 330 is disposed on the wafer 310 and the substrate 32. For electrically connecting the wafer 310 and the substrate 320, in place of the bump and the re-arrangement of the wiring layer on the wafer, bonding the crystal 4 3 1 〇 to replace the conventional viscous material and filling and sustaining The gap between the wafer 3 10 and the substrate 32 is replaced by a conventional underfill and spacer maintenance. Included in a first diagram having a guide The present invention is characterized in that the intermediate layer of the medium & 33 is as shown in Figs. 4 and 5, and the interposer 330 is a core layer 33 of the through hole 33 1A. In the core layer 33, the metal layer 332 is on the same layer as the first patterned metal layer 332, 201117327, a first insulating layer 333, a first adhesive layer 4 on a waste insulating layer 333, at the core | 331 33S a first patterned metal layer 336' under the flute-in &s; a first adhesive layer 335 in the same layer - a second insulating layer and a second adhesive layer under the second insulating layer 336 3". The 杪 ~ 331 is a kind of dielectric material, such as PET or PI film film 'or may be a female communication hole (3) "through the two fiber impregnating resin. The conductive materials are: copper can be electroplated in the holes or filled with a conductive material. The first patterned metal layer 332 and the second patterned layer 335 are selectively etched or selectively plated with other metal layers. The first insulating layer 333 and the second insulating layer 3 = may be made of polyamidamine (10), which may be formed by a thin film printing technique, in which the true dice should first pattern the metal $ 332 and the second patterned metal layer The pattern gap between the 335 is such that the first patterned metal layer and the mth metal layer 335 are not embossed to provide a flat forming surface of the adhesive layer. The first adhesive layer 334 and the second adhesive layer 337 may be a viscous epoxy resin. The first patterned metal layer 332 and the second patterned metal layer 335 are electrically connected to each other through the via holes 331 . The arrangement of the first insulating layer 333 and the second insulating layer 336 are avoided. The first patterned metal layer 332 and the second patterned metal layer 335 are protruded into the corresponding first adhesive layer 334 and the second adhesive layer 337 . Preferably, the thickness of the first insulating layer 333 and the second insulating layer 336 can be equal to the thickness of the first patterned metal layer 332 and the second patterned metal layer 335, respectively, so that the adhesive layers can be 334 and 337 are used as the solder resist layer of the negative 10 201117327 plate 330 to achieve a thinning effect. As shown in Figures 3 and 6, the wafer 310 has a plurality of pads 312 on a major surface 311. Preferably, by using the high-efficiency multi-element replacement characteristic of the interposer HQ, the wafer 31 can be a bare die having no bump and re-distribution circuit layers, and the active surface 3 ιι of the wafer 31 is formed with a protection. The layer 313 ❶ the wafer 310 does not need to be provided with bumps, reconfigured wiring layers and other protective layers, so it has the effect of low wafer cost. In the present embodiment, the pads 312 are arranged in a center (as shown in Fig. 6). Preferably, the interposer 330 has a structural reinforcement function, and the wafer 310 can be thinned so that the thickness of the wafer 31 is slightly smaller than the thickness of the interposer 330, and the interposer 33 can be pasted first. The wafer 3 10 is attached to the wafer for thinning to avoid chipping of the wafer 3 1 during thinning. As shown in FIGS. 3 and 7 , the substrate 32 has an upper surface 321 and a plurality of connection pads 322 on the upper surface 321 . The distance between the connection pads 322 is greater than the distance between the pads 312 . . The substrate 320 can be a printed circuit board for flip chip bonding without bumps. As shown in FIG. 3 , the first adhesive layer 334 is adhered to the active surface 31 of the wafer 310 , and the first patterned metal layer 332 is electrically connected to the pads 312 of the wafer 310 . The second adhesive layer 337 is adhered to the upper surface 321 of the substrate 320, and the second patterned metal layer 335 is electrically connected to the connection pads 322 of the substrate 32. In a preferred embodiment, the first adhesive layer 334 is directly adhered to the protective layer 313 since the wafer 3 can be a bare die. The technical means for electrically connecting the interposer 330 to the wafer 31p 201117327 and the substrate 3 20 is further described below. The first patterned metal layer 332 may include a plurality of first transfer pads 332A, a surface of which is provided with a first solder 338 for soldering the pads 312, and the second patterned metal layer 335 includes a plurality of The second transfer pads 33SA are provided with a second solder 339 on the surface thereof for soldering the connection pads 322. By the arrangement of the first insulating layer 333 and the second insulating layer 336, solder diffusion contamination to the gaps of the corresponding patterned metal layer 332 or 335 can be avoided. More preferably, the first solder 3 38 and the second solder 339 may have the same melting point, which is higher than the viscous activation temperature of the first adhesive layer 334 and the second adhesive layer 337. Therefore, the interposer 3 3 is first attached to the active surface 311 of the wafer 3 i , and then attached to the upper surface 321 of the substrate 32 , and then electrically reconnected by a reflow to avoid the conventional knowledge. The hot pressing of the sandwich structure causes problems with the wafer pads being misaligned. More specifically, the flip chip package structure 300 may further include a glue 340' formed on the upper surface 321 of the substrate 32 to seal the wafer 310 and the interposer 330. Therefore, the flip chip package structure 300 of the present invention can be used as one of the technical means by the multilayer structure of the interposer 330, so that the patterned metal layers 332, 335 are not protruded into the surface adhesive layers 334, 337, instead of Conventionally, bumps and wafers are reconfigured with a circuit layer, a conventional adhesive material, a conventional underfill and a spacer, and the surface adhesion layers 334 and 337 of the interposer 33 are uniformly thinned. There is no risk of the patterned metal layers 332, 335 being shorted to the active surface 311 of the wafer, and the package thickness and wafer cost are further reduced. 12 201117327 Details of the manufacturing process of the chip-free package structure of the bump-free bumps are as follows. As shown in FIG. 8A, the wafer 31 is provided, which may be a bare die. In this step, the wafer 310 is body-formed on the wafer. For example, the 8B factory 'the middle" plate 330 is pressed to the wafer 310. As shown in the figure sc, the interposer 330 is attached to the wafer 31A so that the first adhesive layer 334 of the interposer 33 is adhered to the active surface 3 of the wafer gw. The bonding machine effects alignment of the first transfer pad 33 A with the pad 312. In this step, the first solder Mg may not need to be soldered to the pad 312 in a reflow manner. Alternatively, a wafer thinning step can be performed to reduce the thickness T of the wafer 31' in the structure of the interposer 33, and the wafer 31G can be satisfactorily thinned (about a few mils). After the wafer is diced, the wafer 310 to which the interposer 330 has been attached is singulated. As shown in Fig. 8d, the wafer 3 10 is pressed against the substrate 320. As shown in FIG. 8E, the second adhesive layer 337 of the interposer 330 is adhered to the upper surface 321 of the substrate 32. The second transfer can be realized by a low-profile flip chip bonder or surface bonder. Pad 335A is aligned with the connection pad 322. In this step, the second solder 339 may not need to be soldered to the connection pad 322. Then, a reflow step is performed to solder the second solder pad 335A and the connection pad 322, and the first solder 338 is soldered to the first transfer pad 332 and the pad 312. The electrical connection between the wafer 310 and the substrate 3 20 is achieved. Finally, a sealant is formed on the substrate 3 2 by a mold or a known encapsulation technique to seal the wafer 13 201117327 310 and the interposer 33, a flip chip package. The above description of the invention is not limited to the preferred embodiment of the present invention, and the present invention has been disclosed in the preferred embodiments as described above. 'However, it is not intended to limit the invention, and any person skilled in the art can make any simple without departing from the technical scope (four) of the present invention.
修改、等效性變化與修飾，均仍屬於本發明的技術範圍 内0 【圖式簡單說明】 第1圖：為一種習知打線連接之半導體封裝構造之截面 示意圖。 第2圖：為一種習知使用凸塊之覆晶封裝構造之截面示 意圖。 第3圖 第4圖 第5圖 .依據本發明之一具體實施例，一種免用凸塊之 覆晶封裝構造之截面示意圖。 •依據本發明之一具體實施例，—種免用凸塊之 覆晶封裝構造之中介板之截面示意圖。 .依據本發明之一具體實施例，一種免用凸塊之 覆晶封裝構造之中介板在導通孔之局部截面放 大不意圖。 第6圖：依據本發明之一具體實施例，該覆晶封裝構造 之晶片主動面不意圖。 第7圖：依據本發明之一具體實施例，該覆晶封裝構造 之基板上表面示意圖。 14 201117327 第8A至8E圖：依據本發明之一具體實施例，一種免用 凸塊之覆晶封裝冑造在製程中之m面示意圖。 【主要元件符號說明】Modifications, equivalent changes and modifications are still within the technical scope of the present invention. [Simplified description of the drawings] Fig. 1 is a schematic cross-sectional view showing a conventional semiconductor package structure in which wire bonding is connected. Fig. 2 is a cross-sectional view showing a conventional flip chip package structure using bumps. Figure 3 is a cross-sectional view of a flip chip package structure excluding bumps in accordance with an embodiment of the present invention. A cross-sectional view of an interposer of a flip chip package structure that is free of bumps in accordance with an embodiment of the present invention. According to an embodiment of the present invention, an interposer having a flip chip-free flip chip package structure is enlarged in a partial cross section of the via hole. Figure 6: In accordance with an embodiment of the present invention, the wafer active surface of the flip chip package structure is not intended. Figure 7 is a schematic view showing the upper surface of a substrate of the flip chip package structure according to an embodiment of the present invention. 14 201117327 Figures 8A to 8E are diagrams showing an m-plane of a bump-free flip-chip package fabricated in a process according to an embodiment of the present invention. [Main component symbol description]
100習知打線連接之‘半導體封裂構造 110 晶片 111 主動面 112 銲墊 120 基板 121 上表面 122 連接墊 130 黏晶材料 140 封膠體 150 銲線 200 習知使用凸塊之覆晶封裝構造 210 晶片 211 主動面 212 銲墊 213 第一保護層 214 重配置線路層 215 第二保護層 216 凸塊 220 基板 221 上表面 222 連接墊 230 底部填充膠 240 封膠體 300 免用凸塊之覆晶封裴構造 3 10 晶片 311 主動面 3 12 銲墊 313 保護層 320 基板 321 上表面 322 連接墊 330 中介板 331 核心層 331A導通孔 332 第一圖案化金屬層 332A第一轉接墊 333 第一絕緣層 334 第一黏著層 335 第二圖案化金屬層 335A第二轉接墊 336 第二絕緣層 337 第二黏著層 15 201117327 340封膠體 338第一銲料 339第二銲料100 conventional wire bonding connection 'semiconductor cracking structure 110 wafer 111 active surface 112 pad 120 substrate 121 upper surface 122 connection pad 130 die bonding material 140 sealing body 150 bonding wire 200 conventional use flip chip flip chip package structure 210 wafer 211 active surface 212 solder pad 213 first protective layer 214 reconfiguration circuit layer 215 second protective layer 216 bump 220 substrate 221 upper surface 222 connection pad 230 underfill adhesive 240 encapsulant 300 free bump bumping structure 3 10 wafer 311 active surface 3 12 solder pad 313 protective layer 320 substrate 321 upper surface 322 connection pad 330 interposer 331 core layer 331A via 332 first patterned metal layer 332A first transfer pad 333 first insulating layer 334 An adhesive layer 335 a second patterned metal layer 335A second transfer pad 336 a second insulating layer 337 a second adhesive layer 15 201117327 340 sealant 338 first solder 339 second solder
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