201246496 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種功率半導體元件及盆赞作' 關於一種溝槽式功率半導體元件及其製作^。去’特別是 【先前技術】 平面式功率半導體元件（例如功率 (=sFET))將閘極設置於餘表面，嫩通道‘冗 广材表面的走向流動’會占據基板的面積，而導致 (1=隔距離無法任意縮減。相較之下，溝渠式功率 兀件將閘極設置於漢槽内，使電流通道改為垂直走向 以縮短單元間的間隔距離，提高積集度⑽聊i〇n)。 了 第1圖係-典型溝槽式金氧半場效電晶體之 中所示’此溝槽式金氧半場效電晶體具有- n ====6 ΪΓ型井區17、複數個源區 型重养雜曰2型輕摻雜蟲晶層12係位於n „〇上’閘極溝槽14係位於N型輕摻雜磊晶層 2二':構16係位於閘極溝槽14内。P型井區17俜位 _晶層12之上部分，並且環繞閘極^槽!二 » _之週圍包覆有一閘極介電層15，藉以與P型井區17 =輕摻雜蟲晶層12相區隔。源極摻雜區18係位於p型 覆ί於門層’並且環繞閘極溝槽14。層間介電層19係 源極接^窗6±方。此層間介電層19内並製作有複數個 原極接觸_，以裸露源極摻雜區18。 -此溝槽式金氧半場效電晶體之源極電壓係透過 極C層19上方之源極金屬層(未圖示)施加於源 閘極電壓係透過—形成於層間介電層19上方之 甲，層(未圖示)施加於閘極結構16，汲極電廢則是透過一 201246496 形成於N型重摻雜基板ι〇下方之汲極金屬層(未圖示)施加於 N.型重掺雜基板1〇。因此，晶片封裝時需同時連接基板上下 表面之電極，.而造成封裝技術上的限制。 爰是，如何簡化既有之溝槽式功率半導體元件之結構盘製 作方法，是本技術領域一個重要的課題。 〃 【發明内容】 有鑑於此，本發明之主要目的是提出一種溝槽式功 體7G件以及此溝槽式功率半導體元件之製作方法 程，降低製作成本。 間衣 為達成上述目的，本發明提供一種溝槽式功率 件。此溝槽式功率半導體元件具有—第—導電型之=換201246496 VI. Description of the Invention: [Technical Field] The present invention relates to a power semiconductor device and a pottery as described in relation to a trench type power semiconductor device and its fabrication. Going 'Specially' [Prior Art] Planar power semiconductor components (such as power (= sFET)) set the gate to the remaining surface, and the 'passing flow of the surface of the redundant material' will occupy the area of the substrate, resulting in (1 = The distance can not be reduced arbitrarily. In contrast, the ditch-type power element sets the gate in the Han channel, so that the current channel is changed to the vertical direction to shorten the separation distance between the units, and improve the accumulation degree (10) ). Figure 1 shows a typical trench-type MOS field-effect transistor. This trench-type MOS field-effect transistor has -n ====6 ΪΓ-type well region 17, a plurality of source regions. The heavy-duty hybrid type 2 lightly doped insect layer 12 is located on the n 〇 ' 闸 gate trench 14 is located in the N-type lightly doped epitaxial layer 2 ′′: the structure 16 is located in the gate trench 14 . The P-type well region 17 is located at the upper part of the crystallization layer 12, and surrounds the gate electrode slot; the periphery of the second layer _ is covered with a gate dielectric layer 15, thereby being associated with the P-type well region 17 = lightly doped insect crystal The layer 12 is separated by a phase. The source doping region 18 is located at the p-type gate layer 'and surrounds the gate trench 14. The interlayer dielectric layer 19 is connected to the source gate 6± square. 19 is formed with a plurality of primary contact _ to expose the source doped region 18. - The source voltage of the trench MOS field-effect transistor is transmitted through the source metal layer above the C-layer 19 (not The voltage applied to the source gate is transmitted through a layer formed above the interlayer dielectric layer 19, a layer (not shown) is applied to the gate structure 16, and the gate electrode is formed in the N-type through a 201246496. Bipolar gold under the doped substrate ι〇 A layer (not shown) is applied to the N. type heavily doped substrate 1 . Therefore, the wafer package needs to be connected to the electrodes on the upper and lower surfaces of the substrate at the same time, which causes limitations in packaging technology. Therefore, how to simplify the existing trench The method for fabricating a structure of a trench power semiconductor device is an important subject in the art. 〃 [Invention] In view of the above, the main object of the present invention is to provide a trench-type power 7G device and the trench power. The manufacturing method of the semiconductor component reduces the manufacturing cost. In order to achieve the above object, the present invention provides a trench type power device. The trench power semiconductor device has a -first conductivity type =
Si少二個溝槽閘極結構、—第二導電型之井區Ϊ 一‘電型之弟一摻雜區、至少二個溝 窗盘一導雷㈣賴底°卩重雜區、一接觸 這些溝槽中包括至少一個心:於:二 =反5 = 方。溝槽底部重摻雜區係形成於這些溝槽的乂：，並° = 與前述溝槽保持-預設距t i板上’並 連接溝槽底部重雜區。 、。“真人接觸自’以電性 與至括至少-個第-溝槽 槽係用以容納-終端結構。用以谷納—閘極導線’第二溝 在本發明之一實施例中， 部重摻雜區形成於接觸窗底部， >蜍電5之接觸窗底 重摻雜區電性連接至溝槽底部重參，、、纟1 構係透過此接觸窗底部 在本發明之一實施例中， 構，分別填入溝槽之一下部八，'，至〉、二個重摻雜磊晶結 雜區於輕摻雜基板内。77，以形成相對應之溝槽底部重摻 5 201246496 换她Ϊ本發明之一實施例中，更包括至少二個第二導電型之重 私雜之―下料，難結構係位於此 在本發明之—實施例中，接觸f與溝槽之開口係位於輕捧 雜丞板之一上表面。 在本發明之一實施例中，接觸窗係位於輕摻雜基板之一側 在本發明之-實施例中，溝槽底部重摻雜區係為第 ，以製造一功率金氧半場效電晶體。 在，發明之-實施例中，溝槽底部重摻雜區係為第二 ，以j造一絕緣閘極雙極電晶體。 依據前述槽式功率半導體元件，本發明亦提供一製造方 。此製造方法至少包括下列步驟： .一 ^溝槽式功率半導體元件之製造方法，至少包括下列步 供一第一導電型之輕摻雜基板；（b)形成至少二個溝 摻雜基板上’這些溝槽包括至少一侧極溝槽；⑻形成 ;接，於輕摻雜基板上;(d)形成至少二個溝槽底部重摻$ =相對應之溝槽底部；(e)施卩熱擴散製程使溝槽底部重摻雜 ，係^相連接成—閘極結構於閘極溝槽内；⑻形成1 第二導電型之井區環繞閘極結構；（h)形成―第—導電型之第 ^雜區於井區上方，以及⑴填入一導電結構於接觸窗内，以 電性連接溝槽底部重摻雜區。 關於本發明之優點與精神可以藉由以下的發明詳述及 附圖式得到進一步的瞭解。 邊 型 型 法 驟 【實施方式】 ㈣溝槽式功率半導體元件社要技婦徵係透過 溝槽底。卩重摻腿之製作’取代傳統製財法所f的重捧雜美 板，同時可以省卻形成錄絲板上層，藉簡 結構，降低製造成本的目的。 n匕Si has two trench gate structures, a second conductivity type well region, an 'electric type brother-doped region, at least two trench window disks, a thunder guide (4) a bottom portion, a heavy cross region, and a contact These grooves include at least one core: at: two = inverse 5 = square. The heavily doped regions at the bottom of the trench are formed in the trenches of the trenches: and are maintained at a predetermined distance from the trenches and connected to the bottom regions of the trenches. ,. "A human contact comes from 'electrically and at least a first-trench slot system for receiving a terminal structure. The second groove for the valley-gate conductor' is in one embodiment of the invention, The doped region is formed at the bottom of the contact window, and the heavily doped region of the contact window of the neodymium 5 is electrically connected to the bottom of the trench, and the structure of the 纟1 is transmitted through the bottom of the contact window. The middle, the structure, respectively, fills the lower part of the trench eight, ', to>, two heavily doped epitaxial regions in the lightly doped substrate. 77, to form the corresponding trench bottom doping 5 201246496 In one embodiment of the present invention, there is further included at least two second conductive types of heavy-duty materials, which are located in the present invention, in the embodiment of the present invention, the opening of the contact f and the trench In one embodiment of the present invention, the contact window is located on one side of the lightly doped substrate. In the embodiment of the present invention, the heavily doped region at the bottom of the trench is First, to manufacture a power MOS half field effect transistor. In the invention - the embodiment, the trench bottom is heavily doped The second is to form an insulated gate bipolar transistor. According to the foregoing slot type power semiconductor device, the present invention also provides a manufacturing method. The manufacturing method includes at least the following steps: 1. Trench type power semiconductor device The manufacturing method comprises at least the following steps for a light-doped substrate of a first conductivity type; (b) forming at least two trench-doped substrates on which the trenches comprise at least one side trench; (8) is formed; Lightly doped on the substrate; (d) forming at least two trench bottoms with a re-doped $= corresponding trench bottom; (e) applying a thermal diffusion process to heavily dope the bottom of the trench, connecting the gates to the gate The pole structure is in the gate trench; (8) forming a second conductivity type well region surrounding the gate structure; (h) forming a "first conductivity type" impurity region above the well region, and (1) filling a conductive structure In the contact window, the heavily doped region is electrically connected to the bottom of the trench. The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings. (4) Trench-type power semiconductor components Through the bottom of the groove, the production of 掺 heavy-filled legs replaces the traditional pledge of the traditional financial method, and at the same time, it can eliminate the formation of the layer on the silk, and reduce the manufacturing cost by simplifying the structure.
S 6 201246496 第2A至2G圖顯示本發明溝槽式功率半導體元件之制、告 方法之第一實施例。本實施例係以一功率金氧半場效電晶 例。惟.，本，發明並不限於此P本發明亦可適用於其他功^導 體元件，如絕緣閘極雙極性電晶體(IGBT)，的製^乍。. 如第2A圖所示，首先，不同於傳統之金氧半場效電晶體 之製造方法，係於一 N型重摻雜基板上製作N型磊晶層=為 底材，本實施例直接利用一 N型輕摻雜基板11〇作為麻 以省卻N型Μ層之製作。隨後，在此N型輕摻^^11〇 上製作一圖案層115，以定義溝槽之位置。在本實施例中，此 圖案層115係於此N型輕摻雜基板110上，由内而外依序定義 閘極結構、閘極導線、終端(termination)結構與一接觸窗之位 置。 ’、 接下來，如第2B圖所示，透過圖案層115蝕刻N型輕摻 雜基板110，以形成至少一個閘極溝槽122、至少一個第一溝 槽124以容納閘極導線、至少一個第二溝槽126以容納終端結 構以及至少一接觸窗128於N型輕摻雜基板11〇上。前述^ ，窗128可為-完整的溝槽，或是呈現階梯狀結構。隨後，如 第2C圖所示，透過圖案層115，植人高漠度型摻雜於間 極溝槽122、、第一溝槽124、第二溝槽126以及接觸窗128底 部，以形成複數個溝槽底部重摻雜區132於前揭各個溝槽 122,124,126底部與-接觸窗底部重摻雜區134於接觸窗⑶ 底部。然LX-熱擴散製程’使各個賴底部重摻雜區 132與接觸窗底部重摻雜區134互相連接，以形成一導電通道 130 ί本貝加ΐ)中，此導電通道區13〇即用以通入汲極電位。 隨後’如帛2D圖所* ’於閘極溝槽122、第—溝槽124 二溝槽126内，分別製作閘極結構150、閘極導線160與 端結構170。本實施例在形成閘極結構150、閘極導線160 二=端結構17G ^各個溝槽122，124,126内之步驟前，先形成 140覆蓋各個溝槽122，124，126之内側表面，以隔絕 閘極、、。構15G、閘極導線_、終端結構17()與其下方之導電 7 201246496 通道區130。本實施例係以同一道步驟製作閘極結構15〇、間 極導f 160與終端結構17〇，不過，本發明並不限於此。就— .較佳實i施例而言，終端結構17〇亦可以採取不同於閘極結構 150之設計。 然後，如第2E圖所示，以離子植入方式植入p型摻雜於 N型輕摻雜f板〗1〇，以形成p型井區152於相鄰之閘極結構 1 =間。值得注意的是，此p型井區m需與其下方之導電通 這區130維持一定距離，以維持足夠的崩潰電壓。接下來，如 第、2F圖所不’形成一 N型表面摻雜區154於P型井區152内， 以通入源極電位。然後，形成一層間介電層⑽於N型輕接 ，基板110上。此層間介電層18〇具有複數個開口，以裸露井 區152 N型表面接雜區154、閘極導線160與接觸窗128。 =，形成p型重摻雜區156於井區152巾。值得注意的是， ^製作開口於制介電層之步驟中，縣於接觸窗 内側表面的介電層M。同時被去除，以裸露位於接觸窗 128底部之導電通道區13〇。 ，後’如第2G圖所示’形成三個各自獨立的導電結構192, 俜透過介電層180上’這些導電結構192，194，196 U電層之開°，分別電性連接至表面掺雜區154、 線160與導電通道區13〇，以通入源極、問極與汲極的 電位。 而Ϊΐ ’本實施例所描述之Ρ型與Ν型僅為例示’ 本發明製作方法亦可適用於製作溝槽式 鱼乳牛=效電晶體於—P型輕摻雜基板上。 如帛2B與2C圖所示，本實施例在姓刻製作溝槽 接觸窗，128 lit，啊在輕摻雜基板110的邊緣處製作 區132 在後，利用離子植入方式形成溝槽底部重摻雜 :區在接觸窗128底部形成接觸窗底部重推 m電_==彳=132彳_賴絲物參雜區 接♦電、、.。構196。不過’本發明並不限於此。舉 201246496 例來說，接觸窗】28可以在完成閘極結構15〇後， =基板110上。此外’適當調整接觸窗128的位置Γ亦可^ 窗128直接延伸至溝槽底部重摻雜區132内，而不 ^妾觸窗128底部製作接觸窗底部重摻雜區134。舉例^另外 =據基板110的側邊向内削除部分基板11〇的材料 形成接觸窗以裸露溝槽底部重摻雜區。 P可 、相較於傳統之溝槽式金氧半場效電晶體的製造方法 用N型輕摻雜基板11G取代傳統製造方法所需之J ^曰曰^，亚以溝槽底部重摻雜區132作為源祕間之導^ ^ ’因而可以省卻形成N型蟲晶層之製作，同時，也 製作導電金屬層。其次，本實施例之用以通 = 位之導電通道區130係緊接於溝槽122,124,126之底部， =^表面摻雜區154與導電通道區13G間之N “ 區的厚度，有助於降低導通修(〇㈣sistanee)。此外，j 施例亦將原本位於基板背面之祕導電結 二 正面，有助於後續封裝製程之進行。 〜^板 士ΐ从與iB圖顯示本發明溝槽式金氧半場效電晶體之製 之第二實施例。第3A圖之製作步驟係接續第2B圖二 不同於本發明之第—實施例係以離子植人方式在閘 極溝匕122、第—溝槽124與第二溝槽126 槽底部重摻雜區Π2，本實施例先在各個溝槽- 下部分填入N型重摻雜磊晶結構23卜隨後，再施以熱擴散 程使重摻雜蟲晶結構231 N之摻雜物向外擴散，以形成多個^ 相連接之溝槽底部重摻雜區232於]Si型輕摻雜基板11〇内。 接了來，如第3B圖所示，直接於閘極溝槽122、第一溝枰124 與第二溝槽126内，分別形成閘極結構250、閘極導線/60盥 終端結構27〇。後續製作步驟與_本發明第—實施例相類 似，在此不予贅述。 、S 6 201246496 Figures 2A to 2G show a first embodiment of the method of manufacturing and reporting the trench power semiconductor device of the present invention. This embodiment is a power metal oxide half field effect transistor. However, the invention is not limited to this P. The invention can also be applied to other functional components such as an insulated gate bipolar transistor (IGBT). As shown in FIG. 2A, firstly, unlike the conventional method for manufacturing a gold oxide half field effect transistor, an N-type epitaxial layer is formed on an N-type heavily doped substrate as a substrate, and this embodiment directly utilizes An N-type lightly doped substrate 11 is used as a fabrication to eliminate the N-type germanium layer. Subsequently, a pattern layer 115 is formed on the N-type light doping film to define the position of the trench. In this embodiment, the pattern layer 115 is disposed on the N-type lightly doped substrate 110, and sequentially defines the gate structure, the gate conductor, the termination structure and a contact window from the inside to the outside. Next, as shown in FIG. 2B, the N-type lightly doped substrate 110 is etched through the pattern layer 115 to form at least one gate trench 122, at least one first trench 124 to accommodate the gate wire, at least one The second trench 126 is configured to receive the termination structure and the at least one contact window 128 on the N-type lightly doped substrate 11A. The window 128 can be a complete trench or a stepped structure. Subsequently, as shown in FIG. 2C, through the pattern layer 115, the implanted high-intensity type is doped to the interpole trenches 122, the first trenches 124, the second trenches 126, and the bottom of the contact window 128 to form a plurality The heavily doped regions 132 at the bottom of the trench are exposed to the bottom of the trenches 122, 124, 126 and the heavily doped regions 134 at the bottom of the contact window at the bottom of the contact window (3). However, the LX-thermal diffusion process 'connects each of the heavily doped regions 132 and the bottom doped regions 134 of the contact window to form a conductive via 130, which is used in the conductive channel region. In order to pass the bungee potential. Then, the gate structure 150, the gate wiring 160 and the end structure 170 are formed in the gate trench 122 and the first trench 124 trench 126, respectively. In this embodiment, prior to the step of forming the gate structure 150, the gate conductor 160, and the gates 122, 124, 126, the inner surface of each of the trenches 122, 124, 126 is formed to isolate the gate. pole,,. 15G, gate wire _, terminal structure 17 () and the underlying conductive 7 201246496 channel region 130. In the present embodiment, the gate structure 15A, the interpole guide f160, and the termination structure 17A are formed in the same step, but the present invention is not limited thereto. In the case of the preferred embodiment, the termination structure 17A can also take a different design than the gate structure 150. Then, as shown in Fig. 2E, a p-type doped N-type lightly doped f-plate is implanted by ion implantation to form a p-type well region 152 adjacent to the gate structure 1 =. It is worth noting that this p-type well region m needs to maintain a certain distance from the conductive region 130 below it to maintain a sufficient breakdown voltage. Next, an N-type surface doping region 154 is formed in the P-type well region 152 as shown in Figs. 2F to pass the source potential. Then, an interlayer dielectric layer (10) is formed on the N-type light-bonded substrate 110. The interlayer dielectric layer 18 has a plurality of openings to expose the well region 152 N-type surface junction region 154, the gate conductor 160 and the contact window 128. =, forming a p-type heavily doped region 156 in the well region 152. It is worth noting that, in the step of fabricating the opening in the dielectric layer, the dielectric layer M on the inner side surface of the contact window is formed. At the same time, it is removed to expose the conductive via region 13 位于 at the bottom of the contact window 128. Then, as shown in FIG. 2G, three separate conductive structures 192 are formed, which are transmitted through the dielectric layer 180, and the conductive layers 192, 194, and 196 are electrically connected to the surface. The impurity region 154, the line 160 and the conductive channel region 13A are connected to the potentials of the source, the drain and the drain. However, the Ρ type and the Ν type described in the present embodiment are merely exemplified. The manufacturing method of the present invention can also be applied to the production of a grooved fish cow = effect transistor on a -P type lightly doped substrate. As shown in FIG. 2B and FIG. 2C, in this embodiment, a trench contact window is formed in the last name, 128 lit, and the region 132 is formed at the edge of the lightly doped substrate 110, and the bottom of the trench is formed by ion implantation. Doping: The area at the bottom of the contact window 128 forms the bottom of the contact window and pushes the m electricity _==彳=132彳_赖丝物分区接接电,,. Structure 196. However, the invention is not limited thereto. For example, in 201246496, the contact window 28 can be on the substrate 110 after completing the gate structure 15〇. In addition, the position of the contact window 128 can be appropriately adjusted, and the window 128 can be directly extended into the heavily doped region 132 at the bottom of the trench without forming the heavily doped region 134 at the bottom of the contact window at the bottom of the contact window 128. For example, the material of the portion of the substrate 11A is removed inwardly according to the side of the substrate 110 to form a contact window to expose the heavily doped region at the bottom of the trench. P can be compared with the conventional trench type MOS field-effect transistor manufacturing method. The N-type lightly doped substrate 11G is used to replace the J ^ 曰曰 ^ required for the conventional manufacturing method, and the heavily doped region at the bottom of the trench is used. 132 as a guide to the source secret ^ ^ 'thus can be omitted to form the formation of the N-type insect layer, while also making a conductive metal layer. Secondly, the conductive via region 130 of the present embodiment is immediately adjacent to the bottom of the trenches 122, 124, 126, and the thickness of the N" region between the surface doped region 154 and the conductive via region 13G helps to reduce Inductive repair (〇(四)sistanee). In addition, the j example will also be located on the back side of the substrate on the front side of the conductive junction 2, which will help the subsequent packaging process. ~ ^ 士士ΐ from iB diagram showing the grooved gold of the present invention A second embodiment of the manufacture of an oxygen half field effect transistor. The fabrication step of Fig. 3A is continued. Fig. 2B Fig. 2 is different from the first embodiment of the present invention by ion implantation in the gate sill 122, the first groove The groove 124 and the second groove 126 are heavily doped in the bottom of the groove Π2. In this embodiment, the N-type heavily doped epitaxial structure 23 is first filled in each groove-lower portion, and then the thermal diffusion process is applied to make the heavy doping. The dopant of the worm crystal structure 231 N is outwardly diffused to form a plurality of interconnected trench bottom heavily doped regions 232 in the ]Si type lightly doped substrate 11 。. Next, as shown in FIG. 3B As shown, the gate structure 250 is formed directly in the gate trench 122, the first trench 124 and the second trench 126, respectively. . The gate conductor / 60 termination structure 27〇 wash step subsequent to the production of the present invention, the first _ - embodiment with similar embodiments, not described herein.
第4A與4B圖顯示本發明溝槽式金氧半場 造方法之第三實施例。第4A圖之製作步驟係接J 201246496 製作步驟。在以熱擴散製程形成導雷诵憎F μ 雜基板m㈣驟後，在各個溝槽ΐ2=〇26=輕摻 入蟲晶結構336。此蟲晶結構336 ρ換θ ^刀填 摻雜。隨後，如第4Β圖所-马1裕雜或疋Ν型輕 閘極結構35G、f懈線=構=方形成 與前;本發明第-實施例相類續製作步驟 f DA與5B圖顯示本發明溝 造方法之第四實施例。第5A圖之製作步製 製作步驟。在以埶擴散势程’，，喟第C圖之 Γ形成導電通道區130於N型 雜2 m内之步驟後，在各個溝槽122，ΐ24，ΐ26 = -厚氧化層440。此厚氧化層44()可以採 方== 性成長於各個溝槽122 124 1 %从泛如 乳方式選擇 122 m i，，的底部’亦可先在各個溝槽 ‘ ~， 内真入氧化矽，然後再以回韻的方式形成此严童 ί ;2= 5，如第5B圖所示’形成一導電結構442 :溝 二心，之下部分。此導電結構442之側面係透過-介 ί曰mi 1通道區130相分隔。然後，在閘極溝槽122、 第一溝槽124與第二溝槽126之上部分， 450、閘極導線460盘線嫂处姐1 別形成間極結構 、’ …··ς^、，，。構470。刖揭位於閘極溝槽122 構442的電位會隨著其上方之問極結構450的電位 第6圖顯示本發明應用於絕緣閘極雙 ^佳實施例。相較於本發明之第一實施例，& 氐邛所形成之溝槽底部重摻雜區132係為N型重摻雜，其導 與輕摻雜基板110相同；在本實施例中，溝槽122，124，126 氏部所形成之溝槽底部重摻雜區532與接觸1128底部卿成 ^接觸窗底部重摻雜區534均是P型重摻雜。因此，在導電通 ^區530與形成於P型井區152上方之n縣面播雜區554 =形成PNPN交替之絕緣閘極雙極電晶體結構。在此絕緣閘極 ς極電晶體結構中，N型表面摻雜區554係透過導電結構592 電性連接至一射極(emitter)，溝槽底部重摻雜區532則是透過4A and 4B are views showing a third embodiment of the trench type MOS half field method of the present invention. The fabrication steps of Figure 4A are linked to the J 201246496 production steps. After the formation of the Thunder F μ impurity substrate m (4) by a thermal diffusion process, 虫2 = 〇26 = lightly incorporated into the insect crystal structure 336 at each trench. This insect crystal structure is 336 ρ for θ ^ knife filling doping. Subsequently, as shown in Fig. 4, the horse 1 yu or 疋Ν type light gate structure 35G, the squat line = structure = square formation and the front; the first embodiment of the present invention is similar to the steps of f DA and 5B A fourth embodiment of the trenching method of the present invention. Step 5A production steps. After the step of forming the conductive via region 130 within the N-type impurity 2 m with the 埶 diffusion potential path ', 喟 C, the respective trenches 122, ΐ 24, ΐ 26 = - the thick oxide layer 440. The thick oxide layer 44() can be grown in each groove 122 124 1% from the pan-like mode to select 122 mi, and the bottom ' can also be in each groove '~, the inner yttrium oxide Then, in the manner of rhyme, this kind of Yan Tong ί; 2=5, as shown in Fig. 5B, 'forms a conductive structure 442: the groove two cores, the lower part. The sides of the conductive structure 442 are separated by a channel 1300. Then, in the gate trench 122, the upper portion of the first trench 124 and the second trench 126, 450, the gate conductor 460, the wiring line 嫂, the sister 1 forms an interpole structure, '...·ς^, ,. Structure 470. It is revealed that the potential at the gate trench 122 is at the potential of the gate structure 450 above it. Figure 6 shows a preferred embodiment of the invention applied to the insulating gate. Compared with the first embodiment of the present invention, the heavily doped region 132 of the trench formed by & is N-type heavily doped, which is the same as the lightly doped substrate 110; in this embodiment, The heavily doped region 532 of the trench formed by the trenches 122, 124, 126 and the heavily doped region 534 at the bottom of the contact 1128 are all P-type heavily doped. Therefore, the conductive pass region 530 and the n-counter-side miscellaneous region 554 formed over the P-type well region 152 form an insulated gate bipolar transistor structure in which PNPN is alternated. In the insulated gate-drain transistor structure, the N-type surface doping region 554 is electrically connected to an emitter through the conductive structure 592, and the heavily doped region 532 at the bottom of the trench is transparent.
S 10 201246496 形成於接觸窗128内之導電結構596電性連接至—隹搞 (collector)。 ^ 其次’前揭溝槽式金氧半場效電晶體之製造方法之各個實 施例，均可依第6圖所揭示之方式調整溝槽底部重摻雜區之4 電型，應用於製造絕緣閘極雙極電晶體。惟，在第4A與4B 圖之實施例中’填入溝槽122,124，126下部分之磊晶結構336 受限於溝槽底部重摻雜區532，僅能為N型摻雜。 弟7圖係本發明溝槽式金氧半場效電晶體之汲極接觸窗 的5又置位置之一較佳實施例。圖中顯示輕摻雜基板110之角 洛。在本實施例中，元件區A1係位於輕摻雜基板11〇之中央 處，導線區A2與終端區A3依序位於元件區A1之外側。接 觸窗128則是呈階梯狀，環繞輕摻雜基板11〇之四周。不過， 本發明並不限於此。接觸窗128可以僅僅環繞輕摻雜基板之部 分側邊’亦可以形成於輕摻雜基板11()之表面。 其次，請參照第2G圖所示，在前述各實施例中，位於閘 極結構150下方之溝槽底部重摻雜區132係依序透過位於閘極 導線160與終端結構170下方之溝槽底部重摻雜區132，電性 連接至導電結構196。不過，本發明並不限於此。隨著輕摻雜 基板上’元件、閘極導線160、終端結構170與接觸窗128之 配置位置的改變，位於閘極結構150下方之溝槽底部重摻雜區 132亦可以直接電性連接至導電結構196，而不透過位於閘極 導線160與終端結構Π0下方之溝槽底部f摻雜區132。 此外，請參照第2G圖所示，在前述各實施例中，接觸窗 128之開口與各個溝槽122,124,126之開口，位於輕摻雜基板 110之同一側。不過，本發明並不限於此。此接觸窗128亦可 以形成於輕摻雜基板11〇之下表面，或是形成於輕摻雜基板 110之側邊。 相較於傳統之溝槽式金氧半場效電晶體，本發明具有下列 優點： 一、本發明所提供之溝槽式功率半導體元件的製造方法， 201246496 可以賓卻f晶層之製作，有助於降低製作成本。 閘極導電結構削與祕itir二為表 面，有利於後續續裝製程之進行。恤於基板之上表 三、本發明所提供之溝槽式功率半導 與導電通道區13G間的輕摻雜區的厚度，有助於降“ 准以上所述者，僅為本發明之較佳 此限定本發明實施之翻，即大凡發 涵蓋之範圍内。另外本發明的任修^; ί仍屬本發明專利 達成本發騎鑛之全部目獅不須 和標題僅是用來輔助專利文件搜尋之^寺 此摘要部分 之權利範圍。 來限制本發明 【圖式簡單說明】 氧半場效電晶社勤示意圖。 法之二不本發明溝槽式金氧半場效電晶體之製造方 綠本㈣触式錢半場效電㈣之製造方 示本發明溝槽式金氧半場效電晶體之製造方 本發明溝槽式金氧半場效電晶體之製造方 示本發明應用於絕緣開極雙極電晶體(騰)之-較 錢半紐電—接觸窗之S 10 201246496 The conductive structure 596 formed in the contact window 128 is electrically connected to a collector. ^ Secondly, the various embodiments of the method for manufacturing the trench-type gold-oxygen half-field effect transistor can adjust the four-type of the heavily doped region at the bottom of the trench in the manner disclosed in FIG. Extreme bipolar transistor. However, in the embodiment of Figures 4A and 4B, the portion of the epitaxial structure 336 filled in the lower portions of the trenches 122, 124, 126 is limited to the heavily doped region 532 at the bottom of the trench and can only be N-doped. Figure 7 is a preferred embodiment of a five-position position of the drain contact window of the trench type MOS field effect transistor of the present invention. The figure shows the angle of the lightly doped substrate 110. In the present embodiment, the element area A1 is located at the center of the lightly doped substrate 11A, and the wire area A2 and the terminal area A3 are sequentially located outside the element area A1. The contact window 128 is stepped around the circumference of the lightly doped substrate 11 . However, the invention is not limited thereto. The contact window 128 may only surround a portion of the side of the lightly doped substrate or may be formed on the surface of the lightly doped substrate 11(). Next, referring to FIG. 2G, in the foregoing embodiments, the heavily doped region 132 at the bottom of the trench under the gate structure 150 sequentially passes through the bottom of the trench under the gate wire 160 and the termination structure 170. The heavily doped region 132 is electrically connected to the conductive structure 196. However, the invention is not limited thereto. With the change of the arrangement position of the 'element, the gate line 160, the termination structure 170 and the contact window 128 on the lightly doped substrate, the heavily doped region 132 at the bottom of the trench under the gate structure 150 can also be directly electrically connected to The conductive structure 196 does not pass through the trench bottom doped region 132 located under the gate conductor 160 and the termination structure Π0. In addition, as shown in FIG. 2G, in the foregoing embodiments, the opening of the contact window 128 and the opening of each of the trenches 122, 124, 126 are located on the same side of the lightly doped substrate 110. However, the invention is not limited thereto. The contact window 128 may also be formed on the lower surface of the lightly doped substrate 11 or on the side of the lightly doped substrate 110. Compared with the conventional trench type MOS field effect transistor, the present invention has the following advantages: 1. The method for manufacturing the trench power semiconductor device provided by the present invention, 201246496 can be made by the guest but the f crystal layer can help To reduce production costs. The gate conductive structure and the secret itir are the surface, which is beneficial to the subsequent continuation process. Above the substrate, Table 3, the thickness of the lightly doped region between the trench power semiconductor and the conductive channel region 13G provided by the present invention helps to reduce the above, only for the present invention. The invention is not limited to the scope of the invention, and the invention is still in the scope of the invention. The scope of the file is found in the summary section of this appendix. To limit the invention [simplified description of the drawing] Oxygen half-field effect electro-crystals are schematic diagrams. The second method is not the invention of the grooved galvanic half-field effect transistor. The manufacturing method of the (4) touch-type half-field electric power (4) shows the manufacture of the trench type gold-oxygen half field effect transistor of the present invention. The manufacturing method of the trench type gold-oxygen half field effect transistor of the present invention shows the application of the invention to the insulated open double Polar crystal (Teng) - more money and half-new electricity - contact window
S 12 201246496 【主要元件符號說明】 重摻雜基板:io 、… 輕摻雜磊晶層12 閘極溝槽14 閘極介電層15 閘極結構16 井區17 源極彳梦雜區18 層間介電層19 輕摻雜基板110 圖案層115 閘極溝槽122 第一溝槽124 第二溝槽126 接觸窗128 溝槽底部重摻雜區132,232,532 接觸窗底部重摻雜區134,534 導電通道區130,530 閘極結構 150,250,350,450 閘極導線 160,260,360,460 終端結構 170,270,370,470 井區152 表面摻雜區154,554 重摻雜區156 層間介電層180 導電結構 192，194，196,592,594,596 重摻雜磊晶結構231 磊晶結構336 厚氧化層440 201246496 導電結構442 介電層443 . 元件區A1 導線區A2 終端區A3S 12 201246496 [Description of main components] Heavy doped substrate: io,... Lightly doped epitaxial layer 12 Gate trench 14 Gate dielectric layer 15 Gate structure 16 Well region 17 Source 彳梦杂区18 层层Dielectric layer 19 lightly doped substrate 110 pattern layer 115 gate trench 122 first trench 124 second trench 126 contact window 128 trench bottom heavily doped region 132, 232, 532 contact window bottom heavily doped region 134, 534 conductive channel region 130, 530 Gate structure 150, 250, 350, 450 gate conductor 160, 260, 360, 460 terminal structure 170, 270, 370, 470 well region 152 surface doped region 154, 554 heavily doped region 156 interlayer dielectric layer 180 conductive structure 192, 194, 196, 592, 594, 596 heavily doped epitaxial structure 231 epitaxial structure 336 thick oxide layer 440 201246496 Conductive structure 442 Dielectric layer 443 . Component area A1 Conductor area A2 Terminal area A3