TW201236139A - Semiconductor device - Google Patents

Abstract

This invention relates to semiconductor technology in providing a semiconductor device using two controllable current sources to control electron current and hole current of the voltage-sustaining region of the thyristo when being conducted, such that total current under high voltage between anode and cathode features a saturated characteristic, so as to prevent current concentration of an individual region in order to increase reliability of the thyristor. This invention also provides the method for realizing two current sources inside the device and speeding up the process from turn-on to turn-off and from turn-off to turn-on.

Description

201236139 VI. Description of the Invention: [Technical Field] The present invention relates to the field of semiconductor technology, and more particularly to high power components. [Prior Art] A vertical high-voltage semiconductor element of the tenth is required to have a high-resistivity semiconductor material as a voltage-sustaining region. In the prior art, in the components such as thyristor, GTO (Gate Gate Turn-Off Thyristor), MCT (m〇s control thyristor), unbalanced carriers are used, so that high resistivity is used. The conduction voltage drop in the voltage-sustaining region is greatly reduced. In GTO and MCT clamped by an external signal control element, a current concentration effect is often encountered, resulting in component damage. This is because such components themselves utilize the regenerative effect, and the voltage of each local or each cell is increased, and the current of the local or the cell is greatly increased, resulting in current concentration. This effect greatly reduces component reliability. References [1] Chen Xingyu, "A High Speed IGBT", ZL200910119961.3, and USAppl. No. 12/712,583 (2010); [2] Chen Xingyu, "A Surface Withstand Voltage Region for Semiconductor Devices," ZL 95108317.1 ' and US 5,726,469 A ; [3] Chen Xingyu, "Low-Voltage Power Supply", Chinese Patent Application No. 201010000034.2 'Publication No. CN101719721 A, Publication Date 2010.06.02 〇201236139 Summary of the Invention One of the objects of the present invention is: in steady state In the on-state case, the current increases sharply as the applied voltage across the high-voltage-resistant component increases; the applied voltage further increases, and the current tends to be saturated. This saturation current changes as the signal that controls conduction turns. A second object of the present invention is that the element does not produce a current concentration effect in the time period from pinch to conduction and after the time to full conduction when the element is originally clamped and has a signal to control conduction. A second object of the present invention is that the element does not produce a current concentration effect in the time period from conduction to pinch when the element is originally conducting and there is a signal to control the pinch. The fourth object of the present invention is that when the components are clamped, the number of two carriers in the voltage-sustaining region is gradually reduced by eliminating the two carriers to the withstand voltage region (in this case, the drift region). Injection). This method can achieve the purpose of fast clamping. The contents of the present invention are described below by providing specific examples. 1 . Embodiments of the present invention provide a semiconductor device having a working region on a first main surface of a semiconductor (the uppermost surface of the semiconductor in each drawing) and a second main surface (the lowermost surface of the semiconductor in each of the figures) Between the two types of το cells or the second type of cells or the third type of cells or both of any two or all of the three types of cells; the characteristics of the first type of cells (Figure), Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 1, Figure, Figure 12 and Figure 12): The first zone (11 inches in each figure, or 11〇 and 1〇3 together) 4 201236139 Main pressure zone 'all or most of the range is lightly doped; one side of the first N zone and one of the heavier doped A p-region (each map...〇) is connected; the other two P regions of the first one (12〇 in each figure) are connected; and the second P region (in each figure) At least a part of the other side of 12〇) is connected to a second N zone (13〇 in each figure); the first N zone (the disk in each figure) and the first one Controlled current source The first chasing phase of the (200 in each figure) is coupled, and the second region (120 in each figure) has another portion and a second controlled current source (each graph) The first one of the 300) is coupled, and the two second turns of the first and second controlled two current sources are coupled together and are coupled to the first conductor 'Shaw-first conductor a first pole (Κ in each figure) as two controlled electrodes; the second main surface has any one of two electrode connections: the first connection is only a second conductor (each The thick black line connected to 〇1 in the figure is coupled to the first Ρ region (101 in each figure), and the second conductor serves as the second electrode of the two controlled electrodes (in each figure) The second connection is that in addition to the second conductor, there is a third conductor and a lightly doped first Ν region (110 in each figure) passing through a question area (Fig. 4 (sentence or Figure 4 (f)) is connected, the third conductor is the base (b of Figure 4 _); the first controlled current source controls the flow through the first N zone (11 各 in each figure) ) the electronic flow 0丨0 to "〇门( ^""", the second controlled current source controls the hole current flowing through the first N zone (11〇 in each figure); controlling the two carrier currents The current source controls the current between the two controlled electrodes (electrode A and electrode κ); 5 201236139 The second type of cell has the following characteristics in addition to the characteristics of the first type of cell, The first N zone (110) also has a region directly communicating to the first major surface (N zone 11〇 in FIGS. 13, 14, 15, 16 and 17) having the first insulating layer (162 in FIG. 13 and 162 in FIG. 14, FIG. 15, FIG. 16, and FIG. 17), the insulating layer also covers the second P region on the first main surface (122 in FIG. 13 and FIG. 121) in FIG. 15, FIG. 16, and FIG. 17, and a second N-region (132 in FIG. 13 and 130 in FIG. 14, FIG. 15, FIG. 16, and FIG. 17), the top of the insulating layer is covered with a conductor. (Gon in Figs. 13, 14, 15, 16 and 17); the first N region connected to the first major surface (11 in Figs. 13, 14, 15, 16 and 17) 〇) and the second n-zone (132 and Figure 14 in Figure 13, 15. 130 in FIG. 16 and FIG. 17 respectively constitute a drain region and a source region (source regj0n) of an n_MIS (Meta-Insulator-Semiconductor). The second P region (122 in Fig. 13 and 121 in Fig. 14, Fig. 15, Fig. 16, and Fig. 17) serves as a base region (s〇u "ce_b〇cJyregj〇n"), and the conductor covered at the top of the insulating layer serves as a conductor The gate of the n_MIS; the gate is added with k to control the current of the drain region and the source region of the η - ΜIS; the third type of cell has the following features in addition to the characteristics of the first type of cell; One side of the second sputum (601 in Figure 18) is covered by a second insulating layer (660 in Figure 18), which also covers the edge of the work area. The other side of the P region (6〇2 in Fig. 8) which is the junction edge termination region (juncj〇n edge termination regi〇n); the junction edge termination region (junctj〇n edge termination region) is The working area boundary of the semiconductor element on the first main surface starts as the first side opening 201236139 until the two controlled electrodes (electrical The region between the first electrode and the electrode κ) that has no electric field even if a high voltage is applied is present (the one in Fig. 18) ends as the second side; the second insulating layer (the heart of the figure 660) The top of the ) has a conductor covering as a pinch gate (0 in Figure μ). The junction edge termination region is provided with a low voltage circuit outside the second side (the low voltage circuit in FIG. 19 is provided with two output ports (the _ and Β in the region of FIG. 19), and the first output 皡The second electrode (electrode A) of the semiconductor component is coupled by one conductor 'the second output 埠 is connected to the base of the second connection (B in FIG. 19) through the other conductor; The low-end waste, the sacrifice + | 7 low-voltage circuit has two input ports, and the first input Tan can be the _ zone in Figure 19, or it can be controlled with two

A region of the first N region where no electric field exists even if a high voltage is applied between the electrodes is directly connected, and an input 埠 of the first electrode is a control of the low voltage circuit (81 图 in Fig. 19) , the channel μ~ 匕 is connected by a conductor to a region of the junction edge ending in the vicinity of the second side; when the clamping gate (r, ndt, u 〒 G0 in Fig. 18) When a pulse signal is added, there can be a large current flowing between the two output ports of the low-voltage circuit (A and B in the 800 area of Fig. i 砰, 圃 19), and the voltage between the two wheel nets is very low. Thus, the first P zone (1〇1) is not smashed) and the first N zone (110 of each figure) is injected into the hole. 2. Refer to Figures 4(c) and 4(d). According to Zhao, +. 4 θ ^ ; according to ", the base (electrode Β) 上述 in the above 1 is directly connected to the second electrode (electrode phase), instead of passing through another conductor and the low voltage circuit The second one is adjusted to be connected to the rod. 3. The above two current sources can be connected to the first and second controlled current sources of 筮_ & „ μ of the first controlled current 7 201236139 source (200 in each figure) The first current source of 300) in each figure, the two current sources of the 扪 扪 。. The present invention also provides a method that can be done inside the component as follows. Referring to Figure 5 and Figure 13, the whistle & Separating the first p. According to the first P described in the above 1, the three sub-zones are separated by a first N-zone (m), and each sub-four has its own second Each of the two N regions in the three sub-regions is surrounded by the second P region (121, 123, 122) and the first main surface; the first one The doping dose of the second N region (13〇) in the sub-region is much larger than the doping dose of the second P region (121) in the first sub-region, and the second N in the second sub-region The doping dose of the region (131) is much smaller than the doping amount of the second p region (123) of the second subregion. The second N region (132) and the third subregion of the third subregion Second P area (1 22) a first ohmic contact (FOC) is coupled to the first main surface, and a second P region (14 〇) is present within the second inter-region (n) of the third sub-region, the third There are two n-MISs in the p region (14〇) to >, 3, the source regions (202 and 302) of the two n-MISs, and the third P region (14〇) constituting the base region at the first The main surface has conductors (conductors constituting the electrode K) coupled to form a first electrode of the two controlled electrodes (electrode K); the two n-MIS drain regions (201 and 301) are respectively associated with the first The second N zone (13〇) in the sub-zone and the second N zone (131) in the second sub-zone are connected by wires; at least two insulating layers (260 and 360) on the first main surface Each covers a part of the source regions (2〇2 and 302), some of the drain regions (2〇1 and 3〇1), and a base region (14〇) therebetween, and the two insulating layers have conductor covers as two The gate of n_Mis (G. ” 〇2 ) 'The two gates respectively control two electric 8 as two kinds of carriers 201236139

4. Reference β _

The doping dose of the region (131) is greater than the second p region (123) of the second subregion, and the second (132) and the second P region (122) of the third subregion are used for the first major surface. The floating ohm is as described in the above 1: The sub-regions have an insulating groove (the second ΝΙ region of each of the 171 (the doping region of the second Ν region (130) in the 130 (1 21)) Gentleman

The doping dose is much smaller, the second PH contact (FOC) of the third and third sub-zones is connected; and the third crotch zone within the third sub-region of the third sub-zone (13" 140), the third ρ region contains at least two n-MIS, two η_Μ丨S source regions (2〇2 and 3〇2) and constituent groups

The conductors of the crucible are coupled to form a first electrode of the two controlled electrodes (electrode Κ); the drain regions (201 and 301) of the two n_MIS and the second N region of the first sub-region, respectively (130) and a second N-zone (1 31) in the second sub-region are connected by wires; at least two insulating layers (260 and 360) on the first main surface, each covering a part of the source regions ( 202 and 302), part of the non-polar region (201 and 301) and the base region (140) therebetween, the two insulating layers have conductors covered as two n-MIS gates (〇1 and G2), these two The gate controls the current of the η-MIS of the two current sources as two carriers, respectively. 5. Referring to Figure 8, the second ρ region can also be partially separated by an insulating groove. 9 201236139 According to the second p described in the above 1, it is divided into three sub-areas, and three sub-areas are connected with some second P-regions (122 and 121 are connected, also connected to 1 23), and other parts are The insulating grooves (i 71 and i 72 ) are separated, and each sub-region has a respective second question region (13〇, 131, 132); wherein the second Ng (13〇) in the first sub-region The doping dose is much larger than the doping dose of the second P region (彳21) of the first sub-region, and the doping dose of the second N region (131) in the second sub-region is lower than that of the second sub-region. The doping dose of the second P region (123) is much smaller, the second N region (132) in the third subregion and the second p region (122) in the third subregion are used on the first major surface. The floating ohmic contact (F0C) is connected; there is a third P zone (14〇) in the third two N zones (10), and the = P zone (140) contains at least two n_M丨s, two The source regions (202 and 302) of Bu (4) and the third p region (彳4〇) constituting the base region are coupled with a conductor (a conductor constituting the electrode κ) on the first main surface to form two controlled electrodes. First electrode Extreme κ); two η·Μ|3 bungee regions (201 and 301) and a second N region (13〇) in the first sub-region and a second self-N 1 in the second sub-region (13" is connected by wires; at least two insulating layers (26〇 and 36〇) on the first main surface, each covering part of the source regions (202 and 302) and partial non-polar regions (2()1 With 3〇1) and the base region (140) 'The two insulating layers have conductors covered as two n-MIS gates ((51 and g2), which are controlled as two kinds of carriers respectively The current of the two current sources of the stream. 6 · Referring to Figure 6, the three sub-regions of the second p-region can be closed. According to the second p described in the above 1, the three sub-regions are divided into three sub-regions. The second P zone (121, 123, 122) is connected to each other, 10 • 201236139 Each subzone contains its own second N zone (13〇, 13彳, 132), and each of the three subzones The second N region (13〇, 131, 132) is surrounded by the first P region (121, 123, 122) and the first major surface; wherein the second Ng (13〇) in the first subregion The doping dose is the same as that of the first sub-region The doping dose of the p region (121) is much larger, the doping dose of the second N region (131) in the second subregion is smaller than the doping dose of the second P region (123) in the second subregion. Much smaller, the second n-zone (132) in the third sub-region and the second (122) of the third sub-region are connected by floating ohmic contact (F0C) on the first major surface; the third sub-region There is also a third relaxation zone (14〇) within the second (four) zone (10)), the third P zone (140) containing at least two n_M丨s, two source zones (202 and 302) a third p-region ((iv)) constituting the base region is coupled to the first main surface with a conductor (conductor constituting electric #K) to form a first electrode (electrode κ) of the two controlled electrodes; The drain regions (201 and 301) of 胄_ are respectively connected by wires with the second _ in the first sub-region and the second N region (131) in the second sub-region; at least on the main surface There are two insulating layers (26〇 and 36〇), each covering part of the source regions 202 and 302), some of the drain regions (2〇1 and 3〇1) and the base region (SOUrce_body regi〇n) ( 14〇), on two insulation layers As the conductor is covered two n_MIS gate ((31 and G2), the two knife gate current as the other two control current sources of both carriers Bu. 7. The second sub-region of the second P region has (131 in Fig. 3), and the conductor is connected to the other p region (133 in Fig. 3) in addition to the N region. Refer to Figure 3. 11 201236139 According to the second n zone (1 31 ) in the second sub-region of 3-6 above, the conductor is connected, and the conductor is also connected to a P zone which is not connected to the second p zone (1 33 ). 8. The current source of the second p-region can be placed in the third sub-region. Refer to Figure 12. The method of coupling the other portion of the second P region (12 各 in each figure) described in the above 1 with the first 珲 of the second controlled current source (3 各 in each figure) is Making an N zone (132) surrounded by the second P zone and the first major surface and connected to the second p zone by the floating ohmic contact (F〇c) on the first major surface, and then a third P region (140) surrounded by the n region and the first major surface, the third p region containing at least two n-MIS, two n-MIS source regions (202 with 302) and a third P region (140) constituting the base region is coupled to the conductor on the first main surface to form a first electrode (electrode κ) of the two controlled electrodes; two n MIS; a bungee region in the region has a p region (143) surrounded by the immersion region (ΜΑ) and the first major surface, the p region having a wire coupled to the first P region (123); At least two insulating layers (26〇 and 36〇) on a major surface each cover a portion of the source regions (202 and 302), a portion of the drain regions (201 and 301), and a base region (14〇) therebetween. On the two insulation layers As the shutter member to cover two poles S n_M Shu (Gi and g2), the two poles apart knives do not control the current as the two current sources both carriers of the n-M S, Shu. 9. The current source can be placed in SIS (Silicon lnsLI|at〇r Silicon). Refer to Figure 9 and Figure *. The two current sources as described in the above 1 are formed in the third turn region 12 201236139 (140), and the third p region is isolated from the other semiconductor regions with insulators (in, 172, and 173). An embodiment of the present invention also provides an automatic voltage method. Refer to Figure 15. The gate (G〇n) for 'n_M|s of the second type of cell described in the above 1 is connected by a wire to one of the first N regions (11〇) in the first main table Doping a larger dose of the N region (111). 11 Embodiments of the present invention also provide a method in which two current sources have neither a current in the second N region nor a current in the second p region, despite the presence of a control voltage in their control electrodes. That is, the method of adding Gw, referring to FIG. 16 and FIG. 17β, there is no need to clamp at this time. According to the third sub-area of the above 3, 4, 5, 6, 9 and 1 ,, the second Ρ area is used as the source area (123) of the P-MIS, and the second Ν area is used as the a base region (132) of the p-MIS, the third ρ region serving as a drain region (140) of the P-MIS, and a portion of the first main surface from the portion of the source region through the base region to the drain region Insulation layer ('63), this insulating layer is covered with a conductor, which is used as p_M|S (G〇ff), when the voltage is applied to the gate to turn on p-MIS, the second ρ region (123) and the first There is only a small voltage between one electrode (electrode K) (it is less than 77 volts for the 矽 element. From the existing semiconductor knowledge, the method to achieve this kind of small voltage can also be An n_ms is formed between the second N zone (彳32) and the third P zone (140) in the third sub-region. 1 2 . In order to prevent the voltage between the two ends of the current source provided by the present invention from being too high The present invention also provides a method of clamping the voltage at both ends. Refer to Figures U, 12, 14, 15 and 16° 13 201236139 as described in Figures 4, 5, 6, 8, 9, and 11 above. Two p zones Two series-connected diodes are formed between (1 22 ) and the third p-region (彳4〇) by making an N-region (126) in the second P-region (122) to form the first One pole; in the third p region (14〇), an n region (142), which in the N region is a p region (141), forming a second diode; the second diode Ng(142) is coupled to the third p-region (14〇) in the first major surface conductor (the conductor of the electrode K); the N-region of the first diode passes through the conductor and the second diode The p regions are coupled. 13. The invention also provides a low voltage with respect to the first electrode (κ in each figure) using a heavily doped N region disposed on the first major surface of the first n region The method of power supply is used to provide the electrical energy required at the input of the two current sources of the third aspect of the invention, with reference to Figure 21. According to the first type of cells described in the above 1, one has a first major surface and The first doped region (11〇) is in direct contact with the heavily doped germanium region (111). This tantalum region has direct contact with the conductor (electrodeΗ) on the first major surface, and a floating ohm on the first major surface. Contact (F〇c) The second ρ zone (120) is coupled to the second Ν zone (132) in the second ρ zone (12〇), and a third 卩 zone (14〇) is in the In the second crotch region (132), there is a third (146) in the third crotch region (140), and a fourth p region (145) in the third a fourth germanium region (146); the fourth germanium region (45) has a direct contact with the conductor on the first major surface, and the conductor in contact with the heavily doped germanium region (11) through the wire The (n) phase is coupled; the third germanium region (146) has a direct contact with the conductor (F) on the first major surface, which is coupled to a capacitor (one end of the CO) through a wire, the other end of the capacitor The first electrode (κ) of the two controlled electrodes of 201236139 is coupled; the capacitor acts as a power supply for the low voltage circuit disposed in the third ρ region (140), and the input terminal (Gc) of the low voltage circuit is externally connected The control voltage, the output of the low circuit is the control voltage as a controlled current source or as the second ρ zone (12 〇) control voltage. 14. The present invention also provides a low voltage circuit other than the junction end edge region of the second electric # (A in each figure) (juncti〇n edge "(7)... regj〇n) For the power supply, refer to FIG. 2, 〇β is provided with a conductor on a small area under the first main surface in the second side of the junction edge termination region described in the above 1, and the conductor is connected through the wire. A crotch region (8Q2) outside the second edge of the edge termination region is coupled; the N region is surrounded by a p region (8〇) except the first main surface, and the P region is in the first main The surface has a direct contact with a conductor which is coupled to one end of a capacitor (C〇) by a wire; the other end of the capacitor (c〇> and the first N region outside the first edge of the junction edge termination region ( 11〇) phase-connected; the capacitor (C〇) acts as a power source for the low-voltage circuit disposed outside the second side of the junction edge termination region. [Embodiment] The present invention will be more fully described below with reference to the accompanying drawings. The exemplary embodiments of the present invention are described. In all the tissues, the same numbers represent the same meaning. The conductors in the drawings of the present invention are collectively indicated by thick lines, and will not be described again in the future. The active region of the thyristor of the present invention (active "egj〇n" principle of the knot 15 201236139 structure and its simple equivalent circuit as shown Figure 1 (a) shows the schematic structure of the active region of the present invention. The lowermost electrode A of the figure is the anode 'which is coupled to the first p-region 1〇1 by a conductor for injecting a hole To the lightly doped first N region 11 〇, the n region 11 〇 is a voltage-sustaining region. There is a second P region 120 above the pressure-resistant region. The second p region 彳 2〇 The upper right portion is connected in series to a current source 300 via a conductor and then coupled to the cathode κ. Thus, when the applied voltage VAK is greater than zero, the p-region 1〇1, the N-region 11〇, and the p-region 12〇 constitute the first electricity. The emitter region, the base region and the collector region of the crystal (PNP). In the upper portion of the left side of the second P region 120, there is a question region 13〇, which is connected in series to a current source 200 via a conductor and then connected to the cathode κ. When vak

When it is greater than zero, the N region 130 can emit electrons to the p region 彳2〇 region, and then the electrons are taken away by the N region 11〇. Thus, the interrogation zone 130, the Pg 120, and the interrogation zone 11〇 constitute the emitter, base, and collector regions of the second transistor (NPN). The equivalent circuit formed by the connection of two transistors to two current sources is shown in Figure 1 (b). The structure shown in Figure 1(a) differs from the GT〇 and MCT in that there are two current sources. The purpose of sighing two current sources is to ensure that the two carrier concentrations in the withstand voltage region 110 satisfy the following conditions as much as possible in the presence of a current: np-ND + «0 (,) where η is the electron concentration , p is the hole concentration, and Nd+ is the effective ionization donor concentration of the 11 〇 region. When the current is large, and thus n and p are both much larger than ND + , if n >> p, the withstand voltage zone is subjected to an external electric house, and its function is like a heavily doped P zone, which cannot withstand very high Voltage. If 16 201236139 >n' acts like a heavily doped N[i, it cannot withstand very high voltages. Both cases cannot achieve current saturation at large voltages. Note that in Si, when the electric field strength is greater than 2x1 〇 4v/cm, the speeds of electrons and electricity are approximately equal to their saturation values ^ and vSh. When the electric field strength is above 2x 10 V'cm, there is a significant impact ionization rate. Therefore, the above conditions only require the ratio of the electron current to the hole flow in the early area to be (je/jh) = (vSe/vSh). Since it is in the Si towel, only the electron current is required to be equal to the hole flow. According to the method of FIG. 1, since the p-region 12〇 and the N-region 13〇's PN junction Guncti〇n) are to be positively biased, so that there is an injection, the potential of the 120-zone connected to the 3〇〇 is more than 200. The potential of the n region 130 is high. In the middle of the high (four) _7V or so 'this obviously needs to consume more power per unit area. To this end, like the schematic structure shown in Fig. 2 (8), we can divide the uppermost n region into a heavily doped 130 and a lightly doped N region 131. At the same time, the doping amount of the 12-zone 12 〇 around W 130 is made very low; the doping dose of the P region 120 around the N region 131 is made high. Thus, 彳 and PS 12 〇 constitute a Ν, Ρ · junction 'the current through which the electron flow is dominated by 1 zone (3) * PS 120 constitutes a Ν·_ρ + junction, the current through which the hole flows the Lord. Fig. 2(b) is a simple equivalent circuit diagram of Fig. 2(a). The conductor of 300 in FIG. 2(a) coupled to the crotch region 131 may also be in simultaneous contact with a & region 133 as shown in FIG. 3(8). This connection is equivalent to a ρΝρ transistor in which the collector junction of the ρ region 120, the Ν region 131 and the Ρ region 133 is short-circuited, and the equivalent circuit is as shown in Fig. 3(b). The lower portion 100 of the withstand voltage region 110 of Fig. 1 (8) has several structures, as shown in Fig. 17, 201236139. Head 4 (4) is that the withstand voltage region 11G is directly connected to the P region 101, and the p region 101 is connected to the electrode A. 14 (b) is different from the case of Fig. 4 (8). An N region is added between 11 and 1〇1. 3 as a buffer layer, N (I 1 〇 3 has a heavier doping concentration than 110, but is relatively thin. Figure 4 (c) shows an anode short circuit connection, electrode A is in contact with p region 1 〇 1 It is also connected to the withstand voltage zone 11 by contact with the N zone 102. Sometimes the effect of the anode short circuit is better. 'There is a N zone 103 below the I 110 which has a heavier doping concentration than the 11 ,, as shown in Fig. 4 (d Fig. 4(4) is a structure in which the N withstand voltage region 11〇 is connected through a NH 1 02 as a base, and Fig. 4(1) is more effective for the anode short circuit on the basis of Fig. 4(e). There is a structure of a heavily doped N-zone 1〇3 on the 1〇彳 and the top. Figures 4(1) and 4(e) are used for quick clamping, the usage of which will be described later. , regardless of which one of the diagrams shown in @4(a), Fig. 4(b), Fig. 4(g), Fig. 4(d), @4(e) or Fig. 4(f), for simplicity For the sake of reference, we all use Figure 4(a) to show it. Just pass the N pressure-resistant zone 11 When the n-zone 彳〇2 is connected as a base method, the method shown in Fig. 4(e) is used regardless of the use of Fig. 4(e) or Fig. 4(f). The current sources 2〇〇 and 3〇〇 may not be external to the wafer, but are made inside the wafer of the component. Figure 5(a) shows a cell that does this. Here, the p region is 彳2〇 divided into three independent p

Zone: 121, 122, 123 ′ Set the N zone 130 in the P zone 121, N

The area 1 31 is set in the P area 1 23 . The current source is disposed in the p-region 14A, 140 is surrounded by the N-region 132, which in turn is coupled to the P-region 122 at the surface by a floating ohmic contact (FOC) on the first major surface (the uppermost surface). The P region 140 serves as a base region for two n-MISs, which are coupled to the source regions 202 and 302 of the two n-MIS 18 .201236139 via conductors, and the two non-polar regions of the n_M|S are N+ regions, respectively. 201 and N + regions 301 each having a conductor D to the electrode D! on the N region 130 and an electrode d2 on the N region 131. There are two insulators 260 and 360 covering a portion of the source regions of the two n-MISs, a portion of the base region and the drain region, respectively. A conductor on the insulator constitutes two n-MIS gates G1 and G2. Controlling the voltages of G1 and G2 controls the currents of the two η - Μ丨S, thereby controlling the current flowing through the n regions 1 3 〇 and n regions 131. In the actual design, the doping amount of the germanium region 12 Ρ can be made much smaller than the doping amount of the germanium region 1 30 surrounded by it, so that the current flowing through the germanium region 主要 3 主要 is mainly a downward flowing electron current. In contrast, the doping amount of the ρ region 彳 23 is much larger than the doping amount of the Ν region 1 31 surrounded by it. Therefore, the current flowing through the ρ region 彳 23 is mainly an upward flowing current. The PN junction formed by the 彳3〇 and ρ areas] and the p_N junction formed by the P area 123 and the N area 131 are both 〇7V in the forward direction (for the case of 矽) ^ The two n-MISs are done completely, and the current flowing through the two pN junctions is not equal. The voltage of the two n_MIS flowing will not be equal to the larger current side, resulting in a large voltage drop. The voltage drop of the PN junction voltage becomes small. With this principle of negative feedback, it is easy to achieve equal or nearly equal requirements for the flow of electrons and the flow of holes. Fig. 5(b) is a simple equivalent circuit diagram of the structure of Fig. 5(a). In order to realize the two current sources 2〇〇 and 3〇〇 in Fig. 2, it is not necessary to divide the S picture into three independent segments, but the three segments can be connected together. Figure 6(a) shows the structural schematic for achieving this goal. Here, the area number and! I 5, the working principle is no longer described. It is worth mentioning that the doping dose of p region 122 in scoop w can be heavier, making its lateral resistance 19 201236139 smaller. Thus, the voltages on both sides (p region 121 and p region 123) are not unequal due to the occurrence of lateral current. Fig. 6(b) is a simple equivalent circuit diagram of Fig. 6(a). It is also possible that the question area 13A and/or the N area 131 in Fig. 5(a) or Fig. 6(a) are not completely surrounded by the P area 121 and/or 123. This is the use of groove technology. Fig. 7 is a schematic view showing a method of completely separating three media 171 and a medium 172 of Fig. 5 (a) or Fig. 6 (a), and Fig. 8 is a view of Fig. 5 (a) or Fig. 6 (three P zones) Schematic diagram of a method partially separated by a medium. In these two figures, 'N zone 13 〇 and N zone 131 only the bottom is connected p zone and its side is surrounded by no P zone" in Figure 5 (a) or Figure 6 ( a) Use n_MIS to do two current sources. This is because it requires less drain-source voltage at the same on-current, which can save conduction loss. In order to achieve n_M|S, a p-type base region is required. 〇, and this P zone cannot be replaced by P zone 122. Otherwise, the hole injected by p region 1〇1 will flow directly into electrode κ through P zone 122, losing the ability to control the equal current of the two carriers. An N region 132 equal to the potential of the p region 彳22 is added. If the current source is made in a semiconductor region insulated from other semiconductor regions, the N region 1 32 is not necessary. Figure 9 shows such a method. 'The method is to separate the current source region (current s〇urce region) with insulators 171 and 172 (for example, using Ding "clamping technology", and below The insulators 73 are spaced apart (e.g., using the S|S technique), and the base region is the p-region 140. There is also a certain flexibility in the method of isolation. For example, a portion of the germanium region 122 may remain in the isolation region. Lower _, as shown in Fig. 〇. This will make the hole through the pressure-resistant zone 110 have a larger passage to the upper layer. At the same time, 20 201236139 can also bring the potential between the P zone 121 and the P zone 123 closer, making the resistance The electron flow density in the nip is closer to the hole flow density. In Figure 11 (a), a PN diode composed of a P region 122 and an N region 126 is extracted, and 126 is connected to the P region 141 through the interconnect. The latter is located in the n region 142 'and thus forms a diode." The N region 142 is directly coupled to the P region 140 and the cathode K by a conductor. That is, there are two diodes from the P region 122 to the cathode K. Thus, even if the p-region 1 22 to K has a large current, the voltage between the two does not exceed the sum of the forward voltage drops of the two diodes (about 1.5 V in the Si element), which can be avoided. At high currents, the leakage currents of two n-MISs controlled by G1 and G2 are too large. In other words, the two diodes act as a clamp. FIG. 11(b) is a simplified equivalent circuit diagram of FIG. 11(a). The figure is fabricated in the element of the present invention, and the current source 3〇〇 in FIG. 2 is further omitted. There is a method of making the PN junction formed by the p region 123 and the N region 131 in the two figures within the p region 14A shown in Fig. 5(a) or Fig. 6(a). The ground is shown in Fig. 12(a). In this figure, the drain region of n M|S controlled by G2 is an N-type region 144, and in 144, a p region 143 is formed, and 143 and 144 form a PN junction. 143 is connected to the P area 123 through the line F 〇c in the figure. Fig. 12 (b) is a simple equivalent circuit diagram of Fig. 12 (a). While each of the above structures can turn the component on, the time required to enter the conduction state from the pinch state may be long. This is because, in order to make the P-zone 101 have a hole/main entry into the N-zone 11 先决, the prerequisite is that electrons are taken from the n-zone ^ 3 〇 through the p-region 121 to the N-region 1 1 〇 'and reach the p-region] 〇1 flows out from the electrode a. And k requires P zone 12 " 十问区13〇 has a forward bias (in the s丨 component 21 201236139 is about 0_7V) 'and p zone 121 must have forward bias and must rely on p zone 1〇1 Hole injection, this loop process takes a long time to regenerate the thyristor. In order to speed up the opening speed, we can try to make the component start from the beginning of the opening, the electron does not enter the pressure-resistant zone 11〇 from the N zone 130 through the crotch zone 121, but directly enters the withstand voltage zone 11 (Fig. 13(a) shows A structural diagram of such a method is based on the structure of Fig. 5(a), using N-zone 11 〇 as the N-zone 201 of the non-polar region 卩 作为 as the source region. There is an insulating layer on the surface. 161 covers the two regions and the p region 122, the N region 132 and the p region 14A. The insulating layer 161 has a conductor as a gate of n_M丨s, which is called an opening gate G. The opening gate Gon is connected with the G1. Together, two n-MISs are connected in series that share a gate signal. From the pinch state to the initial stage of the turn-on, both ns are turned on. 'There is electron flow to the N region, 1〇. Because of these two n_M|s It is connected in series 'so the total electron flow is still controlled by the gate Gi, so that the electron flow and the hole flow (controlled by G2) are always equal after being turned on. Fig. 13(b) is the equivalent circuit of Fig. 13(a) Schematic. The acceleration start process can also use different gate signals for h and G〇n, and Figure 14(a) shows one such structure. It is N 1 13G of the figure as a source region, p region 121 as a substrate region, N region 110 as a non-polar region, and an insulating layer 162 covering a portion of the N region 13 〇, the p region 121, and a portion of the N region 110, on which There is a conductor to form the gate electrode. Fig. 14(b) is a simple equivalent circuit diagram of Fig. 14(a). This month also provides a method for automatically obtaining the required voltage of G. " as shown in Fig. 15(a) It is shown that there is a N withstand voltage zone 111 at the boundary of the N 1 -cell cells connected by .1 to 10, which is large in VAK and the current is very small. 22 201236139 will be exhausted 'its unconsumed The area is opposite to the P area 121. There is a conductor contact in the positive depletion zone, and the connection is connected to the 6th. After the vAK is reported, the zone is subjected to the lightning pressure of the P zone 121. R- pad is lowered. Therefore, this area is suitable for use as a voltage for turning on. Fig. 15(b) is a simple equivalent circuit diagram of Fig. 15(a). The process of the element of the present invention from the on state to the pinch state, In principle, the current controlled by 彳 and G2 can be gradually reduced, but the regenerative effect of the formation of the two transistors will take a long time. The method of short-circuiting the anode, that is, the method shown in Fig. 4(G) and Fig. 4(d), can also speed up the pinching process. This is because when the electron flow through the N-zone 11 is small, P! 1 The voltage with respect to 1Q2 is small (for example, 'less than 〇·5ν for Si elements) 'μ 1〇1 is almost no holes and then injected into 110. At this time, the regeneration of the thyristor no longer exists. The method of short-circuiting the anode can only make the voltage of the P-zone 101 relatively small with respect to the N-zone 1〇2 when the current is small to a certain extent. To this end, the present invention also provides a fast-clamping square & This method is to add a gate G〇ff for clamping. Fig. 16(a) shows a method of adding a pinch gate to Fig. 14 (on the upper surface, starting from a portion of the p region 彳23, passing through the N region 1 32 to the p region 140 A portion is covered with an insulating layer 彳63, and the insulating layer is covered with a conductor as a pinch gate. This is a p-region 123 as a source region, N region 132 as a base region, and p region 14 is a bungee region. p_M丨s. When the GoffK voltage is lower than the threshold voltage of the MIS and the M|S is turned on, the P region 123 and the P region 140 are turned on. If the p region 123 and the P region 140 are turned on, the conduction voltage is lowered to the positive of the PN junction. The conduction voltage drop (about 77V in the 矽 element), there is almost no current between the P area 123 and the N area 131. Similarly, the p area 121 and 23 201236139 N area 1 30 also have almost no current. Two Π_ΜIS It does not work. At this time, the component is like a PNP transistor composed of P region 1〇1, N region 110, P region 123 (and p region 121 and P region 122), which can be used for very high voltage and almost no current. Fig. 16(b) is a simple equivalent circuit diagram of Fig. 16(a). It goes without saying that it is known from the existing semiconductor knowledge that the p-portion of the p-region 1 23 and the p-region 14 is reduced to the positive of the PN junction. Wizard The method of voltage drop (about 0.7 V for germanium elements) may also be to form an n-MIS between n region 132 and P region 140. In fact, the two clamp diodes in Fig. 16. The two series-connected diodes formed by the PN junction formed by 122 and 26 and the p-N junction formed by the P-region 141 and the N-region 142 are no longer needed in FIG. 16(a) because FIG. 16 When the p-MIS has sufficient voltage and is turned on, the potential difference between 121 (and 122 and 123) and the P region 140 has been suppressed. The structure of the ligandless diode is as shown in the figure. The method of increasing the pinch speed is effective by using the inventor's invention patent "a high speed 16 巳 71 71_2009101 19961.3, and us 叩丨 叩丨 N〇 12/712, 583 (2010)". A number of specific structures have been proposed in this patent. A specific structure is shown in Fig. 18. This figure is a reproduction of Fig. 21 in the patent, except that the symbols of the respective regions adopt the symbols of this patent. Here, P area 602 and P area 600 is a box of your sr & * 楂 as junction edge termination (junctj〇r | edge termination) (four) pressure structure. The region is started from the right side of the P region 601 of the junction electrode K until the left & ^ edge of the heavily doped N region 400 as the field termination region. The surface of the segment is provided with an insulating layer 6 61, which has a conductor 〇8〇, which is coupled to

A resistor Ri, the other end of which is coupled to the N region 400. When the gate 24 201236139 G 该 of the figure has a negative pulse signal and the surface of the N region 11 下 under the gate insulating layer 660 forms an inversion region, the potentials of the germanium region 602 and the germanium region 600 become more Close to the potential of the electrode ,, so that the potential under 661 becomes lower than the value when there is no negative pulse signal on G〇, so the capacitance formed by 080 and the semiconductor surface is charged, and the current of the charging circuit starts from 400, and R| From the conductor 〇8〇 to the P region 600, and finally to the electrode κ. Thus, there is a voltage across the resistor Rj, and there is a pulse voltage on the junction conductors 080 and Ri 埠81 0 with respect to the neutral N region 110. As described above, a principle for generating a pinch-out signal is obtained. As for the N + region 603 and the N+ region 604 and the P+ region 605 and the floating ohmic contact FOC in the figure, the above-described control is irrelevant, and therefore will not be described. In short, a signal having a different polarity can be output from 81 0 at the moment of opening or at the moment before and at the moment of clamping or immediately before. As shown in Fig. 19, a low voltage circuit can be fabricated in the neutral region 800 outside the junction edge termination. 81〇 is used as the input end, and the output ends are two electrodes A and B, which are respectively connected by wires to the electrode A electrode B of Fig. 4(e). When clamping, the electrode A and the electrode B can be made. The voltage is less than the voltage at which the ρ-n junction is turned on (about 77V for Si components). This eliminates the infusion of holes from the lower surface to the N zone 11 〇. The C〇 in the above figure represents a power supply that can be used as a low-voltage circuit in the 800 zone. For a small current component, this power supply is not required. However, for a component with a large current, since the initial phase of the pinch process will have a large current between the electrode A and the electrode B, the low-voltage circuit is required to have a large driving capability. At this time, it is necessary to provide an instantaneous high current. Power supply. This power supply is indicated by the capacitor C〇 in the figure. The present invention also provides a method of charging a capacitor c 25 25 201236139 current. The structure is shown in FIG. 20. The dotted line of the figure represents the edge of the depletion region of the N region 110 at a high voltage when the component is clamped, and the portion of the p region 6〇〇 is the junction edge termination technique. A region which can be patented as "a surface withstand voltage region for semiconductor components, ZL 95108317.1' and Us. 5,726 469 a", which is the best variable doping region, which is nearly depleted in the P region 600. At the edge of the zone there is a conductor in contact with 600 which is connected by wires to W 802 surrounded by a P zone 801 in a neutral zone. The p region 8〇1 has another conductor coupled to the capacitor C. At one end, capacitor C. The other end is connected to the NT zone 803 located in the neutral zone. When the Vak of the component is large (for example, when it is turned off), there may be a current from the rr region 803 through the capacitor c〇, and then through the p-region 8〇1 ^ region 802 to form a forward PN junction, and then through the junction The edge termination zone: zone_flow to Kf which allows the capacitor to be charged. When the capacitor is on (4) = - fixed value, charging stops. This capacitor can be used as a diode of the low-voltage circuit. The diode formed by the UN 80UN region 802 can prevent the automatic discharge of the capacitor c0 when the power supply is not needed.闸 Μ丨 的S gate G B p as a control current source

There is a capacitance on the surface of the At ^ conductor, which can be: from external power consumption. Therefore, it is preferable to determine the positive M of the pair of t by the elemental drive 2 of the present invention to reduce the external motion requirement. In addition, 'from pinch to guide (2) is positive with respect to _13(). If p is favorable for electrons to enter N zone m and then reach negative power plant, £121 has one phase. For κ electrode, positive, · Ρ 开 开 ^ ^ 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本The surface of the region 11 has a heavily doped N region 1 1 1 (see reference [3]). ^ This region is connected to the surface of a p region 145 disposed in the N region 146 by a line, and the Ng 146 has another The electrode F is on the surface, and a capacitance is indirectly from the electrode F to the electrode κ. When VAK>0, electrons can flow from the N + region m to the n region 11〇, and then flow to the lower surface. Then, there is current flowing from the lower surface. After 1 N to the N + region, and then through the PN junction formed by the p region 145 and the N region 146, the electrode F flows to the electrode K via the capacitor C1, so that the capacitor c! is charged. Which structure is in Fig. 4, it is impossible for the hole flow to continuously flow to the electrode κ in the figure. This is because the 'P region 与4〇 connected to the electrode is N region 13 Surrounded by 2, the latter is again connected to the p-region 12〇 by a floating ohmic contact (F〇C) provided on the surface. When the p-region 120 is charged with a positive charge, the p_N junction formed by the N region 132 and the p region 14〇 is In addition, the PN junction formed by the n-region 146 and the P-region 140 coupled to the F-electrode is also reverse-biased after the capacitor C1 is charged. It should also be noted that 'one of ordinary skill in the art will readily recognize that The capacitor of the present invention can be not only an external capacitor, but also a capacitor fabricated inside the wafer 'for example, a Μ丨S capacitor. The positive power supply with the counter electrode 可以 can be conveniently obtained by applying a control signal to the foregoing. The gate voltage required for I and G2, and the positive voltage for the ρ region 1 21 (and the P region 122 and the P region 123). Fig. 21(b) schematically shows this case 'it is in the p region 120 (representing the p region 121 Or a 'P region 140' on the n region 132 formed on the P region 122 or the P region 123 or a similar region) can realize a usual low voltage integrated circuit in the p region 14A. The low voltage circuit has a wire connection. Into the electrode κ and the electrode F as a power source, which is relative to 27 201236139

The output of the electrode K may include 埠 for the voltage of G... and G2, and may also include 埠 for the P region 120. In this case, the voltages of the outputs are both controlled by an input 埠Gc plus a signal. The following is an analogy result according to Figure 14 (4), the bottom of which uses the method of reading the short circuit of Figure 4 (4) 'The specific structure is as shown in Figure 22, here is the use of the bar graph 'the impurity concentration width used in each area ["m 】 and thickness [/zm] are as follows: 110 area: 1χ1〇ΐ4, 57 3〇〇; ι〇ι area: 3x1〇18, 40, 2; 102 area: 1x1〇19,17,2; 12i area: 5χΐ 〇ΐ6, 20, 10; 122 District: 1Χ1017, 17 10; 130 District: 3χ1〇17,10,2 10; 123 District: 5χ1〇17,13,131 District: 2χ1〇16,1〇,7; .1Χ10,15,4; The distance between 2〇1 and 2〇2 is 〇3, the thickness of 260 is G_Q3; the distance between 3G1 and 302 is 0.3, and the thickness of 36〇 is 0.03; two n_MOS The threshold voltage is 3v; the distance between the 110 area and the 13G area below the area is 5, the thickness of the 162 area is 〇〇3, and the threshold voltage of the n_MOS controlled by G0N is '_4V. Models such as SRH, CONMOB, FLDM0B, and IMpACT are used in the analogy, and the lifetimes of the two carriers are set to 2 〇〇 private s. Figure 23 is a simulation of the DC characteristics "current density of the component Jak _ 200A / cm2, the conduction voltage drop is 彳 35N ^ the breakdown voltage of the component is 1 300V (the short circuit at the anode and the voltage of the three gates are combined with the κ electrode Equal situation). Fig. 24 shows the analogy result of the switching characteristics of the element. As can be seen from the figure, the turn-on time of the component is 〇_45ms (the current rises from 1〇% to 90% of the maximum current), and the clamping time is 4 # δ (the current drops from 9〇0/〇 of the maximum current to 10%). 28 201236139 Here, for the sake of analogy, an n-MOS is added between the electrode A and the electrode b of the element instead of the method of Figs. 18, 19, 2〇. The opening of the component firstly uses V(G0N) and V(G1) simultaneously in synchronization with 〇彳 to linearly increase from 0V to 1QV in s, and then waits for ... 3 to use v(G2) with the heart time 攸0V linear Increase to 10V. The clamping of the component firstly achieves a short circuit between the electrode A and the electrode B in the "〇", at the same time, v(g〇n) uses the time of "〇" "s linearly decreases from 10v to 〇v, and then waits He 1) and V(G2) use 10/ZS time to linearly reduce from 1〇v to 〇ν〇. From the above characteristics, the analogy result of this component is already better than Infineon's IGBT product SIGC156T120R2C (current density 63A/ At cm2, the turn-on voltage drop is 2.5V) and the current density is greater at the same forward voltage drop. It should be stated that 'not the best design given here. It is important to note that the most likely cause of power component failure is the current concentration effect. It can be seen from the DC characteristics of FIG. 23 that for the elements of the present invention, any local cell's VAK increase or gate voltage increase can generate a larger current, but is not an unacceptable current density, and is reported in the high Electrical breakdown does not occur under the voltage. The cells described above, in addition to the cells of the strip structure, can of course have many other structures. Fig. 25(a) shows a cell in which the structure of Fig. 22 is hexagonally densely packed, where the N region 110 exposed on the surface is at the edge of the hexagonal cell, so that a large opening element can be obtained. . Figure 25(b) shows a schematic representation of the close packing of many such cells. Although the various cases mentioned above are N-type with a withstand voltage zone. However, it is obvious that they also apply to the case where the .. waste zone is p-type. At that time, the various N-type regions described in this patent should be replaced with P regions, and electrode A and electrode κ should be reversed to each other. The above examples of the invention have been described. It goes without saying that many other application examples can be made without departing from the scope of the invention by those skilled in the art. The description of the present invention has been presented for purposes of illustration and description. Many modifications and variations will be apparent to those skilled in the art. The embodiment was chosen and described in order to best explain the principles and embodiments of the invention, and, BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(a) is a schematic view showing the principle structure of the present invention. Figure 1 (b) is a simple equivalent circuit diagram of circle 1 (a). Fig. 2(a) is a schematic view showing another principle structure of the present invention. Fig. 2(b) is a simple equivalent circuit diagram of Fig. 2(a). Fig. 3(a) is a schematic view showing still another principle structure of the present invention. Fig. 3(b) is a simple equivalent circuit diagram of Fig. 3(a). Figure 4 is a schematic illustration of several configurations of the lower portion of the pressure resistant zone. Fig. 5(a) is a schematic view showing the current source in the interior of the wafer of the present invention. Fantasy, - Figure 5 (b) is a simple equivalent circuit diagram of Figure 5 (a). Fig. 6(a) is a schematic view showing another embodiment of the present invention in which a current source is formed in a wafer. Figure 6(b) is a simple equivalent circuit diagram of Figure 6(a). 30 201236139 Figure 7 is a schematic view showing the structure of dielectric isolation based on Figure 5(a) or Figure 6(a). Figure 8 is a schematic view showing another structure in which media isolation is used in Fig. 5 (sentence or Fig. 6(a). Fig. 9 is a method of adopting S|S on the basis of Fig. 5(a) or Fig. 6(a). Figure 10 is a schematic view showing another structure of the method of using S|S on the basis of Fig. 5(a) or Fig. 6(a). Fig. 11(a) is a schematic view showing the structure of the clamped diode. Fig. 11(b) is a simple equivalent circuit diagram of Fig. 11(a) Fig. 12(8) is a schematic diagram showing the structure of a method for providing a current source of a hole flow in (8) and Fig. 2(8). Fig. 12(b) It is a simple equivalent circuit diagram of Fig. 12(a). Fig. 1 3(a) 结构 A structural diagram of increasing the opening gate to speed up the opening speed. Fig. 13(b) is a simple equivalent circuit diagram of Fig. 13(a). Fig. 14(8) Fig. 14(b) is a simple equivalent circuit diagram of Fig. 14(a). Fig. 15(a) is a type of automatic opening switch signal for quick opening. Figure 15 (b) is a simple equivalent circuit diagram of Figure 15 (a). Figure 16 (a) is a structural diagram of the addition of a clip on the basis of Figure 14 (4). - Figure 16 (b) is a simple equivalent circuit diagram of Figure 16 (a). 31 201236139 Figure 17 疋 a structure for removing the clamp diode on the basis of Figure 16 (a) is not intended to be 0 Figure 18 is based on Schematic diagram of a method for generating a low voltage circuit control signal of Fig. 21 in Document [1]. Fig. 19 is a schematic diagram of a low voltage circuit for implementing an anode short circuit. Fig. 2A is a schematic structural view of a method for manufacturing a low voltage circuit power supply. Figure 21 (a) is a schematic structural view of a method of generating a power source with a positive voltage relative to the cathode generated by the component itself. Figure 21 (b) is a schematic diagram of a control circuit. Figure 22 is Figure 14 using Figure 4 (e Fig. 23 is a diagram showing the DC characteristics obtained by using the TMA-MEDICI analogy based on the cell structure of Fig. 22. Fig. 24 is a diagram showing the switching characteristics obtained by using the tmA-MEDICI analogy based on the cell structure of Fig. 22. (a) is a schematic structural view of a cell in which hexagons are densely packed. Fig. 25(b) is a schematic view showing the result of close packing by Fig. 25(a). [Description of main components] 101 P area I 03 N area II 1 N + zone 122 P zone 080 conductor 100 lower 102 N zone 11 0 N zone 120 P zone 121 P zone 32 201236139 123 IP zone 126 N zone 130 N zone 131 N zone 132 N zone 133 P zone 140 P zone 141 P zone 142 N zone 143 P zone 144 N type zone 145 P zone 146 N Zone 161 Insulation 162 Insulation 163 Insulation 171 Insulation Slot 172 Insulation Slot 173 Insulator 200 Current Source 201 > Polar Region 202 Source Region 260 Insulation Layer 300 Current Source 301 Nom Region 302 Source Region 360 Insulation Layer 400 N Zone 600 P Zone 601 P Zone 602 P Zone 603 N + Zone 604 N + Zone 605 P + Zone 660 Insulation 661 Insulation Layer 800 Low Voltage Circuit Zone 801 P Zone 802 N Zone 803 N + Zone 810 埠 33

Claims (1)

201236139 VII. Patent application scope: 1_- kinds of semiconductor components, whose working area is between the first main surface and the second main surface of the semiconductor, containing the first type cell or the second type cell or the second type 7C cells or both types of cells or all three types of cells; the first type of cells are characterized by: a first first conductivity type region as a main withstand voltage region; said first first One side of the conductivity type region is connected to the first second conductivity type region by a first conductivity type region; the other two conductivity types of the first first conductivity type region a phase connection; at least one of the other surfaces of the second second conductivity type region is connected to a first first conductivity type region; the second component of the semiconductor component The conductivity type region is coupled to the first 埠 of the first controlled current source, and the second second conductivity type region has another portion and the second controlled current source — Connected, two of the two current sources The two turns are coupled together and are each coupled to a first conductor that serves as the first electrode of the two controlled electrodes; the second major surface has any of the two electrode connections. One connection is that only the second conductor is coupled to the first second conductivity type region, the conductor acts as the second electrode of the two controlled electrodes; the second connection is the second conductor In addition, a third conductor is electrically coupled to the first first conductivity type region of the first conductivity type, and the third conductor is a base; the first is controlled The current source controls the first carrier current & flowing through the first conductivity type of the 201236139 conductivity type, and the second controlled current source controls the flow through the first first a second type of carrier motor of the conductivity type zone, controlling the lightning between the two controlled electrodes by controlling the current source of the two carrier currents; the motor of the 23⁄4 · &, +, # 』 In addition to the characteristics of the first type of cells, g has the following characteristics. The first first conductivity type region also has a region directly communicating to the first major surface, the region being covered by a first insulating layer, the insulating layer also covering the second surface of the first main surface Two conductivity type regions and a second first conductivity type (four), the top of the insulation layer is covered with a conductor; the first first conductivity type region connected to the first main surface and the second first type The conductive type regions respectively constitute a secret region and a source region of the first conductive type MIS, and the second second conductive type region serves as a substrate 1 , and the conductor covered at the top of the insulating layer serves as the first conductive a type of conductor 'insulator · semiconductor Μ丨S gate; the gate plus signal can control the first carrier type of the conductor of the first conductivity type _ insulator _ semiconductor MIS of the first carrier current; The second type of cell has the following features in addition to the characteristics of the first type of cell, and the second second conductivity type has a second insulating layer covering one side of the region. As a junction outside the edge of the Weizu District Edge termination region - a region of a second conductivity type - side; the junction edge termination !! % in the first main table from the working area boundary of the semiconductor component as the first side, until the first controlled electrode is even if there is a voltage: there is no electric field, the first first conductivity type One region of the # region ends as the second side; the top of the second insulating layer has a conductor covering 'as a clamping gate; the #face edge termination region has a low voltage circuit outside the second side; The low-voltage circuit is provided with two output ports, the first 35th of which is 201236139, the output electrode is connected to the second electrode of the semiconductor component through a difficult phase, and the second output port and the base of the second connection are passed through another a phase connection; the low voltage circuit outside the junction edge termination region has two rims, and there is no electric field between the first input 埠 and the two controlled electrodes even if the force has a very high voltage An area of the first first conductivity type is directly coupled, and the second input port is a control of the low voltage circuit, and the conductor is coupled to a station having a junction near the second side of the junction edge termination region; # when When a pulse signal is applied to the clamp gate, a large current can pass between the output turns of the low voltage circuit, and the two output itches are low, so that the area of the first second conductivity type is not The first conductivity type region is implanted into the hole; when the first conductivity type region is the N region, the first carrier is electrically, the second conductivity type region is the p region, and the second carrier is It is a hole; when the first conductivity type region is the P region, the first carrier is a hole, the first conductivity type is (4), and the second carrier is electron. 2. The semiconductor component as claimed in the claim, wherein the base is directly coupled to the second electrical = instead of being coupled to the first output of the low voltage circuit by another conductor. 3. For the semiconductor component described in the claim, the electrical type is divided into three sub-zones, and the three sub-zones are:: species: the conductivity type is separated by zones, and each solid-type ^mm bucket 3 has its own The second first type of conduction is surrounded by: the second second conductivity type region of the first sub-region within each of the three sub-regions and the first main surface; and its 36 201236139 The doping dose of the region of the first _ + + + conductivity type in the first sub-region is the doping dose of the region of the second pedigree & The flute-/talAsir „^ λ in a sub-^ is the doping dose of the first first conductivity type region is smaller than the second sub-region second wall-first conductivity type region. 'The second sub-zone flute - « . ^ , a solid first type of conductivity type and the third sub-first second track #^ raw area on the first main surface with floating ohmic contact There is also a third type of second mine in the third sub-section: the second type of zone of the first conductivity type a conductor-insulator having at least two conductive conductivity types of at least two conductive conductors, a source region of ten conductor-insulator-semiconductors of the first conductivity type and a first one of the first region constituting the base region Distant snow phase, 叼罘 a first conductivity type zone® with conductors connected to form the first electrode of two controlled electrodes; two _ _ _ _ _ _ _ _ _ _ _ _ _ And the polar regions respectively _ _ _ with the second first conductivity type region in the first sub-region and the 笙_ connection in the second sub-region, · the wire for the region of the mth conductivity type The phase βγΛ has two insulating layers, each covering a part of the source & part of the base region of the drain region, and the two insulating layers are covered with conductors as the two first type of thunder. The type (four) body-insulator-semiconductor MIS Ψ 廷 廷 廷 廷 廷 廷 廷 廷 廷 廷 坦 坦 坦 坦 坦 坦 坦 坦 坦 坦 坦 铃 铃 铃 铃 铃 铃 铃 铃 铃 铃 铃 铃 铃 铃 铃 铃Two: 6' of the semiconductor element described in claim 1 'the second The distinction between the two conductivity types 蛊-plus JH: Γ9* t 守 Μ ^ The sub-regions are separated by an insulating groove, one "3" has its own second first conductivity type region; the first one The doping dose of the second second == of the second first eight sub-regions in the sub-region is larger than that of the first conductivity type region, and the second one of the second sub-region of the second 37 201236139 sub-region The doping dose of one conductivity type region is smaller than that of the second second conductivity type region of the first subregion, and the third: = second second conductivity type region and The second second conductivity type region of the third sub-region is coupled by a galvanic ohmic contact on the first side and a second one of the second first conductivity type region in the second sub-region. The second conductivity type region 'the third second conductivity type region contains at least two conductors of the first conductivity type 'insulator-semiconductor Μ丨S' two conductors of the first conductivity type' The source region of the insulator_semiconductor_ and the third second conductivity type constituting the base region The region has a conductor on the first main surface coupled to form a first electrode of the two controlled electrodes; ^ a conductor of the first conductivity type _ insulator _ semiconductor _ (four) pole region knife /, in the first sub-region a second first conductivity type region and a second: a second first conductivity type region in the subregion are connected by wires; at least: two insulating layers on the first: main surface, each covering a portion The source region and the knives; and the polar regions and the base region therebetween' have two conductor layers covered with conductors as the conductors of the two first conductivity types, the insulator-semiconductor MIS, which are controlled separately. The current of the first conductivity type conductor-insulator-semiconductor M|S as the two current sources of the two carriers. 5. The semiconductor component according to claim 1, wherein the second second conductivity type is divided into three sub-regions, and the three sub-regions are partially connected to each other by a second region of the first conductivity type. Portions are separated by insulating grooves, each sub-region containing a respective second first conductivity type region; wherein the second first conductivity type region in the first sub-region has a doping dose The doping dose of the second second conductivity type region of one sub-region is larger, and the doping dose of the second first conductivity type region of the second sub-region is smaller than that of the second sub-38 201236139 region The doping amount of the two second conductivity type regions is small, the second first conductivity type region in the third subregion and the second first conductivity type region in the third subregion are in the first The main surface is coupled by a floating ohmic contact; the second first conductivity type region of the third sub-region has a third second conductivity type region, and the third second conductivity type The zone contains at least two conductors of the first conductivity type_insulator_ a conductor M|S, a source region of the conductor-insulator-semiconductor Μ丨S of the two first conductivity types and a third region of the second conductivity type constituting the base region are electrically connected to each other on the first main surface, Forming the first electrode of the two controlled electrodes; the two-first conductivity type conductor 'insulator_semiconductor_'s non-polar region and the second first conductivity type region and the first sub-region The second first conductivity type region in the two sub-regions is connected by wires; at least two insulating layers on the first main surface each cover a part of the source region, a portion of the drain region, and a base region therebetween The two insulating layers have conductors covering the idle electrodes of the conductors of the two first conductivity types, the insulator-semiconductor, which control the two current sources as two carriers. The current of the first conductivity type conductor-insulator-semiconductor MIS. 6. The semiconductor component according to claim 1, wherein the electrical type is divided into three sub-regions, and the three sub-regions are fixed by ^^^. A second conductivity class is connected to each other, and each sub-section a region of conductivity type, three sub-sections: surrounded by respective first-surfaces, wherein the doping dose of the first sub-region = electric = region and the first main region is more conductive than the first one The doping amount of the type region is large, and the doping dose of the second sub-region 2: the first conductivity type to the first conductivity type 39 201236139 is lower than the second conductivity type of the second sub-region The dopant of the region; the second region of the second first conductivity type in the third sub-region and the second region of the second conductivity type of the third sub-region are in floating ohmic contact phase on the first major surface Coupling; there is a third region of the second conductivity type within the region of the second first conductivity type in the third sub-region, and the region of the third second conductivity type contains at least two regions The first type of conductor = conductor 'insulator semi-conducting 豸M丨S, two first type of conductivity The source region of the insulator-semiconductor MIS and the third region of the first conductivity type constituting the base region have a conductor phase increase on the first major surface "妾, forming the first electrical I of the two controlled electrodes The first one conductivity type conductor 'insulator-semiconductor MIS's drain region and the first: first conductivity type region in the first sub-region and the second first region in the second sub-region The conductive type regions are connected by wires; at least two insulating layers on the first main surface, the partial source regions, the partial non-polar regions and the base regions between the two are provided with conductor coverings on the two insulating layers The two first conductivity types: the conductor L semiconductor, the gate 'the two gates do not control the current of the first conductivity type conductor insulator semiconductor MIS which is the two current sources of the two carriers. The semiconductor component according to any one of claims 3 to 6, wherein the second first conductivity type region in the _ sub-region is connected by a conductor: the drain conductor is also connected to a second and a second A region of the second conductivity type in which the second conductivity type region is connected. 8. The method of connecting another phase of the region of the request item type is the semiconductor component of 1, the second second conductor portion is made with the first one of the second controlled current source a second conductivity type region and a first conductivity type of the first and second conductivity type regions of the fourth and third conductivity types =: a second sign - a type of conductivity type surrounded by the first conductivity type region and the first main surface, the third type of the second type of at least the female A third conductor having two first conductivity types, an insulator _ semiconductor MIS, two conductors of the first conductivity type, an insulator, a semiconductor (4), and a conductor of a third second conductivity type constituting the base region Connected to form a first electrode of two controlled electrodes, one of the two first conductivity type conductor-insulator-semiconductor MIS regions has a bungee region and a first main gauge The area surrounded by the first conductivity type, the first The conductive type region has a wire connected to the second second conductivity type region; at least two insulating layers are killed on the first main surface 'I cover part of the source region, part of the gate region, and between In the base region, two insulating layers are covered with conductors as gates of two conductors of the first conductivity type: insulator-semiconductor MIS, and the two gates control two (four) current sources as two types of carriers. The first conductivity type of conductor 'insulator_semiconductor 嶋 current. 9. The semiconductor device according to claim 1, wherein the two current sources are formed in a region of the first first conductivity type, and the third region of the second conductivity type has a region with other semiconductor regions. The insulator is isolated. The semiconductor component of claim 1, wherein the gate of the first conductivity type conductor-insulator-semiconductor MIS of the second type of cell is connected to the region of the first-first conductivity type by a wire A doped t dose in the first major surface is larger than the first conductivity type region. 11. The semiconductor device according to claim 3, 4, 5, 6 or 1 wherein: 41 201236139 is used between the second second conductivity type region and the third second conductivity type region a conductor-insulator-semiconductor element controls its conduction; the conductor-insulator-semiconductor element is a second second conductivity type region as a source region of the component, and a second sub-region second a conductivity type region as a base region, a third second conductivity type region as a drain region; the conductor-insulator-semiconductor element or a third second conductivity type in the third sub-region A region of the first conductivity type is set as the source region of the component, and a region of the third conductivity type of the third subregion is used as the base region, and the second region of the third subregion is a conductive type region as a non-polar region; the conductor-insulator-semiconductor element has an insulating layer on a portion of the first main surface from a portion of the source region through the base region to the drain region, and the insulating layer is covered There is a conductor 'this conductor as a place Gate conductor-insulator-gate field-applied voltage of the semiconductor element can make the second conductivity type conductive insulator _ _ MIS semiconductor conduction. 12. The semiconductor device according to claim 4, 5, 6, 8, 9 or 11, wherein two regions between the first conductivity type region and the third second conductivity type region are formed Two or more diodes connected in series. The semiconductor component of claim 1, wherein the first-type cell, the heavily doped first phantom under direct contact with the region of the first first conductivity type under the major surface In the region of the tantalum conductivity type, the region of the first conductivity type has a direct contact with the conductor on the first main surface, and a region between the first-second two-order ohmic contact and the second second conductivity type. The second -m, f &# °° in the region of the second conductivity type of the second type of conductivity = and the second region of the second conductivity type in the second a flute _ in the first conductivity type zone, there is also a third 42nd 201236139 a conductivity type zone in the third second conductivity type zone, and a fourth second a region of the conductivity type is in the region of the third first conductivity type; the fourth region of the second conductivity type has a direct contact with the conductor on the first major surface 'it passes through the wire and the Coupling with a conductor in contact with a heavily doped first conductivity type region; said third The conductive type region has a direct contact with the conductor on the first major surface, which is coupled to one end of a capacitor by a wire, and the other end of the capacitor is coupled to the first electrode of the two controlled electrodes; the capacitor is disposed as a The second low-voltage circuit of the second conductivity type, the input of the low-voltage circuit is an external control voltage, the output of the low-voltage circuit is the control voltage of the controlled current source or as the second second The control voltage of the zone of the conductivity type. 14. The semiconductor component of claim 1, wherein a small area under the first major surface within the first side of the junction edge termination region is provided with a conductor through the wire and at the junction edge termination region a second conductivity type region other than the side is coupled; the first conductivity type region is surrounded by a second conductivity type region except for the first main domain surface. The first type of electrical type has direct contact with the conductor on the first major surface, which is coupled to one end of the capacitor by a wire; the other end of the opposite end of the junction and the second edge of the junction edge termination region The first conductivity type regions are coupled; the capacitor acts as a low power source disposed outside the second side of the junction edge termination region. The semiconductor component of claim 12, wherein the first conductivity type region is formed in the second second conductivity type region to form a first one body, and the second second conductivity type In the zone, a zone of the first type 43 201236139 is used. In the zone of the first conductivity type, a zone of the second conductivity type is formed to form a second diode; the second diode is The first conductivity type region is coupled to the third second conductivity type region by the floating ohmic contact on the first major surface; the first conductivity type region of the first diode is passed through the conductor and the second The second conductivity type of the diode is connected to each other. Eight, the pattern: (such as the next page) 44