CN105161527B - Utilize a kind of insulated gate bipolar device of surface structure of voltage-sustaining layer - Google Patents

Abstract

The terminal surface withstand voltage region structure of the insulated gate bipolar transistor and thyristor of the present invention has a p-type semiconductor withstand voltage layer (168), which is located between the device cell region (122) and the n ⁺ field stop region (400) ; An insulating dielectric layer (800) is arranged on the p-type semiconductor withstand voltage layer (168), and a diode is arranged on the insulating dielectric layer; the diode is composed of sequentially connected p ⁺ anode regions (902), semiconductor regions (901) and n ⁺ cathode region (903). The present invention utilizes the gate-source voltage (V _GK ) of the cell region of the device to directly or indirectly generate a control signal through the surface withstand voltage region to control the emitter junction voltage (V _AB ) of the device, so as to eliminate the trailing current when the device is turned off, and thus to turn off the device quickly.

Description

Insulated-gate bipolar device using a surface withstand voltage layer structure

technical field

The invention relates to semiconductor high-voltage device and power device technology, in particular to a bipolar device and a thyristor whose surface withstand voltage region is used in insulating gate control.

references

[1] "HIGH SPEED IGBT", U.S. Patent, US 20100219446A1;

[2] "BOTH CARRIERS CONTROLLED THYRISTOR", PCT/CN2011/083710;

[3] "A Surface Voltage Sustaining Structure for Semiconductor Devices", Chinese Patent ZL 95108317.1, or "Surfacevoltage sustaining structure for semiconductor devices", US 5,726,469;

[4] "Low Voltage Power Supply", ZL 201010000034.2, U.S.8294215B2.

Background technique

As we all know, ordinary IGBTs have severe current tailing during the turn-off process. Existing measures to improve the switching speed of IGBT mainly include the method of anode short circuit, the method of reducing the lifetime of unbalanced carriers in the withstand voltage region, and the method of reducing the injection efficiency of the emitter junction. However, these methods are all at the cost of sacrificing the effect of conductance modulation when the device is turned on, and cannot essentially eliminate the current tail when turned off, but only achieve a compromise between switching speed and turn-on voltage drop.

A high-speed IGBT is given in reference [1] "HIGH SPEED IGBT", US Patent, US 20100219446A1, and its structure and equivalent circuit diagram are shown in FIG. 1 . Wherein, G is the gate electrode of the IGBT, K is the cathode, A is the anode, and B is the base. When the voltage applied on G exceeds the threshold voltage V _th0 of the device, the IGBT is turned on. At this time, if the voltage between the electrodes A and B is not less than the voltage required when a large amount of unbalanced holes are injected from the p region 110 into the n region 102, a strong conductance modulation will be formed in the n ^- region 101, so that the conductance The voltage drop V _AK is greatly reduced. When the IGBT is to be turned off, if the voltage between the electrodes A and B is less than the voltage required to inject a large amount of unbalanced holes into the p-region 110 into the n-region 102, then no unbalanced holes will be emitted from the n-region 102 during the turn-off process. The junction continuously injects into the drift region, which eliminates the current tailing phenomenon of the IGBT during the turn-off process.

In reference [2] "BOTH CARRIERS CONTROLLED THYRISTOR", PCT/CN2011/083710, a thyristor controlling two kinds of carriers is given, and its structural diagram is shown in FIG. 2 . Among them, A is the anode of the thyristor, K is the cathode, and B is the base. Its working principle has been described in detail in the literature [2], and will not be repeated here. When the device is turned off, if the voltage between electrodes A and B decreases so that the P region 110 no longer injects non-equilibrium carriers into the N ⁻ region 101, the purpose of rapid turn off can be achieved.

Both references [1] and [2] give specific methods for controlling the voltage between electrodes A and B. For convenience, unless otherwise specified in this patent, an IGBT device is taken as an example. Figure 3 shows a method of controlling the voltage between electrodes A and B by inducing a control signal in the surface withstand voltage area. This figure is a reproduction of Figure 7 in reference [1], except that the symbols of each area use Symbol of this patent. Wherein, the p-region 168 between the cathode K and the n-type stop ring (Stop Ring) 400 is according to the literature [3] "<A surface withstand voltage region for semiconductor devices>, Chen Xingbi, Chinese patent ZL 95108317.1, or "Surface voltage sustaining structure for semiconductor devices", US5,726,469 "surface pressure-resistant region. When the IGBT is turned off, as the voltage V _AK between the anode and the cathode increases, a potential slightly lower than the neutral region 200 of the substrate will be induced on the p region 500, which can be used for the p -MIST is turned on. After the p-MIST is turned on, the potentials of its source and drain regions are close to each other. Therefore, the p region 110 and the n region 111 are short-circuited, preventing non-equilibrium carriers from being injected into the n ⁻ region 101 from the p region 110 .

The method for obtaining the induction potential in the above-mentioned p-region 500 is passively generated due to the change of the voltage V _AK between the anode A and the cathode K. In fact, at the initial stage of IGBT turn-off, the voltage V _AK between the anode and the cathode is very small, so the potential induced on the p region 500 is also very small; moreover, when V _AK is small, the p-type surface withstand voltage region The depletion region between 168 and n ^- type substrate region 101 is very thin, so there is a large differential capacitance between these two regions, and most of the current flowing through the surface withstand voltage region is used for charging and discharging the capacitance , so that the magnitude of the voltage change induced on the p-region 500 is very small, and there is a relatively large delay compared with the voltage change of V _GK .

Contents of the invention

The purpose of the present invention is to use the gate-source voltage of the bipolar device controlled by the insulated gate to directly or indirectly generate a control signal through the surface withstand voltage region to control the emitter junction voltage.

To achieve the above object, the present invention provides a cell of an insulated gate controlled bipolar device and a surface withstand voltage region as a junction edge, wherein,

The cells of the insulated gate controlled bipolar device have a first n-type semiconductor region (101, 102, 111), and the first n region has two main surfaces (001 and 002); There is at least one p-type source substrate region (121, 122) between the two main surfaces and close to the first main surface (001), and there is at least one n-type electron in the p-type source substrate region The source region (124, 125), part of the source substrate region and part of the source region are connected by conductors to form the first electrode (K) of the bipolar device controlled by the insulated gate; in part of the source The surface of the region and part of the source substrate region and part of the drift region is covered with an insulating layer (130), on which a conductor is covered, serving as the gate (G) of said insulated gate controlled bipolar device;

There is at least a first p-type semiconductor region (110) between the two main surfaces and close to the second main surface (002); said first p-region (110) and said first n regions (101, 102, 111) each having a conductor connection on the second main surface (002), respectively becoming the second electrode (A) and the third electrode (B) of said insulated gate controlled bipolar device;

All cells in the source substrate region are surrounded by a surface withstand voltage region. The surface withstand voltage region can be a p-type semiconductor region (168) between the two main surfaces and close to the first main surface as the first part of the surface withstand voltage region, and the surface withstand voltage region is between the two main surfaces. There is an insulating layer (800) outside the two main surfaces and close to the first main surface as the second part of the surface withstand voltage region, and the insulating layer is covered with a third part of the surface withstand voltage region.

The third part of the surface withstand voltage region is a diode. The diode is covered with a conductor at one end of the cell close to the source substrate region, as the anode (J) of the diode; the other end of the third part of the surface withstand voltage region has at least one n-type semiconductor region (903 ), which is covered with a conductor, as the cathode (T) of the diode; between 902 and 903 is a semiconductor region (901), whose scale in the direction of surface withstand voltage is larger than that of 902 and 903 in the direction of surface withstand voltage Generally much larger.

The anode (J) of the above-mentioned diode can be directly connected with the grid (G) of the bipolar device controlled by the insulated gate through a wire, or indirectly through the first low-voltage circuit (in the 300 area in Fig. 6 The low-voltage circuit) is connected to the gate (G). The cathode (T) of said diode is connected by wire to an input port of the second low voltage circuit (low voltage circuit in zone 200). The second low-voltage circuit area also has at least two output ports, and the two output ports are respectively connected to the second electrode (A) and the third electrode (B) of the second main surface through wires.

When the maximum allowable reverse bias voltage is added between the second electrode (A) and the first electrode (K), the first n-type semiconductor material will have a depletion region (the dotted line in each figure upper left part), but this depletion region does not reach the first p region (110), nor is it outside the surface withstand voltage region;

The depletion region is surrounded by a neutral region that is not depleted but remains neutral when the maximum allowable reverse bias voltage is applied between the second electrode (A) and the first electrode (K) (each Area 101 on the right side of the dotted line in the figure);

Through the change of the potential of the gate (G) of the bipolar device controlled by the insulating gate, the voltage of the two output ports connected to the A and B phases of the second low-voltage circuit area (200) is controlled, thereby adjusting The minority carrier injection efficiency injected from the first p region (110) to the first n region (101). In particular, there is almost no minority carrier injection during the turn-off process of the bipolar device controlled by the insulating gate, thereby reducing the time required for turn-off.

In the above technical scheme, when the maximum reverse bias voltage is applied between the anode and the cathode, the voltage of any point along the first main surface relative to the above-mentioned neutral zone that is not depleted and maintains neutrality is along with this point. The distance between the cells decreases until it is zero.

The n-type semiconductor and the p-type semiconductor in the above technical solutions can be interchanged under the idea of the present invention. In the above technical solution, the first main surface refers to the upper surface in the following specific implementation manners, and the second main surface refers to the lower surface.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention and constitute a part of the application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations to the present invention. In the attached picture:

Figure 1 is a cell structure and its equivalent circuit diagram of the n ^- -IGBT used in reference [1].

Fig. 2 is a cell structure of a thyristor used in reference [2] to control two kinds of carriers.

FIG. 3 is a structural schematic diagram of a specific implementation method for adjusting the injection efficiency of the IGBT emitter junction by using the surface withstand voltage region in reference [1].

Fig. 4 (a, b, c) is a schematic diagram of a specific implementation method of the present invention using a diode in the surface withstand voltage region to induce a control signal whose potential is close to the neutral region.

Fig. 5 is a schematic diagram of making the low-voltage circuit controlling the AB junction voltage on another substrate in the present invention.

Figure 6 is a schematic diagram of the present invention with a low voltage circuit near the cell area.

Fig. 7 is a schematic diagram showing that the cathode of the diode in the surface withstand voltage region of the present invention is connected to electrode A through a resistor.

FIG. 8 is a schematic diagram of a specific method of replacing the resistor in FIG. 7 with a gate-drain short-circuited n-MOS in the present invention.

FIG. 9 is a schematic diagram of the time-varying results of the voltage at terminal T relative to terminal A obtained by simulating the structure shown in FIG. 8 using MEDICI in the present invention.

Fig. 10 is another specific implementation method of the medium and low voltage circuit of the present invention.

FIG. 11 is a schematic diagram of a specific implementation method of the present invention using a surface withstand voltage region to realize a low-voltage negative power supply equivalent to a neutral base region.

Fig. 12 is a schematic diagram of the floating field confining ring technology used in the surface pressure-resistant region of the present invention.

Fig. 13 is a schematic diagram of the gate electrode of the IGBT connected to an output terminal of the low-voltage circuit near the cell area.

Detailed ways

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. For the sake of convenience, unless otherwise specified, this patent takes the IGBT device as an example. The technical schemes in the drawings and embodiments are also applicable to gate-controlled thyristors, IGCTs, MCTs and other bipolar devices.

Fig. 4(a) is a schematic structural diagram of the n ⁻ -IGBT cell and its junction edge used in this patent. Wherein, there is a p-type region 110 and an n-type region 111 from the n ^- type substrate 101 to the lower surface 002, and each of these two regions is covered with a conductor to form the anode A and the base B of the n ⁻ -IGBT. Under the upper surface 001 of the n ^- type substrate 101, there are two source substrate regions 121 and 122 of n-MIST, and there are respectively source regions 124 and 125 of an electron in the two source substrate regions. The source region and the source substrate region surrounding it are each covered with a conductor, constituting the cathode K of the IGBT, and an insulating layer 130 is covered on the semiconductor region between the n ⁺ region 124 and the n ⁺ region 125, the insulating layer It is covered with a conductor, which serves as the gate electrode G of the IGBT. Surrounding the source substrate region of the IGBT is a surface withstand voltage region composed of a p-type semiconductor region 168 , a dielectric region (I region) 800 and a semiconductor region S region 901 . There is a p ⁺ region 902 at the left end of the S region 901 and an n ⁺ region 903 at the right end of the S region 901 . The p ⁺ region 902, the S region 901 and the n ⁺ region 903 constitute a diode, wherein the p ⁺ region 902 is the anode region of the diode, and the n ⁺ region 903 is the cathode region of the diode, and the anode region and the cathode region are respectively covered with A conductor that forms the anode J and cathode T of the diode. The anode of the diode is connected to the gate G of the IGBT through a wire. Surrounding the surface withstand voltage region is an n ⁺ region 400 that still has a neutral region (or field stop ring) when the maximum voltage is applied between the anode A and cathode K of the IGBT. The dotted line in the figure indicates the boundary of the depletion region in the n ^- region 101 when the IGBT is in reverse withstand voltage. When the reverse bias voltage is applied to a certain level, the n ^- region 101 and p-region 168 on the upper left of the dotted line are all depletion regions, while the lower right part of the dotted line is all neutral regions. If the setting of the surface withstand voltage region is the method of reference [3], the value of the anode-cathode voltage V _AK can make the depletion region reach the left side of the n ⁺ region 400 in a large range of fluctuations, only in the pole With small V _AK values, the depletion region does not reach the n ⁺ region 400. There is a low-voltage circuit region 200 outside the n ⁺ region 400, and the depletion region only reaches the left side of the low-voltage circuit region 200 when the maximum voltage is applied between the anode A and the cathode K. Two electrodes are drawn from the circuit in the low-voltage circuit area 200 on the upper surface as the two output terminals of the low-voltage circuit, and the two output terminals are connected to the anode A and the base B on the lower surface through their respective connecting lines . The low-voltage circuit also has an input terminal, which is connected to the cathode T of the diode through a wire.

In Figure 4(a), when the voltage applied to the gate electrode G of the IGBT is greater than the threshold voltage V _th of its n-MIST, electrons pass from the electrode K through the n ⁺ region 124 (or n ⁺ region 125), gate The lower channel region, n ^- region 101, and n-region 102 reach the p-region 110. At the same time, a large number of holes are injected from the p-region 110 into the n ^- region 101 to form a strong conductance modulation in the n ^- region 101. At this time, electrode A has a small positive voltage V _AK relative to electrode K. When this voltage is less than the voltage V _GK of electrode G relative to electrode K, the potential of electrode G is higher than that of electrode A, then the diode composed of p ⁺ region 902, S region 901 and n ⁺ region 903 will be forward biased , at this time, a current flows from the electrode G through the diode to the input terminal of the low-voltage circuit in the low-voltage circuit region 200 .

At the moment when the IGBT is turned on and turned off, V _GK drops below the threshold voltage. Under normal circumstances, the potential of the electrode G at this time is lower than that of the electrode A. Then the diode formed by the p ⁺ region 902 , the S region 901 and the n ⁺ region 903 will be reverse biased, and no current will flow from the electrode G into the input terminal of the low voltage circuit in the low voltage circuit region 200 . By using the low-voltage circuit in the low-voltage circuit area 200 to detect the change of the current flowing into the input terminal of the area 200, a signal of current change is obtained in the low-voltage circuit area 200 while the gate G signal changes, and the signal is processed by the low-voltage circuit, so that The voltage between the two output terminals of the low voltage circuit in zone 200 varies, thus causing the voltage between the anode A and base B of the IGBT to vary. If the voltage between the electrodes A and B is less than the voltage required to inject a large amount of unbalanced holes into the p-region 110 into the n-region 102 during the turn-off process of the IGBT, there will be no unbalanced holes during the turn-off process. The drift region is continuously injected from the emitter junction, thereby largely eliminating the current tailing of the IGBT during the turn-off process.

The electron source region n ⁺ region 125 in the p region 122 close to the surface withstand voltage region in FIG. 4( a ) may not be needed, as shown in FIG. 4( b ). Also, the p-region 122 may be floating, as shown in FIG. 4(c).

The above-mentioned low-voltage circuit region 200 can be made on the same substrate as the IGBT cells, or can be made on a different substrate. FIG. 5 is a schematic diagram of making the low-voltage circuit 200 region for controlling the voltage of the AB junction on another substrate in the present invention. Wherein the S region 600 is a substrate of semiconductor material. The turn-on and turn-off process of the IGBT is similar to the situation described in Figure 4, and will not be repeated here.

6 shows a method in which the gate electrode G first passes through the input terminal of a low-voltage circuit in the low-voltage circuit region 300, and then connects its signal to the anode J of the diode through an output terminal of the low-voltage circuit. The low-voltage circuit region 300 is built in the source-to-bottom region 122 of the IGBT cell. The low-voltage circuit area 300 includes at least one input terminal and one output terminal, wherein the input terminal is connected to the gate electrode G of the IGBT through a wire, and the output end of the low-voltage circuit in the low-voltage circuit area 300 is connected to the anode J of the diode through a wire. When the potential of the gate electrode G of the IGBT changes, the output terminal of the low-voltage circuit region 300 can generate a signal of potential change or current change, and the signal can be synchronized with the change of the gate G signal, or can be delayed after the gate G signal. In the structure shown in FIG. 6 , the turn-on and turn-off processes of the IGBT are similar to those described in FIG. 4 , and will not be repeated here.

The low-voltage circuit area 300 in Figure 6 itself needs a low-voltage power supply. For the low-voltage power supply, please refer to the method in [4] "Chen Xingbi, "Low-Voltage Power Supply", Chinese Patent No. 201010000034.2, and US Patent No. US8294215B2".

FIG. 7 shows a schematic diagram of a specific method for obtaining a voltage signal for controlling a low-voltage circuit by using a resistor. Wherein between electrode T and electrode A is a resistor R. When the IGBT is turned on, if the potential on the gate G is greater than the potential on the electrode A, the diode composed of the p ⁺ region 902, the S region 901 and the n ⁺ region 903 will be forward biased, and at this time, a current starts from the electrode G It reaches electrode J and passes through the diode to electrode T, then passes through resistor R and finally reaches electrode A. The electrode T has a positive voltage V _TA with respect to the electrode A since the current flowing through the resistor R will cause a voltage drop across the resistor. At the moment when the IGBT is turned on to off, V _GK drops rapidly. If the electrode G has a negative voltage relative to the electrode A at this time, the diode composed of the p ⁺ region 902, the S region 901 and the n ⁺ region 903 will be reverse-biased, and no current will flow from the electrode G through the resistor R, so the electrode T is opposite to the electrode The voltage V _TA of A is zero. Use the low-voltage circuit in the low-voltage circuit area 200 to detect the change of V _TA value, and through the low-voltage circuit processing, the voltage between the two output terminals of the 200 area changes, so that the anode A and base B of the IGBT voltage change between.

FIG. 8 shows a schematic diagram of a specific method for replacing the resistor R shown in FIG. 7 with a gate-drain short-circuited n-MOS. There is an n-MISFET on the upper surface of the p-type substrate 600, wherein the p-region 600 is the source substrate region of the n-MOSFET, and the n ⁺ region 621 and the n ⁺ region 622 constitute the drain region and the n-MOSFET respectively. The source region is covered with conductors respectively to form the drain and source of the n-MOSFET. The n ⁺ region 622 is in turn connected to the p ⁺ region 623 through a conductor. The substrate region between the n ⁺ region 621 and the n ⁺ region 622 is covered with an insulating layer 630 , which is covered with a conductor to form the gate of the n-MOSFET. The drain of the n-MOSFET is connected to its gate through a wire and is connected to the electrode T at the same time, and the source of the n-MOSFET is connected to the anode A of the IGBT through a wire. When the voltage V _TA between the electrode T and the electrode A is greater than the threshold voltage of the n-MOSFET, a current flows from the electrode T into the drain region of the n-MOSFET, and flows through the channel region below the gate to the source region, and finally to electrode A. The gate-drain shorted n-MOSFET acts as a resistor. The situation during the turn-on and turn-off process of the IGBT is the same as that described in FIG. 7 , and will not be repeated here.

Figure 9 shows the time-varying waveforms of V _GK and V _TA in the structure shown in Figure 8 obtained by using the simulation software MEDICI. The abscissa represents time t, and the ordinate represents V _GK or V _TA . In the simulation, a terminal structure with a maximum reverse withstand voltage of 2.1kV was adopted. The gate-drain short-circuited n-MOSFET in the low-voltage circuit area 200 has a gate width w=1 μm, a gate length l=6 μm, and a T terminal with a size of 3 x 10 ^-15 F capacitors. During the simulation, V _GK maintains a value of 12V during t=0~300ns, and V _GK drops from 12V to -5V within 100ns when t=300ns, and the value of V _TA can be seen from the figure Falls from 8.4V to 0V in 200ns.

It should be pointed out that the parameters used in the results shown in Fig. 9 are not the optimal design.

FIG. 10 shows another specific implementation method of the low-voltage circuit in the low-voltage circuit area 200 . The low-voltage circuit area 200 has a resistor R and a CMOS circuit composed of p-MOSFET 220 and n-MOSFET 230 . The gates of p-MOSFET220 and n-MOSFET 230 are connected through wires and connected to electrode T at the same time; the source of p-MOSFET220 is connected with electrode A; the drain of p-MOSFET 220 is connected with the drain of n-MOSFET 230 The source of the n-MOSFET 230 is connected to the electrode F. Wherein the electrode F is one end of a low-voltage negative power supply with a negative voltage relative to the electrode A. Between electrode T and electrode F there is a resistor R. When the voltage of the gate G relative to the electrode F changes, the current flowing through the resistor R changes accordingly, and a signal of voltage change is obtained at both ends of the resistor R. The output terminal T' can obtain a signal of a voltage change in opposite phase to that of the T terminal. Due to the use of a low-voltage power supply, a weak signal change on the electrode T can obtain a signal with a larger output power on T'.

The low-voltage circuit shown in Figure 10 requires an additional low-voltage power supply, and the low-voltage power supply can be conveniently provided by the method of the reference "<A semiconductor device and the application of the low-voltage power supply provided by it>, Chen Xingbi, Chinese patent application number: 200810097388.6". accomplish. A method for generating a low-voltage power source proposed in this patent is shown in FIG. 11 .

In FIG. 11 , there is a p ⁺ region 500 near the end of the p region 168 of the surface withstand voltage region 400 near the n ⁺ region. The p-region 500 is covered with a conductor to form an electrode F; the electrode F is connected to one end of a capacitor _C0 through a wire, and the other end of the capacitor _C0 is connected to the electrode A. As mentioned above, if the setting method of the surface withstand voltage region in the reference "<lateral low-side high-voltage device and high-side high-voltage device>, Chen Xingbi, ZL 200310101268.6, or US 6998681B2 (2006.02.14)", then V _AK The corresponding negative voltage relative to the n ⁺ region 400 can be induced in the p ⁺ region 500 within a wide range of variation. This negative voltage is the voltage between the two plates of the capacitor C ₀ . Capacitor C ₀ as the power supply of the low-voltage circuit can supply power for the low-voltage circuit.

The p-region 168 mentioned above can actually be a Planar Junction Termination Extension (Planar Junction Termination Extension) technology or a Variation Lateral Doping (Variation Lateral Doping) technology or RESURF (Reduced Surface Field) technology. In fact, no matter which junction edge termination technology is available, it can be used. This is because various junction edge termination technologies use the charges generated to change the electric field on and near the surface of the semiconductor. In fact, there is a relatively thick insulating layer 800 on the semiconductor surface, and then there are conductive p regions 902, S regions 901 and n ⁺ regions 903. The potentials of these points may not match the potentials of the semiconductor surface. Difference. However, as long as the insulating layer 800 is thick enough and its permittivity is not very large, the electric flux passing through the insulating layer 800 caused by the potential difference is very small, and the electric field generated under the semiconductor surface is very small. Moreover, precise design can take this effect into account.

FIG. 12 is an example of the technology proposed in this patent applied to a junction termination technology as a floating FCL technology. In this figure, p-regions 171, 172, 173 and 174 represent floating field-confining loops. Here, the first type of surface voltage-sustaining region is formed by a floating field-limiting ring, and the form of the second surface-sustaining voltage region is the same as that described above.

The gate electrode G of the IGBT can also be connected to an output terminal of the low-voltage circuit area 300, and FIG. 13 shows such a method. In FIG. 13, the low-voltage circuit region 300 is built in the source-to-bottom region 122 of the IGBT cell. The low-voltage circuit area 300 has two output ends, one of which is connected to the gate electrode G of the IGBT through a wire, and the other output end is connected to the anode J of the diode through a wire. The low-voltage circuit area 300 also has an input terminal G _C . When the potential of G _C changes, the two output terminals of the low-voltage circuit area 300 can respectively generate signals of potential change or current change. The low-voltage circuit area 300 in Figure 13 itself needs a low-voltage power supply. For the low-voltage power supply, please refer to the method in [4] "Chen Xingbi, "Low-Voltage Power Supply", Chinese Patent No. 201010000034.2, and US Patent No. US8294215B2". In Fig. 13, n ^- region 101 has an n ⁺ region 128 close to the upper surface, which is covered with electrode H. When electrode A has a certain positive voltage relative to electrode K, electrode H will induce a positive voltage relative to electrode K. The positive voltage of K, which can be used as the power supply of low-voltage circuits in the 300 area.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that: the present invention can still be Modifications to the specific implementation of the invention or equivalent replacement of some technical features; without departing from the spirit of the technical solution of the present invention, should be included in the scope of the technical solution claimed in the present invention.

Claims (5)

1. a kind of bipolar semiconductor for the gate control that insulate, its active area at least contain a cellular, the cellular is place Between the first main surface of semiconductor chip and the second main surface；Each cellular has the semiconductor of the first conduction type The firstth area as it is described insulation gate control bipolar semiconductor drift region, the drift region it is at least part of with First main surface directly contacts；

The cellular at least also has the secondth area of the semiconductor of the first conduction type as an insulated-gate field-effect crystalline substance The source region of body pipe, it is surrounded by the area of semiconductor first of second of conduction type and the first main surface；Described second Source substrate zone of the area of semiconductor first of conduction type as the isolated-gate field effect transistor (IGFET), it is by the source region, first Main surface and drift region are surrounded；

Partial source substrate zone and partial source region are connected by conductor, form the bipolar semiconductor of described insulation gate control First electrode of device；The first main surface covering in the source region of part and partial source substrate zone and partial drift region There is the first insulating barrier, covered with conductor on the first insulating barrier, partly led as insulation the ambipolar of gate control The grid of body device；

Be close to the second main surface and between two main surfaces the semiconductor of at least one second of conduction type second Area；Firstth area of the semiconductor of the area of semiconductor second of second of conduction type and the first described conduction type is the There is the associated knot of conductor on two main surfaces respectively, each form it is described insulation gate control bipolar device second electrode with 3rd electrode；

Between the first main surface and the second main surface and it is close to first in the bipolar semiconductor of the insulation gate control At main surface, there is a resistance to nip in the first surface that all cellulars are surrounded with plane terminal technology；The resistance to nip in the first surface Both sides in the first side be in the side of first electrode, the second side of the resistance to nip in the first surface then with the first conductive-type The unspent area in the firstth area of the semiconductor of type is connected；

The bipolar semiconductor of the insulation gate control is characterised by, in the where the resistance to nip in the first surface Second of insulating barrier it has been close to outside one main surface, it is pressure-resistant to cover second of surface again on second of insulating barrier Area；The resistance to nip in second of surface is a diode, and it has second of conductive-type in the side of the cellular close to active area The 3rd area covering of the semiconductor of type, has conductor covering, first electrode as this diode again thereon；Second of surface is resistance to Nip has the 3rd of the semiconductor of the first conduction type on the second side of the resistance to nip in the first close described surface Area, there is conductor covering thereon, second electrode as the diode；In the 3rd area of the semiconductor of second of conduction type It is a semiconductor region between the 3rd area of the semiconductor of the first conduction type；First electrode of the diode and institute State grid to be directly connected by wire, or be connected by first low-voltage circuit with the grid；The of the diode Two electrodes are connected by second electrode of second low-voltage circuit and the bipolar semiconductor of the insulation gate control Connect.

2. the bipolar semiconductor of insulation gate control according to claim 1, it is characterised in that described second low Volt circuit is a resistance.

3. the bipolar semiconductor of insulation gate control according to claim 1, it is characterised in that described second low Volt circuit is the MOSFET of a gate-drain short circuit, wherein, the MOSFET of the gate-drain short circuit drain electrode and the diode Second electrode is connected, the bipolar semiconductor device of the MOSFET of gate-drain short circuit source electrode and the insulation gate control Second electrode of part is connected.

4. the bipolar semiconductor of insulation gate control according to claim 1, it is characterised in that described second low Volt circuit is arranged in the cellular chip of the bipolar semiconductor of the insulation gate control.

5. the bipolar semiconductor of insulation gate control according to claim 1, it is characterised in that described second low Volt circuit is arranged in another chip of the cellular chip of the bipolar semiconductor different from the insulation gate control.