201206069 jyv i w 34863twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種重置電路，且特別是有關於一種 電源的開機重置(power on reset)電路。 【先前技術】 在設計電子電路時’往往會加入重置(reset)機制在電 φ 路中，以使所設計之電子電路在需要時得以回復為初始狀 態。尤其在對電子電路開啟電源(開機)之初時，電路中各 元件(例如暫存器）處於不確定狀態，此時即需要重置此些 電路元件，以將電路中各元件設定為初始狀態。 圖1A為習知之電源重置電路的電路圖。請參照圖1A， 習知之電源重置電路1〇〇包括電阻R卜電容C1以及反相 器A1。其中電阻R1耦接於電源電壓VDD與反相器A1 的輸入端之間，電容Cl耦接於反相器A1的輸入端與接地 電壓GND之間。 籲 請同時參照圖1A、圖2A以及圖2B，其中，圖2A為 圖1A之電源重置電路中反相器A1輸出端的電壓波形圖， 而圖2B為圖1之電容C1上跨壓的電壓波形圖。當系統的 電源開啟時’電源電壓VDD的電壓漸漸上升，此時電容 C1上的f壓亦隨之漸漸上升，當電容C1JL的跨壓被充電 ^反相器A1的轉態準位時，反相器A1的輸出端便由邏輯 面準位轉為邏輯低準位。而當電源電壓VDD因為某種原 因而下降時(非關閉電源），電容C1中所儲存的電能將透過 ^63ΐ\νί·(1οε/η 201206069 電晶體Q1流向電源電壓VDD’而使得電容α上的 下降噹電容Cl上的跨壓下降至反相魏的轉態準位 反相器=便可依據其輸人端的電壓準位於其輸出端輸 -邏輯高準位的重置信號SR以重置系統，而避免系統因 為所接收的電源電壓VDD過低轉致誤動作的發生。’ 然如圖2B所示，若是當電容C1上的放電速度過慢 將使得電容ci上的跨壓無騎時下降至反相^αι的轉離 準位，就會使得反相H A1無法於其輸出端輸出重置^ R’並進而使系統目為電源輕VDD過低而導致不可預 期之狀態發生。當電源電壓VDD回復正作電壓後， 系統將因其内部訊號錯亂而無法正常工作。 上述圖1A為習知之電源重置電路剛a僅為多種習 知電源重置電路的其中一種’其它習知的電源重置電路例 如可將電源重置電路100A中的電阻R1置換為-P型電晶 體Q1或N型電晶體⑷，其_的方式如圖1B〜1D所示。 反相器A1輸出端的電壓波形以及電源重置電路201206069 jyv i w 34863twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a reset circuit, and more particularly to a power on reset circuit for a power supply. [Prior Art] When designing an electronic circuit, a reset mechanism is often added to the circuit to allow the designed electronic circuit to return to its original state when needed. Especially when the electronic circuit is turned on (power on), each component (such as the scratchpad) in the circuit is in an indeterminate state, and then the circuit components need to be reset to set the components in the circuit to the initial state. . 1A is a circuit diagram of a conventional power supply reset circuit. Referring to FIG. 1A, a conventional power supply reset circuit 1A includes a resistor Rb capacitor C1 and an inverter A1. The resistor R1 is coupled between the power supply voltage VDD and the input terminal of the inverter A1, and the capacitor C1 is coupled between the input terminal of the inverter A1 and the ground voltage GND. Referring to FIG. 1A, FIG. 2A and FIG. 2B simultaneously, FIG. 2A is a voltage waveform diagram of the output end of the inverter A1 in the power reset circuit of FIG. 1A, and FIG. 2B is a voltage waveform of the voltage across the capacitor C1 of FIG. Figure. When the power of the system is turned on, the voltage of the power supply voltage VDD gradually rises. At this time, the f voltage on the capacitor C1 gradually rises. When the voltage across the capacitor C1JL is charged, the reverse state of the inverter A1 is reversed. The output of phase comparator A1 is switched from the logic plane level to the logic low level. When the power supply voltage VDD drops for some reason (non-power off), the stored energy in the capacitor C1 will pass through the ^63ΐ\νί·(1οε/η 201206069 transistor Q1 flows to the power supply voltage VDD' to make the capacitor α The drop in voltage across the capacitor C1 drops to the reverse phase of the Wei state of the inverter inverter = can be reset according to the voltage of its input terminal at its output - logic high level reset signal SR to reset The system avoids the system from malfunctioning due to the received power supply voltage VDD being too low. 'But as shown in Figure 2B, if the discharge speed on the capacitor C1 is too slow, the voltage across the capacitor ci will fall. To the inversion of the ^αι turn-off level, the inverted H A1 can not output the reset ^ R ' at its output and thus make the system look like the power supply light VDD is too low and cause an unpredictable state. After the voltage VDD returns to the positive voltage, the system will not work properly due to the internal signal disorder. The above-mentioned FIG. 1A is a conventional power supply reset circuit just a kind of one of the various conventional power supply reset circuits. The reset circuit can be, for example A power reset circuit 100A of the resistor R1 is replaced with an N-type transistor Q1 or ⑷ -P type electric crystal which 1B~1D _ manner shown in FIG. A1 output terminal voltage waveform of the inverter and a power supply reset circuit
〜腦中電容C1上跨壓的電壓波形分別類似於圖2A 與圖2B所示的電壓波形，其作動原理類似於圖认之電源 重置電路100A，在此不再贅述。 【發明内容】 本發明提供-種電源重置電路，確保在電源下降成低 電壓時可有效發出重置信號。 本發明提出-種電源重置電路，包括一電源重置單 201206069 jyoivv 34S63twf.doc/n 元 〜一電塵偵别單元以及一開關單元。其中電源重置單元 具有-電阻電容電路域至電源重置單元的輸人端並產生 一延遲輸入電壓，電源重置單元依據延遲輪入電壓及一第 :臨界電鮮仙在其輸出端輸出-重置錢。電㉝貞測 單元接收並偵測一電源電壓，並依據電源電壓的電壓準位 下降-偏移電壓來產生—關信號。另外，關單元輕接 在電壓_單元與電源重置單元之輸人端間，依據開關信 號導通而使電源重置單元之輸入端導通至一參考電壓。 ，本發明之-實施例中，上述之電壓偵測單元包括一 壓降單元與_緩衝II。其巾壓降單元_接電源電壓，並將 電源電^的電壓準位下降一偏移電壓以使電壓搞測單元產 ΐ開關信號。另外緩衝器之輸入端與輸出端分別耗接壓降 單元與開關單元，當電源電壓下降一偏移電壓後之電壓準 位低於—第二臨界電壓準位時，緩衝器輸出開關信號。 在本發明之一實施例中，上述之緩衝器為一反相器。 —在本發明之一實施例中，電源重置電路更包括一第一 電容單元.，其耦接於電源電壓與緩衝器之輸入端之間。 一在本發明之一實施例中，上述之壓降單元為一二極體 ，其中二極體元件的陽極耦接電源電壓，二極體元件 的陰極靱接緩衝器之輸入端。 一雷f本發明之一實施例中’上述之二極體元件包括一第 B曰體，第一電晶體之源極耦接電源電壓，第一電晶體 /及，接緩衝器，第—電晶體之閘極與錄相互輕接。 本發明之一實施例中，上述之開關單元包括一 N型 201206069 w63twf.d〇c/n 電晶體，其閘極耦接電壓偵測單元，N型電晶體的汲極與 源極分別耦接電源重置單元與參考電壓。 、 在本發明之一實施例中，上述之電源重置單元包括— ，抗單元、一第二電容單元以及一第二反相器。其中阻抗 單元轉接於電源電壓與電源重置單元的輸入端之間。第二 電谷單元叙接於電源重置單元的輸入端與參考電壓之間， 第二電容單元與阻抗單元形成電阻電容電路，其中延遲輸 入電壓為第二電容單元上之跨壓。第二反相器之輸入端與 輸出端分別耦接電源重置單元之輸入端與輸出端，當第二 電谷單元之電壓低於第一臨界電壓準位時，輸出重置信號。 在本發明之一實施例中，上述之阻抗單元包括一第一 延遲電晶體，其源極耦接電源電壓，第一延遲電晶體之汲 極耦接第二電容單元，第一延遲電晶體之閘極與汲極相互 輕接。 在本發明之一實施例中，上述之阻抗單元包括一第二 延遲電晶體，其源極麵接電源電壓，第二延遲電晶體之没 極耦接第二電容單元，第二延遲電晶體之閘極耦接參考電 壓。 基於上述，本發明利用提高電源重置單元中電容電阻 電路的放電速度，將電源重置單元輸入端上延遲輸入電壓 的電壓快速拉低，以確保電源重置單元可發出重置信號， 避免系統因為電壓過低而導致誤動作的發生。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 201206069 ττ 34863twf.doc/n 【實施方式】 圖3為本發明一實施例之電源重置電路的示意圖。請 參照圖3，其中電源重置電路300内建於一系統(未繪示） 中，電源重置電路300包括電源重置單元302、電壓彳貞測 單元304、以及開關單元306。其中開關單元306耦接在電 壓偵測單元304與電源重置單元302的輸入端之間，電源 重置單元302具有一電阻電容電路(未繪示），其耦接至電 • 源重置單元302的輸入端，並在電源重置單元302的輸入 端產生一延遲輸入電壓Vd。電壓偵測單元304用以價測系 統的電源電壓VDD，並依據電源電壓VDD下降一偏移電 壓後的電壓來產生開關信號S1。開關單元306則依據開關 信號S1將電源重置單元3〇2的輸入端導通至參考電壓The voltage waveforms of the voltage across the capacitor C1 in the brain are similar to those of the voltage waveforms shown in FIG. 2A and FIG. 2B, respectively, and the operation principle is similar to that of the power supply reset circuit 100A, which will not be described herein. SUMMARY OF THE INVENTION The present invention provides a power reset circuit that ensures that a reset signal can be effectively asserted when the power supply drops to a low voltage. The invention provides a power reset circuit, including a power reset unit 201206069 jyoivv 34S63twf.doc/n yuan ~ a dust detection unit and a switch unit. The power reset unit has a resistor-capacitor circuit domain to the input end of the power reset unit and generates a delayed input voltage, and the power reset unit outputs the output voltage according to the delay turn-in voltage and a first: Reset the money. The power detection unit receives and detects a power supply voltage, and generates a -off signal according to the voltage level drop-offset voltage of the power supply voltage. In addition, the off unit is lightly connected between the voltage_unit and the input end of the power reset unit, and the input end of the power reset unit is turned on to a reference voltage according to the switch signal being turned on. In the embodiment of the present invention, the voltage detecting unit includes a voltage drop unit and a buffer unit II. The towel voltage drop unit_ is connected to the power supply voltage, and the voltage level of the power supply voltage is lowered by an offset voltage to cause the voltage detection unit to generate the switching signal. In addition, the input terminal and the output terminal of the buffer respectively consume the voltage drop unit and the switch unit, and when the voltage level of the power supply voltage drops by an offset voltage is lower than the second threshold voltage level, the buffer outputs a switching signal. In an embodiment of the invention, the buffer is an inverter. In one embodiment of the invention, the power supply reset circuit further includes a first capacitor unit coupled between the power supply voltage and the input of the buffer. In an embodiment of the invention, the voltage drop unit is a diode, wherein an anode of the diode element is coupled to a power supply voltage, and a cathode of the diode element is coupled to an input end of the buffer. In one embodiment of the present invention, the diode component includes a B-body, the source of the first transistor is coupled to a power supply voltage, the first transistor/and, the buffer, and the first The gate of the crystal is connected to the record. In an embodiment of the invention, the switch unit includes an N-type 201206069 w63 twf.d〇c/n transistor, the gate is coupled to the voltage detecting unit, and the drain of the N-type transistor is coupled to the source respectively. Power supply reset unit and reference voltage. In an embodiment of the invention, the power reset unit comprises - an anti-cell, a second capacitor unit and a second inverter. The impedance unit is connected between the power supply voltage and the input of the power reset unit. The second valley unit is connected between the input end of the power reset unit and the reference voltage, and the second capacitor unit and the impedance unit form a resistor-capacitor circuit, wherein the delayed input voltage is a voltage across the second capacitor unit. The input end and the output end of the second inverter are respectively coupled to the input end and the output end of the power reset unit, and when the voltage of the second electric valley unit is lower than the first threshold voltage level, the reset signal is output. In an embodiment of the invention, the impedance unit includes a first delay transistor, the source of which is coupled to the power supply voltage, the drain of the first delay transistor is coupled to the second capacitor unit, and the first delay transistor The gate and the bungee are connected to each other. In an embodiment of the invention, the impedance unit includes a second delay transistor, the source of which is connected to the power supply voltage, the second delay transistor is coupled to the second capacitor unit, and the second delay transistor The gate is coupled to the reference voltage. Based on the above, the present invention utilizes increasing the discharge speed of the capacitor resistance circuit in the power reset unit, and rapidly lowering the voltage of the delay input voltage at the input end of the power reset unit to ensure that the power reset unit can issue a reset signal to avoid the system. The malfunction occurs because the voltage is too low. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. 201206069 ττ 34863twf.doc/n Embodiments FIG. 3 is a schematic diagram of a power reset circuit according to an embodiment of the present invention. Referring to FIG. 3, the power reset circuit 300 is built in a system (not shown). The power reset circuit 300 includes a power reset unit 302, a voltage detection unit 304, and a switch unit 306. The switch unit 306 is coupled between the voltage detecting unit 304 and the input end of the power reset unit 302. The power reset unit 302 has a resistor-capacitor circuit (not shown) coupled to the power source reset unit. An input of 302 and a delayed input voltage Vd is generated at the input of power reset unit 302. The voltage detecting unit 304 is configured to measure the power supply voltage VDD of the system, and generate a switching signal S1 according to the voltage of the power supply voltage VDD falling by an offset voltage. The switch unit 306 turns on the input end of the power reset unit 3〇2 to the reference voltage according to the switch signal S1.
Vf’其中此參考電壓vf可為系統中電壓準位較低的電壓， 例如接地電壓。 電源重置早元302的輸入端被導通至參考電壓vf 後，將使得電源重置單元302中的電阻電容電路經由開關 鲁 單元306往參考電壓Vf放電，而使得電源重置單元3〇2 輸入端上的延遲輸入電壓Vd的電壓準位快速的下降，一 旦延遲輸入電壓Vd的電壓準位低於第一臨界電壓準位 時’電源重置單元302便於其輸出端輸出重置信號SR以 重置系統中的電路元件。如此藉由電壓偵測單元3〇4偵測 電源電壓VDD雜降來蝴開财元料通狀態， 進而將延遲輸入電壓Vd的電壓準位迅速的拉低至低於與 第-臨界電壓準位，即可確保電源重置單元3〇2有效的在 201206069 >4863twf.doc/n 其輸出端輸出重置信號SR，避免電源電壓VDD從低電壓 回復正常工作電壓後，系統因其内部訊號錯亂而無法正常 工作。 進一步來說，圖3所示之電源重置電路300可以圖4 的方式來實現。圖4為本發明另一實施例之電源重置電路 的示意圖。在本實施例中’電源重置電路4〇〇中的電壓偵 測單元304包括壓降單元402·、緩衝器B1以及電容單元 404。其中緩衝器B1用以緩衝其輸入端的電壓，其可如本 實施例利用一反相器A2來實施，然不以此為限。壓降單 7L 402耦接於電源電壓VDD與緩衝器B1的輸入端之間， 電容單元404則耦接於緩衝器B1的輸入端與電源電壓 VDD之間。壓降單元4〇2可利用一二極體元件來實施，其 中二極體it件的陽極祕電源電壓VDD，4航件险 極^麵接緩衝H B1的輸人端例如在本實施例中，二: 體S件為P型的金氧半場效電晶體 的源=電源電壓，電晶體Q2的汲極_^ 壓降單元 402的一極體讀也可以 N型的金氧半場 、他:;=广曰體’以耦接成二極體的組態 5 本實施例之電容單元4〇4蛊 傅 本實施例的_單元3G6為—N : = C2來實施’而 電二體m的閘_接至電壓價測單元3緩、中n二 N型電晶魏 201206069 34863twf.doc/n 另外，電源重置單元302包括阻抗單元4〇6、電容單 元408以及反相胃A3。其中阻抗單元4〇6_接於電源電歷 VDD與電源重置單元3〇2的輸入端之間，電容單元4〇8輕 接於電源重置單元302的輸入端與參考電壓Vf之間，其 中電容單元408與阻抗單元4〇6形成一電阻電容電路 410。反相器A3之輸入端與輸出端分別耦接電源重置單元 302的輸入端與輸出端。在本實施例中，阻抗單元4〇6為 利用一延遲電晶體Q3來實現，其中延遲電晶體Q3的源極 耦接電源電壓VDD，延遲電晶體Q3的汲極耦接反相器 A3，延遲電晶體Q3的閘極與汲極相互耦接。其中，電容 早元408在本實施例中為一電容C3。 以下凊參照圖5A〜圖5D，圖5A〜圖5D分別繪示重置 1吕號SR與電源電壓VDD、開關信號S1與電源電壓VDD、 電容C2上跨壓與電源電壓VDD以及電容C3上跨壓與電 源電壓VDD的電壓準位波形圖。以下將配合圖5A〜5D進 行電源重置電路400的說明。 鲁 當系統的電源開啟時’電源電壓VDD的電壓漸漸上 升，此時電容C2、C3被電源電壓VDD充電，而使電容 C2、C3上的跨壓漸漸上升。其中由於電容C3為經由延遲 電晶體Q3被充電，因此電容C3上跨壓的起始上升時間點 將略晚於電容C2,且電容C3上的跨壓小於電源電壓VDD 一臨界電壓值。類似地，由於壓降單元402可依據電源電 壓VDD的電壓準位將其下降一偏移電壓(亦即電晶體Q2 的臨界電壓）’因此電容C2被充電至飽和時，電容C2上 ^»63twf.doc/n 201206069 的跨壓亦會小於電源電壓VDD 一個臨界電壓值β 另一方面’重置信號SR的電壓準位亦隨電源電藤 VDD漸漸上升，當電容上的跨壓被充電至第一臨界電 壓準位時，反相器A3便依據其輸入端的電壓(亦即電容C3 上的跨壓)將其輸出端的重置信號SR轉為邏輯低電麈举 位。在此期間，由於反相器A2輸入端的電壓準位隨電滹 電壓VDD持續升高’因此反相器A2輸出端的開關信成 S1將持續維持邏輯低電壓準位，而保持n型電晶體Ml處 於關閉狀態。 當電源電壓VDD因為某種原因而下降時，電容C2 與電容C3上的跨壓亦隨之下降。其中電容C2中所儲存的 電能可直接對電源電壓VDD進行放電，且由於電容C2〆 端的電壓受制於電晶體Q2,因此電容C2上的跨壓下降時 保持低於電源電壓VDD —個偏移電壓值。另外，電容C3 由於只能透過延遲電晶體Q3放電，因此其跨壓的下降速 度將會小於電源電壓VDD的下降速度。 當電源電壓VDD反相器A2輸入端上的電壓（亦即電 容C2上的跨壓)小於一第二臨界電壓準位(亦即反相器A2 的轉態點電壓準位，在本實施例中為2V)時，反相器A2 將開關信號S1的電壓準位由邏輯低電壓準位轉為邏輯高 電壓準位，如圖5C所示，開關信號S1的電壓準位將等於 電源電壓VDD的電壓準位。同時，開關單元306(亦即N 型電晶體Ml)將受控於開關信號S1而被開啟。如此一來， 電源重置單元302的輸入端便可經由開N型電晶體Ml連 201206069 * τ, 34863twf.doc/n 接至參考電壓Vf，而將電容C3上的跨愿瞬間拉至邏輯低 電壓準位，使電容C3可經由N型電晶體Ml對參考電壓 Vf進行放電。 在此同時，由於電容C3上的跨壓瞬間被拉低至小於 第-臨界電麗準位(2V)，因此反相器A3將重置信號张的 電壓準位由邏輯低電壓準位轉態為邏輯高電壓準位，進而 將系統中的電路元件重置，避免系統因為電壓過低而導致 誤動作的發生。 值知注意的是，上述之開關單元306以及電廢偵測單 元304中所包括的壓降單元402與電容單元404的實施方 式僅為示範性的實施例，在實際應用上並不以此為限。另 外，電壓偵測單元304以及開關單元30ό亦可配合具有不 同電阻電容電路的電源重置單元3〇2，來確保電源重置單 元302可發出重置信號sr。 舉例來說，圖6、7為本發明配合不同電源重置單元 的電源重置電路的實施例的示意圖。其中圖6之電源重置 • 電路600與圖4之電源重置電路4〇〇的不同之處在於，圖 6之電阻電容電路61〇中的延遲電晶體(^的閘極為耦接至 參考電壓Vf’而圖7之電源重置電路700與圖4之電源重 置電路400的不同之處在於，圖7之電阻電容電路71〇以 一 N型電晶體M2取代延遲電晶體q3。其中n型電晶體 M2的汲極耦接電源電壓VDD，N型電晶體M2的源極耦 接電容C3，N型電晶體M2的閘極則耦接至N型電晶體 M2的汲極。圖6與圖7之電源重置電路6〇〇、7〇〇的作動 f&63twf.doc/n 201206069 4所揭露的實施例，本領域具通常知識者 應可依據上述實施儀教㈣推得，因此不再資述。Vf' wherein the reference voltage vf can be a voltage having a lower voltage level in the system, such as a ground voltage. After the input of the power reset early 302 is turned on to the reference voltage vf, the resistor-capacitor circuit in the power reset unit 302 will be discharged to the reference voltage Vf via the switch unit 306, so that the power reset unit 3〇2 inputs The voltage level of the delayed input voltage Vd on the terminal is rapidly decreased. When the voltage level of the delayed input voltage Vd is lower than the first threshold voltage level, the power reset unit 302 facilitates outputting the reset signal SR at its output terminal to Place the circuit components in the system. In this way, the voltage detecting unit 3〇4 detects the power supply voltage VDD noise drop to open the fiscal material pass state, and then rapidly lowers the voltage level of the delayed input voltage Vd to be lower than the first critical voltage level. , it can ensure that the power reset unit 3〇2 effectively outputs the reset signal SR at its output end in 201206069 >4863twf.doc/n, to avoid the internal signal being disordered after the power supply voltage VDD returns from the low voltage to the normal working voltage. It doesn't work. Further, the power reset circuit 300 shown in FIG. 3 can be implemented in the manner of FIG. 4 is a schematic diagram of a power reset circuit according to another embodiment of the present invention. The voltage detecting unit 304 in the 'power reset circuit 4' in the present embodiment includes a voltage drop unit 402·, a buffer B1, and a capacitor unit 404. The buffer B1 is used to buffer the voltage at its input, which can be implemented by using an inverter A2 as in this embodiment, but not limited thereto. The voltage drop unit 7L 402 is coupled between the power supply voltage VDD and the input end of the buffer B1, and the capacitor unit 404 is coupled between the input end of the buffer B1 and the power supply voltage VDD. The voltage drop unit 4〇2 can be implemented by using a diode element, wherein the anode terminal power supply voltage VDD of the diode element is connected to the input end of the buffer H B1 , for example, in this embodiment. 2: The body S is the source of the P-type MOS field-effect transistor = the power supply voltage, the drain of the transistor Q2 _^ The one-pole reading of the voltage drop unit 402 can also be the N-type MOS half-field, he: ; = 曰 ' 以 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 耦 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容The gate is connected to the voltage price measuring unit 3, and the n-n-type N-type electric crystal Wei 201206069 34863twf.doc/n In addition, the power reset unit 302 includes an impedance unit 4〇6, a capacitor unit 408, and a reverse phase stomach A3. The impedance unit 4〇6_ is connected between the power supply VDD and the input end of the power reset unit 3〇2, and the capacitor unit 4〇8 is lightly connected between the input end of the power reset unit 302 and the reference voltage Vf. The capacitor unit 408 and the impedance unit 4〇6 form a resistor-capacitor circuit 410. The input end and the output end of the inverter A3 are respectively coupled to the input end and the output end of the power reset unit 302. In this embodiment, the impedance unit 4〇6 is implemented by using a delay transistor Q3, wherein the source of the delay transistor Q3 is coupled to the power supply voltage VDD, and the drain of the delay transistor Q3 is coupled to the inverter A3, and the delay is delayed. The gate of the transistor Q3 is coupled to the drain. The capacitor early 408 is a capacitor C3 in this embodiment. 5A to 5D, FIG. 5A to FIG. 5D respectively show resetting the 1st SR and the power supply voltage VDD, the switching signal S1 and the power supply voltage VDD, the voltage across the capacitor C2 and the power supply voltage VDD, and the capacitor C3. Voltage level waveform diagram of voltage and power supply voltage VDD. The description of the power reset circuit 400 will be made in conjunction with Figs. 5A to 5D. When the power of the system is turned on, the voltage of the power supply voltage VDD gradually rises. At this time, the capacitors C2 and C3 are charged by the power supply voltage VDD, and the voltage across the capacitors C2 and C3 gradually rises. Since the capacitor C3 is charged via the delay transistor Q3, the initial rise time of the voltage across the capacitor C3 will be slightly later than the capacitor C2, and the voltage across the capacitor C3 is less than the threshold voltage of the power supply voltage VDD. Similarly, since the voltage drop unit 402 can drop it by an offset voltage (that is, the threshold voltage of the transistor Q2) according to the voltage level of the power supply voltage VDD, so when the capacitor C2 is charged to saturation, the capacitance C2 is ^63wf The cross-voltage of .doc/n 201206069 will also be less than the power supply voltage VDD. A threshold voltage value β On the other hand, the voltage level of the reset signal SR also rises with the power supply vine VDD. When the voltage across the capacitor is charged to the first At a threshold voltage level, inverter A3 converts the reset signal SR at its output to a logic low power 麈 according to the voltage at its input (ie, the voltage across capacitor C3). During this period, since the voltage level at the input of the inverter A2 continues to rise with the voltage VDD, the switching signal S1 at the output of the inverter A2 will continue to maintain the logic low voltage level while leaving the n-type transistor M1 at Disabled. When the power supply voltage VDD drops for some reason, the voltage across the capacitor C2 and the capacitor C3 also decreases. The electric energy stored in the capacitor C2 can directly discharge the power supply voltage VDD, and since the voltage at the end of the capacitor C2 is controlled by the transistor Q2, the voltage across the capacitor C2 drops below the power supply voltage VDD-offset voltage. value. In addition, since capacitor C3 can only discharge through the delay transistor Q3, the speed at which the voltage across the voltage drops will be less than the rate at which the power supply voltage VDD falls. When the voltage on the input terminal of the power supply voltage VDD inverter A2 (that is, the voltage across the capacitor C2) is less than a second threshold voltage level (that is, the voltage point of the inverter A2), in this embodiment. In the middle of 2V), the inverter A2 turns the voltage level of the switching signal S1 from the logic low voltage level to the logic high voltage level. As shown in FIG. 5C, the voltage level of the switching signal S1 will be equal to the power supply voltage VDD. Voltage level. At the same time, the switching unit 306 (i.e., the N-type transistor M1) will be turned on by the switching signal S1. In this way, the input end of the power reset unit 302 can be connected to the reference voltage Vf via the open N-type transistor M1, 201206069 * τ, 34863 twf.doc/n, and the cross-hopping moment on the capacitor C3 is pulled to the logic low. The voltage level allows the capacitor C3 to discharge the reference voltage Vf via the N-type transistor M1. At the same time, since the voltage across the capacitor C3 is pulled down to less than the first critical voltage level (2V), the inverter A3 shifts the voltage level of the reset signal sheet from the logic low voltage level. It is a logic high voltage level, which in turn resets the circuit components in the system to prevent the system from malfunction due to low voltage. It should be noted that the implementations of the voltage drop unit 402 and the capacitor unit 404 included in the above-mentioned switch unit 306 and the power waste detection unit 304 are merely exemplary embodiments, and are not used in practical applications. limit. In addition, the voltage detecting unit 304 and the switching unit 30A can also cooperate with the power reset unit 3〇2 having different resistor-capacitor circuits to ensure that the power reset unit 302 can issue the reset signal sr. For example, Figures 6 and 7 are schematic views of an embodiment of a power reset circuit of the present invention in conjunction with different power reset units. The power reset circuit 600 of FIG. 6 is different from the power reset circuit 4 of FIG. 4 in that the delay transistor in the resistor-capacitor circuit 61 of FIG. 6 is coupled to the reference voltage. Vf' and the power reset circuit 700 of FIG. 7 is different from the power reset circuit 400 of FIG. 4 in that the RC circuit 71 of FIG. 7 replaces the delay transistor q3 with an N-type transistor M2. The drain of the transistor M2 is coupled to the power supply voltage VDD, the source of the N-type transistor M2 is coupled to the capacitor C3, and the gate of the N-type transistor M2 is coupled to the drain of the N-type transistor M2. Figure 6 and Figure The embodiment of the power-reset circuit of the power-reset circuit of 6 〇〇, 7 f f & 63 twf. doc / n 201206069 4, the general knowledge of the field should be based on the above-mentioned implementation instrument (4), so no longer Capital statement.
另外，上述實施例雖皆設定重置信號SR在邏輯高電 壓準位時對系統中的電路元件進行重置，然實際應用上並 不以此為限。視乎系統中電路元件的特性亦可設定重置作 號SR在邏輯低電壓準位時對系統中的電路元件進行重置: •綜上所述，本發明利用電壓偵測單元偵測電源電壓的 壓降，並依據電源電壓的壓降將電源重置單元的輸入端導 通至一參考電壓，以加速電源重置單元中電容電阻電路的 放電，將電源重置單元輸入端上延遲輸入電壓的電壓快速 拉低’以確保電源重置單元可發出重置信號，避免系統因 為電壓過低而導致誤動作的發生。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明’任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤倚，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。In addition, although the above embodiment sets the reset signal SR to reset the circuit components in the system at the logic high voltage level, the actual application is not limited thereto. Depending on the characteristics of the circuit components in the system, the reset signal SR can be reset to reset the circuit components in the system at the logic low voltage level: • In summary, the present invention utilizes the voltage detection unit to detect the power supply voltage. Voltage drop, and according to the voltage drop of the power supply voltage, the input end of the power reset unit is turned on to a reference voltage to accelerate the discharge of the capacitor resistance circuit in the power reset unit, and the input voltage of the power reset unit is delayed. The voltage is pulled low quickly to ensure that the power reset unit can issue a reset signal to prevent the system from malfunction due to low voltage. The present invention has been disclosed in the above embodiments, and is not intended to limit the scope of the present invention, and the invention may be modified and practiced without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
【圖式簡單說明】 圖1A〜圖1D為習知之電源重置電路的電路圖。 圖2A為圖1之電源重置電路中反相器A1輸出端的 電壓波形圖。 圖2B為圖1之電容上跨壓的電壓波形圖。 圖3為本發明一實施例之電源重置電路的示意圖。 圖4為本發明另一實施例之電源重置電路的示意圖。 圖5A〜5D為圖4實施例之電源重置電路的多個電壓 12 34863twf.doc/n 201206069 j y\j x »▼ 準位波形圖。 圖6、7為本發明配合不同電源重置單元的電源重置 電路的實施例的示意圖。 【主要元件符號說明】 100A〜100D、300、400、600、700 :電源重置電路 302 :電源重置單元 304 :電壓偵測單元 • 3〇6:開關單元 402 :壓降單元 404、408 :電容單元 406 :阻抗單元 410、610、710 :電阻電容電路 A1〜A3 :反相器 B1 :緩衝器 Ql、Q2 :電晶體 Q3 :延遲電晶體 _ VDD:電源電壓 GND :接地電壓 C1〜C3 :電容 Vf:參考電壓 S1 :開關信號 SR:重置信號 Ml〜M2 : N型電晶體 Vd :延遲輸入電壓 13BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are circuit diagrams of a conventional power supply reset circuit. 2A is a voltage waveform diagram of the output terminal of the inverter A1 in the power supply reset circuit of FIG. 1. 2B is a voltage waveform diagram of the voltage across the capacitor of FIG. 1. 3 is a schematic diagram of a power reset circuit according to an embodiment of the present invention. 4 is a schematic diagram of a power reset circuit according to another embodiment of the present invention. 5A-5D are a plurality of voltages of the power reset circuit of the embodiment of FIG. 4 12 34863 twf.doc/n 201206069 j y\j x »▼ level waveform diagram. 6 and 7 are schematic views of an embodiment of a power reset circuit of the present invention in conjunction with different power reset units. [Main component symbol description] 100A to 100D, 300, 400, 600, 700: power supply reset circuit 302: power supply reset unit 304: voltage detection unit • 3〇6: switch unit 402: voltage drop unit 404, 408: Capacitor unit 406: impedance unit 410, 610, 710: resistor-capacitor circuits A1 to A3: inverter B1: buffers Q1, Q2: transistor Q3: delay transistor _ VDD: power supply voltage GND: ground voltage C1 to C3: Capacitor Vf: Reference voltage S1: Switching signal SR: Reset signal M1 to M2: N-type transistor Vd: Delayed input voltage 13