JP5267392B2 - Pulse generation circuit and level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reproducibility of an L/H ratio of an input signal. <P>SOLUTION: An edge detection circuit 13 detects the trailing edge of an input binary signal, and an edge detection circuit 14 detects the rising edge of the binary signal. A latch circuit 15 is set when the trailing edge is detected. A delay circuit 17 delays the output signal of the latch circuit 15 by a predetermined time and outputs the same. A latch circuit 16 is set when the rising edge is detected. A delay circuit 18 delays the output signal of the latch circuit 16 by a predetermined time and outputs the same. In this case, the latch circuit 15 is reset by the output of the delay circuit 17 and also reset by the detection of the rising edge. The latch circuit 16 is reset by the output of the delay circuit 18 and also reset by the detection signal of the trailing edge. The output signals of the latch circuits 15 and 16 become generated pulse signals. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an electronic circuit technology, and more particularly to a technology of an electric pulse generation circuit suitable for use in a level shift circuit used in a DC-DC converter or the like.

  There are some known level shift circuits that shift the signal level of an input signal that is a binary signal using a pulse generation circuit that detects the edge of the input signal and generates a pulse signal. .

  A first example of a level shift circuit including a pulse generation circuit is shown in FIG. This level shift circuit shifts a binary signal represented by the power supply potential VDD and the ground potential, which is input to the input terminal IN, to a signal represented by V2H and V2L, and outputs it from the output terminal OUT. Circuit.

  In FIG. 4, the inverters U101 and U102 are applied with V2L as the reference potential and V2H as the power supply potential. A resistor R101 is connected between the input of the inverter U101 and the output of the inverter U102, and a resistor R102 is connected between the output of the inverter U101 and the input of the inverter U102. Note that the output of the inverter U102 is led to the output terminal OUT.

  The drain terminal of the transistor M101 is connected to the input of the inverter U101, and the drain terminal of the transistor M102 is connected to the input of the inverter U102. The transistors M101 and M102 are both N-channel MOS (Metal Oxide Semiconductor) transistors, and both of their source terminals are connected to the circuit ground.

  When the pulse generation circuit 100 detects the falling edge of the signal input to the input terminal IN, the pulse generation circuit 100 outputs a pulse signal having a very small width from the output OUT1 and inputs the pulse signal to the gate terminal of the transistor M101. In addition, when the pulse generation circuit 100 detects a rising edge of a signal input to the input terminal IN, the pulse generation circuit 100 outputs a pulse signal having a very small width from the output OUT2 and inputs the pulse signal to the gate terminal of the transistor M102.

  When a pulse signal is output from the output OUT1, the drain-source of the transistor M101 transitions to an on (conductive) state. As a result, the input of the inverter U101 is pulled down to the ground potential. As a result, the output of the inverter U101 is H (high). ) Level, that is, V2H. At this time, since the transistor M102 is in the off state, the output of the inverter U102, to which the output of the inverter U101 is connected to the input via the resistor R102, is L (low) level, that is, V2L.

  On the other hand, when a pulse signal is output from the output OUT2, the drain-source of the transistor M102 transitions to an on (conducting) state. As a result, the input of the inverter U102 is pulled down to the ground potential. Level, that is, V2H. At this time, since the transistor M101 is in the OFF state, the output level of the inverter U101 to which the output of the inverter U102 is input via the resistor R101 is L level, that is, V2L.

Since the circuit of FIG. 4 operates as described above, the level of the output terminal OUT of the level shift circuit to which the output of the inverter U102 is guided each time the value of the binary signal input to the input terminal IN is inverted. Alternate between V2H and V2L. This level shift circuit consumes less power because the transistors M101 and M102 are kept off during a period in which the potential of the input IN is not changed.

  Next, FIG. 5 will be described. FIG. 5 shows a second example of a level shift circuit including a pulse generation circuit. This level shift circuit is a circuit that shifts the level of a binary signal input to the input terminal IN and outputs it to the output terminal OUT, and is disclosed in Patent Document 1.

  In FIG. 5, the pulse generator 110 selects either the first output terminal OR or the second output terminal OS according to the edge direction of the signal input from the input terminal ID via the input terminal IN of the level shift circuit. A pulse signal is output from either one of the two. The pulse signal output from the first output terminal OR is input to the gate terminal of the transistor M111, and the pulse signal output from the second output terminal OS is input to the gate terminal of the transistor M112.

  Both the transistors M111 and M112 are N-channel MOS transistors. The drain terminals of the transistors M111 and M112 are individually connected to the level shift circuit 111, and both of the source terminals are connected to the circuit ground. The diodes DR and DS are parasitic diodes between the source and drain of the transistors M111 and M112, respectively.

  The level shift circuit 111 includes therein a connection point between the drain terminal of the transistor M111 and the reset input terminal IR of the flip-flop circuit 112, a resistor (not shown) that pulls up the connection point to a reference voltage, and a drain of the transistor M112. A connection point between the terminal and the set input terminal IS of the flip-flop circuit 112 and a resistor (not shown) for pulling up the connection point to a reference voltage are provided. A reference voltage is applied as a power supply potential to the flip-flop circuit 112, and this output terminal OQ is led to the output terminal OUT of the level shift circuit of FIG.

  In the circuit of FIG. 5, when a pulse signal is output from the first output terminal OR of the pulse generator 110, the drain-source state of the transistor M <b> 111 is turned on, so that the reset input terminal IR of the flip-flop circuit 112. As a result, the flip-flop circuit 112 is reset. On the other hand, when a pulse signal is output from the second output terminal OS of the pulse generator 110, the drain-source state of the transistor M112 is turned on, so that the input to the set input terminal IS of the flip-flop circuit 112 is the ground. As a result of being pulled down to the potential, the flip-flop circuit 112 is set.

  Since the circuit of FIG. 5 operates as described above, every time the value of the binary signal input to the input terminal IN is inverted, the set / reset for the flip-flop circuit 112 is alternately performed and the output terminal OUT Output levels alternately change between H level and L level.

  Next, FIG. 6 will be described. FIG. 6 is an example of a pulse generation circuit. This pulse generation circuit is disclosed in Patent Document 1 as an example of the pulse generator 110 in the level shift circuit of FIG.

  In the pulse generation circuit of FIG. 6, one of the first output terminal OR and the second output terminal OS outputs a pulse signal according to the rising edge of the signal input to the input terminal ID, and the other according to the falling edge. Outputs a pulse signal.

  In FIG. 6, the input terminal ID is connected to one input terminal of the AND circuit 121 having two inputs, and the inverting output terminal QN1 of the D-type flip-flop circuit 122 is connected to the other input terminal. . The output terminal of the AND circuit 121 is connected to the clock input terminals CK1 and CK2 of the D-type flip-flop circuits 122 and 123, respectively.

  The D-type flip-flop circuit 122 has a negative logic at the clock input terminal CK1, and therefore performs a transition operation in response to a falling edge of a signal input to the clock input terminal CK1. The input terminal D1 of the D-type flip-flop circuit 122 is fixed to logic “1” (that is, an input of H level). The non-inverting output terminal Q1 of the D-type flip-flop circuit 122 is connected to the input terminal of the delay network 124, and the output terminal of the delay network 124 is connected to the reset input terminal R1 of the D-type flip-flop circuit 122. Has been. The first output terminal OR of the pulse generation circuit is connected to the inverting output terminal QN1 of the D-type flip-flop circuit 122.

  On the other hand, the D-type flip-flop circuit 123 has a positive input at the clock input terminal CK2, and therefore performs a transition operation in response to a rising edge of a signal input to the clock input terminal CK2. The input terminal D2 of the D-type flip-flop circuit 123 is also fixed to logic “1” (that is, an H level input). The non-inverting output terminal Q2 of the D-type flip-flop circuit 123 is connected to the input terminal of the delay network 125, and the output terminal of the delay network 125 is connected to one input terminal of the OR circuit 126 having two inputs. It is connected. The other input terminal of the OR circuit 126 is connected to the non-inverting output terminal Q1 of the D-type flip-flop circuit 122, and the output terminal of the OR circuit 126 is connected to the reset input terminal R2 of the D-type flip-flop circuit 123. ing. The second output terminal OS of the pulse generation circuit is connected to the inverting output terminal QN2 of the D-type flip-flop circuit 123.

  The delay networks 124 and 125 are circuits that delay a rising edge in an input signal for a predetermined time while preventing a falling edge in the signal from causing such a delay.

The operation of the pulse generation circuit of FIG. 6 configured as described above will be described with reference to FIG.
FIG. 7 is a timing chart showing an example of signals at the input / output terminals of the pulse generation circuit of FIG. Here, “ID” indicates an example of an input signal to the input terminal ID of the pulse generation circuit, and “OS” and “OR” indicate the second output of the pulse generation circuit according to the input signal, respectively. Signals output from the terminal OS and the first output terminal OR are shown.

  In FIG. 7, first, when the input signal rises at time ta, the output signal from the second output terminal OS (that is, the inverting output terminal QN2 of the D-type flip-flop circuit 123) is as shown in FIG. It becomes L level for a period corresponding to the delay time by the delay network 125.

  Next, when the input signal falls at time tb, the output signal from the first output terminal OR (that is, the inverted output terminal QN1 of the D-type flip-flop circuit 122) is transferred to the delay circuit as shown in FIG. The period becomes L level corresponding to the delay time by the network 124. Since this output signal is input to the AND circuit 121, even if the input signal changes during this period, this change is not transmitted to the clock input terminal CK2 of the D-type flip-flop circuit 123. The output signal from the OS does not change.

Next, when the input signal rises at time tc, the output signal from the second output terminal OS becomes L level as shown in FIG. 4C, but here, the delay by the delay network 125 is thereafter performed. The input signal falls at time td before the period corresponding to time elapses. At this time, the D-type flip-flop circuit 122 sets the output signal from the first output terminal OR to the L level as shown in FIG. 123 is reset to return the output signal from the second output terminal OS to the H level.

  Next, when the input signal rises at time te, the output signal from the second output terminal OS becomes L level for a period corresponding to the delay time by the delay network 125 as shown in FIG.

  Next, when the input signal falls at time tf, the output signal from the first output terminal OR becomes L level as shown in (f) of FIG. Here, at this time, the input signal rises at time tg before the period corresponding to the delay time by the delay network 124 elapses. However, since this output signal is input to the AND circuit 121, the rising change of the input signal is not transmitted to the clock input terminal CK 2 of the D-type flip-flop circuit 123. For this reason, the output signal from the second output terminal OS does not change immediately. However, after that, when a period corresponding to the delay time by the delay network 124 elapses and the output signal from the first output terminal OR returns from the L level to the H level, this signal change (rising edge) causes the AND circuit 121 to change. Via the clock input terminal CK2 of the D-type flip-flop circuit 123. Then, the output signal from the second output terminal OS becomes the L level for a period corresponding to the delay time by the delay network 125 as shown in FIG.

  Thereafter, when the input signal falls at time th, the output signal from the first output terminal OR becomes L level for a period corresponding to the delay time by the delay network 124 as shown in FIG.

  The pulse generation circuit of FIG. 6 operates as described above.

JP-A-9-167948

  As described above as the operation at the times tb and tf in FIG. 7, in the pulse generation circuit in FIG. 6, even if the input signal to the input terminal ID rises immediately after it falls, it corresponds to the delay time by the delay network 124. The output signal from the second output terminal OS does not change and the output signal from the first output terminal OR does not return from the L level to the H level until the period of time to pass. In other words, in the pulse circuit of FIG. 6, the L level period of the output signal from the first output terminal OR is reduced by the delay network 124 no matter how short the L level period of the input signal to the input terminal ID is. It cannot be shorter than the delay time.

  Assuming that the level shift circuit of FIG. 5 having the pulse generation circuit of FIG. 6 is used for a switching power supply used for a DC-DC converter or the like, a signal output from the output terminal OUT of the level shift circuit is Therefore, it is used as a signal for driving a switching element on the high side that is a component of the switching power supply.

The L / H ratio (the ratio between the L level period and the H level period) of the driving signal determines the on-time ratio of the high-side switching element, that is, the output voltage of the switching power supply is determined. It is an important parameter to determine. Therefore, when the L level period in the input signal input to the input terminal IN (that is, the input signal to the input terminal ID in FIG. 6) is shortened, the L level period of the output signal from the first output terminal OR is reproduced. As for the accuracy and clogging, the deterioration of the accuracy of the reproduction of the period in the signal output from the output terminal OUT significantly affects the characteristics of the switching power supply. More specifically, for example, assuming that the high-side switching element is turned on when the signal output from the output terminal OUT is L level, the L level of the input signal input to the input terminal IN Although the output voltage for a light load is to be lowered by the control for shortening the period, the output voltage is not sufficiently lowered. Further, for example, assuming that the high-side switching element is turned off when the signal output from the output terminal OUT is at L level, the L level period of the input signal input to the input terminal IN is shortened. Although it is going to supply more current with respect to heavy load by control, the increase in the supply current will stop.

  Further, in recent switching power supplies, since there is a tendency to increase the switching frequency, the influence of the length of the delay time by the delay network 124 has become relatively larger. However, it is not easy to realize a delay network 124 that has a minimum delay time and that does not become zero even under various usage conditions. Further, as long as this delay time is present, the above-described influence on the characteristics of the switching power supply is essentially left.

  The present invention has been made in view of the above-described problems, and a problem to be solved is to improve the reproducibility of the L / H ratio of the input signal.

  A pulse generation circuit according to one aspect of the present invention includes a first edge detection circuit that detects a falling edge of an input binary signal, a second edge detection circuit that detects a rising edge of the binary signal, A first latch circuit that is set by a falling edge detection signal from the first edge detection circuit; a first delay circuit that outputs the output signal of the first latch circuit with a predetermined first delay time; and A second latch circuit that is set by a rising edge detection signal from the second edge detection circuit, and a second delay circuit that outputs the output signal of the second latch circuit after being delayed by a predetermined second delay time. The first latch circuit is reset by a signal output from the first delay circuit, and a rising edge detection signal from the second edge detection circuit. The second latch circuit is reset by a signal output from the second delay circuit, and also reset by a falling edge detection signal from the first edge detection circuit. An output signal of each of the latch circuit and the second latch circuit is output as a generated pulse signal, and this feature solves the above-described problem.

According to another aspect of the present invention, a pulse generation circuit includes a first edge detection circuit that detects a falling edge of an input binary signal, and a second edge that detects a rising edge of the binary signal. A detection circuit; a first latch circuit set by a falling edge detection signal from the first edge detection circuit; and a first delay for outputting an output signal of the first latch circuit with a predetermined first delay time delay A second latch circuit that is set by a rising edge detection signal from the second edge detection circuit, and a second delay circuit that outputs the output signal of the second latch circuit with a delay of a predetermined second delay time. When the first delay circuit receives a rising edge detection signal from the second edge detection circuit, the first delay circuit receives the output signal of the first latch circuit as When the second delay circuit receives a falling edge detection signal from the first edge detection circuit, the output signal of the second latch circuit is output without delaying a predetermined first delay time. The first latch circuit is reset by a signal output from the first delay circuit, and the second latch circuit is output from the second delay circuit without delaying the predetermined second delay time. It is reset by the output signal, and the output signal of each of the first latch circuit and the second latch circuit is output as a generated pulse signal. Solve.

  In addition, a level shift circuit which is one of further another aspects of the present invention includes the pulse generation circuit which is one of the above-described aspects of the present invention, and alternately includes the first latch circuit and the second latch circuit. In response to the pulse signal output to the signal, a signal in which the signal level is alternately switched between the first voltage value and the second voltage value is output. Solve the problem.

  According to the present invention, it is possible to improve the reproducibility of the L / H ratio of the input signal as described above.

It is a figure which shows the 1st example of a structure of the pulse generation circuit which implements this invention. It is a figure which shows the 2nd example of a structure of the pulse generation circuit which implements this invention. FIG. 3 is a timing chart (part 1) illustrating an example of signals of each part of the edge detection circuit in the pulse generation circuit of FIG. 2; FIG. 3 is a timing chart (part 2) illustrating an example of signals of each part of the edge detection circuit in the pulse generation circuit of FIG. 2. It is a figure which shows the 1st example of a level shift circuit provided with a pulse generation circuit. It is a figure which shows the 2nd example of a level shift circuit provided with a pulse generation circuit. It is a figure which shows an example of a pulse generation circuit. 7 is a timing chart illustrating an example of signals at input / output terminals of the pulse generation circuit of FIG. 6.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, FIG. 1 will be described. FIG. 1 shows a first example of the configuration of a pulse generation circuit that implements the present invention.

  The circuit shown in FIG. 1 can be used as the pulse generation circuit 100 in the level shift circuit shown in FIG. 4, and detects a falling edge of an input signal that is a binary signal input to the input terminal IN. A minute width pulse signal is output from the output terminal OUT1, and when a rising edge of the input signal is detected, a minute width pulse signal is output from the output terminal OUT2.

  The input terminal IN is connected to the respective inputs of the inverter 11 and the buffer 12, the output of the inverter 11 is connected to the input of the edge detection circuit 13, and the output of the buffer 12 is connected to the input of the edge detection circuit 14. Has been.

  The edge detection circuits 13 and 14 are both circuits that detect the rising edge of the input signal. However, since the inverter 11 inverts the value of the input signal, the edge detection circuit 13 detects the falling edge of the binary signal input to the input terminal IN. On the other hand, for example, the buffer 12 constituted by the two-stage cascade connection of the inverter circuits outputs the value of the input signal without inversion, so that the edge detection circuit 14 has the rising edge of the binary signal input to the input terminal IN. Will be detected.

The falling edge detection signal that is the output of the edge detection circuit 13 is connected to the set input of the latch circuit 15, and the rising edge detection signal that is the output of the edge detection circuit 14 is connected to the set input of the latch circuit 16. . Accordingly, the latch circuit 15 is set by the falling edge detection signal from the edge detection circuit 13, and the latch circuit 15 is set by the rising edge detection signal from the edge detection circuit 14.

  The output of the latch circuit 15 is connected to the output terminal OUT1 of this pulse generation circuit and the input of the delay circuit 17. The output of the latch circuit 16 is connected to the output terminal OUT2 of the pulse generation circuit and the input of the delay circuit 18. That is, this pulse generation circuit outputs the output signals of the latch circuits 15 and 16 as generated pulse signals.

The delay circuit 17 delays and outputs the output signal of the latch circuit 15 by a predetermined delay time, and the delay circuit 18 delays and outputs the output signal of the latch circuit 16 by a predetermined delay time.
Each of the latch circuits 15 and 16 has two reset inputs. In the latch circuit 15, one reset input is connected to the output of the delay circuit 17, and the other reset input is connected to the output of the edge detection circuit 14. Therefore, the latch circuit 15 is reset by the output signal of the latch circuit 15 output from the delay circuit 17 and is also reset by the edge detection signal from the edge detection circuit 14. In the latch circuit 16, one reset input is connected to the output of the delay circuit 18, and the other reset input is connected to the output of the edge detection circuit 13. Therefore, the latch circuit 16 is reset by the output signal of the latch circuit 16 output from the delay circuit 18 and is also reset by the edge detection signal from the edge detection circuit 13.

  The pulse generation circuit of FIG. 1 is configured as described above. Here, first, attention is paid to the operation of the latch circuit 15. The latch circuit 15 generates a pulse signal whose pulse width is a period from when the edge detection circuit 13 detects the falling edge of the binary signal input to the input terminal IN to when the delay time by the delay circuit 17 elapses. , Output to the output terminal OUT1. However, when the edge detection circuit 14 detects the rising edge of the binary signal input to the input terminal IN before the delay time by the delay circuit 17 elapses, the output to the output terminal OUT1 is detected at this detection time. To reset immediately. Therefore, in this case, a pulse signal whose pulse width is shorter than the delay time by the delay circuit 17 is output to the output terminal OUT1.

  Next, when attention is paid to the latch circuit 16, this operation is the same as that of the latch circuit 15. That is, the latch circuit 16 is a pulse signal whose pulse width is a period from when the edge detection circuit 14 detects the rising edge of the binary signal input to the input terminal IN to when the delay time by the delay circuit 18 elapses. Is output to the output terminal OUT2. However, when the edge detection circuit 13 detects the falling edge of the binary signal input to the input terminal IN before the delay time by the delay circuit 18 elapses, the output to the output terminal OUT2 is detected. It is reset immediately at that time. Therefore, in this case, a pulse signal whose pulse width is shorter than the delay time by the delay circuit 18 is output to the output terminal OUT2.

  As described above, the pulse generation circuit in FIG. 1 outputs the pulse signals alternately output from the latch circuits 15 and 16 in accordance with the change in the value of the binary signal input to the input terminal IN, and the output terminals OUT1 and OUT1. Output from OUT2. Therefore, by applying this pulse generation circuit to the level shift circuit shown in FIG. 4, the signal level is alternately changed between V2H and V2L in accordance with the pulse signals output alternately from the latch circuits 15 and 16. The switched signal can be output from the output terminal OUT. Moreover, in the level shift circuit to which this pulse generation circuit is applied, even if the L level period in the input signal input to the input terminal IN is shortened, the period in the signal output from the output terminal OUT is accurately reproduced. The That is, the reproducibility of the L / H ratio of the input signal is high.

Next, FIG. 2 will be described. FIG. 2 shows a second example of the configuration of a pulse generation circuit that implements the present invention.
The circuit shown in FIG. 2 can also be used as the pulse generation circuit 100 in the level shift circuit shown in FIG. 4, and when a falling edge of an input signal that is a binary signal input to the input terminal IN is detected. A minute width pulse signal is output from the output terminal OUT1, and when a rising edge of the input signal is detected, a minute width pulse signal is output from the output terminal OUT2.

The pulse generation circuit of FIG. 2 includes an inverter 21, a buffer 22, edge detection circuits 30 and 40, latch circuits 50 and 60, and delay circuits 70 and 80.
The input terminal IN is connected to the respective inputs of the inverter 21 and the buffer 22, the output of the inverter 21 is connected to the input of the edge detection circuit 30, and the output of the buffer 12 is connected to the input of the edge detection circuit 40. Has been.

  The edge detection circuits 30 and 40 are both circuits that detect the rising edge of the input signal. However, since the inverter 21 inverts the value of the input signal, the edge detection circuit 30 detects the falling edge of the binary signal input to the input terminal IN. On the other hand, for example, the buffer 22 constituted by two-stage cascade connection of inverter circuits outputs the value of the input signal without inversion, so that the edge detection circuit 40 has the rising edge of the binary signal input to the input terminal IN. Will be detected.

  The edge detection circuit 30 includes inverters U31 and U32, a transistor M31, a resistor R31, and a capacitor C31. The edge detection circuit 40 includes inverters U41 and U42, a transistor M41, a resistor R41, and a capacitor C41. Has been.

  The output signal of the inverter 21 is input to the edge detection circuit 30, and the output signals of both the inverters U 31 and U 32 are led to the latch circuit 50 and the delay circuit 80 as output signals of the edge detection circuit 30. However, although details will be described later, it is the output signal of the inverter U32 that shows the detection result of the edge in the output signal of the inverter 21.

  The output signal of the buffer 22 is input to the edge detection circuit 40, and the output signals of both the inverters U41 and U42 are led to the latch circuit 60 and the delay circuit 70 as output signals of the edge detection circuit 40. However, although details will be described later, it is the output signal of the inverter U42 that shows the edge detection result in the output signal of the buffer 22.

Since the edge detection circuit 30 and the edge detection circuit 40 have the same circuit configuration, only the edge detection circuit 30 will be described in detail and the operation thereof.
The output of the inverter 21 is connected to the input of the inverter U31 and the gate terminal of the transistor M31. The output of the inverter U31 is connected to the input of the inverter U32 via the resistor R31. The connection point between the input of the inverter U32 and the resistor R31 is connected to the drain terminal of the transistor M31 and one terminal of the capacitor C31. The source terminal of the transistor M31 and the other terminal of the capacitor C31 are both L It is connected to the ground of the circuit which is the potential of the level. The transistor M31 is an N-channel MOS transistor.

The edge detection circuit 30 is configured as described above. In this configuration, first, when the input signal of the inverter U31 transits from the L level to the H level, the drain-source transition of the transistor M31 transits to the ON state, so that the input of the inverter U32 becomes the L level, and accordingly, the inverter U32 Output signal becomes H level. At this time, the output signal of the inverter U31 becomes L level.

  Thereafter, when the input signal of the inverter U31 transits from the H level to the L level, the drain-source of the transistor M31 transits to an off (cutoff) state, and the output signal of the inverter U31 becomes the H level. Then, the capacitor C31 is charged via the resistor R31. When this charging is started and a predetermined time elapses and the terminal voltage of the capacitor C31 exceeds the threshold value of the inverter U32, the output signal of the inverter U32 transits from the H level to the L level. However, if the input signal of the inverter U31 transitions from the L level to the H level before the terminal voltage of the capacitor C31 exceeds the threshold value, that is, before a predetermined time elapses after the charging of the capacitor C31 is started, the transistor A transition between the drain and source of M31 is turned on. At this time, the capacitor C31 is immediately discharged, and the input of the inverter U32 remains at the L level. Therefore, in this case, the output signal of the inverter U32 is maintained at the H level.

  The latch circuit 50 includes inverters U51 and U52, transistors M51, M52, and M53, and a resistor R51. The latch circuit 60 includes inverters U61 and U62, transistors M61, M62, and M63, and a resistor R61. Configured.

  The latch circuit 50 receives the output signals of the inverters U31 and U32, which are the outputs of the edge detection circuit 30, as set input signals, and the output signal of the delay circuit 70 as a reset input signal. The output signal of the inverter U51 is led to the delay circuit 70 and the output terminal OUT1 as an output signal indicating a latch result by the latch circuit 50.

  The latch circuit 60 receives the output signals of the inverters U41 and U42, which are the outputs of the edge detection circuit 40, as a set input signal, and the output signal of the delay circuit 80 as a reset input signal. The output signal of the inverter U61 is led to the delay circuit 80 and the output terminal OUT2 as an output signal indicating a latch result by the latch circuit 60.

Since the latch circuit 50 and the latch circuit 60 have the same circuit configuration, only the details of the circuit configuration and operation of the latch circuit 50 will be described here.
The output of the inverter U32 of the edge detection circuit 30 is connected to the gate terminal of the transistor M51, and the output of the inverter U31 of the edge detection circuit 30 is connected to the gate terminal of the transistor M52. The output of the delay circuit 80 is connected to the gate terminal of the transistor M53. The transistors M51 and M52 are N-channel MOS transistors, and the transistor M53 is a P-channel MOS transistor.

  A source terminal of the transistor M53 is connected to a power supply line of a circuit having an H level potential, and a drain terminal thereof is connected to a drain terminal of the transistor M51. The source terminal of the transistor M51 is connected to the drain terminal of the transistor M52, and the source terminal of the transistor M52 is connected to the ground of the circuit which is an L level potential.

  The input of the inverter U51 is connected to the connection point of the drain terminals of the transistors M53 and M51, and the output of the inverter U51 is connected to the input of the inverter U52. The output of the inverter U52 is connected to the input of the inverter U51 via the resistor R51.

The latch circuit 50 is configured as described above. The operation of the latch circuit 50 will be described.
First, the setting operation of the latch circuit 50 will be described. The gate terminal of the transistor M51 (that is, the output of the inverter U32 of the edge detection circuit 30) and the gate terminal of the transistor M52 (that is, the output of the inverter U31 of the edge detection circuit 30) are both set to the H level. When both the drain and source transition to the on state, the input of the inverter U51 becomes L level. Therefore, the output of the inverter U51, that is, the output signal indicating the latch result by the latch circuit 50 becomes H level. At this time, since the output of the inverter U52 becomes L level, even if at least one of the gate terminals of the transistors M51 and M52 becomes L level and the drain-source state transitions to the off state. The input of the inverter U51 is pulled down by the output of the inverter U52 via the resistor R51, and the L level is maintained. Therefore, at this time, the output of the inverter U51, that is, the output signal indicating the latch result by the latch circuit 50 is maintained at the H level.

  Next, the reset operation of the latch circuit 50 will be described. When the gate terminal of the transistor M53 (that is, the output of the delay circuit 70) becomes L level and the source and drain of the transistor M53 are turned on, the input of the inverter U51 becomes H level. Therefore, the output of the inverter U51, that is, the output signal indicating the latch result by the latch circuit 50 becomes L level. At this time, since the output of the inverter U52 becomes H level, even if the gate terminal of the transistor M53 subsequently becomes H level and the source-drain of the transistor M53 is turned off, the input of the inverter U51 is Pulled up by the output of the inverter U52 through the resistor R51, and maintained at the H level. Therefore, at this time, the output of the inverter U51, that is, the output signal indicating the latch result by the latch circuit 50 is maintained at the L level.

  The delay circuit 70 outputs the output signal of the latch circuit 50 with a predetermined delay time, and the delay circuit 80 outputs the output signal of the latch circuit 60 with a predetermined delay time. However, the delay time of the delay circuit 70 is controlled by the output of the edge detection circuit 40, and the delay time of the delay circuit 80 is controlled by the output of the edge detection circuit 30.

  The delay circuit 70 includes a buffer B71, transistors M71, M72, M73, and M74, a resistor R71, and a capacitor C71. The delay circuit 80 includes a buffer B81, transistors M81, M82, M83, and M84, and a resistor R81. And a capacitor C81.

  The output signal of the inverter U51 that is the output of the latch circuit 50 is input to the delay circuit 70, and the output signal of the buffer B71 is led to the latch circuit 50 as the output of the delay circuit 70. Further, the output signals of the inverters U41 and U42, which are the outputs of the edge detection circuit 40, are input to the delay circuit 70 as delay time control signals.

  The output signal of the inverter U61 that is the output of the latch circuit 60 is input to the delay circuit 80, and the output signal of the buffer B81 is led to the latch circuit 60 as the output of the delay circuit 80. Furthermore, the output signals of the inverters U31 and U32, which are the outputs of the edge detection circuit 30, are input to the delay circuit 80 as delay time control signals.

Since the delay circuit 70 and the delay circuit 80 have the same circuit configuration, details of the circuit configuration and operation of only the delay circuit 70 will be described here.
The output of the inverter U51 of the latch circuit 50 is connected to the gate terminals of the transistors M71 and M72, and the output of the inverter U42 of the edge detection circuit 40 is connected to the gate terminal of the transistor M74. The output of the inverter U41 of the edge detection circuit 40 is connected to the gate terminal. The transistor M71 is a P-channel MOS transistor, and the transistors M72, M73, and M74 are N-channel MOS transistors.

  A source terminal of the transistor M71 is connected to a power supply line of a circuit having an H level potential, and a drain terminal thereof is connected to a drain terminal of the transistor M72. The source terminal of the transistor M72 is connected to the ground of the circuit which is an L level potential. Therefore, the transistors M71 and M72 constitute an inverter, and the signal level at the connection point between the drain terminals of the transistors M71 and M72, which is the output of the inverter, is the transistor M71 that is the input of the inverter. And the signal input to the gate terminals of both the transistor M72 and the transistor M72 are inverted.

  One terminal of a resistor R71 is connected to the output of the above inverter constituted by the transistors M71 and M72, and a capacitor C71 is connected between the other terminal of the resistor R71 and the circuit ground. Has been. The input of the buffer B71 is connected to the connection point between the resistor R71 and the capacitor C71.

  The drain terminal of the transistor M74 is connected to a connection point between the resistor R71, the capacitor C71, and the input of the buffer B71. The source terminal of the transistor M74 is connected to the drain terminal of the transistor M73, and the source terminal of the transistor M73 is connected to the connection point between the output of the inverter constituted by the transistors M71 and M72 and the resistor R71. ing.

  The delay circuit 70 is configured as described above. In this configuration, as described above, since the inverter is configured by the transistor M71 and the transistor M72, the output signal level of the inverter to which the resistor R71 is connected is obtained by inverting the output signal of the latch circuit 50. It becomes. Accordingly, when the output signal of the latch circuit 50 becomes L level, the capacitor C71 is charged via the resistor R71. When a predetermined time elapses after this charging is started and the terminal voltage of the capacitor C71 exceeds the threshold value of the buffer B71, the output of the buffer B71 transitions from the L level to the H level. Further, when the output signal of the latch circuit 50 becomes H level with the capacitor C71 being charged, the capacitor C71 is discharged via the resistor R71. When a predetermined time elapses after this discharge is started and the terminal voltage of the capacitor C71 falls below the threshold value of the buffer B71, the output of the buffer B71 transitions from the H level to the L level. In this way, the delay circuit 70 delays the output signal of the latch circuit 50 by a predetermined delay time and outputs it, thereby resetting the latch circuit 50.

  However, in the above state, the gate terminal of the transistor M73 (ie, the output of the inverter U41 of the edge detection circuit 40) and the gate terminal of the transistor M74 (ie, the output of the inverter U42 of the edge detection circuit 40) are both at the H level. When both the drains and the sources of the transistors M73 and M74 are turned on, both ends of the resistor R71 are short-circuited. Then, charging / discharging of the capacitor C71 performed at that time is completed immediately, and the output of the buffer B71 transitions. That is, at this time, the signal delay operation by the delay circuit 70 is interrupted, and the output signal of the latch circuit 50 is output without delay. As a result, if the output signal of the latch circuit 50 is at the H level, the latch circuit 50 is immediately reset at this point. If the output signal of the latch circuit 50 is at the L level, the output signal of the latch circuit 50 is kept at the L level, and at any point in time, the output signal of the latch circuit 50 is fixed at the L level.

The pulse generation circuit of FIG. 2 is configured as described above. Next, the operation of the entire pulse generation circuit will be described with reference to FIGS. 3A and 3B.
3A and 3B are timing charts showing signal examples of each part of the edge detection circuit in the pulse generation circuit of FIG. In FIG. 3A and FIG. 3B, the signal waveform “IN” shows an example of an input signal to the input terminal IN of the pulse generation circuit, and each signal waveform “a” to “f” is “IN”. FIG. 3 shows the waveform of a signal generated based on this signal waveform, and shows the signal waveform of each part of the edge detection circuits 30 and 40 with the symbols “a” to “f” displayed in FIG. However, the output signal of the inverter U31, which is a signal at the position b in FIG. 2, is a waveform obtained by inverting the signal of the input terminal IN twice by the inverter 21 and the inverter U31, that is, a signal waveform of “IN”. Since they are the same, illustration is omitted.

Since the signal waveform “a” is a signal obtained by inverting the input signal to the input terminal IN by the inverter 21, the signal waveform “a” is a signal obtained by inverting the signal waveform “IN” as illustrated.
The signal waveform “c” is a terminal voltage of the capacitor C31. Since the capacitor C31 is charged by the output of the inverter U31 whose current is limited by the resistor R31, the capacitor C31 starts to rise from the position of the rising edge of the signal waveform “IN” (that is, the output signal waveform of the inverter U31), and then H The signal waveform reaches the level. However, when a falling edge appears in the signal waveform “IN”, the transistor M31 is turned on and the capacitor C31 is discharged, so that the signal waveform “c” continues to be at the L level thereafter.

  The signal waveform “d” is an output signal of the inverter U32. Accordingly, when the signal waveform “c” representing the terminal voltage of the capacitor C31 exceeds a predetermined threshold value (Vth1) that the inverter U32 uses as a criterion for determining the H level / L level of the input signal level, the signal waveform “ “d” is at the L level, and the waveform continues to be at the H level while it is below the threshold value Vth1.

  The signal waveform “e” is a terminal voltage of the capacitor C41. Since the capacitor C41 is charged by the output of the inverter U41 whose current is limited by the resistor R41, the capacitor C41 starts to rise from the position of the rising edge of the signal waveform “a” (that is, the output signal waveform of the inverter U41), and then H The signal waveform reaches the level. However, when a falling edge appears in the signal waveform “a”, the transistor M41 is turned on and the capacitor C41 is discharged, so that the signal waveform “e” continues to be at the L level thereafter.

  The signal waveform “f” is an output signal of the inverter U42. Therefore, when the signal waveform “e” representing the terminal voltage of the capacitor C41 exceeds a predetermined threshold value (Vth2), which is used as a criterion for the determination of the H level / L level of the input signal level by the inverter U42, the signal waveform “ “f” is at the L level, and the waveform continues to be at the H level while it is below the threshold value Vth2.

Among the signal waveforms shown in FIGS. 3A and 3B, the signal waveform shown in FIG. 3A is a case where the signal waveform “IN” is a waveform that falls after rising.
In FIG. 3A, in the waveform group indicated by [A], the signal waveform “IN” has a short time after rising (more specifically, the signal level expressed by the signal waveform “c” increases). In this case, the waveform falls in such a short time that the threshold value Vth1 cannot be reached. In the waveform group displayed as [B], the signal waveform “IN” has a long time after the rise (more specifically, the rise in the level represented by the signal waveform “c” has the threshold value Vth1). This is a case where the waveform falls after a long time).

On the other hand, what is shown in FIG. 3B is a case where the signal waveform “IN” is a waveform that rises after falling.
In FIG. 3B, the waveform group indicated by [C] indicates that the signal waveform “IN” has a short time after the falling (more specifically, the signal level rise represented by the signal waveform “e”). Is a waveform that rises in such a short time that the threshold value Vth2 cannot be reached. In the waveform group displayed as [D], the signal waveform “IN” has a long time after the fall (more specifically, the increase in the level expressed by the signal waveform “e” is the threshold Vth2 This is the case where the waveform rises after a long time).

  In each of the above signal waveforms, the signal waveform “b” and the signal waveform “d” are a set input signal for the latch circuit 50 and a delay time control signal for the delay circuit 80. Here, in the period when both of these waveforms are at the H level, that is, the period T1 shown in FIGS. 3A and 3B, the set input signal is input to the latch circuit 50 and the delay operation of the delay circuit 80 is performed. There is no signal delay due to. Here, the rising edge detection signal is constituted by the signal waveform “b” and the signal waveform “d”, and when both are at the H level, it means that the rising edge of the signal waveform “IN” is detected. .

  In each of the above signal waveforms, the signal waveform “a” and the signal waveform “f” are a set input signal for the latch circuit 60 and a delay time control signal for the delay circuit 70. Here, in the period when both of these waveforms are at the H level, that is, the period T2 shown in FIGS. 3A and 3B, the set input signal is input to the latch circuit 60 and the delay operation of the delay circuit 70 is performed. There is no signal delay due to. Here, the falling edge detection signal is composed of the signal waveform “a” and the signal waveform “f”, and when both are at the H level, it means that the falling edge of the signal waveform “IN” is detected. ing.

  Here, as described above, the output signal of the delay circuit 80 is a reset input signal for the latch circuit 60, and the output signal of the delay circuit 70 is a reset input signal for the latch circuit 50. Therefore, in FIG. 3A and FIG. 3B, in the period T1, the set input signal is input to the latch circuit 50 and the reset input signal to the latch circuit 60 is input (the output of the latch circuit 60 is determined at L level). The period T2 is a period in which the set input signal is input to the latch circuit 60 and the reset input signal to the latch circuit 50 is input (period in which the output of the latch circuit 50 is fixed at the L level). Can be seen. Therefore, a pulse signal having a pulse width during the period T1 in FIGS. 3A and 3B is output from the output terminal OUT1 from which the output of the latch circuit 50 is guided, and from the output terminal OUT2 from which the output of the latch circuit 60 is guided. A pulse signal having a pulse width of the period T2 in 3A and 3B is output. Here, in any of [A] to [D] shown in FIG. 3A and FIG. 3B, the period T1 and the period T2 exist without overlapping each other. Therefore, even in the pulse generation circuit of FIG. In response to a change in the value of the input binary signal, pulse signals output alternately from the latch circuits 50 and 60 are output from the output terminals OUT1 and OUT2.

  Therefore, even if the pulse generation circuit shown in FIG. 2 is applied to the level shift circuit shown in FIG. 4, the signal levels of V2H and V2L are changed according to the pulse signals output alternately from the latch circuits 50 and 60. A signal alternately switched between them can be output from the output terminal OUT. Moreover, in the level shift circuit to which this pulse generation circuit is applied, even if the L level period in the input signal input to the input terminal IN is shortened, the period in the signal output from the output terminal OUT is accurately reproduced. The That is, the reproducibility of the L / H ratio of the input signal is high.

  In addition, this invention is not limited to embodiment described so far, In the implementation stage, it can change variously in the range which does not change the summary.

11, 21, U31, U32, U41, U42, U51, U52, U61, U62
, U101, U102 Inverter 12, 22, B71, B81 Buffer 13, 14, 30, 40 Edge detection circuit 15, 16, 50, 60 Latch circuit 17, 18, 70, 80 Delay circuit 100 Pulse generation circuit 110 Pulse generator 111 Level shift circuit 112 Flip-flop circuit 121 AND circuit 122, 123 D-type flip-flop circuit 124, 125 Delay network 126 OR circuit C31, C41, C71, C81 Capacitor M31, M41, M51, M52, M53, M61, M62, M63 M71, M72, M73, M74, M81, M82, M83, M84, M101, M102, M111, M112 Transistors R31, R41, R51, R61, R71, R81, R101, R102 Resistance

Claims (3)

A first edge detection circuit for detecting a falling edge of an input binary signal;
A second edge detection circuit for detecting a rising edge of the binary signal;
A first latch circuit set by a falling edge detection signal from the first edge detection circuit;
A first delay circuit that outputs the output signal of the first latch circuit with a predetermined first delay time delay;
A second latch circuit set by a rising edge detection signal from the second edge detection circuit;
A second delay circuit that outputs the output signal of the second latch circuit with a predetermined second delay time delay;
With
The first latch circuit is reset by a signal output from the first delay circuit, and is also reset by the rising edge detection signal from the second edge detection circuit,
The second latch circuit is reset by a signal output from the second delay circuit, and is also reset by the falling edge detection signal from the first edge detection circuit,
The output signals of the first latch circuit and the second latch circuit are output as generated pulse signals.
A pulse generation circuit characterized by the above. A first edge detection circuit for detecting a falling edge of an input binary signal;
A second edge detection circuit for detecting a rising edge of the binary signal;
A first latch circuit set by a falling edge detection signal from the first edge detection circuit;
A first delay circuit that outputs the output signal of the first latch circuit with a predetermined first delay time delay;
A second latch circuit set by a rising edge detection signal from the second edge detection circuit;
A second delay circuit that outputs the output signal of the second latch circuit with a predetermined second delay time delay;
With
When the first delay circuit receives a rising edge detection signal from the second edge detection circuit, the first delay circuit outputs the output signal of the first latch circuit without delaying the predetermined first delay time,
When the second delay circuit receives a falling edge detection signal from the first edge detection circuit, the second delay circuit outputs the output signal of the second latch circuit without delaying the predetermined second delay time. ,
The first latch circuit is reset by a signal output from the first delay circuit,
The second latch circuit is reset by a signal output from the second delay circuit,
The output signals of the first latch circuit and the second latch circuit are output as generated pulse signals.
A pulse generation circuit characterized by the above. The pulse generation circuit according to claim 1 or 2 is provided,
Outputting a signal in which the signal level is alternately switched between the first voltage value and the second voltage value in response to the pulse signal alternately output from the first latch circuit and the second latch circuit. A level shift circuit characterized by the above.

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