TW201138050A - Semiconductor device packages with electromagnetic interference shielding - Google Patents

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

Description

201138050

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a device for a semiconductor device package, and more particularly to a device for shielding an electromagnetic interference semiconductor device package. Due to the demand for increased process speed and size reduction, semiconductor devices have become more and more complicated. When the process speed is increased and the benefits of size reduction are significantly increased, the characteristics of semiconductor components are also problematic. In particular, higher working hours. Clock speed leads to a more frequent transition between signal levels (transiti〇n). At higher frequencies or shorter wavelengths, these signal levels result in a higher level of intensity. Electromagnetic emission. Electromagnetic radiation can be emitted from a source of a semiconductor device and can be incident on an adjacent semiconductor device. If the level of electromagnetic radiation adjacent to the semiconductor device is sufficiently high, then some radiation Will adversely affect the operation of the semiconductor device. This situation is often referred to as Electromagnetic interference (:rference, fine). In a monolithic electronic system is a high-density semiconductor device, which will make the effect of electromagnetic interference worse, because & on adjacent semiconductor devices There is a higher level of intensity of electromagnetic radiation that is not desired. The method of reducing electromagnetic light is to shield the semiconductor device from the semiconductor device and the entire semiconductor device in the cow. In particular, the shielding Can be made by including a close to the outside of the package. 201138050

I W6Jyt) PA electrically conductive housing or cover to achieve. When electromagnetic radiation from inside the package invades the inner surface of the housing, at least a portion of the electromagnetic beam can be electrically shorted, thereby reducing the level of radiation intensity through the housing and proximity Adverse effects of semiconductor devices. Similarly, a similar electrical shorting condition occurs when electromagnetic radiation from a nearby semiconductor device attacks the outer surface of the housing to reduce electromagnetic interference to the semiconductor device within the package. Although an electrically conductive housing reduces electromagnetic interference, the housing encounters some disadvantages in use. In particular, the housing is generally attached to the exterior of the semiconductor device package by an adhesive. Unfortunately, since the adhesive properties of the adhesive are unfavorable by temperature, moisture, and other environmental conditions, the body is easily peeled off or detached. Similarly, when the housing is placed against the package, the size and shape of the housing and the size and shape of the package should be matched at a lower tolerance level. The matching of the dimensions and shape of the housing and the package, as well as the combined accuracy of the housing and the package at the relevant locations, will result in manufacturing costs as well as time consumption. Considering the matching of dimensions and shapes, semiconductor device packages of different sizes and shapes may require different housings, which are used to accommodate different housings of different packages to further increase manufacturing cost and time.曰 / / Overcoming this situation] A semiconductor device package and related methods are described herein. SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device package that shields electromagnetic interference. In an embodiment, a semiconductor device package comprises: (1) a 201138050 丨wtuy〇r eight substrate unit, comprising (a) an upper surface, (b) a lower surface, a lateral surface disposed adjacent to the substrate unit And extending completely between the upper surface and the lower surface of the substrate unit, and a grounding member disposed adjacent to the periphery of the substrate unit and extending at least partially between the upper surface and the lower surface of the substrate unit; (2) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (3) a package disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package including a plurality of external surfaces, The external surface includes a lateral surface; and (4) the electromagnetic interference shielding member is disposed adjacent to the outer surface of the package and the lateral surface of the substrate unit, the electromagnetic interference shielding member is electrically connected to the grounding member, and Adjacently recessed to the recessed portion of the ground element.

In another embodiment, a semiconductor device package includes: a) a sheet of soap comprising 'a (a) a first surface, (b) a second opposing surface, and (c) at least partially extending from the substrate unit a first surface and a _, a pair of surface-to-ground elements, the grounding element comprising - a plate-like channel and a filler, the plate-shaped channel residue being recessed inwardly to accommodate the object The remnant of the channel and the filler define a lateral surface that is disposed adjacent to the ground element around the side plate unit; (2). Providing a first surface adjacent to the substrate unit and electrically connected to the board unit; (3) a package disposed adjacent to the first unit of the substrate unit and covering the semiconductor device, the package comprising a plurality of external surfaces, The electromagnetic interference shielding member is disposed adjacent to the outer side of the material body=the lateral surface connected to the grounding element, wherein the semi-conductive material is disposed on the side rim of the semi-conductor as a plane, and the second relative table relative to the substrate material 5 201138050 I wojyor/λ The face is essentially a right angle. In accordance with another aspect of the invention, a method of forming a semiconductor device package that shields electromagnetic interference is provided. In one embodiment, a method includes: (1) providing a substrate including a ground via and a core component, the ground via extending at least partially between the upper surface and the lower surface of the substrate, the ground via defining a substantially core (2) electrically connecting the semiconductor device to the upper surface of the substrate; (3) applying a bonding material to the upper surface of the substrate to form a sealing structure covering the semiconductor device; (4) Forming a plurality of slits extending completely through the encapsulation structure and the substrate, the slitting systems being aligned with the substrate such that: (a) the substrate is subdivided to form a divided substrate unit, and (b) the encapsulation structure is further divided Forming a divided package disposed adjacent to the substrate unit; and (c) a residual portion of the ground via and a residual portion of the core member disposed adjacent to the ground member adjacent to the substrate unit. The ground member includes an exposed connection surface; and (5 After forming the slit, an electromagnetic interference coating is applied to the outer surface of the package and the connection surface of the grounding member to form an electromagnetic interference shielding member. Other aspects and embodiments of the invention are also contemplated. The above summary of the invention, as well as the following detailed description, [Embodiment] The following definitions are illustrative of the application of certain embodiments of the invention in certain aspects. These definitions are also described in detail herein. Unless the context clearly indicates otherwise, the singular items "a", "an", and "the" as used herein are intended to include a plurality of indicating objects. Thus, for example, in addition to the explicit reference in 201138050, when a grounding component is referred to, the grounding component can include a plurality of grounding components. The item "set" as used herein refers to a collection of one or more components. Thus, for example, a layer group can include a single layer or multiple layers. A component of a set can also be referred to as a member of the set. A group of components can be the same or different. In some examples, a group of elements may share one or more common features. φ The item "adjacent" used herein means close to or adjacent. The adjacent elements may be separated from each other or substantially in direct contact with each other. In some examples, adjacent elements may be interconnected or integrally formed. As used herein, for example, "inner", "interior"', '''''''''''''' , ''bottom', ', front', '', '''''''''''''''''''''''''''''''''''' Φ (downwardly), "vertical" (vertically vertical (laterally laterally), ''above'' and "below" The related items indicate the direction of one component group relative to another component group, for example, as shown in the figure, but these components do not need to be limited to a specific direction during the manufacturing process or in use. "Connect", "connected", and "connection" are operational couplings or links. Several connected components can be directly coupled to each other, or 201138050 i wojyom is indirectly coupled to each other. , mutually indirect coupling examples This is achieved by another set of components. The items used herein are "substantially", and "substantial", which indicates the degree or extent of the hierarchy to be considered. When an event or situation is used together, the above items may represent instances in which an event or situation occurs accurately, and instances in which the event or situation may occur in a very close condition, such as a tolerance of a general manufacturing process as described herein. The number of series. "The item used here is "electrica丨丨y conductive," = conductivity (electncal c〇nductivity)" - the ability to conduct current" and the item used here is "non-electric Sexual conduction (electrically café - ductive), and "non-conductivity (...w non conductivity)" means the lack of ability to conduct current. Conductive materials are usually those that show little or no resistance to current flow: electricity and = electricity = Often those materials that show little or no tendency to conduct electricity. Each Siemens is Siemens (Siemens per "S.m1") is a measure of conductivity. In general, a conductive material has a conductivity greater than 1 (}4^, for example, at least about 1 〇S:m or at least about 1 〇6w, less than; 传导sr conductivity, for example, is not greater than 丨 = unless otherwise specified, - the material's thunder of the degree of degradation. In addition to the first please refer to the i and 2: the room. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 . Schematic, and its 2 201138050

_ ' i wojyopA Figure 1 is a cross-sectional view of the semiconductor device package 100 taken along line 1 of the figure. In this embodiment, the plurality of sides of the semiconductor device package 100 are substantially two, 'face' sub- and have a substantially right-angle direction to define a side:: around: the wheel substantially surrounds the semiconductor device package The 疋 of the workpiece 100, the lateral profile of the right angle can reduce the size of the overall seal by reducing the pin area of the semiconductor package or minimizing the semiconductor device package. However, the general profile of the φ-like device such as the body device package 100 may be any shape that is slanted, stepped, or rough (roughly although the position described below is in the semiconductor device package -) =:: The group position is recessed inwardly, however, the side wheel body is substantially referred to in FIG. 2, the semiconductor device package unit 1〇2, the substrate unit 102 includes the substrate early and lateral surfaces 142 and 144, and the side two lower surfaces 1 〇6, :Ϊ = the side of the plate unit 1〇2, and extends to the upper surface: = between. In this embodiment, the lateral surfaces ... 4 have substantially the same angle = with respect to the upper surface 104 or the lower surface 106 = and the direction may vary. The substrate unit can be surface-corrected on the top surface of the board unit (10) - the base connector can include a merge between the substrates 106. For example, this layer. The electrically conductive layers can be connected to each other by internal through-holes. The core components formed by the sandwiches of the humans are sandwiched by the guides 201138050 I w〇3y〇PA. , this = column as two by bis-eimide (bis_eimide) and three 氤 stupid

a resin consisting of a servant or a resin made of epoxy resin (-w and polyphenylene oxidp J). For example, =1 may include a substantially flat core component. The core U is adjacent to the electrically conductive layer on the upper surface of the core element, and the other set is adjacent to the press; the electrically conductive layer of the lower surface of the "Ding" member of the body is clamped in three ways. In some embodiments, the end of the substrate unit 1 ' 2, that is, the distance ' between the upper surface 104 and the lower surface 106 of the substrate unit 102' may be about (M millimeter ("fine") to about 2 Within the range of house rice, for example, from about 2 cm to about 15 centistokes, 'spoon 0.4 mm to about 6 mm. Although not green is shown in Figure 2, a solder mask layer can be placed adjacent to the substrate. One of the upper surface 04 and the lower surface 106 of the unit 102, or both. As shown in Fig. 2, the substrate unit 102 includes a grounding member 1183 disposed adjacent to the periphery of the substrate unit 兀_1〇2. And n8b. More specifically, the grounding element U8a #118b is substantially disposed at the base The periphery of the board unit 102 and the blade 5 are again adjacent to the lateral surfaces 142 and 144. The grounding elements 118a and iigb are connected to other electrical connectors in the substrate unit 1〇2, and as described below, this grounding element] 18& and U8b will provide a plurality of electrical paths to reduce electromagnetic interference. In this embodiment, the grounding element a 彳 118 b is a grounding hole, and in particular the remaining portion of the grounding hole after a set of cutting spears Formed by (remnant), the set of cutting processes will be described later. Referring to Figure 2, each grounding element 118a and 1 8b includes upper via pad padding 146a or 146b, lower via pad padding 148a or 201138050

I wo^yoKA 148b, and a plate-like channel stub 150a or 15b, wherein the upper via pad residue 146a or 146b is disposed adjacent to the upper surface 104 of the substrate unit 1〇2, and the lower via pad residue 148a or 148b is disposed. Adjacent to the lower surface 106 of the substrate unit 1〇2, the plate-shaped channel stub i5〇a or 15〇b extends between the upper via pad residue 146a or 146b and the lower via pad residue 148& or 14讣. Although the grounding elements 118a and 118b are depicted herein as extending completely between the upper surface 1 〇4 and the lower surface of the substrate unit 102, in other implementations, the range of the grounding elements 118a and 118b may be Changed. Referring to Fig. 2, the grounding members 118a and 118b respectively include connection faces S1 and S2 which are side faces facing away from the inside of the semiconductor device package 100, and are disposed adjacent to the periphery of the substrate unit 1〇2. More specifically, the connection faces S1 and S2 are substantially electrically exposed to the periphery of the substrate unit 102 and are electrically contacted adjacent to the lateral surfaces 142 and 144, respectively. In this embodiment, the joint faces S1 and the magical system correspond to the electrical contact faces of the upper through-hole pad stubs 146a and 146b, the lower via pad stubs 148a and 148b, and the plate-like channel stubs 150a and 150b. Advantageously, the larger connection surfaces S1 and S2 increase the reliability and effectiveness of the electrical connections to reduce electromagnetic interference. The grounding members 1A and 8b are formed of a metal, a metal alloy, a material having a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. For some implementations, a height of the grounding elements 118a and 118b, i.e., a vertical extent of the grounding elements U8a and U8b, may be substantially equivalent to the thickness f of the substrate unit ι2 and may be about 〇1. In the range of up to about 2 mm, for example, from about 0.2 mm to about 丨5 mm, or from about 〇4 mm to about 〇6 mm. A width W1 of the grounding elements 118 & and 118b, that is, an abutment 201138050

TW6396PA may be in the lateral extent of one of the upper surface 104 or the lower surface i6, which may be in the range of about 75 microns (micrometer, to about 275 microns, such as from about 100 microns to about 250 microns, or from about 125 microns). Up to about 225 μm. As shown in Fig. 2, the semiconductor device package 1A also includes semiconductor devices 108a, 108b, and 10c, and electrical contacts H〇a, 11〇b, and 110c. The devices i 8a , 8 8 , and 8 8 are disposed adjacent to the upper surface of the substrate unit 102 , and the electrical contacts 110 a , 110 b , and 11 c are disposed adjacent to the substrate unit 1 2 The lower surface 106. The semiconductor device 1 〇 8b is wire bonded (wire_b〇ncjeci) to the substrate unit 102 by a set of bonding wires 112 formed of gold or other suitable electrically conductive material, and the semiconductor device 108a and 〇8c The surface is fixed on the substrate unit 102. In this embodiment, the semiconductor device is a semiconductor wafer, and the semiconductor devices 1a and 8b are passive components, such as germanium resistors, capacitors, or inductors. Electrical contact 110b, and 11〇c provide input and output electrical connections for the semiconductor device package, and at least a portion of the electrical contacts 110a, 110b, and U0c are electrically connected through the electrical connections in the substrate unit 丨02 Connected to the semiconductor devices 108a, 10b, and 8c. In this embodiment, at least one of the electrical contacts 110a, UOb, and n〇c is a grounded electrical contact 'and The electrical connectors in the substrate phantom 02 are electrically connected to the grounding elements 118a and 11b. Although two semiconductor devices are illustrated in FIG. 2, in other implementations, there may be more or fewer semiconductor devices. Included, and in general, the semiconductor device can be any active component, any passive component, or any combination thereof. Similarly, 201138050

I W〇jy〇pA The number of electrical contacts shown in Figure 2 can vary.

The semiconductor device package 100 of the June solar photo package 100 also includes a package body 114 disposed adjacent to the upper surface 1〇4 of the substrate unit 1〇2. The package body 114 is connected to the substrate unit 1〇2, and substantially covers the ground element two 118b, the semiconductor devices 1〇8a, 108b, and 10b, and the bonding wires 112 or encapsulates the above components inside to provide mechanical Stability and protection of these components to prevent oxidation, moisture, and other environmental conditions. The package 114 is formed from a sealant material, and the package 114 includes a plurality of external surfaces that include abutment to the package. The side surface of the body 114, the facing surfaces 120 and 12> In this embodiment, the lateral surface 12 of the lance spear 122 is flat and has a right angle direction with respect to the upper surface i or the lower surface 106. However, in other implementations, the lateral surfaces 120 and 122 can be large, sloping 'stepped or rough&y textured. In addition, the lateral surfaces 12A and 122 are qualitatively aligned with the lateral surfaces 142#144, respectively, or are coplanar with the lateral surfaces 142 and 144. More specifically, while performing this alignment, the connection surface s"〇S2 is electrically exposed, for example, by reducing or minimizing the coverage of the package 114 and the connection faces si and S2) . In other implementations, the alignment of the lateral surfaces from the shapes of (3) and (2) and the alignment of the lateral surfaces 120 and 122 and the lateral surfaces 142 and (4) may be as long as the connection surface and the S2 system are allowed to be at least partially electrically exposed. Different from Figure 2. As shown in Figs. 1 and 2, the semiconductor device package _ further includes an electromagnetic interference shield 124. The electromagnetic interference shielding member 12 is adjacent to a plurality of external surfaces of the package body m, the grounding member (10) and the intestine 201138050

The connection faces S1 and S2 of the TW6396PA and the lateral surfaces 142 and (4) of the substrate unit 102. The electromagnetic interference shield 124 is formed of an electrically conductive material and is disposed substantially circumferentially around the semiconductor device in the semiconductor device package to provide protection against electromagnetic interference. The magnetic interference shield 124 in the embodiment includes an upper #126 and a side portion 128 that extends across the entire circumference of the package 114 and defines a right-angled side porch of the semiconductor device package. As shown in Fig. 2, the side portion 128 extends downwardly from the upper portion 126 and along the lateral surfaces 142 and 144 of the substrate unit 〇2, the side portion 28 including the lower end, the lower end portion being substantially aligned The lower surface 1〇6 of the substrate unit 1〇2 or the surface 1G6 is coplanar. However, in other implementations, the extent of the sides and the alignment of their lower and lower surfaces 1 〇 6 may vary. As shown in Fig. 2, the electromagnetic interference shielding member 124 is electrically connected to the connection faces S1 and S2 of the connectors 118a and mb. When the electromagnetic light is emitted from the inside of the conductor package, and the electromagnetic light is blocked, at least a part of the radiation can be effectively grounded through the grounding elements (10) and U8b, thereby reducing electromagnetic interference. The level of light that the shield is lightly exposed, as well as reduced adverse effects on adjacent semiconductor devices. Similarly, when an electromagnetic light from a neighboring semiconductor device invades the electromagnetic interference shield 124, a similar grounding action occurs to reduce the semiconductor package m (10)b in the semiconductor device package 1 and the electromagnetic interference. During the process, the semiconductor device package 100 can be disposed over a printed circuit board (PCB) and electrically connected to the via via electrical contacts 110a, 110b, and 110c.

I Wo^yopA

A printed circuit board. As described above, at least one of the electrical contacts u〇a ii〇b, and (10) is a grounded electrical contact, and the grounded electrical contact is electrically connected to a printed circuit board. One of the grounding voltages is provided. The electromagnetic path incident on the electromagnetic interference shield 124 may be grounded through an electrical path, which may include the grounding elements ι 8 & mb, other electrical connections included in the substrate unit 102, And grounding electrical contacts. Since the lower end of the electromagnetic interference shielding member 124 is substantially aligned with the lower surface 1〇6 of the substrate unit 102, the lower end can also be electrically connected to a ground voltage provided by the printed circuit board, thereby providing It is used to ground the undesired electromagnetic light-emitting ground: electricity = in the connection structure, the 'lower through-holes (10) and (10) are electrically connected to the ground voltage provided by the printed circuit board. In this embodiment, the electromagnetic interference shielding 24 is formed as one of a set of thin films, and the conformal mask (4) 24 can be formed without using an adhesive; ^ directly contacting the outer surface of the semiconductor device package or The exterior of the semiconductor 100 is in direct contact, thereby enhancing reliability and resistance to milk, as well as other environmental conditions. Electromagnetic interference shielding, the second magnetic interference shielding and the like, can reduce the different semiconductor electromagnetic dry 1 = 1 to less than about 500 micrometers, such as about _micron, from about micron to about 5 micron, or to Micron. This embodiment is another preferred, ★;, to —-like housing 15 201138050 I W6J96PA (casing), the reduced thickness of the electromagnetic interference shield 124 allows for a reduction in the size of the entire semiconductor device package. Please refer to Figure 3A. Fig. 3A is an enlarged cross-sectional view showing a portion of the semiconductor device package 1 of the second and second drawings. More specifically, FIG. 3A illustrates a specific implementation of an electromagnetic interference shield 124 disposed adjacent to the package 114. As shown in FIG. 3A, the electromagnetic interference shielding 24 is multi-layered and includes an inner layer and an outer layer. The inside of the crucible f 300 is disposed adjacent to the package body 114. The outer layer 3 2 is disposed adjacent to the inner layer 300 and exposed to the outside of the semiconductor device package 1 . Generally, each of the layer 300 and the outer layer 3〇2 may be a metal, a metal alloy, a material having a metal or a metal alloy interspersed therein, or: another suitable electrically conductive material form. For example, each of the inner layer (10) and the layer 302 may be formed of ingot, copper, chromium, titanium, gold, silver, nickel, stainless steel, or combinations thereof. The inner layer 3〇〇 and the outer layer 3〇2 may be formed of an electrically conductive material or a different electrically conductive material. For example, a two-metal, such as nickel, can be selected to be used as an inner layer. In the wider example, different electrically conductive materials can be used as: inner layer 3G0 and outer layer 3〇2, Provide complementary functions. Lift. Brother's - metal with * electrical conductivity, for example, is used as the inner layer to provide electromagnetic interference shielding. The metal can be selected to have a low electrical conductivity, such as nickel. The suede k is prepared as the outer layer 302 to protect the inner layer 3 from being affected by the environment. In this case, the outer layer 3〇2 also provides the function of electric oblique disturbance, while providing protection. 201138050

I wojyoPA Although the second layer is illustrated in Figure 3A, in other implementations, more or fewer layers may be included. Next, please refer to FIG. 3B and FIG. 3C. 3B and 3C are enlarged cross-sectional views showing a portion of the semiconductor device package 100 of Figs. 1 and 2. More specifically, FIG. 3B illustrates a specific embodiment of a grounding element 118b, and FIG. 3C illustrates another embodiment of a grounding component 118b. For clarity of presentation, the following features are described with reference to grounding elements 118b disposed adjacent to the lateral surface 144 of the substrate unit 102, although it is contemplated that these features can be similarly applied to grounding components of other semiconductor device packages 100. Above, for example, the grounding element 118a. Referring to FIG. 3B, the grounding member 118b is formed by a remaining portion of the grounding hole after a set of cutting processes, and includes an upper via pad remaining portion 146b, a lower through hole pad remaining portion 148b, and a plate-like channel residual portion 150b. The plate-like channel stub 150b corresponds to a recessed portion of the grounding member 118b and is recessed inwardly with respect to the lateral surface 144 of the substrate unit 102. • More specifically, the plate-like channel stub 150b is recessed inwardly to define a cutout or groove that includes a curved lateral surface, wherein the curved lateral surface is substantially The upper portion is of a concave pattern and is electrically exposed to allow electrical connection to the electromagnetic interference shield 124. As shown in FIG. 3B, the upper via pad residual portion 146b, the lower via pad pad portion 148b, and the plate-like channel residue portion 150b include substantially planar lateral surfaces and are substantially aligned or coplanar with the substrate unit 102. The lateral surface 144, and the connecting surface S2 of the grounding member 118b includes a substantially concave lateral surface of the plate-like passage residual portion 150b, and an upper through-hole pad residual portion 146b and a lower through hole 201138050

I WOJVOKA

The pad residual portion 148b and the substantially planar lateral surface of the plate-like passage residue 150b. Advantageously, the inwardly recessed plate-like channel stubs l5〇b provide a larger area of the connection surface S2, thus increasing the reliability and efficiency of the electrical connections to reduce electromagnetic interference. Still referring to FIG. 3B, the electromagnetic interference shield 124 is recessed inwardly at a particular set of locations, and the electromagnetic interference shield 124 is formed to provide a lateral orientation of the substantially planar semiconductor device package 100. profile. Specifically, the electromagnetic interference shielding member 124 conformally covers the connecting surface S2, and the connecting surface S2 includes the concave surface of the concave portion of the plate-shaped passage residual portion 150 such that the side portion 128 of the electromagnetic interference shielding member 124 is recessed inwardly. Adjacent to the plate-shaped passage residue 15〇. In March, refer to Figure 3 C, the grounding element ....---- 叩 地 地 于 in a group of seven; the remaining part after the cutting process is formed 'and includes the upper through hole pad residual' 1 partial, lower through hole Pad residue 148b, and plate-like channel stub (10) where 'ground element 118b also includes a filler (service r_ber) 304. The filler _ substantially fills the pattern grooves defined by the plate-like channel stubs 150. As described below, the filler 3G4 forms a phase

= component-residue, which fills the via-hole defined by the grounding hole. A set of dicing processes can be performed to obtain one side of the filler 304: 'This lateral surface is substantially planar and electrically exposed to electrically connect to the electromagnetic interference shield 124. More specifically:: the direction, the surface is substantially aligned or coplanar to the substrate = - and; the filler 3〇4 may be a metal, a metal alloy, a suitable metal alloy dispersed therein, or another - 2 Hi forms 'and in this case, the grounded meta-connection surface S2 includes a substantially planar lateral table of fillers 18 201138050

I w〇jy〇 PA face 'and substantially planar lateral surface of upper via pad residue 146b, substantially planar lateral surface of lower via pad pad 148b, and substantially planar of plate-shaped channel stub 150b Lateral surface. Advantageously, the filler 304 contains an electrically conductive inclusion 'thereby providing a relatively large joint surface S2 and enhancing the structural rigidity of the ground element 118b, thereby enhancing the reliability and efficiency of the electrical connection. To reduce power interference. The filler 304 may also be formed of a non-electrically conductive material. In this case, the connection surface S2 of the grounding member 118b includes an upper via pad residue 146b, a lower via pad residue 148b, and a plate-like channel residue i5〇b. A substantially planar lateral surface. The filler 30 may also contain a non-electrically conductive inclusion that enhances the structural rigidity of the grounding member 118b, thereby enhancing the reliability and efficiency of the electrical connection to reduce electromagnetic interference. Referring still to FIG. 3C, the formation of the electromagnetic interference shield 124 results in a right-angled lateral profile of the substantially planar semiconductor device package 100, which is substantially planar and substantially inwardly in the side portion 128. Recessed. Although the grounding element 11gb illustrated in Figures 3B and 3C is fully extended across the thickness of the substrate unit 102, in other implementations, the range of the grounding element 118b may vary. Specifically, 'the grounding element 118b may extend partially through the thickness of the substrate unit 102 as described below, for example, may be implemented as an internal grounding via or a blind grounding via. One of the remnants. Figure 4A is a cross-sectional view showing a semiconductor device package 400 in accordance with another embodiment of the present invention. Some aspects of the semiconductor device package 4 are a semiconductor device similar to the above-described FIGS. 1 to 3C.

I W03V0PA The package 100' is therefore not repeated here. Referring to FIG. 4A, the semiconductor device package 400 includes grounding members 418a and 418b disposed substantially around the substrate unit 102. In this embodiment, the grounding elements 418a and 418b are recesses of the grounding via, extending between the top surface 丨〇4 of the substrate early element 102 and an electrically conductive layer 452. This electrically conductive layer 452 is disposed between the upper surface 1〇4 and the lower surface 106 of the substrate unit and is regarded as an internal ground layer. Specifically, each of the grounding members 418a and 418b includes an upper via pad stub 446a or 446b, a lower via pad stub 448a or 448b, and a plate-like channel stub 450a or 450b. The upper via pad residue 446a or 446b is disposed adjacent to the upper surface 1 〇4 of the substrate unit 102; the lower via pad residue 448a or 448b is electrically connected to the electrically conductive layer 452 and disposed under the substrate unit 102. The distance above the surface 1〇6 is separated by a certain distance; the plate-shaped passage residual portion 450a or 450b extends between the upper through-hole pad residual portion 446a or 44讣 and the lower through-hole pad residual portion 448a or 448b. Although the grounding elements 418a and 418b are partially extended between the upper surface 104 and the lower surface 106 of the substrate unit 1〇2, in other implementations, the range of the grounding elements 418% and 418b is Can be changed. In this embodiment, grounding members 418a and 418b include connecting faces S1, and S2, respectively, and connecting faces S1, and S2' are electrically contacted adjacent to lateral surfaces 142 and 144, respectively. Advantageously, the relatively large connecting faces S1, and S2 enhance the reliability and efficiency of the electrical connections to reduce electromagnetic interference. In some implementations, the heights & grounding elements 418a and 418b can be slightly less than the thickness of the substrate unit 1〇2 and are in the range of about (Mm to about h8 mm, such as from about 0.2 mm to about 1). Mm' or from about 3 mm to about 5 mm. Grounding 20 201138050 One of the widths W2 of elements 418a and 418b, ie a lateral extent adjacent to the upper surface 104, may be in the range of about 75 microns to 275 microns, For example, from about 100 microns to about 250 microns, or from about 125 microns to about 225 microns. As shown in Figure 4A, the semiconductor device package 400 also includes a semiconductor device 408b. The semiconductor device 408b is disposed adjacent to a semiconductor wafer on the upper surface 104 of the substrate unit 102. In this embodiment, the semiconductor device 408b is, for example, flip-chip bonded to the substrate unit 102 by a set of solder bumps. A method, for example, electrically connected to the substrate unit 102 by a bonding wire. FIG. 4B is a cross-sectional view of a semiconductor device package 460 according to another embodiment of the present invention. Some aspects are similar to the semiconductor device package 100 of FIGS. 1 to 3C and the semiconductor device package 400 of FIG. 4A, and thus similar parts will not be described here. Please refer to FIG. 4B, the semiconductor device The package 460 includes substantially grounding elements 462a and 462b disposed around the substrate unit 102. In this embodiment, the grounding elements 462a and 462b are recesses of the grounding hole, extending over the lower surface 106 of the substrate unit 102 and an electric The electrically conductive layer 464 is disposed between the upper surface 104 and the lower surface 106 of the substrate unit 102 and is regarded as an internal ground layer. Specifically, each of the ground elements 462a and 462b An upper via pad residue 466a or 466b, a lower via defect 468a or 468b, and a plate channel residue 470a or 470b are included, wherein the upper via pad residue 466a or 466b is electrically connected to the electrically conductive layer 464. And disposed at a distance below the upper surface 104 of the substrate unit 102 201138050 i wojyor/Λ; the lower via pad residue 468a or 468b is disposed adjacent to the lower surface of the substrate unit 1〇2 1板6; the plate-shaped channel stub 470 extends between the upper via pad residue 466a or 46讣 and the lower via pad residue 468a or 468b. Advantageously, the ground elements 462a and 462b are positioned lower than the substrate unit 1 The upper surface 1〇4 of 〇2 retains the useful area of the upper surface 104, which not only has an electromagnetic interference shielding function, but also allows an overall size reduction by reducing or minimizing the pin area of the semiconductor device package 46〇. Package. In other implementations, however, the location and extent of grounding elements 462a and 462b can vary. In this embodiment, the grounding members 462a and 462b respectively include connecting faces S1, and S2"' and the connections ® Sr > S2" are electrically exposed adjacent to the lateral surfaces 142 and 144, respectively. Advantageously, the relatively large joint faces si, and s2, can enhance the reliability and efficiency of the electrical connection to reduce electromagnetic interference while achieving the goal of reducing the overall package size. In some implementations, the heights HB of the grounding elements 462a and 462b can be slightly less than the thickness of the substrate unit 1〇2 and are in the range of about U mm to about 18 mm, for example, from about 0,2 mm to Approximately 1 mm, or from about 3 mm to about φ mm. One of the widths Wb of the grounding elements 462a and 462b, i.e., a lateral extent adjacent to the lower surface 106, may be between about 75 microns and 2 microns. In the range, for example, from about 〇〇 micron to about 25 〇 micron, or from about IK micron to about 225 micron. FIG. 4C illustrates a semiconductor device package 480 according to another embodiment of the present invention. A cross-sectional view of the semiconductor device package 48 is similar to the semiconductor device package 100 of the aforementioned FIGS. 3C, and the semiconductor device package 4A of FIG. 4A. 201138050 1 ?τ ν»«» XVI 半导体 4 Β semiconductor device package 460, so similar parts will not be described here. Referring to FIG. 4C, the semiconductor device package 480 includes substantially disposed around the substrate unit 102 Grounding elements 482a and 482b. In the example, the grounding elements 482a and 482b are implemented as a residual portion of the grounding hole or the internal grounding hole, and extend over a pair of electrical properties disposed between the upper surface 1〇4 and the lower surface 1〇6 of the substrate unit 102. The 'electrically conductive layers 484a and 484b' between the conductive layers 484a and 484b are treated as a pair of internal/ground layers. Specifically, each of the ground elements 482a and 482b includes an upper via pad residue 486a or 486b. The hole pad residue 488a or 488b, and a plate-shaped channel residue 490a or 490b, wherein the upper via pad residue 486a or 486b is electrically connected to the electrically conductive layer 484a, and is disposed on the upper surface of the substrate unit 102. 4 is spaced apart by a certain distance; the lower via pad residue 488a or 488b is electrically connected to the electrically conductive layer 484b and is disposed above the lower surface 1〇6 of the substrate unit 102 to be separated by a certain distance; The plate-like passage residue 490a or 490b extends between the upper through-hole pad residual portion 486a4 486b and the lower through-hole pad residue 488& or 4881). Advantageously, the grounding elements 482a and 482b are located between the upper surface 104 and the lower surface 106 of the substrate unit 1〇2 to retain the useful area of the upper surface from the (10) and lower surface 106, which not only has electromagnetic interference shielding functions, but also allows The package of the overall size reduction is obtained by reducing or minimizing the pin area of the semiconductor device enclosure. However, in other embodiments, the position and extent of the grounding elements 482a and 482b can vary. In this embodiment, the grounding elements 482a and 482b include connecting faces S1,,, and S2, respectively, and the connecting faces S1_port S2 & are electrically exposed adjacent to the lateral surfaces (4) and 23 201138050 144. Advantageously, the relatively large joint faces $],,, and s2, can enhance the reliability and efficiency of the electrical connections to reduce electromagnetic interference, and at the same time achieve the goal of reducing the overall package size. In some implementations, the heights of the grounding elements 482a and 482b may be slightly less than the substrate, and may range from about 0 mm to about "mm, such as from about G. 2 mm to about 〇. 8. 8 mm, or from about Q2 mm to about mm. The width Wc of one of the grounding elements 482a and 482b, i.e., the lateral extent adjacent to the electrically conductive layer 484a or 484b, may range from about 纳微米 to 275 microns. For example, from about 1 〇〇 micron to about 2 刈 micron, or from about 125 micron to about 225 micron. 5A to 5E illustrate forming a semiconductor device package according to an embodiment of the present invention. - Method. For the sake of simplicity, the following granulation is described in accordance with the semiconductor device package of Figures 1 to 3C. However, it should be noted that this process can be similarly used for execution to form other The semiconductor device package is, for example, the semiconductor device package of FIG. 4A, the semiconductor device package paste of FIG. 4B, and the semiconductor device package of FIG. 4C. First, please refer to FIG. 5A and FIG. 5B. Provide a substrate 5〇〇, increase for I For the production capacity, the substrate 500 includes a plurality of substrate units, including the substrate unit 102 and an adjacent substrate unit, thereby reliably allowing the process to be easily performed in a parallel manner or in a continuous manner. A plurality of substrate units are continuously arranged in a straight line. Alternatively, a plurality of substrate units are arranged in an array in a two-dimensional direction (submerged in a phantom form. For simplicity of representation, the following processes are mainly referred to as substrate units. 102 and its related components are described, however, such processes can be similarly applied to 24 201138050 1 w〇jy〇r/\ other substrate units and their related components for execution. As shown in Figures 5A and 5B, A plurality of ground vias are disposed adjacent to each of the substrate units. Specifically, the ground vias 502a, 502b, 502c, 502d, and 502e are disposed adjacent to the sides of the substrate unit i〇2. In this embodiment, each A grounding hole includes an upper through hole 塾, such as an upper through hole 塾 546a or 546b, a lower through hole pad, such as a lower through hole 塾 548a or 548b, and a plate-shaped passage, such as a plate-shaped passage 550a Or 550b. The ground holes 502a, 502b, 502c, 502d, and 502e may be formed by any of a variety of methods, including, for example, yellow lithography, chemical scribing, laser drilling, or mechanical drilling to form a plurality of openings. And the openings of the ore layers are dispersed in one of the materials, or other suitable electrically conductive materials, using a metal, a metal alloy, a metal or a metal alloy. The forged layers of the openings are formed at about 1 The thickness in the range of micrometers to about 20 microns, such as from about 5 microns to about 20 microns, or from about 1 〇 to about 15 microns, while leaving a via channel that extends substantially across the ground vias 502a, 502b Vertical ranges of 502c, 502d, and 502e. In some implementations, an electrically conductive material may be applied and placed in the via channel to form an electrically conductive core component 'the core components are housed in such via channels' and substantially Fill these through-hole channels. For example, the electrically conductive material may comprise a metal, a solder, or an electrically conductive adhesive, wherein the metal is, for example, copper, and the solder is, for example, any solder having a focal point between 90 C and 450 C. The metal alloy 'electrically conductive adhesive is, for example, a silver paste, an epoxide containing a copper filler, or any resin containing an electrically conductive filler dispersed therein. In other implementations; 3 a non-electrically conductive material may be applied and placed in the via channel to form a non-25 201138050,

i w〇jy〇KA The core component of electrical conduction' These core components are housed in such via channels and substantially fill the via vias. For example, the non-conductive conductive material may comprise a solder mask, an electrical conductive adhesive, or any other suitable resin, wherein the # electrically conductive adhesive is, for example, substantially free of an electrical conduction. The epoxide of the filler. Filling these through-hole channels allows a large area to be formed and enhanced structural rigidity, thereby enhancing the reliability and efficacy of the electrical connectors to reduce electromagnetic interference. Although the grounding holes 502a' 502b, 502c, 502d, and 502e shown herein extend completely between one of the upper surfaces 504 of the substrate 500 and the lower surface 524', in other implementations, the grounding holes 502a, 502b, The range of 502c, 502d, and 502e can vary. For example, at least one of the ground vias 502a, 502b, 502c, 502d, and 502e can be implemented as a hidden ground via or an internal ground via. In this embodiment, a through-hole pad having a ring shape, such as an upper via pad 546a or 546b, and a plate-like channel, such as a plate-like channel 550a or 550b' defines a via channel, the via channel The outer shape is a cylindrical shape comprising a substantially circular cross section. In general, the shape of the through hole pad and the shape of a through hole channel may be any shape. For example, 'a through-hole channel may have other types of columnar or non-columnar' columnar shape, for example, an elliptical column, a square column, or a rectangular column. The non-columnar shape may be, for example, a cone shape. A funnel shape, or other tapered shape. - The plurality of lateral surfaces of the via passage may be curved or rough. For some implementations, one of the lateral extents W3 (also sometimes referred to as a via size) of each via channel may be in the range of from about 50 microns to about 350 mils, for example from about 1 〇〇 microns to about 300 microns, or from 26 201138050 1 w〇j^or/\ about 150 microns to about 25 microns, and the lateral extent of each via pad (sometimes referred to as a through hole size) It may be in the range of from about 150 microns to about 550 microns, such as from about 200 microns to about 5 microns, or from about 250 microns to about 450 microns. If a through-hole or a through-hole pad has an irregular shape, the lateral extent W3 or W4 may, for example, be averaged over one of a plurality of lateral ranges corresponding to a plurality of orthogonal directions. In order to enhance the reliability and efficacy of the electrical connector to reduce electromagnetic interference 'several grounding holes are arranged adjacent to all four side Φ faces of each substrate unit'. However, these grounding holes can also be placed adjacent to four Side - subgroup. The ground vias may also be provided with a subset of all four corners or four corners adjacent to each substrate unit. For some implementations, a spacing 1^ (sometimes referred to as a via spacing) between the most adjacent grounding holes of a substrate unit can range from about 0.1 mm to about 3 mm. Within, for example, from about 0.2 mm to about 2 mm, or from about 0.5 mm to about 15 mm. Referring to FIG. 5B, a dotted line boundary in each substrate unit defines a "forbidden" area ("keep-〇ut"' portion), which is internally provided with a plurality of semi-conductor devices. In order to process the semiconductor device The adverse impact in the reduction or minimization can be set, the grounding holes of several substrate units can be set, and the grounding holes are separated from the forbidden area by a distance L2 (sometimes referred to as a forbidden distance ("keep-out" For some implementations, the pitch l2 can range from about 50 microns to about 300 microns, such as from about 50 microns to about 200 microns or from about 100 microns to 150 microns. The number and arrangement position of the grounding holes may be different from those of Figures 5A and 5B. The rows of grounding holes may also be disposed adjacent to each substrate unit. The concealed grounding disposed under the upper surface 504 Hole or inner 27 201138050 I wo^vor/vt section grounding hole case does not need to configure the spacing L2. Specifically, such hidden grounding hole or internal grounding hole can be partially or completely set in the forbidden zone And disposed under the semiconductor device The objective of reducing the size of an integral semiconductor device package is achieved by reducing or minimizing adverse impacts in the fabrication process of the semiconductor device. Once the substrate 500 is provided, the semiconductor devices 108a, 1B, 8b, and 108c are disposed adjacent to the substrate. The upper surface 504 of the 500 is electrically connected to the substrate unit 102. Specifically, the semiconductor device 108b is wire bonded to the substrate unit 1 〇2 by the bonding wire 112, and the semiconductor device 丨〇8a and 肇108c are surface-fixed. The surface is mounted on the substrate unit 1 〇 2. Please refer to FIG. 5A. The lower surface 524 of the substrate 500 is disposed adjacent to a tape 506. The tape 506 may be a single-sided or double-sided adhesive tape. Advantageously, The tape 506 can secure the substrate unit 1 〇 2 and its associated adjacent substrate unit 'and allow the placement of these elements adjacent to the tape 506 to perform various continuous processes without the need to invert or transfer to another carrier. As shown in FIG. 5C, a glue material 514 is applied to the upper surface 504 of the substrate 500 to substantially cover or enclose the ground holes 5〇2a φ and 502b, and the semiconductor. Let l 8a, 108b, and i 8c, and bond wire n2. For example, 'sealing material 514 may include a novolac-based regin, an epoxy resin (ep〇xy-based region) ), a silicon-based resin, or other suitable sealing material. Suitable fillers may also include, for example, powdered cerium oxide. The sealing material 514 may be applied by any of a number of sealing techniques, such as It is a compression sealant, an injection sealer, and a conversion sealant. Once applied, the hardened or cured sealant material 514' is formed, for example, by lowering the temperature below the melting point of one of the sealants 28 201138050. In order to assist the substrate 500 in finding the proper position during the continuous cutting process, the position mark can be formed in the encapsulation structure 516 using, for example, a laser marker. Alternatively, in the connection, the alignment marks may be formed adjacent to one of the substrates 500. A cutting process is then performed on one of the upper surfaces 516 of the encapsulation structure 526. The method of such a cutting process can be referred to as a "front-side" cutting process. Referring to Figures 5C and 5D, the front end cutting process is performed using a dicing saw 518 to form a plurality of slits, including slits 520a and 520b. Specifically, the slits 520a and 520b extend downwardly and completely through the sealant structure 526 and the substrate 500, and partially through the tape 506, thereby subdividing the sealant structure 526 and the substrate 500 into separate units, including the package. 114 and substrate unit 102. The manner of such a cutting process can be referred to as a "full-cut" singulation because the re-cutting of the encapsulation structure 526 and the substrate 500 at each different location can be produced via a cutting process without Multiple cutting processes are required, such as a few half-cut singulations. Advantageously, using this full cutting process instead of a half-cutting process can increase manufacturing throughput by reducing the number of cutting processes and reducing the time required for such processes. Increasing the manufacturing cost of one of the substrates 500 can also reduce the manufacturing cost, and can also increase the overall yield by reducing the probability of defects caused by cutting errors. As shown in Fig. 5D, in the full cutting process, the tape 506 secures the substrate unit 102 and the package 114 and the associated substrate units and packages associated therewith. Please continue to refer to Figure 5D, the cutting saw 518 is set laterally and 29 201138050

I WOiVOPA ^ is substantially aligned with each ground hole, such as - removing a certain volume or weight percentage of the ground hole, for example: yes: 10% to about 90%, from about 3〇% to 7G%, or It is from Joppa to about _ Γ If the core components are included, the resulting slits are also. A certain volume or percentage of weight of the component, such as = heart /. To about 9G%, from about to Qing = = volume or weight. In this method, two ^ and wide ' are formed and the grounding elements _ and (10) respectively include a connecting surface _ exposed to the base == surrounding environment. In the cutting process, the alignment of the cutting ore 518 can be assisted by the positioning marks, and the cutting can be provided in the form of a cut (4) 8 in a certain manner, in each of the joints 520a and 52 One of the % wide yields c (the village is said to be - the full cut width, or the complete cut line ^ in the range of 1 micron US micron to about _ micron, for example from about 200" 1 micron, or from about From 250 micrometers to about 35 micrometers. Referring to the first graph, forming a surface adjacent to the electromagnetic interference coating 522, the exposed contact surfaces include a package body: b: 2. The grounding element 11 δ "the connection surface of σ 1185 w 5 is the lateral surface 142 of the original 102 and 44. Electromagnetic interference coating, I:: any coating technology, such as chemical vapor deposition..., electroplating, electroplating, printing, spraying, splashing The plated or vacuumed EMI coating 522 can comprise a single-degree electrical power t formed by the brocade, and having a thickness of at least about 5 microns, about 10 η 疋 、 = 5 Å to about 50 microns. 'Or from about 5 microns to the release. Right electromagnetic interference coating 522 is a multi-layer coating, then not 201138050

i wo^yorA The same layer can be formed by the same coating _/, for example, by sputum or different coating techniques. It can be used to make electricity from electricity or electricity to form an inner layer of steel. If the other 4 ♦ is formed by any of the nickel forms, formed by copper = with / (^ no: electric ore and t and it has - a thickness of at least about 1 micron - the base layer), 5 〇 micron, or from! Micron to about 1^, for example, from about 1 micron to about stainless steel, nickel, or steel, and one layer formed by sputtering, and having an outer layer (which can be regarded as an anti-oxidation) Micron to, about 1 micron, or about the thickness of the mountain, for example, from about 〇.〇1 example, 'sound to electromagnetic interference::: about 0.1 micron. In these processes to help the inner layer The roughening of the surface and the pretreatment process of the open type are, for example, by the chemical etching of the "formation of the German seed layer" surface roughening example: base:: mechanical light. Using, for example, pick and place technology The scooping of the thunder, the 兀#02 and its related components are separated from the winning belt 506, and the semiconductor device of the 匕-〃 magnetic concealing member 124 is sealed. The body is formed by the second embodiment. The guide bushing indicates that the following process is described with reference to the Galvanic device package 380. However, it should be noted that Ή can be similarly used for execution to form other semiconductor devices, for example, The semiconductor device package 460 of the semiconductor device package of FIG. 3B of FIG. 3C, And the second conductor of Figure 4C, the package is placed. Some aspects of the process can also be implemented in a manner similar to the 5A to 5E diagrams described in the month, so the similar part 8 will not be in this one - description Knife 31 201138050

I W03y〇KA Referring to Fig. 6, the hardened sealant 614 and the substrate 6 are disposed adjacent to a tape 606 which can be implemented as a single or double adhesive tape. Next, a surface 616 of the hardened encapsulant 614 is subjected to a cutting process. As shown in Fig. 6, the cutting process is performed using a dicing saw 618 to form slits 62 〇 & and 62 〇 b. Wherein, the slits 62A and 620b extend downwardly and completely pass through the hardened sealant 614, the substrate 600, and partially pass the tape 6〇6, thereby splitting the hard rubber material 614 and the substrate 600 again. For several separate units,

The saw blade includes a package body 114 and a substrate unit 102. Specifically, the cutting is performed, and is arranged to the ground and substantially aligned with each of the grounding holes, so that the grounding-serving slits divide the grounding hole into two grounding elements, and the two cores are They are spaced apart from each other and are disposed adjacent to the opposing substrate unit. The component is then included. The resulting slit will also form a fill component for each core and 418b. In this manner, the grounding members 418a and S2 are formed, and the grounding members 4, 83, and 41, respectively, include connection faces S1 which are circumferentially in contact with the periphery of the substrate unit 1〇2. Right first from a

The cutting process method shown in FIG. 6 is used to reduce the number of cutting processes and reduce the number of cutting processes required to increase the manufacturing capacity; by further increasing the substrate 600 Mistaken 1 rate to reduce manufacturing costs; and by further reducing the cutting error, increasing the overall yield per consistent defect probability. For some implementations, the through-hole size Ws of one of the grounding holes of the bamboo can also be made from about 100 micrometers to 700. The column is from about 200 micrometers to 600 micrometers, or from about 200 micrometers to 600 micrometers. 5 〇〇 micron, and each of the grounding holes has a through-hole pad w J - * 密 m to a range of about 11 〇〇 micrometers, for example, from about 32 201138050 I wojvor / v 4 - 00 micrometers to about 1000 micrometers Or from about 5 〇〇 micrometers to about 9 〇〇 micrometers. The width c: 2 of each of the slits 620a and 620b may be substantially the same as the width C1 of the 5D figure of the aforementioned reference, and the width 仏 may be From about 1 〇〇m to about 600 microns, for example from about 2 microns to about 4 microns, or from about 250 microns to about 350 microns. However, in other implementations, the width C2 can The change can be made with respect to the through hole size W5 of a grounding hole or the through hole pad size W6 of a grounding hole to allow it to be further divided into a plurality of grounding elements. For example, the general width C2 can be indicated by It is: C2 < W5 < W6. In summary, although the present invention has been disclosed above in the preferred embodiment, However, it is not intended to limit the invention, and various modifications and changes may be made without departing from the spirit and scope of the invention as defined by the appended claims. Further modifications may be made to adapt to a particular situation, material, material composition, method, or process objective, spirit, and scope of the invention. All such amendments are covered by the appended claims. In particular, the methods disclosed herein have been described in the context of a particular process, which may be combined, divided, or rearranged to form the same method without departing from the teachings of the invention. Therefore, unless otherwise specified herein, the arrangement or classification of the process does not limit the present invention. [FIG. 1] FIG. 1 is a schematic view of a semiconductor device package according to an embodiment of the present invention. A cross-sectional view of one of the semiconductor device packages taken along line A-A of Figure 3. 33 201138050

TW6396PA large section (4) m semiconductor device package - partial amplification diagram. + + 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体4th Γ-Γ=Semiconductor device according to another embodiment of the present invention: FIG. 1 is a first embodiment of forming a first semi-conductive body 6: setting = present = ... forming a first embodiment [Description of main component symbols] Semiconductor device package 100, 400, 460, 480 upper surface 102, 102'. Substrate unit 104' 504 > 516 > 616 106, 524. Lower surface 108a, 108b, 108c, 408b: semiconductor Device 110a, 110b, 11〇c: electrical contact 112: bonding wire 114: package 34 201138050

I WUJVUr/A 118a, 118b, 418a, 418b, 462a, 462b, 482a, 482b: grounding elements 120, 122, 142, 144: lateral surface 124: electromagnetic interference shield 126: upper portion 128: side portions 146a, 146b, 446a, 446b, 466a, 466b, 486a, 486b: upper via pad stubs 148a, 148b, 448a, 448b, 468a, 468b, 488a, 488b: underpass vias 150a, 150b, 450a, 450b, 470a, 470b 490a, 490b: plate-shaped passage residual portion 300: inner layer 3 0 2 : outer layer 304: fillers 452, 464, 484a, 484b: electrically conductive layers 500, 600: substrates 502a, 502b, 502c, 502d, 502e: grounding holes 506, 606: tape 518, 618: dicing saw 520a, 520b, 620a, 620b: slit 522: electromagnetic interference coating 546a, 546b: upper through hole 塾 548a, 548b: lower through hole pad 550a, 550b: plate channel 514, 614: sealing material 35 201138050 i wojvoka ' ' c,, c2: slit width

Hi, H2, HB, Hc: the height L of the grounding element, the distance between the nearest adjacent grounding holes L2. The distance between the grounding hole and the forbidden interval is SI, S2, SI', S2', SI,,, S2,,: Connection surface W,, w2, WB, wc: width w3, w4: lateral range w5: through hole size w6: through hole pad size •

36

Claims (1)

201138050 VII. Patent application scope: 1. A semiconductor device package comprising: a substrate unit comprising an upper surface, a lower surface, a lateral surface disposed adjacent to one of the substrate units, and extending completely Between the upper surface of the substrate unit and the lower surface of the substrate unit, and φ a grounding member disposed adjacent to the periphery of the substrate unit and extending at least partially over the upper surface of the substrate unit and the substrate unit Between the lower surfaces, the grounding member includes a recessed portion disposed adjacent to the lateral surface of the substrate unit; a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to The substrate unit is disposed adjacent to the upper surface of the substrate unit and covers the semiconductor device, the package includes a plurality of external surfaces, the external surface includes a lateral surface, and an electromagnetic interference shielding Electromagnetic interference shield, which is disposed adjacent to the package The outer surface and the lateral surface of the substrate unit are electrically connected to the grounding element and recessed inwardly adjacent the recessed portion of the grounding element. 2. The semiconductor device package of claim 1, wherein the grounding element comprises a plate-shaped channel stub, the plate-shaped channel stub corresponding to the recessed portion of the grounding element, and the electromagnetic interference shield 37 The 201138050 covers the plate-like passage portion in a shape such that the electromagnetic interference shielding member is recessed inwardly adjacent to the plate-shaped passage portion. The semiconductor device package plate-shaped channel residual portion described in the second aspect of the invention includes a connection surface which is inwardly recessed relative to the second surface, and the electromagnetic interference system /, covering the connecting surface of the plate-shaped passage residual portion. Piece, loaded. The semiconductor device package surface described in the '1 patent, and the portion extending partially between the upper surface of the substrate unit, the grounded one-degree piece, and the semiconductor device package described in (4) The heart includes - an internal ground plane, and the ground element extends between the pair of internal ground planes. Η兀 Piece, two Ming special. The lateral surface of the r/plate early 70 of the semiconductor device package of the invention is substantially a plane, and the lateral surface of the surface is substantially aligned with the substrate unit. The lateral member, the semiconductor device package of the range: *1, wherein the interference shielding member comprises a lateral portion and the lateral surface portion, and the lateral portion is along the lateral portion The lower end of the lateral portion of the lateral portion of the substrate unit is substantially aligned with the substrate. 8. A semiconductor package, comprising: a substrate unit comprising: a first surface, 38 201138050 1 wo^yo^A, an opposite surface, and a grounding element extending at least partially from the substrate unit Between a surface and the second opposing surface of the substrate unit, the grounding member includes a plate-shaped passage residue and a filler, the plate-shaped passage residue being recessed inwardly to accommodate the filler, the plate-shaped passage residue And the filler is disposed adjacent to a lateral surface of the grounding member adjacent to the substrate unit; a semiconductor device disposed adjacent to the first surface of the substrate unit and electrically connected to the substrate unit a J• package disposed adjacent to the first surface of the substrate, and a semiconductor device including a plurality of external surfaces; An electromagnetic interference shielding member disposed adjacent to the outer portion of the county body and the lateral surface electrically connected to the grounding member, wherein the semiconductor component is laterally oriented and opposite to the substrate unit Bay Bureau. It’s early. The sorrow--the surface is essentially a piece, and the lateral surface of the semiconductor device package /, the medium-to-ground 7L piece of the Lean (4) item 8 is flat. The semiconductor device package /, the medium 5 hai filler system described in claim 9 has electrical conductivity. 11. The object of claim 9 wherein the substrate unit further comprises a lateral surface, the package extending all the way to the first surface, the second opposing surface, the substrate between the substrate units The lateral surface of the early % is substantially 39 201138050 1 WOJVO^A substantially electrically contacts the abutting member on the side lateral surface of the substrate unit with respect to the second opposing surface of the substrate unit, the Si in the middle The semiconductor device package of claim 1, wherein the outer surfaces include a lateral surface, and the lateral surface of the body is substantially aligned with the lateral surface of the substrate unit.苴 苴 : : : : : : : : : 味 味 味 味 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Between the first through hole 塾戋邛 and the fifth through hole pad residue. In the semiconductor device package described in Item 13, the "substrate is further included", the first layer is disposed on the first surface of the substrate and the second surface of the substrate unit The surface of the first through-hole pad is disposed adjacent to the electrically conductive layer of the substrate unit, and the second via-hole portion is disposed adjacent to the second opposing surface of the substrate unit. The semiconductor device package of claim 8, wherein the electromagnetic interference shielding member is a conformal shielding member, the conformal shielding: the first layer and the second layer 'the second layer system Adjacent to the green first layer. 6 6. The device package according to claim 15 wherein the first layer and the second layer comprise different electrically conductive materials. A method for forming a device, comprising: 201138050 I wojvoka provides a substrate including a ground hole and a core component extending at least partially between an upper surface of the substrate and a lower surface of the substrate, the ground hole defining a pass Hole channel, The via channel is substantially filled by the core component; electrically connecting a semiconductor device to the upper surface of the substrate; applying a glue material to the upper surface of the substrate to form a cover of the semiconductor device Rubber structure Forming a plurality of slits that completely pass through the encapsulation structure and the substrate, and the slits are aligned with the substrate, such that: (a) the substrate is subdivided to form a divided substrate (b) the encapsulation structure is subdivided to form a body adjacent to one of the substrate units, the package includes a plurality of outer surfaces; and (c) the ground hole-residue and the core ^ The component-residue is correspondingly disposed adjacent to the surrounding-grounding component, the grounding component includes an exposed connecting surface; and the body is electrically formed after the slitting is applied to apply the electromagnetic interference coating to the sealing The external surfaces and the magnetic interference of the grounding element interfere with the shield. The semiconductor device of the invention is described as encapsulating an electrically conductive material to a via via, as in the patent application, wherein the substrate is included in the substrate to form the core component. The surface of the package, the 41 201138050 1 w〇jy〇r/\ outer surface includes a lateral surface, and the slits are formed such that the lateral surface of the package is substantially aligned On the lateral surface of the substrate unit. 42