201131952 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種轉換裝置’特別是關於一種昇壓型轉換裝置。 【先前技術】 隨著時代的進步，人們對能源的需求與日倶增，再生能源也隨之 受到相當高的重視。其中，太陽光伏電池是眾多再生能源中最受歡迎 的，乃是因為它有取之不盡、用之不竭及乾淨的優點。為了從太陽能 電池模組得到最大功率，因此需要最大功率追踨器，一般均以昇壓型 φ (boost)轉換器來實現。 如第1圖所示，一般昇壓型轉換器包含一主電感10、一主開關12 與一主二極體14’並連接一負載電容16與一負載電阻，其與4 分別為主開關12之跨電壓與電流》然而，針對大功率應用，元件之應 力、切換損失及EM丨干擾實均來自主開關12導通時二極體14之逆向 回復電流，以及主開關12截止時雜散電感和二極體14順向恢復時間 所造成之開關跨壓’結果造成整個系統不穩定的現象。請同時參閱第 2圖及第3圖，v*與k分別出現電壓尖波與電流尖波，且ν*與k交 越面積大，因此功率損失也大，此為相當嚴重之硬切換，亦是上述各 φ 種損失及不穩定的原因。因此，有被動式及主動式緩衝電路被應用於 昇壓型轉換器中。 如第4圖至第6圖所示，第4圖之昇壓型轉換器係將被動式緩衝 器20與第1圖之昇壓型轉換器整合在一起，可以做到零電壓及零電流 轉態切換的功能，但因主二極體14逆向回復電流及被被動式緩衝器 20循環電流所形成的諧振效應，造成主開關12在轉態導通期間產生 大電流應力》 解決主開關大電流應力的問題，可以用主動式緩衝器來取代被動 式緩衝器，主動式緩衝器可以為降壓型(bUCk)、昇壓型(boost)或返驰 式(flyback)三種。如第7圖至第9圖所示，第7圖係將降壓型主動緩 3 201131952 衝器22與第1圖之昇壓型轉換器整合在一起，其中，降壓型緩衝器 22可以箝制主開關電位，但箝位電容在主開關12導通期間，能量仍 不能完全釋放，會導致主開關12截止時的硬切換。因此，藉由昇壓型 緩衝器，可以解決上述硬切換的缺點。 如第10圖至第12圖所示，第1〇圖係將昇壓型主動緩衝器24與 第1圆之昇壓型轉換器整合在一起。昇壓型緩衝器24在主開關12導 通期間，可以有效地把箝位電容能量傳送至輸出端，製造出下一週期 零電壓轉態(ZVT)切換的機會。雖然，有零電壓轉態切換的優點，但若 系統操作於大電流條件下，主電感1〇大電流對容值較低的箝位電容充 電’相繼衍生出主開關12上高電壓應力的問題。 因此，本發明係在針對上述之困擾，提出一種昇壓型轉換裝置， 以解決上述所產生的問題。 【發明内容】 本發明之主要目的，在於提供一種昇壓型轉換裝置，其係與一抑 制逆向回復電流之電感和一返馳式主動緩衝電路整合，此電感可使主 開關之m紐上升’以朗料絲肋換，麟電剌可將箝位 電容能量抽至負載端及降低主開關兩端之電壓應力，以達到零電壓轉 態切換，如此便能提昇整體裝置之轉換效率。 為達上述目的，本發明提供一種昇壓型轉換裝置，係包含一連接 輸入電壓之主開關，主開關係接收一外部訊號以控制開關狀態，主 開關係連接-箝位電路，其可根駐_之截止觀，顧符位電容 來儲存主電魏叙能量’以㈣糾聽作在零電壓娜(ZVT)，並 ，辅助開關截止時，將H位電容之能量，透過返馳式主動緩衝電路傳 送至緩衝電容中。在箝位電路儲存能量時，相對提供-箝位電壓，使 電感電流能迅速追至主紐，進而達到—般昇_轉換器導通狀 態。另更有—電感’其—端連接主麵、箝位電路與輸人電壓，另一 端連接主二純與返財主祕衝祕，並在返赋线麟電路接 201131952 收能量時，限制主二極體之逆向回復電流，以控制主開關操作在零電 流轉態（ZCT)o 茲為使貴審查委員對本發明之結構特徵及所達成之功效更有進 一步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明 如後： 【實施方式】 以下請參閱第13圓，本發明之轉換裝置包含一主開關26，第一 N型金氧半場效電晶體（以下亦以標號26代表此元件）、一第一電感 ^ 28及其第一漏感30、一第二電感32及其第二漏感34、一主二極體 36、一箝位電路38、一返馳式主動緩衝電路4〇與一二極體42 ,其中 第一 28、第一電感32為共鐵心之搞合電感。 第一 N型金氧半場效電晶體26之源極連接至一輸入電壓γ之負 端，汲極則依序透過第一電感28、第一漏感3〇連接至輸入電壓γ之 正端，閘極則接收一做為外部訊號之數位訊號，以控制主開關26之開 關狀態。第_ Ν型金氧半場效電晶體26的錄與祕，係連接箱位 電路38 ’箝位電路38連接返馳式主動緩衝電路4〇，返驰式主動緩衝 電路40貝ij分別連接主二極體36及二極艘42之正極以透過主二極 • 體^6及二極體42連接輸出負載，此輸出負載包含互相並聯之-負載 電谷44與-負載電阻46。另互相串聯之第二電感32及其第二漏感 3心第二電感32之-端同時連接返馳式主動緩衝電路4〇與主二極體 36之正極’第二漏感34則同時連接第—Ν型金氧半場效電晶體％ 的汲極與箝位電路38。 符位電路38包含-狐二娜48與—麻電容印，餘二極體 )正極連接第一 Ν型場效電晶體26之没極、第一電感28、第二漏 =4 ’箝位電容5〇之—端連接齡二極體明之負極，另一端連接第 40並 1場效電晶體26之源極，籍位電容5〇更與返馳式主動緩衝電路 201131952 在外部訊號為低準位之數位訊號時，主開關26會呈現截止狀態， 此時箝位電路38中的箝位電容50，會依序透過第一電感28及箝位二 極體48儲存輸入電壓h提供之能量，來控制主開關26操作在零電壓 轉態（ZVT);另一方面，返驰式主動緩衝電路40也藉著主開關26截 止期間’箝制一電位，將能量透過主二極體36傳送給輸出負載，順利 完成昇壓型轉換器截止轉態。 在外部訊號為高準位之數位訊號時，主開關26會呈現導通狀態， 在導通瞬間’第二電感32及第二漏感34係限制主二極體36之逆向 回復電流，以控制主開關26操作在零電流轉態（ZCT)。在導通期間， 輔助開關56也同步啟動’以抽取從箝位電容5〇的能量，並儲存至激 磁電感52，進而製造出下一週期零電壓轉態切換的機會。 本發明之返馳式主動緩衝電路40，是操作在不連讀導通模式 (DCM),主要目的是避免其開關上的高電壓及大電流應力的產生。 返驰式主動緩衝電路40更包含一輔助開關56，第二N型金氧半場效 電晶體（以下亦以標號56代表此元件），其源極連接第一 n型金氧半 場效電晶體26之源極、箝位電容50、負載電容44與負載電阻46， 閘極則接收一數位訊號’以控制輔助開關56之開關狀態，其没極連接 一變壓器54之一次側，且此一次側係與一激磁電感52並聯，激磁電 感52之一端係同時連接箝位二極體48之負極與箝位電容5〇，並在辅 助開關56導通時’從箝位電容5〇接收能量，並儲存至激磁電感52。 變壓器54更具有二次側，此二次側係依序透過返驰式輸出二極體 60、二極體42連接負載電容44，並與一緩衝電容58連接。緩衝電容 58之一端係連接第二電感32與主二極體36之正極，另一端連接二極 鱧42。在輔助開關56關閉時，激磁電感52將能量傳送至緩衝電容 58中’當主開關截止時，第―、第二電感28、32之電流相等 ，經二 極體42路徑，使緩衝電容58的能量傳送至負載端。 上述之緩衝電容58之電容值需大於箝位電容5〇 ,主要目的是可 降低主開關26在截止時的高電壓應力。為了使電路圖與下面將介紹的 201131952 波形圖加以對冑先介紹電路圖中各元件之電壓及通過各元件之電流 的代表符號。嗜分顺通過主關26之電流，與主顧26之 跨電壓；y與〜係分別為通過箝位電容5〇之電流，與籍位電容5〇之 跨㈣X係分別為通過輔助開關56之電流，與輔助開關邱 之跨電壓，〜’與’分別為通過激磁電感52之電流，與激磁電感 52之跨電壓；W為通過返跳式輸出二極體6〇之電流；^為通過二極 體42之電流’ k與、係分別為通過緩衝電容58之電流，與緩衝電容 58之跨電磨；L為通過第一電感28之電流；l為通過第二電感32 之電流’ ^"為通，主二極體36之電流；^為控制主開關26之開關狀 ，之電壓訊號；〃⑺為__關56之關狀態之賴訊號；/〇與 〇係分別為通過負載電jt且46之電流，與負載電阻46之跨電壓。 以下請同時參閱第14圖，電路之時序可分成十個模式，每個模式 動作分析如下： 模式一，即to S t<t1:在時間t〇之前，心為高準位之數位訊號， 主開關26是維持導通的狀態。當時間等於t〇之後，匕為低準位之數 位，號’主開關26 始截止，L向符位電容5〇充電，一直充到箝位 電容50紅有減職之緩衝電容58的加總電料於^為止，4 φ *以部分電流對籍位電容50繼續充電，而其餘部分則流經第二電感 32。其中，箝位電容50與緩衝電容58兩者關係是為串聯。 模式二，即h S t<t2:當時間等於b時，部份L改依序走第二漏 感34、第二電感32、緩衝電容58、二極體42、負載電容44、第一 漏^ 30、第—電感28之路徑，且第二電感32、緩衝電容邱及箝位 電今50發生諧振，緩衝電容58開始釋放能量至輸出負載(在模式二期 間，緩衝電容58能量未完全釋放完）；在h時，G = L，〜與Ve達到 最大值。另在時間to至t2間，緩慢上升，主開關26已經發生 壓轉態(ZVT)切換。 模式三，即t2 s t < t3:在這個模式中，緩衝電容58繼續釋放能 量至輸出負載，主酬26之跨崎降至與輸出負載^電位。 7 201131952 模式四，即b $ t<t4:緩衝電容58能量已經釋放完，l改走主 二極體36的路徑，主開關26之跨電壓與輸出負裁同電位，此動作如 同一般的昇壓轉換器的截止狀態模式。 模式五，即U S t<ts:當時間等於U時，L與匕⑺皆為高準位之 數位訊號，以啟動主開關26與輔助開關56。在這個模式中同,&緩慢 上升，以達到零電流轉態(ZCT)的切換，L會慢慢降至零；此時，激磁 電感52係從箝位電容50接收能量，並儲存之，接收過程中，箝位電 容50與激磁電感52產生諧振現象。 模式六，即ts St <tK在這個模式中，主二極體36發生逆向回復 電流心，且此電流被第二電感32與第二漏感34有效地限制著。 模式七’即t6 $ t < t7:由於H位電容5G内的能量未^被傳至 激磁電感52中，卿此模式侧續把箝位電容5Q内的能量傳至激磁 模式八’即h $ t < te:當時間點等於h時，箝位電容5〇内的能 量被抽完。為了確保藉位電容50是零電位，在控制策略中故意將驅 動信號的時間稱稱略大於箱位電容5〇放電的時間，其目的是製造 出下一週期零電壓轉態的機會給主開關26。 模式九’即te S t < t9:當時間等於時，％為低準位之數位訊 號’使辅助開關56截止。此時，變壓器54會將儲存在激磁電感52 令的能量傳錢衝電容58巾。其間，舰_ 52魏賊容58發 生諸振現象。 =十’即t9 $ t $ t。··當時間等於時，儲存於激磁電感52 中=量已完全被傳送至緩衝電容58中，緩衝電容58的電位也將被 -直箝制到下-週期的時間t”至此，—週期的切換動作結束。 能酱閱第、13圖與第15圖’由波形圖可知’在主開關26轉 梅時’第二電感32可以限制主二極體36之逆向回復電流，使，(緩 * ’且沒有電流尖波、震鮮屬硬切換不正常雜訊波形的出現， 以達到零電流轉態柔性切換，進而降低功率損失，並提高轉換效率。 201131952 *奢同時參閱第13圖與第16圖，由波形圖可知，在主開關26轉 態截止時，符位電路38可箝制並儲存輸入電壓所提供的能量，返触式 主動緩衝電路40可降低v*應力，使4緩慢上升，且沒有電壓尖波等 屬硬切換不正常雜訊波形的出現，以達到零電壓轉態柔性切換，進而 降低功率損失，並提高轉換效率。 綜上所述，本發明係與一耦合電感和一返馳式主動緩衝電路整 合，以達到降低成本及零電流之轉態柔性切換。 以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發 明實施之範圍，故舉凡依本發明申請專利範園所述之形狀、構造、特 馨 徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範園 内0 【圖式簡單說明】 第1圖為先前技術之昇壓型轉換器的電路示意圖。 第2圖為第1圖之電路於主開關轉態導通時之波形圖。 第3圖為第1圖之電路於主開關轉態截止時之波形圖。 第4圖為先前技術之整合被動式緩衝器之昇壓型轉換器的電路示意 圖。 第5圖為第4圖之電路於主開關轉態導通時之波形圖。 * 第6圖為第4圖之電路於主開關轉態截止時之波形圖。 第7圖為先前技術之整合降壓型主動緩衝器之昇壓型轉換器的電路示 意圖。 第8圖為第7圖之電路於主開關轉態導通時之波形圖。 第9圖為第7圖之電路於主開關轉態截止時之波形圖。 第10圖為先前技術之整合昇壓型主動緩衝器之昇壓型轉換器的電路 示意圖。 第11圖為第10圖之電路於主開關轉態導通時之波形圖。 第12圖為第10圖之電路於主開關轉誠止時之波形圖。 9 201131952 第13圖為本發明之裝置電路示意圖。 第14圖為本發明之裝置各元件波形圖。 第15圖為本發明之於主開關轉態導通時之波形圖。 第16圖為本發明之於主開關轉態截止時之波形圖。 【主要元件符號說明】 10主電感 14 主二極體 18負載電阻 22降壓型主動緩衝器 26主開關 30第一漏感 34第二漏感 38箝位電路 42二極體 46負載電阻 50箝位電容 54變壓器 58緩衝電容 12主開關 16負載電容 20被動式緩衝器 24昇壓型主動緩衝器 28第一電感 32第二電感 36主二極體 40返馳式主動緩衝電路 44負載電容 48箝位二極體 52激磁電感 56輔助開關 60返驰式輸出二極體201131952 VI. Description of the Invention: [Technical Field] The present invention relates to a conversion device, and more particularly to a boost type conversion device. [Prior Art] With the advancement of the times, people's demand for energy has increased, and renewable energy has also received considerable attention. Among them, solar photovoltaic cells are the most popular among many renewable energy sources because of their inexhaustible, inexhaustible and clean advantages. In order to obtain maximum power from the solar cell module, a maximum power tracker is required, which is generally implemented by a boost type φ (boost) converter. As shown in FIG. 1, a general boost converter includes a main inductor 10, a main switch 12 and a main diode 14', and is connected to a load capacitor 16 and a load resistor, and 4 and 4 are main switches 12, respectively. Cross-voltage and current. However, for high-power applications, the stress, switching loss, and EM丨 interference of the components are all derived from the reverse recovery current of the diode 14 when the main switch 12 is turned on, and the stray inductance and the main switch 12 are turned off. The switching across the voltage caused by the recovery time of the diode 14 results in instability of the entire system. Please refer to Fig. 2 and Fig. 3 at the same time. V* and k respectively appear voltage spikes and current spikes, and the area of ν* and k crossover is large, so the power loss is also large. This is a very serious hard switching. It is the cause of the loss and instability of each of the above φ species. Therefore, passive and active snubber circuits are used in boost converters. As shown in Figures 4 to 6, the boost converter of Figure 4 integrates the passive buffer 20 with the boost converter of Figure 1 to achieve zero voltage and zero current transition. The function of switching, but due to the reverse recovery current of the main diode 14 and the resonance effect formed by the circulating current of the passive buffer 20, the main switch 12 generates a large current stress during the on-state conduction". Solving the problem of large current stress of the main switch Active buffers can be used instead of passive buffers. The active buffers can be buck (bUCk), boost (fly) or flyback. As shown in FIGS. 7 to 9, FIG. 7 integrates the step-down active 3 201131952 punch 22 with the boost converter of FIG. 1 , wherein the buck buffer 22 can be clamped. The main switch potential, but the clamp capacitor is still not fully discharged during the conduction of the main switch 12, which will cause a hard switch when the main switch 12 is turned off. Therefore, the disadvantage of the above hard switching can be solved by the boost type buffer. As shown in Figs. 10 to 12, the first diagram integrates the boost type active buffer 24 and the first round boost converter. The boost buffer 24 can effectively transfer the clamp capacitor energy to the output during the turn-on of the main switch 12, creating an opportunity for the next cycle of zero voltage transition (ZVT) switching. Although there is the advantage of zero-voltage switching, if the system is operated under high current conditions, the main inductor 1〇 large current charges the clamp capacitor with lower capacitance value, and the high voltage stress on the main switch 12 is successively derived. . Accordingly, the present invention has been made in view of the above problems, and proposes a boost type conversion device to solve the above-described problems. SUMMARY OF THE INVENTION The main object of the present invention is to provide a boost type conversion device which is integrated with an inductor for suppressing a reverse return current and a flyback active buffer circuit, which can increase the m of the main switch. With the replacement of the ribs, the cymbal can pump the clamp capacitor energy to the load end and reduce the voltage stress at both ends of the main switch to achieve zero voltage transition switching, thus improving the conversion efficiency of the overall device. To achieve the above object, the present invention provides a step-up type conversion device comprising a main switch connected to an input voltage, the main open relationship receiving an external signal to control the switch state, and the main open relationship connection-clamp circuit, which can be rooted _ The cut-off view, the memory of the capacitor to store the main power Wei Xu energy 'to (four) to listen to zero voltage (ZVT), and, when the auxiliary switch is off, the energy of the H-bit capacitor, through the flyback active buffer The circuit is transferred to the snubber capacitor. When the clamp circuit stores energy, the clamp voltage is relatively supplied, so that the inductor current can quickly catch up to the main button, and then the converter is turned on. In addition, the inductor is connected to the main surface, the clamp circuit and the input voltage, and the other end is connected to the main two pure and returning money secret secret, and when the return line Lin circuit is connected to 201131952, the energy is limited. The reverse return current of the polar body to control the main switch operation in the zero current transition state (ZCT) o. In order to enable the reviewing committee to have a better understanding and understanding of the structural features and the achieved effects of the present invention, it is preferred to The embodiment diagram and the detailed description are as follows: [Embodiment] Referring to the 13th circle, the conversion device of the present invention comprises a main switch 26, a first N-type gold-oxygen half field effect transistor (hereinafter also referred to as a label) 26 represents the component), a first inductor 28 and its first leakage inductance 30, a second inductor 32 and its second leakage inductance 34, a main diode 36, a clamping circuit 38, and a flyback The active buffer circuit 4 is coupled to a diode 42 , wherein the first 28 and the first inductor 32 are integrated inductors of the common core. The source of the first N-type MOS field-effect transistor 26 is connected to the negative terminal of an input voltage γ, and the drain is sequentially connected to the positive terminal of the input voltage γ through the first inductor 28 and the first leakage inductance 3 ,. The gate receives a digital signal as an external signal to control the switching state of the main switch 26. The recording and secret of the _ Ν type MOS half-effect transistor 26 is connected to the box circuit 38 'clamp circuit 38 is connected to the flyback active snubber circuit 4 〇, and the flyback active snubber circuit 40 ij is connected to the main two The anodes of the pole bodies 36 and the poles 42 are connected to the output load through the main diodes 6 and the diodes 42. The output loads include the load grids 44 and the load resistors 46 connected in parallel with each other. The second inductor 32 and the second leakage inductance of the second inductor 32 are connected to each other at the same end of the second inductor 32, and the positive-active active buffer circuit 4 of the main diode 36 is connected to the positive terminal of the main diode 36. The first-Ν type MOS half field effect transistor % of the drain and clamp circuit 38. The bit circuit 38 includes a - Fox Erna 48 and - Capacitance Print, the remaining two polar body) positive electrode connected to the first die type field effect transistor 26, the first inductor 28, the second drain = 4 'clamp capacitance 5〇—the end is connected to the negative pole of the second pole body, and the other end is connected to the source of the 40th and 1 field effect transistor 26, and the home capacitor is 5〇 and the flyback active buffer circuit 201131952 is at the low level of the external signal. When the digital signal is used, the main switch 26 will be in an off state. At this time, the clamp capacitor 50 in the clamp circuit 38 sequentially stores the energy supplied from the input voltage h through the first inductor 28 and the clamp diode 48. The control main switch 26 operates in a zero voltage transition state (ZVT); on the other hand, the flyback active buffer circuit 40 also 'clamps a potential during the off period of the main switch 26 to transmit energy through the main diode 36 to the output load. , successfully complete the boost converter off-state transition. When the external signal is a high-level digital signal, the main switch 26 will be in an on state, and the second inductor 32 and the second leakage inductance 34 limit the reverse return current of the main diode 36 at the turn-on instant to control the main switch. 26 operates at zero current transition (ZCT). During turn-on, the auxiliary switch 56 is also synchronously enabled to extract energy from the clamp capacitor 5 , and store it to the magnetizing inductance 52, thereby creating the opportunity for zero voltage transition switching in the next cycle. The flyback active buffer circuit 40 of the present invention operates in a non-reading conduction mode (DCM), the main purpose of which is to avoid the generation of high voltage and large current stress on the switch. The flyback active buffer circuit 40 further includes an auxiliary switch 56, a second N-type gold-oxygen half field effect transistor (hereinafter also referred to by reference numeral 56), and a source connected to the first n-type gold-oxygen half field effect transistor 26 The source, the clamp capacitor 50, the load capacitor 44 and the load resistor 46, the gate receives a digital signal 'to control the switching state of the auxiliary switch 56, and the pole is connected to the primary side of a transformer 54, and the primary side is In parallel with a magnetizing inductance 52, one end of the magnetizing inductance 52 is simultaneously connected to the negative pole of the clamping diode 48 and the clamping capacitor 5〇, and receives energy from the clamping capacitor 5〇 when the auxiliary switch 56 is turned on, and stores it to Magnetizing inductance 52. The transformer 54 further has a secondary side, which is connected to the load capacitor 44 through the flyback output diode 60 and the diode 42 in sequence, and is connected to a snubber capacitor 58. One end of the snubber capacitor 58 is connected to the positive terminal of the second inductor 32 and the main diode 36, and the other end is connected to the second electrode 42. When the auxiliary switch 56 is turned off, the magnetizing inductance 52 transmits energy to the snubber capacitor 58. When the main switch is turned off, the currents of the first and second inductors 28 and 32 are equal, and the path of the diode 42 is made to make the snubber capacitor 58 Energy is transferred to the load. The capacitance value of the snubber capacitor 58 described above needs to be larger than the clamp capacitor 5 〇. The main purpose is to reduce the high voltage stress of the main switch 26 at the time of turn-off. In order to make the circuit diagram and the 201131952 waveform diagram to be described below, the voltages of the components in the circuit diagram and the representative symbols of the currents passing through the components are first introduced. The singularity passes through the current of the main switch 26 and the voltage across the customer 26; the y and ~ are respectively the current through the clamp capacitor 5 ,, and the load of the home capacitor 5 ( (4) X is the current through the auxiliary switch 56 With the auxiliary switch Qiu's voltage across, ~' and ' respectively' are the current through the magnetizing inductance 52, and the voltage across the exciting inductor 52; W is the current through the return-jump output diode 6〇; ^ is through the pole The current 'k' of the body 42 is the current through the snubber capacitor 58, and the snubber 58 is the electric current; L is the current through the first inductor 28; l is the current through the second inductor 32 ' ^ " For the current, the current of the main diode 36; ^ is the voltage signal for controlling the switch of the main switch 26; 〃 (7) is the signal of the state of __ off 56; / 〇 and 〇 are respectively through the load power jt And the current of 46, and the voltage across the load resistor 46. Please refer to Figure 14 below. The timing of the circuit can be divided into ten modes. The action of each mode is analyzed as follows: Mode one, ie to S t<t1: the digital signal of the high level before the time t〇, the main The switch 26 is in a state of maintaining conduction. When the time is equal to t〇, 匕 is the low-level digit, the number 'main switch 26 starts to cut off, L is charged to the register capacitor 5〇, and is always charged to the clamp capacitor 50 red. The electric material is at 4 φ*, the partial current continues to charge the home capacitor 50, and the rest flows through the second inductor 32. The relationship between the clamp capacitor 50 and the snubber capacitor 58 is in series. Mode 2, that is, h S t<t2: when the time is equal to b, the partial L changes to the second leakage inductance 34, the second inductance 32, the snubber capacitor 58, the diode 42, the load capacitance 44, and the first drain. ^ 30, the path of the first inductor 28, and the second inductor 32, the buffer capacitor Qiu and the clamp current 50 resonate, the snubber capacitor 58 begins to release energy to the output load (during mode 2, the snubber capacitor 58 energy is not completely released End); at h, G = L, ~ and Ve reach the maximum. In addition, between time to and t2, the temperature rises slowly, and the main switch 26 has been switched to a compression state (ZVT). Mode 3, t2 s t < t3: In this mode, the snubber capacitor 58 continues to release energy to the output load, and the crossover of the main pay 26 falls to the output load potential. 7 201131952 Mode 4, ie b $ t<t4: The energy of the snubber capacitor 58 has been released, l changes the path of the main diode 36, and the voltage across the main switch 26 is equal to the output negative, which acts as a general liter. The off-state mode of the voltage converter. Mode 5, that is, U S t<ts: When time is equal to U, both L and 匕(7) are high-level digital signals to activate main switch 26 and auxiliary switch 56. In this mode, & slowly rises to achieve zero current transition (ZCT) switching, L will slowly drop to zero; at this time, the magnetizing inductance 52 receives energy from the clamping capacitor 50, and stores it. During the receiving process, the clamp capacitor 50 and the magnetizing inductance 52 resonate. Mode six, ts St < tK In this mode, the main diode 36 reversely recovers the current center, and this current is effectively limited by the second inductance 32 and the second leakage inductance 34. Mode 7' is t6 $ t < t7: Since the energy in the 5 bit capacitor 5G is not transferred to the magnetizing inductance 52, the mode side continues to transfer the energy in the clamping capacitor 5Q to the excitation mode VIII'. $ t < te: When the time point is equal to h, the energy in the clamp capacitor 5 被 is exhausted. In order to ensure that the borrowing capacitor 50 is zero potential, the time of the driving signal is deliberately referred to in the control strategy to be slightly larger than the time of the tank capacitor 5 〇 discharge, the purpose of which is to create a zero-voltage transition opportunity for the next cycle to the main switch. 26. Mode IX' is te S t < t9: When time is equal, % is a low level digital signal 'turns off auxiliary switch 56. At this time, the transformer 54 transfers the energy stored in the exciting inductance 52 to the capacitor 58. In the meantime, the ship _ 52 Wei thief Rong 58 has a vibration phenomenon. = ten' is t9 $ t $ t. · When the time is equal, stored in the magnetizing inductance 52 = the amount has been completely transferred to the snubber capacitor 58, the potential of the snubber capacitor 58 will also be clamped to the next - period time t" to this, - cycle switching The operation ends. Can read the first, 13 and 15 'from the waveform diagram 'when the main switch 26 turns to the plum', the second inductor 32 can limit the reverse return current of the main diode 36, so that (slow* ' There is no current spike, and the fresh-spot is a hard-switching abnormal noise waveform to achieve zero-current transition flexible switching, thereby reducing power loss and improving conversion efficiency. 201131952 *Luxury also refers to Figure 13 and Figure 16. As can be seen from the waveform diagram, when the main switch 26 is turned off, the bit circuit 38 can clamp and store the energy provided by the input voltage, and the flyback active buffer circuit 40 can reduce the v* stress, causing the 4 to rise slowly, and there is no Voltage spikes and the like are hard switching abnormal noise waveforms to achieve zero voltage transition flexible switching, thereby reducing power loss and improving conversion efficiency. In summary, the present invention is coupled with a coupled inductor and a flyback Master The snubber circuit is integrated to achieve a cost-reducing and zero-current flexible switching. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the implementation of the present invention. The changes, modifications, and modifications of the shapes, structures, special characteristics, and spirits described in Fan Yuan should be included in the patent application field of the present invention. [Simplified description of the drawings] Figure 1 shows the boost conversion of the prior art. The circuit diagram of the device is shown in Fig. 2. The waveform diagram of the circuit of Fig. 1 when the main switch is turned on. Fig. 3 is the waveform diagram of the circuit of Fig. 1 when the main switch is turned off. Circuit diagram of a technology-integrated passive buffer boost converter. Figure 5 is a waveform diagram of the circuit of Figure 4 when the main switch is turned on. * Figure 6 shows the circuit of Figure 4 in the main switch. The waveform diagram of the state at the end of the state. Fig. 7 is a circuit diagram of the boost converter of the prior art integrated buck active buffer. Fig. 8 is a waveform diagram of the circuit of Fig. 7 when the main switch is turned on. Figure 9 is the first Figure 7 is a waveform diagram of the main switch when the main switch is turned off. Fig. 10 is a circuit diagram of the boost converter of the prior art integrated boost type active buffer. Fig. 11 is the circuit of Fig. 10 The waveform diagram of the switch when the switch is turned on. Fig. 12 is the waveform diagram of the circuit of Fig. 10 when the main switch is turned on. 9 201131952 Fig. 13 is a schematic circuit diagram of the device of the present invention. Figure 15 is a waveform diagram of the present invention when the main switch is turned on. Fig. 16 is a waveform diagram of the main switch when the main switch is turned off. [Main component symbol description] 10 main inductance 14 main diode 18 load resistor 22 step-down active buffer 26 main switch 30 first leakage inductance 34 second leakage inductance 38 clamp circuit 42 diode 46 load resistance 50 clamp capacitance 54 transformer 58 buffer capacitor 12 main Switch 16 load capacitor 20 passive buffer 24 boost active buffer 28 first inductor 32 second inductor 36 main diode 40 flyback active buffer circuit 44 load capacitor 48 clamp diode 52 excitation inductor 56 auxiliary switch 60 flyback output two Body