201122643 AU0905008 32092twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於—麵示面板及其配向方法與操作 方法，且特別是有關於一種採用聚合物穩定配向（pl〇ymer Stabilized Alignment，PSA)技術之顯示面板及其配向方法 與操作方法。 【先前技術】 在顯示器的發展上，隨著光電技術與半導體製造技術 的進步，具有高晝質、空間利用效率佳、低消耗功率、無 輻射等優越特性的液晶顯示器已逐漸成為市場之主流。 液晶顯示器包括了背光模組以及液晶顯示面板，而傳 統液晶顯示面板是由兩基板以及填於兩基板之間的一液晶 層所構成。一般而言，在液晶顯示面板的製造過程中，都 會在兩基板上形成配向膜，以使液晶分子具有特定的排 列。習知形成配向膜的方法是先塗佈配向材料之後，再對 配向材料進行配向製程。而配向製程可以分成接觸式配向 製程以及非接觸式配向製程。雖然非接觸式配向製程可解 決接觸式磨擦配向產生的靜電問題及粒子(particle)污染等 問題’但是其往往會發生配向表面之錨定能不足的問題。 而如果配向表面之錨定能不足，將往往導致液晶顯示面板 的顯示品質不佳。 為解決上述問題，目前已提出一種聚合物穩定配向 (Ploymer Stabilized Alignment, PSA)的技術。此技術乃 201122643 AU0905008 32092twf.doc/n 是在液晶材料中摻入適當濃度的單體化合物（m〇n〇mer ) 並且震盪均勻。接著’將混合後的液晶材料置於加熱器上 加溫到達等向性（Isotropy)狀態。然後’當液晶混合物降 溫25°C室溫時液晶混合物會回到向列型（nematic )狀雖。 此時將液晶混合物注入至液晶盒並施予電壓。當施力。恭I 使液晶分子排列穩定時，則使用紫外光或加熱的方式讓單 體化合物進行聚合反應以成聚合物層，由此達到穩定配向 的目的。 一般來說，在PSA的液晶顯示面板中，會在書素、纟士構 的晝素電極中形成配向狹縫，以使液晶分子產生特定的配 向方向。而晝素電極中的配向狹縫越多雖可以越加精確控 制液晶分子的配向，但配向狹缝所佔面積越多也同時會增 加頒示不均勻（mura)現象，這是主要因為配向狹縫之微影 娃刻程序造成狹缝寬度不一致所導致。更詳細來說，在配 向狹缝的微影蝕刻程序中，在曝光裝置的光學鏡組之間的 交界處往往會因為該處之曝光條件與非交界處之曝光條件 不完全一致，因此導致該處的狹缝寬度與其他狹縫寬度不 一致。因而造成顯示面板在這兩處的亮度不同，而導致顯 示不均勻（mura)問題。 【發明内容】 本發明提供一種顯示面板以及可用於此顯示面板之 彩色濾光基板，其可以減少傳統使訂SA技術之顯示面板 Q於旦素電極中所形成之配向狹缝寬度不—致而導致顯示 201122643 AU0905008 32092twf.doc/n 不均勻的問題。 本發明提供一種顯示面板的配向方法，其有別於傳統 的PSA配向方法。 本發明提供一種顯示面板的操作方法，其相較於傳統 使用PSA技術之顯示面板具有較佳的穿透率。 本發明提出一種顯示面板，其包括第一基板、第二基 板以及液晶層。第一基板包括設置有多個晝素結構。第二201122643 AU0905008 32092twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a face panel, an alignment method and an operation method thereof, and in particular to a polymer stabilized alignment (pl〇 Ymer Stabilized Alignment (PSA) technology display panel and its alignment method and operation method. [Prior Art] In the development of displays, with the advancement of optoelectronic technology and semiconductor manufacturing technology, liquid crystal displays with superior properties such as high quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream in the market. The liquid crystal display includes a backlight module and a liquid crystal display panel, and the conventional liquid crystal display panel is composed of two substrates and a liquid crystal layer filled between the two substrates. In general, in the manufacturing process of a liquid crystal display panel, an alignment film is formed on both substrates to have a specific arrangement of liquid crystal molecules. It is conventional to form an alignment film by first applying an alignment material and then aligning the alignment material. The alignment process can be divided into a contact alignment process and a non-contact alignment process. Although the non-contact alignment process solves the problem of electrostatic problems caused by contact friction alignment and particle contamination, it often suffers from insufficient anchoring energy of the alignment surface. However, if the anchoring energy of the alignment surface is insufficient, the display quality of the liquid crystal display panel tends to be poor. In order to solve the above problems, a technique of Ployd Stabilized Alignment (PSA) has been proposed. This technique is 201122643 AU0905008 32092twf.doc/n is to incorporate a suitable concentration of monomer compound (m〇n〇mer) in the liquid crystal material and to oscillate evenly. Next, the mixed liquid crystal material is placed on a heater and heated to reach an isotropic state. Then, when the liquid crystal mixture is cooled at room temperature of 25 ° C, the liquid crystal mixture returns to a nematic shape. At this time, the liquid crystal mixture was injected into the liquid crystal cell and a voltage was applied. When exerting force. In order to stabilize the alignment of the liquid crystal molecules, the monomer compound is polymerized by ultraviolet light or heating to form a polymer layer, thereby achieving the purpose of stable alignment. Generally, in the liquid crystal display panel of the PSA, alignment slits are formed in the pixel electrodes of the book and the gentleman to form a specific alignment direction of the liquid crystal molecules. The more the alignment slits in the halogen electrode, the more precisely the alignment of the liquid crystal molecules can be controlled. However, the more the area occupied by the alignment slits, the more the mura phenomenon is introduced, which is mainly due to the narrow alignment. The lithography process of the seam causes the slit width to be inconsistent. In more detail, in the lithography etching process of the alignment slit, the boundary between the optical lens groups of the exposure device tends to be inconsistent because the exposure conditions at the place and the exposure conditions at the non-junction are not completely identical, thus causing the The slit width at the point is inconsistent with the width of the other slits. As a result, the brightness of the display panel at these two places is different, resulting in display of mura problems. SUMMARY OF THE INVENTION The present invention provides a display panel and a color filter substrate that can be used in the display panel, which can reduce the width of the alignment slit formed by the display panel Q of the conventional SA technology in the dendrite electrode. Caused by the 201122643 AU0905008 32092twf.doc/n uneven problem. The present invention provides an alignment method of a display panel which is different from the conventional PSA alignment method. The present invention provides a method of operating a display panel which has a better transmittance than a conventional display panel using PSA technology. The present invention provides a display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate includes a plurality of halogen structures. second
基板位於第一基板的對向，其中第二基板包括設置有電極 層以及位於電極層上方之圖案化電極層，且電極層與圖荦 化電極層之間彼此電性絕緣。液晶層位於第一基板與第二 基板之間。 本發明提出一種顯示面板之配向方法，其首先提供如 上所述之顯示面板。接著，對第二基板之瞧化電極層施 予配向電壓，並且使第二基板之電極層處於浮置狀態，以 使液晶層之液晶具有預傾角。 本發明提出一種顯示面板之操作方法，其首先提供如 上所述之顯示面板。接著，對第二基板之電極層施予共同 電壓，並且使第二基板之圖案化f極層處於浮置狀態^ 来#本出—卿色濾光基板，其包括基板；彩色遽 3雷:ί 電極層，位於彩色遽光層上;以及圖 :=二位於電極層上，其中圖案化電極層與電極層 之間被此電性絕緣。 祕=於上逑’由於本發明在顯示面板ϋ板上設 電極層以及電極圖奉；，+ α a且电極層與電極圖案層之間彼 201122643 ATJ0905008 32092Uvf.doc/n 電性絕緣。當於進行PSA技術的熟化程序時，同時對圖案 化電極層施予配向電壓並且使電極層處於浮置狀態，如此 便可以達到對液晶產生配向的效果。而於進行顯示面板之 操作程序時，是對電極層施予共同電壓並且使圖案化電極二 層處於浮置狀態便可以對液晶進行正常的顯示操作。而此 種面板設計及所搭配的配向方法與操作方法不但可以使液 晶面板達到與傳統使用PSA技術之顯示面板相同的配向 效果且不影響其正常的顯示操作，且還可提高顯示面板的 穿透率並且避免傳統使用PSA計數之顯示面板中因於晝 素電極中形成之配向狹缝會有寬度不一致而導致顯示不均 勻的問題。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 圖1是根據本發明一實施例之顯示面板的剖面示意 圖。請先參照圖1，本實施例之顯示面板包括第一基板 100、第二基板110以及位於第一基板100與第二基板110 之間的液晶層150。 第一基板100之材質可為玻璃、石英、有機聚合物或 是金屬等等。第一基板1〇〇上包括設置有晝素陣列層102, 所述畫素陣列層1〇2如圖2A所示，其是由多個畫素結構 U1所構成’每一畫素結構U1之佈局如圖3所示。更詳細 而言，請同時參照圖1、圖2A及圖3，晝素陣列層102之 201122643 AU0905008 32092t\vf.d〇c/n =-晝素結構ui包括掃描線队以及資料線沉、主動元 ^。、儲存電容電極線2〇2、上電極圖案綱以及晝素電 及資料線见:位於第一基板上刚。掃描線 ，、貝枓線DL之延伸方向不相同。此外，掃描線化 及貧料線DL是位於不相同的膜層，且 層。掃描線SL·與資料線DL主|田才j人,、、巴緣 的驅動訊號。 时傳遞輯此晝素結構The substrate is located opposite to the first substrate, wherein the second substrate comprises an electrode layer disposed thereon and a patterned electrode layer above the electrode layer, and the electrode layer and the patterned electrode layer are electrically insulated from each other. The liquid crystal layer is located between the first substrate and the second substrate. The present invention provides a method of aligning a display panel, which first provides a display panel as described above. Next, an alignment voltage is applied to the deuterated electrode layer of the second substrate, and the electrode layer of the second substrate is placed in a floating state so that the liquid crystal of the liquid crystal layer has a pretilt angle. The present invention provides a method of operating a display panel that first provides a display panel as described above. Then, a common voltage is applied to the electrode layer of the second substrate, and the patterned f-electrode layer of the second substrate is placed in a floating state, and the color filter substrate includes a substrate; ί an electrode layer on the color light-emitting layer; and a picture: = two on the electrode layer, wherein the patterned electrode layer and the electrode layer are electrically insulated from each other. The invention is based on the present invention. The electrode layer and the electrode pattern are arranged on the display panel of the present invention; + α a and the electrode layer and the electrode pattern layer are electrically insulated. 201122643 ATJ0905008 32092Uvf.doc/n Electrical insulation. When the aging process of the PSA technique is performed, the alignment voltage is applied to the patterned electrode layer at the same time and the electrode layer is placed in a floating state, so that the effect of aligning the liquid crystal can be achieved. When the operation procedure of the display panel is performed, the common display voltage is applied to the electrode layer, and the patterned electrode layer is placed in a floating state to perform normal display operation on the liquid crystal. The panel design and the matching alignment method and operation method can not only make the liquid crystal panel achieve the same alignment effect as the conventional PSA technology display panel, but also affect the normal display operation, and can also improve the penetration of the display panel. The rate and avoidance of the display unevenness caused by the inconsistency in the width of the alignment slit formed in the halogen electrode in the display panel conventionally using the PSA count may be avoided. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention. Referring to FIG. 1 , the display panel of the present embodiment includes a first substrate 100 , a second substrate 110 , and a liquid crystal layer 150 between the first substrate 100 and the second substrate 110 . The material of the first substrate 100 may be glass, quartz, organic polymer or metal or the like. The first substrate 1 includes a pixel array layer 102, and the pixel array layer 1〇2 is formed by a plurality of pixel structures U1, and each pixel structure U1 is formed. The layout is shown in Figure 3. In more detail, please refer to FIG. 1 , FIG. 2A and FIG. 3 simultaneously, the 201122643 AU0905008 32092t\vf.d〇c/n of the halogen array layer 102 includes a scanning line team and a data line sinking and active. Yuan ^. The storage capacitor electrode line 2〇2, the upper electrode pattern and the halogen element and the data line are as follows: located on the first substrate. The scanning line and the extension line of the bellows line DL are different. Further, the scan line and the lean line DL are layers which are located at different layers, and layers. The scanning line SL· and the data line DL main | Tian Cai j,,, and the edge of the driving signal. Passing this morpheme structure
主動兀件T是與掃描、線SL以及資料線DL電性連接。 動元件T例如是薄膜電晶體，其包括閘極G、通 ^層CH、源極S以及没極D。閘極G與掃描線队電性連 接’源極s與資料線DL電性連接，通道層ch位於間極 之上方並且位於源極S姐極D的下方。本實施例之 兀件T是以底部閘極㈣膜電晶體為例來綱，但本發明 不限於此。在其他的實施财，主動元件7也可以是 閘極型薄膜電晶體。 、 儲存電容電極線2〇2是位於第—基 f極線202的延伸方向與掃描線SL平行。在本 中’儲存電容電極線202可以與掃赌％同時形成，因 此儲存電容電極線搬與掃描線％屬於同—膜層 本發明之實施例，各書素結構中@ ' 連接至共同電壓。—#中料谷電極線搬是電性 ，上電極圖案204位於儲存電容電極線2〇2的上方。更 坪細而言，上電極圖案204與電容電極線2()2之間兩者重 201122643 AU0905008 32092twf.doc/n 宜δ又置，且兩者之間夾有絕緣層（未繪示）用以使上電極圖 案204與儲存電容電極線2〇2兩者電性隔離。在本實施例 中，上電極圖案2〇4是於形成資料線DL時同時形成，因 此上電極圖:案204與資料線DI^是屬於同一膜層。 —根據本發明之實施例，在此畫素結構m巾，更包括 遮敝線205。遮蔽線205與資料線DL平行設置，且位於 晝素結構ui的中間位置。在本實施例中，遮蔽線2〇5是 與資料線DL以及上電極圖案綱同時形成，因此遮蔽線 205可以直接與上電極圖案綱連接在一起。然本發明不 限於此，在另—實施例中，遮蔽線205也可以不與上電極 。值得一提的是’遮蔽線205主要的作用為 η 上方之液晶分子的傾倒而產生的顯示現 看到。因此’設計遮蔽線2G5可以使液晶顯 =面板具有較佳的顯示品質，但本發明不限制—定要使用 H…f言之’在其他的實施例中，亦可以省略遮蔽線 205的製作。 晝素生連接。在本實施例中’ t々金主Γ 動件之没極〇電性連接。更詳細而 ;括4古:極p與主動元件τ之汲極D兩者重疊之處更 ；^。+觸1^ C1 ’以使畫素電極p纽極D電性連 Γ素電極P覆蓋住電容電極、線202以及上電極 /去洽 s素電拖P與上電極圖案204之間夹有絕緣層 ’在晝素電極P與上電極圖案204之之間 成有接觸自C2’以使晝素電極P與上電極圖案204電性 201122643 AU0905008 32092twf.doc/n 連接。換言之，藉由接觸窗C2可使晝素電極p與上電極 圖案204共電位。另外，藉由上電極圖案綱與電容電極 線202之間的電性轉合關係便可以將晝素電極p之電荷儲 存於此處如此便可:構成晝素結構U1之儲存電容:器。值 得-提的是，在晝素結構m之晝素電極p上未設置有配 向圖案（配向凸起或配向狹缝）。 请再參照圖1 ’第二基板11〇之材質可為玻璃、石英 • 或有機聚合物等等。第二基板no上包括設置有電極層m 以及圖案化電極層116，其中電極層112與圖案化電極層 116彼此电性絕緣。在本實施例中，電極層η]為透明導 電層:其材質包括金屬氧化物，例如是銦錫氧化物或者是 姻鋅氧化物。電極層112是全面地覆蓋於第二基板ιι〇上。 ^外’圖案化電極層116亦為透明導電材質，其可為金屬 氧化物，例如是銦錫氧化物或者是銦辞氧化物。由於圖案 化電極層116是圖案化膜層，因此並非全面地覆蓋於第二 基板11〇上。在本實施例中，在電極層112與圖案化電極 層116之間更包括設置絕緣層114，其用以使電極層m 與圖案化電極層116之間電性絕緣。 . 、、根據本發明之一較佳實施例，第二基板11〇上亦可區 分為多個單元區域U2，如圖2B所示，其中每一單元區域 ' U2是對應第一基板10〇上之晝素陣列層102的一個晝素結 構U1 „又置。更詳細來說，第二基板11〇具有透光區302 以及遮光區304，遮光區304圍繞在透光區3〇2的周圍， 因此每一透光區302又可稱為單元區域U2。 201122643 /\υυ，υ:>008 32092twf.doc/n 在本實施例中，位於第二基板上之圖案化電極層116 的圖案是對應一個單元區域U2來設計。圖4為根據本發 明實施例之在一個單元區域U2内之圖案化電極層116的 上視圖，圖5為根據本發明實施例之在一個單元區域。U2 内之電極層112的上視圖。請同時參照圖4及圖5，圖5 所繪示之電極層112為完整且沒有圖案化的電極層，而圖 4所繪示之圖案化電極層116具有許多狹缝圖案形成在其 中。更詳細而言，圖案化電極層116具有主狹缝310以及 與主狹縫310連接之多個分支狹縫312。而且分支狹缝312 是自主狹縫310往四個方向延伸。換言之，分支狹缝312 是由主狹缝310往四周延伸至單元區域U2的邊緣處。 此外’在本實施例中，所述主狹缝310包括水平延伸 狹缝310a以及垂直延伸狹缝310b。在此，圖案化電極層 116中之水平延伸狹縫310a是與第一基板100上之晝素結 構U1内的電容電極線202(如圖3所示）重疊設置。此外， 圖案化電極層116中之垂直延伸狹缝310b是與第一基板 100上之晝素結構U1内的遮蔽線205(如圖3所示）重疊設 置。因此水平延伸狹縫310a與垂直延伸狹缝310b在單元 區域U2内大致成十字形。 請再回到圖1，為於第一基板100與第二基板110 之間的液晶層150包括液晶分子。由於本實施例之顯示面 板為使用PSA技術之顯示面板，因此在液晶層150中除了 液晶分子之外，還包括單體化合物。換言之，在此顯示面 板尚未進行單體化合物之熟化程序時，液晶層150中包含 201122643 AUUyU!>008 32092twf.doc/n 有液晶分子以財體化合物。#此顯示面板於進行單體化 合物之齡程序時’單體化合物會進行聚合反應而於晝素 陣列層102以及圖案化電極層U6之表面形成聚合物薄 膜’因此當此齡面板树行單體化合物之熟化程序之 後，液晶層150主要為液晶分子。 在上达之貫施例中，第二基板11〇上主要包括電極層 112以及圖案化電極層116。然，根據本發明之另一實施 例’第二基板110上可更包括設置有彩色渡光層12〇，如 圖f所示’彩色濾光層120包括紅、綠、藍色遽光圖案(未 繪不）’其設置於圖2B所示之透光區3〇2中。此外，另外， 彩色濾光層120還可包括遮光圖案層（未繪示），其又可稱 為黑矩陣，其設置於紅、綠、藍色濾光圖案之間，也就是 設置在圖2B所示之遮光區304中。 承上所述，在圖6之實施例中，第二基板u〇以及形 成於其上之膜層即構成所謂的彩色滤光基板16〇，其包括 基板110、彩色遽光層120、電極層112以及圖案化電極層 116 °彩色濾光層120位於基板11〇上。電極層U2位於彩 色遠光層120上，圖案化電極層116位於電極層η]上， 其中圖案化電極層116與電極層112之間彼此電性絕緣。 在較佳實施例中，圖案化電極層116與電極層112之間具 有絕緣層114,以使圖案化電極層Π6與電極層112彼此 電性絕緣。 曰 在圖6之貫施例中’彩色滤光層120是設置於第二基 板11〇以及電極層112之間。然而，本發明不限於此。根 11 201122643 AUUWb008 32092twf.doc/n 據本發明之其他實施例’上述之彩色濾光層也可以設置在 第一基板100之晝素陣列層102中，以使晝素陣列層102 構成所謂的彩色濾光於陣列上之結構(color fllter on array, COA)。。 , 圖7為根據本發明實施例之顯示面板的配向方法的示 意圖。圖7之實施例是以圖1之實施例所述之顯示面板為 例來說明’但本發明之配向方法不限於僅能用於圖1所示 之顯不面板，其也可以應用在其他實施例之顯示面板中， 例如是圖6所示之實施例之顯示面板。請參照圖7，本實 施例之顯示面板的配向方法包括對第二基板1 上之圖案 化電極層116施予一配向電壓Va，並且使第二基板11〇 上之電極層112處於浮置狀態，以使液晶層15〇中之液晶 分子具有預傾角。 更詳細而言，當於進行PSA技術之熟化程序(curing) % β’同時對第二基板110上之圖案化電極層116施予配向 電壓Va’並且使第二基板110上之電極層112處於浮置狀 態。在本實施例中，於對第二基板11()上之圖案化電極層 116施予配向電壓Va並且使第二基板11〇上之電極層112 處於浮置狀態的時候，更包括使第—基板1〇〇之晝素陣列 層102中的畫素電極接地。此時’液晶層15〇中的液晶分 子因為圖案化電極層116之配向電壓乂&的作用而產生預 疋的配向效果，且同時液晶層15〇中之單體化合物也會同 B寸進行聚合反應而开> 成聚合物薄膜。因此，當完成PSA技 術之熟化程序之後，便可以對液晶層15〇中之液晶分子達 12 201122643The active component T is electrically connected to the scan, the line SL, and the data line DL. The movable element T is, for example, a thin film transistor including a gate G, a pass layer CH, a source S, and a gate D. The gate G is electrically connected to the scan line team. The source s is electrically connected to the data line DL. The channel layer ch is located above the interpole and below the source S. The element T of the present embodiment is exemplified by a bottom gate (four) film transistor, but the present invention is not limited thereto. In other implementations, the active component 7 can also be a gate-type thin film transistor. The storage capacitor electrode line 2〇2 is located in the extending direction of the first base f-pole line 202 and is parallel to the scanning line SL. In the present embodiment, the storage capacitor electrode line 202 can be formed at the same time as the gambling %, so that the storage capacitor electrode line and the scanning line % belong to the same film layer. In the embodiment of the present invention, @ ' is connected to the common voltage in each of the book structures. The #中谷 electrode line is electrically charged, and the upper electrode pattern 204 is located above the storage capacitor electrode line 2〇2. More specifically, between the upper electrode pattern 204 and the capacitor electrode line 2 () 2, the weight of the 201122643 AU0905008 32092twf.doc/n should be δ, and an insulating layer (not shown) is interposed therebetween. The upper electrode pattern 204 and the storage capacitor electrode line 2〇2 are electrically isolated. In the present embodiment, the upper electrode pattern 2〇4 is formed simultaneously when the data line DL is formed, so the upper electrode pattern: the case 204 and the data line DI^ belong to the same film layer. - In accordance with an embodiment of the invention, the pixel structure m is further comprised of a concealer line 205. The mask line 205 is disposed in parallel with the data line DL and is located at an intermediate position of the pixel structure ui. In the present embodiment, the shield line 2〇5 is formed simultaneously with the data line DL and the upper electrode pattern, so that the shield line 205 can be directly connected to the upper electrode pattern. However, the present invention is not limited thereto, and in another embodiment, the shield line 205 may not be connected to the upper electrode. It is worth mentioning that the main function of the shield line 205 is that the display of the liquid crystal molecules above the η is seen. Therefore, the design of the shielding line 2G5 can make the liquid crystal display panel have better display quality, but the present invention is not limited to the use of H...f. In other embodiments, the fabrication of the shielding line 205 can be omitted. Susu is connected. In this embodiment, the main thrust of the metal element is electrically connected. More in detail; including 4 ancient: the pole p and the active element τ the pole D both overlap more; ^. +Touch 1^ C1 ' to make the pixel electrode p-pole D electric galvanic electrode P cover the capacitor electrode, the line 202 and the upper electrode/de-supplemental electric drag P and the upper electrode pattern 204 are insulated The layer 'haves contact between the halogen electrode P and the upper electrode pattern 204 from C2' to connect the halogen electrode P with the upper electrode pattern 204 electrical 201122643 AU0905008 32092twf.doc/n. In other words, the pixel electrode p can be brought to a common potential with the upper electrode pattern 204 by the contact window C2. In addition, the charge of the pixel electrode p can be stored here by the electrical coupling relationship between the upper electrode pattern and the capacitor electrode line 202: the storage capacitor of the pixel structure U1 is formed. It is to be noted that an alignment pattern (orientation protrusion or alignment slit) is not provided on the halogen electrode p of the halogen structure m. Referring to FIG. 1 again, the material of the second substrate 11 can be glass, quartz, or an organic polymer or the like. The second substrate no includes an electrode layer m and a patterned electrode layer 116, wherein the electrode layer 112 and the patterned electrode layer 116 are electrically insulated from each other. In the present embodiment, the electrode layer η] is a transparent conductive layer: the material thereof includes a metal oxide such as indium tin oxide or zinc oxide. The electrode layer 112 is entirely covered on the second substrate. The outer patterned electrode layer 116 is also a transparent conductive material which may be a metal oxide such as indium tin oxide or indium oxide. Since the patterned electrode layer 116 is a patterned film layer, it is not completely covered on the second substrate 11A. In the present embodiment, an insulating layer 114 is further disposed between the electrode layer 112 and the patterned electrode layer 116 for electrically insulating the electrode layer m from the patterned electrode layer 116. According to a preferred embodiment of the present invention, the second substrate 11 can be further divided into a plurality of unit regions U2, as shown in FIG. 2B, wherein each of the unit regions 'U2 is corresponding to the first substrate 10 A halogen structure U1 of the halogen array layer 102 is further disposed. In more detail, the second substrate 11 has a light transmitting region 302 and a light blocking region 304, and the light shielding region 304 surrounds the light transmitting region 3〇2. Therefore, each of the light transmitting regions 302 may be referred to as a unit region U2. 201122643 / \υυ, υ: > 008 32092twf.doc / n In this embodiment, the pattern of the patterned electrode layer 116 on the second substrate is Designed corresponding to one unit area U2. Fig. 4 is a top view of a patterned electrode layer 116 in a unit area U2 according to an embodiment of the invention, and Fig. 5 is a unit area in U2 according to an embodiment of the invention. The top view of the electrode layer 112. Please refer to FIG. 4 and FIG. 5 simultaneously. The electrode layer 112 illustrated in FIG. 5 is a complete and unpatterned electrode layer, and the patterned electrode layer 116 illustrated in FIG. A slit pattern is formed therein. In more detail, the patterned electrode layer 116 has The main slit 310 and the plurality of branch slits 312 connected to the main slit 310. The branch slits 312 extend in four directions from the autonomous slit 310. In other words, the branch slits 312 extend from the main slit 310 to the periphery. To the edge of the unit area U2. Further, in the present embodiment, the main slit 310 includes a horizontally extending slit 310a and a vertically extending slit 310b. Here, the horizontally extending slit 310a in the patterned electrode layer 116 The capacitor electrode line 202 (shown in FIG. 3) in the halogen structure U1 on the first substrate 100 is disposed to overlap. Further, the vertically extending slit 310b in the patterned electrode layer 116 is on the first substrate 100. The shielding lines 205 (shown in FIG. 3) in the halogen structure U1 are overlapped. Therefore, the horizontally extending slits 310a and the vertically extending slits 310b are substantially cross-shaped in the unit area U2. Please return to FIG. The liquid crystal layer 150 between the first substrate 100 and the second substrate 110 includes liquid crystal molecules. Since the display panel of the present embodiment is a display panel using PSA technology, the liquid crystal layer 150 includes a monomer in addition to the liquid crystal molecules. Compound. In other words When the display panel has not been subjected to the aging process of the monomer compound, the liquid crystal layer 150 contains 201122643 AUUyU!>008 32092twf.doc/n having a liquid crystal molecule as a compound. #This display panel is used to perform the monomer compound age program. When the monomer compound undergoes polymerization to form a polymer film on the surface of the halogen array layer 102 and the patterned electrode layer U6, the liquid crystal layer 150 is mainly liquid crystal after the ageing process of the panel metal compound of the age of the panel. molecule. In the application of the upper substrate, the second substrate 11 includes mainly an electrode layer 112 and a patterned electrode layer 116. However, according to another embodiment of the present invention, the second substrate 110 may further include a color light-passing layer 12, as shown in FIG. f, the color filter layer 120 includes red, green, and blue phosphor patterns. It is not shown. It is disposed in the light-transmitting region 3〇2 shown in FIG. 2B. In addition, the color filter layer 120 may further include a light shielding pattern layer (not shown), which may also be referred to as a black matrix, which is disposed between the red, green, and blue filter patterns, that is, disposed in FIG. 2B. In the shaded area 304 shown. As described above, in the embodiment of FIG. 6, the second substrate u〇 and the film layer formed thereon constitute a so-called color filter substrate 16A, which includes the substrate 110, the color light-emitting layer 120, and the electrode layer. 112 and patterned electrode layer 116 ° color filter layer 120 is located on the substrate 11 。. The electrode layer U2 is located on the color high beam layer 120, and the patterned electrode layer 116 is located on the electrode layer η], wherein the patterned electrode layer 116 and the electrode layer 112 are electrically insulated from each other. In the preferred embodiment, an insulating layer 114 is disposed between the patterned electrode layer 116 and the electrode layer 112 to electrically insulate the patterned electrode layer Π6 from the electrode layer 112 from each other. ’ In the embodiment of Fig. 6, the color filter layer 120 is disposed between the second substrate 11A and the electrode layer 112. However, the invention is not limited thereto. Root 11 201122643 AUUWb008 32092twf.doc/n According to other embodiments of the present invention, the color filter layer described above may also be disposed in the pixel array layer 102 of the first substrate 100 such that the pixel array layer 102 constitutes a so-called color. Filtered on the structure (color fllter on array, COA). . Figure 7 is a schematic illustration of a method of aligning a display panel in accordance with an embodiment of the present invention. The embodiment of FIG. 7 is illustrated by taking the display panel of the embodiment of FIG. 1 as an example. However, the alignment method of the present invention is not limited to the display panel shown in FIG. 1, and can be applied to other implementations. In the display panel of the example, for example, the display panel of the embodiment shown in FIG. Referring to FIG. 7, the alignment method of the display panel of the present embodiment includes applying an alignment voltage Va to the patterned electrode layer 116 on the second substrate 1, and placing the electrode layer 112 on the second substrate 11 on the floating state. So that the liquid crystal molecules in the liquid crystal layer 15 have a pretilt angle. In more detail, when the curing process %SA' of the PSA technique is performed, the patterned electrode layer 116 on the second substrate 110 is applied with the alignment voltage Va' and the electrode layer 112 on the second substrate 110 is placed. Floating state. In this embodiment, when the alignment voltage Va is applied to the patterned electrode layer 116 on the second substrate 11 () and the electrode layer 112 on the second substrate 11 is in a floating state, the first step is further included. The pixel electrode in the pixel array layer 102 of the substrate 1 is grounded. At this time, the liquid crystal molecules in the liquid crystal layer 15 are pre-twisted by the action of the alignment voltage 图案& of the patterned electrode layer 116, and at the same time, the monomer compounds in the liquid crystal layer 15 are also polymerized with B. The reaction is opened to form a polymer film. Therefore, when the curing process of the PSA technology is completed, the liquid crystal molecules in the liquid crystal layer 15 can be reached 12 201122643
Auuyua008 32092twf.doc/n 到預定的配向效果。 圖8A為根據本發明實施例之顯示面板的配向方法的 . 不意圖。圖8A之實施例是以圖1之實施例所述之顯示面 •，板為例來說明’但本發明之配向方法不限於僅能用於圖i 所示之顯示面板，其也可以應用在其他實施例之顯示面板 中，例如是圖6所示之貫施例之顯示面板。請參照圖8A， 本實施例之顯示面板的操作方法包括對第二基板11()上之 電極層112施予共同電壓Vc’並且使第二基板11()上之圖 鲁 案化電極層116處於浮置狀態。在此時，第一基板100上 之晝素陣列層102中的各畫素結構將根據其驅動訊號的作 用而使各晝素結構上方的液晶層產生特定的扭轉行為’以 使顯示面板產生特定的影像顯示。 在本實施例之顯示面板中，雖然在電極層112上設置 有圖案化電極層116，但其在進行顯示操作時，主要是對 電極層112施予電壓。因此液晶層15〇中的液晶分子是根 據電極層116與晝素陣列層1〇2之間的電場而產生特定的 Φ 扭轉行為。換吕之，圖案化電極層H6不會影響顯示面板 之正常的顯示操作。另外，由於晝素陣列層1〇2中的晝素 . 中並未形成有任何配向圖案，因此，此顯示面板相較 於傳統使用PSA技術之顯示面板具有更佳的透光率（例如 - 可增加9%的透光率）。再者，由於晝素陣列層1〇2中的 畫素電極中並未形成有任何配向圖案，因此可以避免傳統 使用PSA技術之顯示面板中因於晝素電極中形成之配向 狹縫會有寬度不一致而導致顯示不均勻的問題。 13 201122643 AU〇y〇5〇08 32092twf.doc/n 圖8B為根據本發明一實施例之顯示面板的配向方法 的示意圖。圖8B之實施例是以圖i之實施例所述之顯干 面^為例來說明，但本發明之配向方法不限於僅能用於圖 所不之顯福板，其也可績.用在其他實施例中之顯示 面板二，圖6所示之實施例之顯示面板。請參照圖 8B ’本^例之顯示面板的操作方法包括對第二基板ιι〇 上之電極層112以及圖案化電極層116同時施予共同電麗 I·'士ί此時’第一基板1〇0上之晝素陣列層102中的各晝 =構將根據其驅動訊號的作用而使各晝素結構上方的液 ^曰產生特定的扭轉行為，以使顯示面板產生較的影像 顯示。 類似地，雖然在電極層112上設置有㈣化電極層 1但其在進行顯示操作時，是對電極層m及圖案化電 極層116同時施予電壓。因此液晶層150中的液晶分子是 根據電極層116/電極層112與晝素陣列層撤之間的電場 2生特定的扭轉行為。換言之，®案化電極層116不會 影β使顯示面板之正常的顯示操作。另外，由於晝素陣列 層1〇2中的晝素電極中並未形成有任何配向圖案，因此， 員不面板相較於傳統使用PSA技術之顯示面板具有更 1的透光率。再者，由於晝素陣列層102中的晝素電極中 ^未形成有任何配向圖案，因此可以避免傳統使用PSA技 術之顯不面板中因於畫素電極中形成之配向狹縫會有寬度 不—致而導致顯示不均勻的問題。 雖然本發明已以實施例揭露如上，然其並非用以限定 14 201122643 AU0905008 32092twf.d〇c/n 本::二所屬技術領域中具有通常知識者，在不脫離 ir :範_，當可作些許之更減潤飾，故本 X之保遵範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1疋根據本發明實施例之顯示面板的剖面示意圖。 圖2A疋圖1之畫素陣列層的上視示意圖。Auuyua008 32092twf.doc/n to the intended alignment effect. 8A is a view showing an alignment method of a display panel according to an embodiment of the present invention. The embodiment of FIG. 8A is illustrated by using the display surface of the embodiment of FIG. 1 as an example. However, the alignment method of the present invention is not limited to the display panel shown in FIG. i, and can also be applied to In the display panel of the other embodiment, for example, the display panel of the embodiment shown in FIG. 6 is used. Referring to FIG. 8A, the method for operating the display panel of the present embodiment includes applying a common voltage Vc' to the electrode layer 112 on the second substrate 11() and causing the patterned electrode layer 116 on the second substrate 11(). Is floating. At this time, each pixel structure in the pixel array layer 102 on the first substrate 100 will cause a specific twisting behavior of the liquid crystal layer above each of the pixel structures according to the action of the driving signal thereof to make the display panel specific. The image is displayed. In the display panel of the present embodiment, although the patterned electrode layer 116 is provided on the electrode layer 112, it is mainly applied to the electrode layer 112 when performing a display operation. Therefore, the liquid crystal molecules in the liquid crystal layer 15 are subjected to a specific Φ twisting behavior according to the electric field between the electrode layer 116 and the halogen array layer 1〇2. In the case of Lu, the patterned electrode layer H6 does not affect the normal display operation of the display panel. In addition, since no alignment pattern is formed in the halogen element in the pixel array layer 1〇2, the display panel has better light transmittance than the conventional display panel using PSA technology (for example, Increase the light transmittance by 9%). Furthermore, since no alignment pattern is formed in the pixel electrodes in the pixel array layer 1〇2, it is possible to avoid the width of the alignment slit formed in the pixel electrode in the conventional display panel using the PSA technology. Inconsistent results in uneven display. 13 201122643 AU〇y〇5〇08 32092twf.doc/n FIG. 8B is a schematic diagram of an alignment method of a display panel according to an embodiment of the present invention. The embodiment of FIG. 8B is exemplified by the dry surface described in the embodiment of FIG. i, but the alignment method of the present invention is not limited to the display panel which can only be used for the figure, and can also be used for performance. In the other embodiment, the display panel 2, the display panel of the embodiment shown in FIG. Referring to FIG. 8B, the operation method of the display panel of the present embodiment includes simultaneously applying the common electrode layer 112 and the patterned electrode layer 116 on the second substrate to the first substrate 1 Each of the 昼 构 构 构 构 阵列 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 上 上Similarly, although the (four) electrode layer 1 is provided on the electrode layer 112, when the display operation is performed, the voltage is simultaneously applied to the electrode layer m and the patterned electrode layer 116. Therefore, the liquid crystal molecules in the liquid crystal layer 150 are subjected to a specific twisting behavior according to the electric field between the electrode layer 116 / the electrode layer 112 and the layer of the halogen array. In other words, the case electrode layer 116 does not affect the normal display operation of the display panel. In addition, since no alignment pattern is formed in the halogen electrode in the pixel array layer 1〇2, the panel is lighter than the conventional display panel using the PSA technology. Moreover, since no alignment pattern is formed in the halogen electrode in the pixel array layer 102, it can be avoided that the width of the alignment slit formed in the pixel electrode is not in the panel of the conventional PSA technology. - A problem that causes uneven display. Although the present invention has been disclosed above by way of example, it is not intended to limit 14 201122643 AU0905008 32092twf.d〇c/n. This is a general knowledge in the technical field of the second, without departing from ir: A little more refinement, so the scope of this X is subject to the scope defined in the attached patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention. Figure 2A is a top plan view of the pixel array layer of Figure 1.
圖2B疋圖1之第二基板的上視示意圖。 圖3是根據本發明實施例之晝素陣列層中的一個畫素 結構的上視示意圖。 圖4是根據本發明實施例之在一個單元區域内的圖案 化電極層的上視示意圖。 圖5是根據本發明實施例之在一個單元區域内的電極 層的上視示意圖。2B is a top plan view of the second substrate of FIG. 1. 3 is a top plan view of a pixel structure in a pixel array layer in accordance with an embodiment of the present invention. 4 is a top plan view of a patterned electrode layer in a cell region in accordance with an embodiment of the present invention. Figure 5 is a top plan view of an electrode layer in a cell region in accordance with an embodiment of the present invention.
圖6疋根據本發明另一實施例之顯示面板的剖面示意 —圖7為根據本發明一實施例之顯示面板的配向方法的 示意圖。 圖8A及圖8B為根據本發明之實施例之顯示面板的操 作方法的示意圖。 15 201122643 AUUyU3〇08 32092twf.doc/n 【主要元件符號說明】 100 第一基板 102 晝素陣列層 11G 第二基板 112 電極層 114 絕緣層 116 圖案化電極層 120 彩色濾光層 150 顯示介質 160 彩色遽光基板 SL ： 掃描線 DL ： 資料線 T:主動元件 G ： 明極 S :源極 D :汲極 CH 通道層 P:晝素電極 C1 ' C2 :接觸窗 U1 : 晝素結構 U2 ： 單元區域 202 :電容電極線 204 :上電極圖案 205 :遮蔽線 201122643 AU0905008 32092twf.doc/n 302 :透光區 304 :遮光區 310 :主狹缝 310a :水平延伸狹缝 310b :垂直延伸狹缝 312 :分支狹缝 Va :配向電壓 Vc :共同電壓Figure 6 is a cross-sectional view of a display panel in accordance with another embodiment of the present invention. Figure 7 is a schematic illustration of a method of aligning a display panel in accordance with an embodiment of the present invention. 8A and 8B are schematic views showing an operation method of a display panel according to an embodiment of the present invention. 15 201122643 AUUyU3〇08 32092twf.doc/n [Description of main component symbols] 100 First substrate 102 Alphane array layer 11G Second substrate 112 Electrode layer 114 Insulation layer 116 Patterned electrode layer 120 Color filter layer 150 Display medium 160 Color Polishing substrate SL: Scanning line DL: Data line T: Active device G: Bright pole S: Source D: Diode CH Channel layer P: Alizarin electrode C1 'C2: Contact window U1: Alizarin structure U2: Unit area 202: Capacitor electrode line 204: Upper electrode pattern 205: Mask line 201122643 AU0905008 32092twf.doc/n 302: Light-transmitting area 304: Light-shielding area 310: Main slit 310a: Horizontally extending slit 310b: Vertically extending slit 312: Branch Slit Va: alignment voltage Vc: common voltage