CN102566161B - Pixel structure and display panel - Google Patents

Abstract

The invention provides a pixel structure and a display panel. The scanning lines and the data lines are positioned on the substrate. The active element is electrically connected with the scanning line and the data line. The capacitance electrode line is positioned on the substrate. The upper electrode pattern is located above the capacitance electrode line, wherein the upper electrode pattern is provided with a first opening which exposes the capacitance electrode line. The pixel electrode is electrically connected with the active element and covers the capacitance electrode line and the upper electrode pattern, wherein the pixel electrode comprises a middle part and a plurality of branch parts connected with the middle part, and the middle part is provided with a second opening which exposes the first opening. The invention can increase the area of the electrode and reduce the area occupied by the alignment slits in the pixel electrode, thereby reducing the problem of uneven display caused by inconsistent width of the alignment slits due to the lithography etching process.

Description

Pixel structure and display panel

This application is a divisional application of the patent application with the application number "201010001606.9", the application date is "January 5, 2010", and the invention title is "pixel structure and display panel".

technical field

The present invention relates to a pixel structure and a display panel with the pixel structure, and in particular to a pixel structure using Polymer Stabilized Alignment (PSA) technology and a display panel with the pixel structure.

Background technique

In the development of displays, with the advancement of optoelectronic technology and semiconductor manufacturing technology, liquid crystal displays with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market.

The liquid crystal display includes a backlight module and a liquid crystal display panel, while a traditional liquid crystal display panel is composed of two substrates and a liquid crystal layer filled between the two substrates. Generally speaking, during the manufacturing process of the liquid crystal display panel, an alignment film is formed on the two substrates to make the liquid crystal molecules have a specific arrangement. The existing method for forming an alignment film is to apply an alignment material first, and then perform an alignment process on the alignment material. The alignment process can be divided into a contact alignment process and a non-contact alignment process. Although the non-contact alignment process can solve problems such as static electricity and particle contamination caused by contact friction alignment, it often suffers from the problem of insufficient anchoring energy of the alignment surface. However, if the anchoring energy of the alignment surface is insufficient, the display quality of the liquid crystal display panel will often be poor.

In order to solve the above problems, a polymer stabilized alignment (Polymer Stabilized Alignment, PSA) technology has been proposed. This technology is to mix monomer compound (monomer) of appropriate concentration in the liquid crystal material and vibrate evenly. Next, the mixed liquid crystal material is placed on a heater and heated to reach an isotropic (Isotropy) state. Then, when the temperature of the liquid crystal mixture is lowered to 25° C. to room temperature, the liquid crystal mixture will return to a nematic state. At this time, the liquid crystal mixture is injected into the liquid crystal cell and a voltage is applied. When a voltage is applied to stabilize the alignment of liquid crystal molecules, ultraviolet light or heating is used to polymerize monomer compounds to form a polymer layer, thereby achieving the purpose of stable alignment.

Generally, in the liquid crystal display panel of the PSA, an alignment slit is formed in the pixel electrode of the pixel structure, so that the liquid crystal molecules have a specific alignment direction. The more alignment slits in the pixel electrode, the more precise the alignment of the liquid crystal molecules can be controlled, but the larger the area occupied by the alignment slits will also increase the display non-uniformity (mura), which is mainly because of the alignment slits. The lithography process causes the slit width to be inconsistent. In more detail, in the lithography process of the alignment slit, the junction between the optical mirror groups of the exposure device is often not completely consistent with the exposure conditions at the non-junction, thus causing The slit width here is inconsistent with other slit widths. As a result, the brightness of the display panel at these two locations is different, resulting in the problem of display non-uniformity (mura).

Contents of the invention

The present invention provides a pixel structure and a display panel with the pixel structure, which can reduce the problem of uneven display caused by the inconsistent width of the formed alignment slits in the traditional pixel structure and display panel using PSA technology.

The present invention proposes a pixel structure, which includes scan lines and data lines, active devices, capacitor electrode lines, upper electrode patterns, and pixel electrodes. The scan line and the data line are located on the substrate. The active elements are electrically connected to the scan lines and the data lines. Capacitive electrode lines are located on the substrate. The upper electrode pattern is located above the capacitor electrode lines, wherein the upper electrode pattern has a first opening, which exposes the capacitor electrode lines. The pixel electrode is electrically connected to the active element and covers the capacitor electrode line and the upper electrode pattern, wherein the pixel electrode includes a middle part and a plurality of branch parts connected to the middle part, and there is a second opening in the middle part, which exposes A first opening, wherein the upper electrode pattern includes a first portion and a second portion, wherein the first portion is electrically connected to the pixel electrode, and the first opening is located in the second portion;

Wherein, the middle part of the pixel electrode includes: a horizontal extension part, which is correspondingly arranged above the capacitance electrode line; a vertical extension part, which is vertically arranged with the horizontal extension part; part; there is a gap between the block part and the horizontal extension part and the vertical extension part; in the gap between the block part and the horizontal extension part and the block The gap between the shape portion and the vertical extension portion further includes a plurality of secondary branch portions;

Or, wherein, there is a slit between two adjacent branch parts of the pixel electrode, and the lengths of the slits are not completely the same, including the slit extending from the middle part to the edge of the pixel structure, and the slit not extending to the pixel structure. The slit at the edge of the structure; the branches on both sides of the slit that do not extend to the edge of the pixel structure are partially connected together.

The present invention provides a display panel, which includes a first substrate, a second substrate, and a display medium between the first substrate and the second substrate. There are multiple pixel structures on the first substrate, and each pixel structure is as above. The second substrate is located opposite to the first substrate, wherein the second substrate includes an electrode layer.

Based on the above, in the pixel structure of the present invention, there is a first opening in the upper electrode pattern, and a second opening in the middle of the pixel electrode. When performing the curing process of PSA technology, the high voltage applied to the capacitor electrode line can generate an alignment effect on the liquid crystal molecules above the second opening through the first opening and the second opening, and then make the liquid crystal molecules at the position The liquid crystal molecules reach a predetermined pretilt angle. In this way, the area of the electrode can be increased and the area occupied by the alignment slit in the pixel electrode can be reduced, thereby reducing the display unevenness (mura) problem caused by the inconsistent width of the alignment slit due to the lithographic etching process .

Description of drawings

1 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention;

FIG. 2A is a schematic top view of a pixel structure according to an embodiment of the present invention;

2B is a schematic diagram of a pixel electrode in the pixel structure of FIG. 2A;

Fig. 3 is a schematic sectional view along the section line I-I' of Fig. 2A;

FIG. 4A is a schematic top view of a pixel structure according to an embodiment of the present invention;

FIG. 4B is a schematic diagram of a pixel electrode in the pixel structure of FIG. 4A;

FIG. 5A is a schematic top view of a pixel structure according to an embodiment of the present invention;

FIG. 5B is a schematic diagram of a pixel electrode in the pixel structure of FIG. 5A;

FIG. 6A is a schematic top view of a pixel structure according to an embodiment of the present invention;

FIG. 6B is a schematic diagram of a pixel electrode in the pixel structure of FIG. 6A .

Figure number:

100: first substrate

102: Pixel array layer

110: second substrate

112: electrode layer

150: display media

SL: scan line

DL: data line

T: active component

G: grid

S: source

D: Drain

CH: channel layer

P: pixel electrode

C1, C2: contact window

202: Capacitive electrode wire

204: upper electrode pattern

204a, 204b: first part, second part

205: Shielding line

206: First opening

208: middle part

208a: Horizontal extension

208b: vertical extension

208c: Blocky part

210: Branch Department

210': Secondary branch

210a, 210b, 210c, 210d: alignment slits

211, 214: insulating layer

212: Second opening

S: space

Detailed ways

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the invention. Please refer to FIG. 1 , the display panel of this embodiment includes a first substrate 100 , a second substrate 110 and a display medium 150 located between the first substrate 100 and the second substrate 110 .

The material of the first substrate 100 can be glass, quartz, organic polymer or metal and so on. A pixel array layer 102 is disposed on the first substrate 100, and the pixel array layer 102 is composed of a plurality of pixel structures. The pixel structure in the pixel array layer 102 will be described in detail in the following paragraphs.

The material of the second substrate 110 can be glass, quartz or organic polymer and so on. An electrode layer 112 is disposed on the second substrate 110 . In this embodiment, the electrode layer 112 is a transparent conductive layer, and its material includes metal oxide, such as indium tin oxide or indium zinc oxide. The electrode layer 112 completely covers the second substrate 110 . In addition, according to the embodiment of the present invention, no alignment pattern (such as alignment protrusions or alignment slits) is disposed on the electrode layer 112 . In addition, according to another embodiment of the present invention, the second substrate 110 may further include a color filter array (not shown), which includes red, green and blue filter patterns. In addition, the second substrate 110 may further include a light-shielding pattern layer (not shown), which may also be called a black matrix, which is disposed between the patterns of the color filter array.

The display medium 150 includes liquid crystal molecules. Since the display panel of this embodiment is a display panel using PSA technology, the display medium 150 also includes monomer compounds in addition to liquid crystal molecules. In other words, the display medium 150 contains liquid crystal molecules and monomer compounds when the display panel has not undergone the aging process of the monomer compounds. When the display panel is undergoing the aging process of the monomer compound, the monomer compound will undergo a polymerization reaction to form a polymer film on the surface of the pixel array layer 102 and the electrode layer 112 . Therefore, when the display panel is subjected to the aging process of monomer compounds, the display medium 150 is mainly liquid crystal molecules.

Next, the pixel array layer 102 on the first substrate 100 will be described in detail. As mentioned above, the pixel array layer 102 is composed of multiple pixel structures. In this embodiment, the design of each pixel structure is as shown in FIG. 2A, and FIG. 2B is a schematic diagram of the pixel electrode in FIG. The figure is a schematic cross-sectional view along the section line II' in 2A. Please refer to FIG. 2A , FIG. 2B and FIG. 3 , in this embodiment, the pixel structure includes scan lines SL and data lines DL, active elements T, capacitor electrode lines 202 , upper electrode patterns 204 and pixel electrodes P.

The scan lines SL and the data lines DL are located on the first substrate 100 . The extension directions of the scan lines SL and the data lines DL are different. In addition, the scan lines SL and the data lines DL are located in different film layers with an insulating layer interposed therebetween. The scan line SL and the data line DL are mainly used to transmit the driving signal for driving the pixel structure.

The active element T is electrically connected to the scan line SL and the data line DL. Here, the active element T is, for example, a thin film transistor, which includes a gate G, a channel layer CH, a source S and a drain D. As shown in FIG. The gate G is electrically connected to the scan line SL, and the source S is electrically connected to the data line DL. In other words, when a control signal is input to the scan line SL, the scan line SL and the gate G are electrically connected; When a signal is input into the data line DL, the data line DL is electrically connected to the source S. The channel layer CH is located above the gate and below the source S and the drain D. The active device T in this embodiment is illustrated by taking a bottom gate thin film transistor as an example, but the present invention is not limited thereto. In other embodiments, the active element T may also be a top gate thin film transistor.

The capacitor electrode lines 202 are located on the first substrate 100 . The extending direction of the capacitive electrode lines 202 is parallel to the scanning lines SL. In this embodiment, the capacitive electrode lines 202 and the scanning lines SL can be formed at the same time, so the capacitive electrode lines 202 and the scanning lines SL belong to the same film layer. According to an embodiment of the present invention, the capacitor electrode lines 202 in each pixel structure are electrically connected to a common voltage.

The upper electrode pattern 204 is located above the capacitive electrode line 202 , wherein the upper electrode pattern 204 has a first opening 206 exposing the capacitive electrode line 202 under the upper electrode pattern 204 . In more detail, the upper electrode pattern 204 and the capacitor electrode line 202 are overlapped, and an insulating layer 211 is sandwiched between the two to electrically isolate the upper electrode pattern 204 and the capacitor electrode line 202, as shown in FIG. Figure 3 shows. The first opening 206 in the upper electrode pattern 204 exposes the insulating layer 211 above the capacitor electrode line 202 . In this embodiment, the upper electrode pattern 204 is formed at the same time as the data line DL is formed, so the upper electrode pattern 204 and the data line DL belong to the same film layer.

According to an embodiment of the present invention, the upper electrode pattern 204 includes a first portion 204a and a second portion 204b, and the first opening 206 is located in the second portion 204b. In addition, the first part 204a and the second part 204b of this embodiment are separated from each other. The first portion 204a shown in FIG. 2A is located on both sides of the second portion 204b. However, the present invention is not limited thereto. In other embodiments, only one first part may be designed, or the first part 204a and the second part 204b are connected together.

According to an embodiment of the present invention, the pixel structure further includes a shielding line 205 . The shielding line 205 is arranged parallel to the data line DL, and is located in the middle of the pixel structure. In this embodiment, the shielding line 205 is formed simultaneously with the data line DL and the upper electrode pattern 204 , so the shielding line 205 can be directly connected to the second portion 204 b of the upper electrode pattern 204 . However, the present invention is not limited thereto, and according to other embodiments, the shielding lines 205 may be formed simultaneously with the scan lines SL. Since the shielding line 205 itself is in a floating state, even if the scanning line SL is connected to the shielding line 205 , it will not affect the signal transmission of the scanning line SL. In addition, in another embodiment, the shielding line 205 may not be connected to the upper electrode pattern 204 .

It is worth mentioning that the main function of the shielding line 205 is to prevent the display phenomenon caused by the tilting of the liquid crystal molecules above the shielding line 205 from being seen by human eyes. Therefore, designing the shielding lines 205 can make the liquid crystal display panel have better display quality, but the present invention does not limit the use of the shielding lines. In other words, in other embodiments, the fabrication of the shielding line 205 can also be omitted.

The pixel electrode P is electrically connected to the active element T. As shown in FIG. In this embodiment, the pixel electrode P is electrically connected to the drain D of the active element T. As shown in FIG. More specifically, a contact window C1 is further provided at the overlap between the pixel electrode P and the drain D of the active element T, so as to electrically connect the pixel electrode P and the drain D. In addition, the pixel electrode P covers the capacitor electrode line 202 and the upper electrode pattern 204 , and an insulating layer 214 is sandwiched between the pixel electrode P and the upper electrode pattern 204 (as shown in FIG. 3 ). In addition, a contact window C2 is formed between the pixel electrode P and the first portion 204 a of the upper electrode pattern 204 to electrically connect the pixel electrode P to the first portion 204 a of the upper electrode pattern 204 . In other words, the pixel electrode P and the first portion 204 a of the upper electrode pattern 204 can be made to have a common potential through the contact window C2 . In addition, through the electrical coupling relationship between the first portion 204 a of the upper electrode pattern 204 and the capacitive electrode line 202 , the charge of the pixel electrode P can be stored there, thus forming a storage capacitor of the pixel structure.

In addition, the pixel electrode P includes a central portion 208 and a plurality of branch portions 210 connected to the central portion 208 . In particular, the middle portion 208 of the pixel electrode P has a second opening 212 exposing the first opening 206 . In more detail, as shown in FIG. 3 , the insulating layer 214 is filled into the first opening 206 in the upper electrode pattern 204 , and the second opening 212 exposes the insulating layer 214 above the first opening 206 . According to an embodiment of the present invention, the width of the second opening 212 located in the middle portion 208 of the pixel electrode P is greater than the width of the first opening 206 located in the second portion 204b of the upper electrode pattern 204 . In addition, according to an embodiment of the present invention, the width of the first opening 212 located in the middle portion 208a of the pixel structure P is greater than the thickness of the display medium 150 located between the first substrate 100 and the second substrate 110 shown in FIG. 1 twice as much.

Furthermore, the branch portion 210 of the pixel electrode P extends in four directions from the middle portion 208 , that is, the branch portion 210 extends from the middle portion 208 to the edge of the pixel structure. The gap between the branch portions 210 is also called an alignment slit 210a.

In addition, according to this embodiment, the middle portion 208 of the pixel electrode P includes a horizontally extending portion 208a, a vertically extending portion 208b, and a block portion 208c. The horizontal extension portion 208a is correspondingly disposed above the capacitive electrode line 202 . The vertical extension portion 208b and the horizontal extension portion 208a are perpendicular to each other and are correspondingly disposed above the shielding line 205 . The block portion 208c is located at the intersection of the horizontal extension portion 208a and the vertical extension portion 208b, so the horizontal extension portion 208a and the vertical extension portion 208b extend in four directions from the block portion 208c. In this embodiment, the block portion 208c is directly connected to the horizontal extension portion 208a and the vertical extension portion 208b. In addition, the block portion 208c is mainly located at the center of the pixel structure.

Based on the above, no slit is formed in the middle portion 208 of the pixel electrode P in this embodiment, so compared with the design in which alignment slits are fully formed in the pixel electrode of the conventional pixel structure using PSA technology, this embodiment The area occupied by the alignment slit 210a of the pixel electrode P is relatively small. Since the alignment slit 210a of the pixel electrode P in this embodiment occupies a small area, the problem of display unevenness (mura) caused by the lithographic etching process of the alignment slit can be reduced.

In addition, in this embodiment, the second opening 212 is formed in the pixel electrode P, and the first opening 206 is formed in the upper electrode pattern 204 , so that the capacitor electrode line 202 located under the first opening 206 and the second opening 212 is exposed. Therefore, when the display panel of this embodiment is performing the curing process of the PSA and applying a high voltage to the capacitor electrode line 202, the high voltage on the capacitor electrode line 202 can pass through the first opening 206 and the second opening 212 directly and directly It acts on the liquid crystal molecules above the second opening 212 . In other words, since the liquid crystal molecules have a characteristic of tilting towards a high voltage, the liquid crystal molecules located above the middle portion 208 of the pixel electrode P will have a desired alignment effect due to the influence of the voltage through the first opening 206 and the second opening 212 . Therefore, even if no alignment slit is provided in the middle portion 208 of the pixel electrode P, the liquid crystal molecules above the middle portion 208 can still achieve the expected alignment effect by using the first opening 206 and the second opening 212 .

In other words, in the present invention, the middle part 208 of the pixel electrode P is designed as a complete electrode pattern to reduce the area occupied by the alignment slit in the pixel electrode, and the second opening 212 is designed in the middle part 208 of the pixel electrode P. The first opening is formed under the second opening 122 so that the voltage of the capacitor electrode line 202 can have an alignment effect on the liquid crystal molecules above the middle portion 208 of the pixel electrode P. Therefore, the present invention can make the pixel structure have the same alignment effect as the traditional PSA pixel structure, and at the same time can achieve the purpose of reducing the area occupied by the alignment slit 210a of the pixel electrode P, so as to reduce the lithographic etching process of the alignment slit The display unevenness (mura) problem caused by its inconsistent width.

2A and FIG. 2B, the block portion 208c in the middle portion 208 of the pixel electrode P is in the shape of a rhombus, but the present invention is not limited thereto. According to other embodiments, the block portion 208c can also be in other shapes. design.

FIG. 4A is a schematic top view of a pixel structure according to another embodiment of the present invention, and FIG. 4B is a schematic diagram of a pixel electrode in FIG. 4A . The embodiment shown in FIG. 4A and FIG. 4B is similar to the above-mentioned embodiment shown in FIG. 2A and FIG. 2B , so the same elements are denoted by the same reference numerals and will not be described again. The difference between the embodiment shown in FIG. 4A and FIG. 4B and the embodiment shown in FIG. 2A and FIG. 2B lies in that the block portion 208c of the middle portion 208 of the pixel electrode P is rectangular or square. Designing the block portion 208c in a rectangular shape or a square shape can further reduce the area occupied by the alignment slit 210a in the pixel electrode P. Referring to FIG.

According to other embodiments, besides the aforementioned rhombus, rectangle or square, the block portion 208c may also be in other shapes, such as circle, triangle or other polygons.

FIG. 5A is a schematic top view of a pixel structure according to another embodiment of the present invention, and FIG. 5B is a schematic diagram of a pixel electrode in FIG. 5A . The embodiment shown in FIG. 5A and FIG. 5B is similar to the above-mentioned embodiment shown in FIG. 2A and FIG. 2B , so the same components are denoted by the same reference numerals and will not be described again. The difference between the embodiment shown in FIG. 5A and FIG. 5B and the above-mentioned embodiment shown in FIG. 2A and FIG. There is a gap S between 208b. In other words, the block portion 208c is not completely connected with the horizontal extension portion 208a and the vertical extension portion 208b.

In more detail, the block portion 208c is roughly divided into four blocks, which are respectively located at the sides of the horizontal extension portion 208a and the vertical extension portion 208b. In addition, the gap S between the block portion 208c and the vertically extending portion 208b further includes a plurality of sub-branches 210', and there are slits 210b between the sub-branches 210'. Similarly, the gap S between the block portion 208c and the horizontally extending portion 208a further includes a plurality of sub-branches 210', and there are slits 210b between the sub-branches 210'.

FIG. 6A is a schematic top view of a pixel structure according to another embodiment of the present invention, and FIG. 6B is a schematic diagram of a pixel electrode in FIG. 6A . The embodiment shown in FIG. 6A and FIG. 6B is similar to the above-mentioned embodiment shown in FIG. 2A and FIG. 2B , so the same components are denoted by the same reference numerals and will not be described again. The difference between the embodiment shown in FIG. 6A and FIG. 6B and the embodiment shown in FIG. 2A and FIG. 2B is that the lengths of the alignment slits 210a between two adjacent branch portions 210 of the pixel electrode P may not be exactly the same. For example, the alignment slit 210c shown in the figure is longer, while the alignment slit 210d is shorter. In addition, the alignment slit 210c and the alignment slit 210d are different from the design of the alignment slit 210a. The alignment slit 210a extends from the middle portion 208 to the edge of the pixel structure, but the alignment slit 210c and the alignment slit 210d do not extend to the edge of the pixel structure. Therefore, parts of the branch portions 210 on both sides of the alignment slit 210c and the alignment slit 210d are connected together.

It is worth mentioning that the alignment slit 210c and the alignment slit 210d can be arbitrarily designed between the branch portions 210, for example, an alignment slit 210c or an alignment slit can be designed only after two or three or more branch portions 210 are separated. seam 210d.

To sum up, since the upper electrode pattern in the pixel structure of the present invention has a first opening, and the middle part of the pixel electrode has a second opening. When performing the maturation process of PSA technology, the high voltage applied to the capacitor electrode line can generate an alignment effect on the liquid crystal molecules above the second opening through the first opening and the second opening, and then make the liquid crystal molecules there reach a predetermined level. the pretilt angle. In this way, the area occupied by the alignment slits in the pixel electrodes can be reduced, thereby reducing the display unevenness (mura) problem caused by the inconsistent width of the alignment slits caused by the lithographic etching process.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (17)

1. A pixel structure, characterized in that, the pixel structure comprises: A scanning line and a data line are located on a substrate; an active element electrically connected to the scan line and the data line; a capacitive electrode line located on the substrate; an upper electrode pattern located above the capacitive electrode lines, wherein the upper electrode pattern has a first opening exposing the capacitive electrode lines; and A pixel electrode, which is electrically connected to the active element and covers the capacitor electrode line and the upper electrode pattern, wherein the pixel electrode includes a middle part and a plurality of branch parts connected to the middle part, and There is a second opening in the middle portion exposing the first opening, wherein the upper electrode pattern includes a first portion and a second portion, wherein the first portion is electrically connected to the pixel electrode, and the first opening is located in the second portion; Wherein, the middle part of the pixel electrode includes: a horizontal extension part, which is correspondingly arranged above the capacitor electrode line; a vertical extension part, which is vertically arranged with the horizontal extension part; a lump part, It is located at the intersection of the horizontal extension and the vertical extension; there is a gap between the block and the horizontal extension and the vertical extension; between the block and the horizontal The gap between the extension parts and the gap between the block part and the vertical extension part further include a plurality of sub-branches. 2. The pixel structure according to claim 1, wherein the pixel structure further comprises: a first insulating layer located between the capacitive electrode lines and the upper electrode pattern, wherein the first opening exposes the first insulating layer above the capacitive electrode lines; and A second insulating layer, located between the pixel electrode and the upper electrode pattern, wherein the second insulating layer fills the first opening, and the second opening exposes the above the second insulating layer. 3. The pixel structure according to claim 1, wherein a width of the second opening is greater than a width of the first opening. 4. The pixel structure according to claim 1, wherein the plurality of branch portions of the pixel electrode extend in four directions from the middle portion. 5. The pixel structure as claimed in claim 1, further comprising a shielding line located below the vertically extending portion. 6 . The pixel structure according to claim 5 , wherein the shielding line belongs to the same film layer as the scanning line, or belongs to the same film layer as the data line. 7. The pixel structure of claim 1, wherein the first portion and the second portion are separated from each other. 8. A pixel structure, characterized in that the pixel structure comprises: A scanning line and a data line are located on a substrate; an active element electrically connected to the scan line and the data line; a capacitive electrode line located on the substrate; an upper electrode pattern located above the capacitive electrode lines, wherein the upper electrode pattern has a first opening exposing the capacitive electrode lines; and A pixel electrode, which is electrically connected to the active element and covers the capacitor electrode line and the upper electrode pattern, wherein the pixel electrode includes a middle part and a plurality of branch parts connected to the middle part, and There is a second opening in the middle portion exposing the first opening, wherein the upper electrode pattern includes a first portion and a second portion, wherein the first portion is electrically connected to the pixel electrode, and the first opening is located in the second portion; Wherein, there is a slit between two adjacent branch parts of the pixel electrode, and the lengths of the slits are not completely the same, including the slit extending from the middle part to the edge of the pixel structure, and the slit not extending to the edge of the pixel structure. The slit; the branches on both sides of the slit that do not extend to the edge of the pixel structure are partially connected together. 9. The pixel structure according to claim 8, wherein the pixel structure further comprises: a first insulating layer located between the capacitive electrode lines and the upper electrode pattern, wherein the first opening exposes the first insulating layer above the capacitive electrode lines; and A second insulating layer, located between the pixel electrode and the upper electrode pattern, wherein the second insulating layer fills the first opening, and the second opening exposes the above the second insulating layer. 10. The pixel structure according to claim 8, wherein a width of the second opening is greater than a width of the first opening. 11. The pixel structure according to claim 8, wherein the plurality of branch portions of the pixel electrode extend in four directions from the middle portion. 12. The pixel structure as claimed in claim 8, further comprising a shielding line located below the vertically extending portion. 13 . The pixel structure according to claim 12 , wherein the shielding line and the scanning line belong to the same film layer, or belong to the same film layer as the data line. 14 . 14. The pixel structure of claim 8, wherein the first portion and the second portion are separated from each other. 15. A display panel, characterized in that the display panel comprises: A first substrate, having a plurality of pixel structures on the first substrate, and each pixel structure is as described in claim 1 or 8; A second substrate, located opposite to the first substrate, wherein the second substrate includes an electrode layer; and A display medium is located between the first substrate and the second substrate. 16. The display panel according to claim 15, wherein the width of the first opening in the pixel structure is greater than the thickness of the display medium between the first substrate and the second substrate twice as much. 17. The display panel according to claim 15, wherein the electrode layer on the second substrate is not provided with an alignment pattern.