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TW201118994A - Semiconductor device package and manufacturing method thereof - Google Patents

Semiconductor device package and manufacturing method thereof Download PDF

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Publication number
TW201118994A
TW201118994A TW99110392A TW99110392A TW201118994A TW 201118994 A TW201118994 A TW 201118994A TW 99110392 A TW99110392 A TW 99110392A TW 99110392 A TW99110392 A TW 99110392A TW 201118994 A TW201118994 A TW 201118994A
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TW
Taiwan
Prior art keywords
semiconductor device
package
grounding
redistribution
electrical
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TW99110392A
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Chinese (zh)
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TWI409921B (en
Inventor
Chi-Tsung Chiu
Kuo-Hsien Liao
Wei-Chi Yih
Yu-Chi Chen
Chen-Chuan Fan
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Advanced Semiconductor Eng
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Publication of TW201118994A publication Critical patent/TW201118994A/en
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Publication of TWI409921B publication Critical patent/TWI409921B/en

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Elimination Of Static Electricity (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device package and manufacturing method thereof are provided. In one embodiment, a semiconductor device package includes: (1) a semiconductor device; (2) a package body covering lateral surfaces of the semiconductor device, a lower surface of the package body and a lower surface of the semiconductor device defining a front surface; (3) a set of redistribution layers disposed adjacent to the front surface, the set of redistribution layers including a grounding element that includes a connection surface electrically exposed adjacent to at least one lateral surface of the set of redistribution layers; and (4) an EMI shield disposed adjacent to the package body and electrically connected to the connection surface of the grounding element. The grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Description

201118994201118994

TW5768F 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體裝置封装件及其 法，且特別是有關於一種具有電磁干擾遮 /、製造方 體裝置封裝件及其製造方法。 阳圓級半導 【先前技術】 市場上對於小尺寸及高處理速度之需求漸增在某種 程度上亦驅使半導體裝置日益複雜。雖然小尺寸及高處理 速度之半導體裝置具有其優點，同時亦帶來了其他^二王 題。 在習知晶圓級封裝製程中’晶圓内之半導體裝置係於 切割晶圓之步驟前進行封裝。因此，習知之晶圓級封裝受 到扇入配置（fan-in configuration)之限制，亦即半導體裝 置封裝件之電性接點（electrical contacts )及其他元件受 到由半導體裝置之邊緣所定義之區域的限制。配置於半導 體裝置之邊緣外之任何元件通常無法被支援，且此些元件 通常於切割晶圓之步驟即被移除。當裝置之尺寸縮小時， 扇入配置之限制的問題更顯得嚴重。 此外，尚時脈速度（clock speed)可能使得訊號準位 (signallevel)間之轉態（transition)更為頻繁，亦即可 能造成較高頻率或較短波長之高準位電磁韓射。電磁韓射 可從來源半導體裝置發射出，且可入射至鄰近之半導體裝 置。當鄰近之半導體裝置之電磁輻射準位夠高時，此些放 射可能反過來影響來源半導體裝置之運作。此種現象有時 201118994TW5768F VI. Description of the Invention: The present invention relates to a semiconductor device package and a method thereof, and more particularly to an electromagnetic interference shielding/manufacturing device package and a method of fabricating the same. Yang-level semi-conducting [Prior Art] The increasing demand for small size and high processing speed on the market has also driven semiconductor devices to some extent. Although semiconductor devices of small size and high processing speed have their advantages, they also bring other problems. In conventional wafer level packaging processes, the semiconductor devices within the wafer are packaged prior to the step of dicing the wafer. Therefore, the conventional wafer level package is limited by the fan-in configuration, that is, the electrical contacts of the semiconductor device package and other components are affected by the area defined by the edge of the semiconductor device. limit. Any component that is disposed outside the edge of the semiconductor device is typically not supported, and such components are typically removed at the step of dicing the wafer. When the size of the device is reduced, the problem of the limitation of the fan-in configuration is more serious. In addition, the clock speed may cause a transition between signal levels to be more frequent, which may result in a higher-frequency or shorter-wavelength high-level electromagnetic Han. Electromagnetic Han radiation can be emitted from a source semiconductor device and can be incident on an adjacent semiconductor device. When the electromagnetic radiation levels of adjacent semiconductor devices are sufficiently high, such radiation may adversely affect the operation of the source semiconductor device. This phenomenon sometimes 201118994

' 'TW5768F 稱為電磁干擾（electromagnetic interference，EMI)。由於 小尺寸之半導體裝置在整體電子系統中之半導體裝置密 度較高’因而可能使得電磁干擾問題更為嚴重，進而造成 鄰近之半導體裝置具有不必要之高準位之電磁輻射。 由以上敘述可知，發展出具有電磁干擾遮蔽之晶圓級 半導體封裝件及其方法具有相當之需求性。 【發明内容】' 'TW5768F is called electromagnetic interference (EMI). Due to the high density of semiconductor devices in small-sized semiconductor devices in the overall electronic system, the electromagnetic interference problem may be exacerbated, thereby causing adjacent semiconductor devices to have undesirably high-level electromagnetic radiation. As can be seen from the above description, the development of wafer level semiconductor packages with electromagnetic interference shielding and methods therefor are quite demanding. [Summary of the Invention]

本發明係有關於一種具有電磁干擾遮蔽之晶圓級半 導體裝置封裝件。一實施例中，半導體裝置封裝件包括半 導體裝置、封裝體、一組重新分配層及電磁干擾遮蔽。半 導體裝置具有下表面、鄰近半導體裝置之邊緣配置之數個 側表面並包括接觸墊。接觸墊鄰近半導體裝置之下表面配 置。封裝體覆蓋半導體裝置之側表面並封裝體具有上表 面下表面&數個侧表面。_裝體之侧表面 邊緣配置。封裝體之下麥而β μ 體之下表面及+導體之下表面定義一前表 面重新刀配層鄰近前表面配置且具有數個側表面並包括 m:新分配層之側表面鄰近重新分配層之邊緣配 二括連接表面，連接表面鄰近重新分配層之 鑲些侧表面中至少一本1 + 曰〜 磁干擾遮蔽鄰近封仲夕卜主I 电『逆接之用。電 置。電磁千蛘”裝 表封裝體之側表面配 置電磁干擾遮蔽電性連接 元件提供1性特 狀賴表面。接地 射放電至接地端。场發生在電磁干擾遮蔽的電磁放 另一實施例中 半導體裝置封裝件包括半導體裝置、 201118994The present invention relates to a wafer level semiconductor device package having electromagnetic interference shielding. In one embodiment, a semiconductor device package includes a semiconductor device, a package, a set of redistribution layers, and electromagnetic interference shielding. The semiconductor device has a lower surface, a plurality of side surfaces disposed adjacent the edge of the semiconductor device, and includes contact pads. The contact pads are disposed adjacent to the lower surface of the semiconductor device. The package covers a side surface of the semiconductor device and the package has an upper surface lower surface & a plurality of side surfaces. _The side surface of the body is configured with an edge. The underside of the package and the lower surface of the +-conductor define a front surface re-mating layer adjacent to the front surface and having a plurality of side surfaces and including m: a new distribution layer side surface adjacent to the redistribution layer The edge is provided with a connecting surface, and at least one of the side surfaces of the connecting surface adjacent to the redistribution layer is 1 + 曰 ~ magnetic interference shielding adjacent to the main body of the main body. Electricity. The side surface of the electromagnetic millimeter" package is equipped with an electromagnetic interference shielding electrical connection element to provide a 1-characteristic surface. The grounding is discharged to the ground. The field occurs in the electromagnetic interference shielding electromagnetic discharge. Package includes semiconductor device, 201118994

TW5768F 封裝體、重新分配單元及電磁干擾 主動表面。封裝體覆蓋半導體農置 =體1置包括 動表面暴露出，以作為電性連 1 體骏置之主 面。重新分配單元包括介電層、诗、體包括外部表 電層鄰近半導體震置之主動表面配定二=元件。介 電層之開口對齊於半導體裴置 疋義數個開口。介 介電層延伸並透過由介電層所定義之=門電性走線沿著 性連接於半導體裝置之主動表 ：：：口之-者電 延伸並包括側表面。接地元件 糸沿著介電層 之邊緣配置。電磁干擾遮蔽鄰分配單元 電性連接於接地元件之侧表面 ^表面配置並 括下列步驟。提供具有主動表例令’此製造方法包 材料以形成封膠結構’封膠=詈塗:_ 裝置之主動表面中至少—部份裝置’半導體 成重新分配結構於鄰近於半導體裳置暴露出，·形 新分配結構包括電性連接部， 表面之處。重 新分配結構中，·形成穿透:膠結向地延伸於重 :縫’切割狹縫係對齊於重新分配結構。：::=之 形成包括外部表面之封裝構被分割以 具有暴露之連接表面之接地元件電 裝趙之外部表面及接地元件之連接表:::=: 201118994TW5768F package, redistribution unit and electromagnetic interference active surface. The package covers the semiconductor farm. The body 1 includes the moving surface exposed to serve as the main surface of the electrical connection. The redistribution unit includes a dielectric layer, a poem, and a body including an active surface matching two=element of the external surface layer adjacent to the semiconductor. The openings of the dielectric layer are aligned with the semiconductor device to define a plurality of openings. The dielectric layer extends and is electrically connected to the active device of the semiconductor device by a gate line defined by the dielectric layer and includes a side surface. The grounding element is disposed along the edge of the dielectric layer. The electromagnetic interference shielding adjacent distribution unit is electrically connected to the side surface of the grounding member. The surface configuration includes the following steps. Providing an active watch order to 'this manufacturing method package material to form a sealant structure' sealant = 詈 coating: _ at least part of the active surface of the device 'semiconductor into a redistribution structure exposed adjacent to the semiconductor skirt, · The new distribution structure includes an electrical connection, the surface. In the redistribution structure, a penetration is formed: the cement extends to the ground in a weight: the slit' cutting slit is aligned with the redistribution structure. :::= Forming the connection table including the external surface of the package to be grounded with the exposed connection surface of the ground component and the grounding element:::=: 201118994

' ’ TW5768F 遮蔽。 為讓本發明之上述内容能更明顯易懂，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 以下之疋義係係應用於本發明之實施例之部份方 面。此處可同樣地擴充此些定義。 除非特別且清楚地指出，否則文中所使用之詞彙 「一」、「一個」及「此」係包括複數之形式。因此，舉例 來說，除非另外清楚地說明，否則一接地元件係可包括數 個接地元件。 在此處所用之詞彙「組」係指一或多個元件之集合。 因此，舉例來說，一組膜層可包括一單一膜層或數個膜 層。一組之元件可代表此組中之構件。一組之元件可為相 同或相異。在某些例子中，一組之元件可具有一或多個共 同之特性。' ' TW5768F shaded. In order to make the above description of the present invention more comprehensible, the following description of the preferred embodiments and the accompanying drawings will be described in detail as follows: [Embodiment] The following system is applied to the implementation of the present invention. Some aspects of the example. These definitions can be similarly extended here. The terms “a”, “an” and “the” are used in the plural unless they are specifically and clearly indicated. Thus, for example, a grounding element can include several grounding elements, unless explicitly stated otherwise. The term "group" as used herein refers to a collection of one or more elements. Thus, for example, a group of layers may comprise a single layer or a plurality of layers. A group of components can represent components in this group. A group of components can be the same or different. In some instances, a group of components may have one or more of the same characteristics.

此處所用之詞彙「相鄰」係指接近或緊鄰。相鄰之六 件可彼此分離或可實際上接觸或直接彼此接觸。在某些作 子中，相鄰之元件可彼此連接或可一體成形 厂 此處所用之相對之詞彙，例如是「内」、「内部」、「外 外部」、「頂」、「底」、「前」、「後」、「上」、「向上」、「下 「向下」、「垂直」、「垂直地」 側向」、「側向地 厂 之上 及「之下」，係指一組元件中彼此之方位，例如是根據麗 式之方位。然而，但在製造或使用時並不限定為特定之 位 201118994The term "adjacent" as used herein refers to proximity or proximity. The six adjacent pieces may be separated from each other or may be in actual contact or directly in contact with each other. In some cases, adjacent elements may be connected to one another or may be integrally formed with the relative terms used herein, such as "inside", "inside", "outside", "top", "bottom", "Before", "After", "Up", "Up", "Lower", "Vertical", "Vertical", "Side" and "Below" and "Below" The orientation of each other in a group of components, for example, according to the orientation of the Li style. However, it is not limited to a specific position when it is manufactured or used. 201118994

TW5768F 二用之詞囊「相連」、「被連接」及「連接」係指 ㈣上之_或結合。相連接之元件可直接地 可間接地彼此輕接，例如是透過另-組元件而輕接。 之詞彙「實質上地」及「實質上」係指達到 相备的程度或範圍。當與事件或情況並用時，此些詞囊係 :用以代表事件或情況準確地發生，或代表事 相 ==發生，例如是代表此處所述之製造程序之一般= 处匕处所用之3彙Γ導電」及「導電性」係指傳導電流 材:電：料一般係指對於電流之流動具有很小或無 阻抗之材枓。導電性之單位之一係為每公尺之西門數 (S m )° 一般來說’導電材料係為導電性約大於104S.W 之材料作】如是至少約為1〇5 S 或至少約為^。 材料之導電性有時會隨著溫度變化。除非特職明，材料 之導電性係定義為室溫下之導電性。 ， 半導二 广繪示依照本發明之實施例之晶圓級TW5768F The term "connected", "connected" and "connected" refers to the _ or combination of (4). The connected components can be directly and indirectly connected to each other, for example, by another set of components. The terms "substantially" and "substantially" refer to the extent or extent to which they are available. When used in conjunction with an event or situation, these words are used to represent the event or situation to occur accurately, or to represent the occurrence of a == occurrence, for example, to represent the generality of the manufacturing process described herein. 3 “Conductivity” and “Conductivity” refer to conduction current materials: Electricity: Generally refers to materials that have little or no impedance to the flow of current. One of the units of conductivity is the number of gates per square meter (S m ). Generally, the material of the conductive material is about 104 S.W. The conductivity is at least about 1 〇 5 S or at least about ^. The conductivity of a material sometimes varies with temperature. Unless otherwise specified, the conductivity of a material is defined as conductivity at room temperature. , a semiconductor wafer level in accordance with an embodiment of the present invention

+ ¥體裝置封裝件⑽。具體地來說，第1圖係綠示封I 件100之立體圖，而第2圖係繪示封裝件刚沿著第 之Α-Α線之剖面圖。 回 圖示之實施例中，封裝件100之側面係實質上為平 面’並具有實質上垂直之方位，用以线實質上沿著封裝 件100之整個邊緣延伸之側向形狀。藉由減少 件_之佔用面積—intarea)，此垂直之侧向形= 少了整體半導體封裝件之尺寸。。然而，封裝件HK)之側 向形狀-般來說可為其他形狀，例如是曲面、斜面、 201118994+ ¥ Body device package (10). Specifically, Fig. 1 is a perspective view of the green sealing member 100, and Fig. 2 is a cross-sectional view of the package just along the first Α-Α line. In the illustrated embodiment, the sides of the package 100 are substantially planar' and have a substantially perpendicular orientation for the lateral shape of the line extending substantially along the entire edge of the package 100. By reducing the footprint of the device - inarea, this vertical lateral shape = less overall semiconductor package size. . However, the lateral shape of the package HK) can be other shapes in general, such as curved surfaces, bevels, 201118994

' 1 TW5768F 狀或為粗链材質。 請參照第2圖，封裝件100包括半導體裝置102。半 導體裝置102具有下表面104、上表面106與側表面108 及110。側表面108及110係鄰近於半導體裝置102之邊 緣，並於下表面104及上表面106間延伸。圖示之實施例 中，表面104、106、108及110皆實質上為平面，而側表 面108及110係垂直於下表面104及上表面106。但可了 解的是，在其他的實施方式中，表面104、106、108及110 • 亦可為其他形狀或方位。如第2圖所示，上表面106係為 半導體裝置102之後表面，而下表面104係為半導體裝置 102之主動表面（active surface)半導體裝置102之接觸 墊112a及112b係鄰近於下表面104而配置。接觸墊112a 及112b提供半導體裝置102輸入及輸出之電性連接，而 接觸墊112a及112b中之其中之一係為接地之接觸墊。舉 例來說，接觸墊112b可為接地之接觸墊。圖示之實施例 中，半導體裝置102係為半導體晶片。但可了解的是，一 * 般來說半導體裝置102可為任何主動元件、被動元件或其 組合。當第2圖繪示其中一種半導體裝置時，可了解的是， 本發明之其他實施方式亦可包括其他的半導體裝置。 如第2圖所示，封裝件100亦包括鄰近於半導體裝置 102而配置之封裝體114。封裝體114及重新分配單元124 實質上覆蓋或包覆半導體裝置102,用以提供機械性之穩 定及抗氧化、潮濕及其他環境條件之保護。重新分配單元 124將於之後更詳細地說明。圖示之實施例中，封裝體114 實質上覆蓋半導體裝置102之上表面106及側表面108與[ 201118994' 1 TW5768F shape or thick chain material. Referring to FIG. 2, the package 100 includes a semiconductor device 102. The semiconductor device 102 has a lower surface 104, an upper surface 106 and side surfaces 108 and 110. Side surfaces 108 and 110 are adjacent to the edge of semiconductor device 102 and extend between lower surface 104 and upper surface 106. In the illustrated embodiment, the surfaces 104, 106, 108, and 110 are all substantially planar, while the side surfaces 108 and 110 are perpendicular to the lower surface 104 and the upper surface 106. However, it will be appreciated that in other embodiments, the surfaces 104, 106, 108, and 110 can be other shapes or orientations. As shown in FIG. 2, the upper surface 106 is the rear surface of the semiconductor device 102, and the lower surface 104 is the active surface of the semiconductor device 102. The contact pads 112a and 112b of the semiconductor device 102 are adjacent to the lower surface 104. Configuration. Contact pads 112a and 112b provide electrical connections for input and output of semiconductor device 102, and one of contact pads 112a and 112b is a grounded contact pad. For example, contact pad 112b can be a grounded contact pad. In the illustrated embodiment, the semiconductor device 102 is a semiconductor wafer. It will be appreciated, however, that semiconductor device 102 can be any active component, passive component, or combination thereof. When FIG. 2 illustrates one of the semiconductor devices, it will be appreciated that other embodiments of the present invention may also include other semiconductor devices. As shown in FIG. 2, the package 100 also includes a package 114 disposed adjacent to the semiconductor device 102. The package 114 and the redistribution unit 124 substantially cover or encapsulate the semiconductor device 102 to provide mechanical stability and protection against oxidation, moisture, and other environmental conditions. The redistribution unit 124 will be described in more detail later. In the illustrated embodiment, the package body 114 substantially covers the upper surface 106 and the side surface 108 of the semiconductor device 102 with [201118994]

TW5768F 110，且封裝體114係實質上暴露出或無覆蓋半導體裝置 102之下表面104。然而’可了解的是，封裝體U4^覆 蓋之範圍可不同於第2圖中所示。舉例來說，封裝體ιΐ4 可實貝上僅覆盍側表面1〇8及11〇,且封裝體114可實質 上無覆蓋下表面104及上表面1〇6。 、 如第2圖所示，封裝體114係由封膠材料所形成，且 封裝體114具有下表面116及外料面。封裝體ιΐ4之外 部表面包括上表面118及側表面12〇及122。側表面丨2〇 及122係鄰近於封裝體114之邊緣而配置，並於下表面116 及上表面118之間延伸。圖示之實施例中，表面116、ιΐ8、 120及122係只貝上為平面，而側表面及Η〗係實質 上垂直於下表面116或上表面118。在其他的實施方式中、， 表面116、丨18、120及122之形狀及方位可為不同如第 2圖所示，由側表面120及122所定義之封裝體114之邊 緣可大於半導體裝置102之邊緣，使得封裝件具有扇 出配置（fan-out configurati〇n )。換言之，封裝件1 〇〇之元 件可配置於由半導體装置1〇2所定義之邊緣内及外。此 外，封裝體114之下表面116係實質上對齊於半導體裝置 之:表面104’或與半導體裝置1〇2之下表面剛共 ，面二藉以疋義實質上為平面之一前表面。更具體地來 =、富下表面104實貝上暴露於外或無遮蓋物時可進行對 =例如疋藉由減少或最小化接觸墊ιΐ2&及mb之覆蓋 I已圍在其他實她方式中，可了解的是下表面刚及116 土 方式可不同於第2圖之方式’而下表面⑽係至少 ^伤暴路出來，使接觸墊心及U2b可提供輸入及輸出 201118994TW5768F 110, and package 114 is substantially exposed or uncovered to cover lower surface 104 of semiconductor device 102. However, it can be understood that the range of the package U4^ cover can be different from that shown in Fig. 2. For example, the package ι4 can cover only the side surfaces 1〇8 and 11〇 on the shell, and the package 114 can substantially cover the lower surface 104 and the upper surface 1〇6. As shown in Fig. 2, the package body 114 is formed of a sealant material, and the package body 114 has a lower surface 116 and an outer material surface. The outer surface of the package ι 4 includes an upper surface 118 and side surfaces 12 and 122. The side surfaces 丨2〇 and 122 are disposed adjacent the edges of the package 114 and extend between the lower surface 116 and the upper surface 118. In the illustrated embodiment, the surfaces 116, ι 8, 120, and 122 are planar only on the shell, and the side surfaces and the ridges are substantially perpendicular to the lower surface 116 or the upper surface 118. In other embodiments, the shapes and orientations of the surfaces 116, 18, 120, and 122 may be different. As shown in FIG. 2, the edges of the package 114 defined by the side surfaces 120 and 122 may be larger than the semiconductor device 102. The edge makes the package have a fan-out configuration (fan-out configurati〇n). In other words, the components of the package 1 可 can be disposed inside and outside the edge defined by the semiconductor device 1〇2. In addition, the lower surface 116 of the package body 114 is substantially aligned with the surface of the semiconductor device: the surface 104' or the surface of the lower surface of the semiconductor device 1A2, which is substantially a planar front surface. More specifically, the rich surface 104 can be exposed when exposed to the outer or uncovered material. For example, by reducing or minimizing the contact pad ιΐ2& and the coverage of mb I have been surrounded by other methods. It can be understood that the lower surface just and the 116 soil method can be different from the way of Fig. 2, while the lower surface (10) is at least a wounded road, so that the contact pad and U2b can provide input and output 201118994

! ’ TW5768F 之電性連接。此外，亦可了解的是’封裝體114可包括支 撐結構及封膠材料，或以支撐結構取代封膠材料。舉例來 說，封裝體114可包括一結構或中介層（interposer)，可 由玻璃、矽、金屬、金屬合金、高分子材料或其他適合之 結構性材料所形成。 請參照第2圖，封裝件100亦包括重新分配單元124。 重新分配單元124係鄰近於由下表面104及116所定義的 鲁 蝻表面配置。重新分配單元124係電性連接於半導體裝置 102並提供電性路徑（eiectrjcai pathway )、機械穩定性及 抗環境條件之保護。如第2圖所示，重新分配單元124包 括下表面126、上表面128及侧表面130與132。侧表面 13〇與132係鄰近於重新分配單元124之邊緣而配置，並 於下表面126及上表面128間延伸。在圖示之實施例中， 表面126、128、130及132係實質上為平面，而側表面130 及132係實質上垂直於下表面126或上表面128。可了解 • 的是，在其他的實施方式中，表面126、128、130及132 之形狀與方位可為不同。由侧表面130及132所定義並由 封襞體114所支撐之重新分配單元124之邊緣係大於半導 體裝置102之邊緣，使得封裝件100形成扇出配置。再者， 重新分配單元124之側表面130及132係實質上分別對齊 於封裝體114之側表面120及122，或與封裝體114之側 表面120及122共平面。更具體地來說，由於側表面130 及132係實質上暴露於外或無遮蔽物，使重新分配單元124 之側表面130及132可分別實質上對齊於封裝體114之側 表面120及122，例如是藉由減少或最小化侧表面130及[s 201118994! electrical connection of TW5768F. In addition, it is also understood that the package body 114 may include a support structure and a sealant material, or may replace the sealant material with a support structure. For example, package 114 can include a structure or interposer that can be formed from glass, tantalum, metal, metal alloys, polymeric materials, or other suitable structural materials. Referring to FIG. 2, the package 100 also includes a redistribution unit 124. The redistribution unit 124 is adjacent to the rough surface configuration defined by the lower surfaces 104 and 116. The redistribution unit 124 is electrically connected to the semiconductor device 102 and provides protection for electrical paths, mechanical stability, and environmental resistance. As shown in FIG. 2, the redistribution unit 124 includes a lower surface 126, an upper surface 128, and side surfaces 130 and 132. The side surfaces 13A and 132 are disposed adjacent to the edges of the redistribution unit 124 and extend between the lower surface 126 and the upper surface 128. In the illustrated embodiment, surfaces 126, 128, 130, and 132 are substantially planar, while side surfaces 130 and 132 are substantially perpendicular to lower surface 126 or upper surface 128. It will be appreciated that in other embodiments, the shapes and orientations of surfaces 126, 128, 130, and 132 can be different. The edge of the redistribution unit 124 defined by the side surfaces 130 and 132 and supported by the sealing body 114 is larger than the edge of the semiconductor device 102 such that the package 100 forms a fan-out configuration. Moreover, the side surfaces 130 and 132 of the redistribution unit 124 are substantially aligned with the side surfaces 120 and 122 of the package body 114, respectively, or are coplanar with the side surfaces 120 and 122 of the package body 114. More specifically, since the side surfaces 130 and 132 are substantially exposed to the outside or without the shield, the side surfaces 130 and 132 of the redistribution unit 124 can be substantially aligned with the side surfaces 120 and 122 of the package body 114, respectively. For example, by reducing or minimizing the side surface 130 and [s 201118994

TW5768F 132之覆蓋範圍。在其他的實施方式中，可了解的是側表 亦0 m、130、132之對齊方式可不同於第2圖之對 齊方式，而至少部份之侧表面130及132暴露出來，以作 為電性連接之用。在某些實施方式中，重新分配單元124 之厚度tr’亦即重新分配單元124之下表面及上表面 128 ^之距離’可約介於職米（μη〇至5G微米之間， 例如疋介於約12微米至5〇微米之間，或介於約14微米 至42微米之間。 一請繼續參照第2圖，在其他的實施方式中，重新分配 f元124可包括其他結構。在圖示之實施例中，重新分配 單元124具有數層且包括一對介電層134及136與一導電 層138至；部份之導電層〖％係被介電層1料及所 夹住。-般而言，介電層134及136可由介電材料所形成，Coverage of TW5768F 132. In other embodiments, it can be understood that the alignment of the side meters 0 m, 130, 132 can be different from the alignment of the second figure, and at least some of the side surfaces 130 and 132 are exposed as electrical properties. For connection purposes. In some embodiments, the thickness tr' of the redistribution unit 124, that is, the distance between the lower surface of the redistribution unit 124 and the upper surface 128^ can be between about 职η〇 to 5G microns, such as Between about 12 microns and 5 microns, or between about 14 microns and 42 microns. Please continue to refer to Figure 2, in other embodiments, the redistribution of the f-element 124 can include other structures. In the illustrated embodiment, the redistribution unit 124 has several layers and includes a pair of dielectric layers 134 and 136 and a conductive layer 138; a portion of the conductive layer is % sandwiched by the dielectric layer. Dimensions 134 and 136 may be formed of a dielectric material.

且介電材料可為聚合物或非聚合物。舉例來說介電層"A 及136中至y者為聚亞醯胺（p〇lyimide )、聚苯。惡唾 (P〇lybenzoxazoIe)、苯環丁烯（benz〇cyci〇butene^ 或其 組合。介電層134及136可由相同或不同之介電材料所形 成。在某些實施方式中，介電層134及136中至少一者可 由感光（Ph〇t〇imageabie)或光敏（ph〇t〇active)之介電材 料形成，藉由使用微影製程以進行圖案化之程序，進而減 少製作成本及時間。介電層134及136之厚度τ〇可約介 於1微米至12微米之間，例如是介於約⑽米至1〇微米 之間，或介於約2微米至6微米之間。雖然第2圖中緣示 兩介電層，可了解的是其它實施方式令可包括更多或更少 之介電層。 201118994And the dielectric material can be a polymer or a non-polymer. For example, the dielectric layers "A and 136 to y are polypyridyl (p〇lyimide), polyphenylene. P〇lybenzoxazoIe, benzocyclobutene (benz〇cyci〇butene^ or combinations thereof. Dielectric layers 134 and 136 may be formed of the same or different dielectric materials. In some embodiments, the dielectric layer At least one of 134 and 136 may be formed of a photosensitive material (Ph〇t〇imageabie) or photosensitive (ph〇t〇active), and the process of patterning is performed by using a lithography process, thereby reducing production cost and time. The thicknesses τ of the dielectric layers 134 and 136 may be between about 1 micrometer and 12 micrometers, for example between about (10) meters and 1 micron, or between about 2 and 6 microns. The two dielectric layers are shown in Figure 2, it being understood that other embodiments may include more or fewer dielectric layers.

* f TW5768F 如弟2圖所示，八+ S.f1 σ 1ΛΠ "電層136係定義開口 I40a及】40卜 且開口 140a及l4〇b之你里α "丄 咖及122b分別iC尺寸使至少部份之接觸墊 及_，且開口二：^ 卜開口 142过及 142h 66 -rf* 田，、/ 六 納電性接點144a及144 的寸用乂今 裝件⑽輸人及心之接點⑽及_提供封 中至少個、类道 電性連接，且電性接點144a及144b 圖=二電 (solderh 、電性接•點14知及144b係為鐸料凸塊 umps且電性接點144a及144b中至少一個為 電性連接至接地接魎 ^主一個為 電性接點144b係為接地< 雷+ ]爪0兄 扇屮Η㈣， 接點。根據封裝件100之 導體枣詈;〇Γ i點14乜及14仆往側面的方向配置於半 、置之邊緣的外側。但可了解的是，一般而言電 性接點144a及I44h iT 柄丨；士人 ° 夕、“、亦方向配置於半導體裝置 、内或/且外。如此一來’封裳件1〇〇之扇出配置在配 及隔開電性接點丨術及144b上具有更佳的彈性，並可 ，少與半導體震置102之接觸塾山a及U2b之配置及間 隔之依賴性。 導電層138係做為半導體裝置1〇2之接觸墊Hu及 咖之4新分配網路。依照_件剛之扇出配置導電 層138係於重新分配單元124中及半導體裝置1〇2之邊緣 外側向延伸。如第2圖所示，導電層138包括電性連接部 (electrical intere〇nnect) 14如及 146b。電性連接部 w6a 係電性連接接_ 112a及電性接點144a，電性連接部_ 13* f TW5768F As shown in Figure 2, eight + S.f1 σ 1ΛΠ "Electrical layer 136 defines the opening I40a and 4040 and the openings 140a and l4〇b are your i "丄咖和122b respectively iC size Make at least part of the contact pad and _, and the opening two: ^ 卜 opening 142 and 142h 66 -rf* field, / / six-nano electrical contacts 144a and 144 inches for today's (10) input and heart The contacts (10) and _ provide at least one of the seals, and the electrical connections are electrically connected, and the electrical contacts 144a and 144b are = two electric (solderh, electrical connection, point 14 and 144b are 凸 bump umps and At least one of the electrical contacts 144a and 144b is electrically connected to the grounding interface, and the first one is the electrical contact 144b, which is grounded < ray + ] claw 0 brother fan (four), the contact. According to the package 100 Conductor jujube; 〇Γ i point 14 乜 and 14 servant side direction is placed on the outer side of the half, the edge of the edge. However, it can be understood that generally the electrical contact 144a and I44h iT handle 士; On the eve, ", also in the direction of the semiconductor device, inside or / and outside. As a result, the fan-out arrangement of the cover-up device is equipped with a separate electrical contact and 144b It has better elasticity and can be less dependent on the arrangement and spacing of the contacts of the semiconductors and the U2b. The conductive layer 138 is used as the contact pad Hu of the semiconductor device 1 and 2 The conductive layer 138 is disposed in the redistribution unit 124 and extends outside the edge of the semiconductor device 1〇2. As shown in FIG. 2, the conductive layer 138 includes an electrical connection portion (electrical connection portion). Interconnected with 146b, electrical connection portion w6a is electrically connected to _112a and electrical contact 144a, and electrical connection portion _ 13

201118994 TW5768F 係電性連接接地之接觸墊112b及接地之電性接 更且體妯决句，^ 包j王赉點144b。 '、 ° %性連接部14如及146b包括位〇 140a及140b中之加八 匕祜位於開口 之另-部份。/ 及沿著介電層136之下表面延伸 於開口 140a及140b中之部份侍雷性遠接 ==，咖之導孔购或= —⑽或=矣點=或⑽之電性走線（electHcal 可由金屬、金屬A 1來说，電性連接部146a及146b ,、\ 、/屬5金、金屬或金屬合金散佈於其中之基質 matrix)或其他適合之導電材料所 性連接部146&及由石,t , 牛例术口兑電 組人所拟#。φ 中至^ 一個係可由鋁、銅、鈦或其 導二::電性連接冑⑽及_可由相同或相異之 所形成。在某些實施方式中，電性連接部_ ，146b之厚度Te可約介於i微米至i2微米之間，例如 =介於約1微米至10微米之間’或介於約2微米至6微 未之間。誠第2圖僅繪示—導電層，但其他實施方式亦 可包括其它導電層。 —圖示之實施财，電性連接部祕亦用以做為接地 兀件’以減少電磁干擾。電性連接部腸包括接地部份 且接地部份152係鄰近重新分配單元之邊界而配置。 如第2圖所* ’接地部份152係圍繞重新分配單元124之 =少部份邊緣而延伸。更具體地來說，根據以下所述之製 $序，電性連接部146b係為接地環（g_dingring) =一組接地條（groundingstrip)。請參照第2圖，接地部 2 152包括連接表面si及S2，且連接表面S1及S2係為 背對封裴件1〇〇内部之側表面並鄰近於重新分配單元124 201118994201118994 TW5768F is electrically connected to the grounding contact pad 112b and the grounding of the electrical connection is more and more defamatory, ^ package j Wang Hao point 144b. The '%% connecting portion 14 and the portion 146b include the additional portions of the openings 140a and 140b located at the other end of the opening. / and a part of the opening 140a and 140b extending along the lower surface of the dielectric layer 136, the lightning strike distance ==, the coffee guide hole purchase or = (10) or = 矣 point = or (10) electrical trace (electHcal may be metal, metal A1, electrical connection portions 146a and 146b, \, / 5 gold, metal or metal alloy in which matrix matrix is interspersed) or other suitable conductive material connection 146 & And by the stone, t, cattle, the case of the mouth of the group of electricity. φ 中至^ A system can be made of aluminum, copper, titanium or its two:: electrical connection 胄 (10) and _ can be formed by the same or different. In some embodiments, the thickness Te of the electrical connections _, 146b can be between about 1 micrometer and 2 micrometers, for example, between about 1 micrometer and 10 micrometers, or between about 2 micrometers to 6 micrometers. Micro is not between. 2 is only shown as a conductive layer, but other embodiments may include other conductive layers. - The implementation of the illustration, the electrical connection is also used as a grounding device to reduce electromagnetic interference. The electrical connection portion of the intestine includes a ground portion and the ground portion 152 is disposed adjacent to the boundary of the redistribution unit. As shown in Fig. 2, the 'ground portion 152' extends around the edge of the redistribution unit 124. More specifically, the electrical connection portion 146b is a grounding ring (g_dingring) = a set of groundingstrip according to the manufacturing procedure described below. Referring to FIG. 2, the grounding portion 2 152 includes connection surfaces si and S2, and the connection surfaces S1 and S2 are side surfaces facing away from the inside of the sealing member 1〇〇 and adjacent to the redistribution unit 124 201118994

1 ' TW5768F 之邊緣而配置。更具體地來說，連接表面S1及S2係實質 上於重新分配單元124之邊緣處暴露出來或無遮蔽物，並 分別於鄰近側表面130及132之處暴露出來，以作為電性 連接之用。藉由部份或全部延伸於重新分配單元124之邊 緣，接地部份152提供面積較大之連接表面S1及S2，進 而提供具有更佳的可靠度及效能之電性連接，以減少電磁 干擾。然而，可了解的是，在其他的實施方式中，接地部 份152環繞重新分配單元124之邊緣之範圍可為不同。亦 • 可了解的是，其他實施方式可包括數個不連續之接地元 件，且連接表面S1及S2係指此些接地元件之側表面。 如第1圖及第2圖所示，封裝件100更包括電磁干擾 遮蔽（electromagnetic interference shield) 154。電磁干擾 遮蔽154係鄰近於封裝體114之外部表面、接地部份152 之連接表面S1及S2以及重新分配單元124之侧表面130 及132。電磁干擾遮蔽154係由導電材料所形成，且實質 上環繞封裝件1〇〇内之半導體裝102，以提供防止電磁干 ® 擾之保護。在圖示之實施例中，電磁干擾遮蔽154包括上 部156及側部158。側部158實質上圍繞封裝體114之整 個邊緣延伸，並定義封裝件100之垂直側向形狀。如第2 圖所示，側部158係由上部156向下延伸，並沿著重新分 配單元124之側表面130及132延伸。此外，側部158之 下端係實質上對齊於重新分配單元124之下表面126，或 與下表面126共平面。然而，可了解的是，在其他實施方 式中，側部158之範圍及其下端對齊下表面126之方式可 為不同。 〖 15 2011189941 ' Configuring the edge of the TW5768F. More specifically, the connecting surfaces S1 and S2 are substantially exposed or unobstructed at the edges of the redistribution unit 124 and are exposed at adjacent side surfaces 130 and 132, respectively, for electrical connection. . By extending some or all of the edges of the redistribution unit 124, the ground portion 152 provides a larger area of the connection surfaces S1 and S2, thereby providing an electrical connection with better reliability and performance to reduce electromagnetic interference. However, it will be appreciated that in other embodiments, the extent to which the ground portion 152 surrounds the edge of the redistribution unit 124 can be different. Also, it will be appreciated that other embodiments may include a plurality of discrete ground elements, and the connecting surfaces S1 and S2 refer to the side surfaces of such grounding elements. As shown in FIGS. 1 and 2, the package 100 further includes an electromagnetic interference shield 154. The electromagnetic interference shield 154 is adjacent to the outer surface of the package 114, the connection surfaces S1 and S2 of the ground portion 152, and the side surfaces 130 and 132 of the redistribution unit 124. The electromagnetic interference shield 154 is formed of a conductive material and substantially surrounds the semiconductor package 102 within the package 1 to provide protection against electromagnetic interference. In the illustrated embodiment, the electromagnetic interference shield 154 includes an upper portion 156 and a side portion 158. Side 158 extends substantially around the entire edge of package 114 and defines the vertical lateral shape of package 100. As shown in Fig. 2, the side portions 158 extend downwardly from the upper portion 156 and extend along the side surfaces 130 and 132 of the re-dispensing unit 124. In addition, the lower end of the side portion 158 is substantially aligned with the lower surface 126 of the redistribution unit 124 or coplanar with the lower surface 126. However, it will be appreciated that in other embodiments, the extent of the side portions 158 and the manner in which the lower ends thereof are aligned with the lower surface 126 may be different. 〖 15 201118994

TW5768F 如弟2圖所示，雷朴 連接部1偷之接地^磁干擾遮敝154係電性連接至電性 mnn々“份152之連接表面S1及S2。當由封 時，至電磁補人射至電磁干擾遮蔽154 有效地接地:射可透過電性連接部146b而被 之程度，並減 ,^ 州迎之丰导體裝置之損害。同樣地，告 =近之半導體震置發出之電磁輕射入射田 =二:會發生同樣的接地作用，以減少半導體裝置 、封#件100内之電磁干擾。當運作時，封裝件⑽ :配置於印刷電路板上，並透過電性接點1仏及難電 連接至印刷電路板。如上所述，電性接點1顿係為接 也之電性㈣，且接地之錄接點1桃可電性連接至由 印刷電路板提供之接地電壓。透過包括電性連接部_ 及接地之電性接點丨桃之電性路徑可將人射至電磁干擾 遞蔽154之電磁歸放電至接地端。由於紐連接部離 亦電性連接至半導體裝置1〇2之接地之接觸墊U2b，電性 連接部146b可降低電磁干擾並使半導體裝置1〇2接地， 進而保護封裝件100内之重要區域。然而，可了解的是， 其他的實施方式可包括用以降低電磁干擾《專用的接地 疋件。由於電磁干擾遮蔽154之下端係實質上對齊於重新 分配單元124之下表面126,因此，下端可電性連接至由 印刷電路板提供之接地電壓，進而提供另一種將有害的電 罐韓射放電至接地端的替代電性路徑。 在圖示之實施例中，電磁干擾遮蔽154係為覆蓋 (c〇nformai)遮蔽物，且為一組膜層或薄膜。其優點在於 201118994TW5768F As shown in Figure 2, the Leipu connection part 1 steals the ground ^ magnetic interference concealer 154 is electrically connected to the electrical mnn 々 "part 152 connection surface S1 and S2. When sealed, to electromagnetic supplement The radiation to the electromagnetic interference shielding 154 is effectively grounded: the radiation is transmitted through the electrical connection portion 146b to the extent that it is reduced, and the damage of the conductor device of the state is welcomed. Similarly, the electromagnetic output of the nearby semiconductor is placed. Light shot incident field = two: the same grounding effect will occur to reduce the electromagnetic interference in the semiconductor device and the sealing device 100. When operating, the package (10) is disposed on the printed circuit board and through the electrical contact 1仏 and difficult to connect to the printed circuit board. As mentioned above, the electrical contact 1 is connected to the electrical (four), and the grounding contact 1 can be electrically connected to the ground voltage provided by the printed circuit board. Through the electrical path including the electrical connection part _ and the grounded electrical contact 丨 peach, the electromagnetic radiation from the human electromagnetic interference sinking 154 can be discharged to the ground end. Since the new connection part is also electrically connected to the semiconductor The grounding contact pad U2b of the device 1〇2, the electrical connection portion 146b can be lowered Low electromagnetic interference and grounding of the semiconductor device 1〇2, thereby protecting important areas within the package 100. However, it will be appreciated that other embodiments may include the use of a dedicated grounding element to reduce electromagnetic interference. The lower end of the shield 154 is substantially aligned with the lower surface 126 of the redistribution unit 124. Therefore, the lower end can be electrically connected to the ground voltage provided by the printed circuit board, thereby providing another discharge of the harmful electric canister to the ground. Instead of an electrical path, in the illustrated embodiment, the electromagnetic interference shield 154 is a cover and is a set of layers or films. The advantage is that 201118994

* ' TW5768F 電磁干擾遮蔽154可在不使用黏著劑之情況下鄰近並直接 接觸封裝體114之外部表面，進而提升對於溫度、濕度及 其他環境條件之可靠度及抵抗性。此外，電磁干擾遮蔽154 之覆蓋特性使得相似之電磁干擾遮蔽及相似之製造程序 可快速地應用於不同尺寸及形狀之半導體裝置封裝件，因 而降低應用於不同封裝件之製造成本及時間。在某些實施 方式中，電磁干擾遮蔽154之厚度可介於約1微米至500 微米之間，例如是介於約1微米至100微米之間，介於約 • 1微米至50微米之間，或介於約1微米至10微米之間。 厚度較薄之電磁干擾遮蔽154降低了封裝件之整體尺寸， 因而成為所述之實施例之優點。 第3圖繪示第1圖及第2圖之封裝件100之部份放大 剖面圖。更具體地來說，第3圖繪示鄰近於封裝體114而 配置之電磁干擾遮蔽154之一種實施方式。 如第3圖所示，電磁干擾遮蔽154係為多層之結構並 包括内層300及外層302。内層300係鄰近於封裝體114 ® 而配置，且外層302鄰近内層300配置並暴露於封裝件100 之外部。一般來說，内層300及外層302可由金屬、金屬 合金、金屬或金屬合金散佈其中之基質、或為其他適合之 導電材料所形成。舉例來說，内層300及外層302中至少 一個可由鋁、銅、鉻、錫、金、銀、鎳、不鏽鋼或其組合 而形成。内層300及外層302可由相同或相異之導電材料 所形成。舉例來說，内層300及外層302可由例如是鎳之 金屬所形成。在某些例子中，内層300及外層302可由不 同之導電材料所形成，以提供互補之功能。舉例來說，内t 201118994* ' TW5768F EMI Shield 154 provides proximity and direct contact with the external surface of package 114 without the use of an adhesive, improving reliability and resistance to temperature, humidity and other environmental conditions. In addition, the coverage characteristics of the electromagnetic interference shield 154 allow similar electromagnetic interference masking and similar manufacturing procedures to be quickly applied to semiconductor device packages of different sizes and shapes, thereby reducing the manufacturing cost and time for application to different packages. In some embodiments, the electromagnetic interference shield 154 can have a thickness between about 1 micrometer and 500 micrometers, such as between about 1 micrometer and 100 micrometers, and between about 1 micrometer and 50 micrometers. Or between about 1 micron and 10 microns. The thinner electromagnetic interference shield 154 reduces the overall size of the package and thus is an advantage of the described embodiments. Fig. 3 is a partially enlarged cross-sectional view showing the package 100 of Figs. 1 and 2; More specifically, FIG. 3 illustrates one embodiment of an electromagnetic interference shield 154 disposed adjacent to the package 114. As shown in Fig. 3, the electromagnetic interference shield 154 is a multi-layered structure and includes an inner layer 300 and an outer layer 302. The inner layer 300 is disposed adjacent to the package 114®, and the outer layer 302 is disposed adjacent to the inner layer 300 and exposed to the exterior of the package 100. Generally, inner layer 300 and outer layer 302 may be formed from a matrix of metal, metal alloy, metal or metal alloy, or other suitable electrically conductive material. For example, at least one of the inner layer 300 and the outer layer 302 may be formed of aluminum, copper, chromium, tin, gold, silver, nickel, stainless steel, or a combination thereof. Inner layer 300 and outer layer 302 may be formed from the same or different electrically conductive materials. For example, inner layer 300 and outer layer 302 may be formed of a metal such as nickel. In some examples, inner layer 300 and outer layer 302 can be formed from different electrically conductive materials to provide complementary functionality. For example, inside t 201118994

TW5768F 層300可由具有咼導電性之金屬所形成以提供電磁干擾遮 蔽作用’此處之咼導電性之金屬例如是銘、銅、金或銀， 用。另一方面，外層302可由具有導電性略低之金屬所形 成以保護内層300抵抗氧化、濕度及其他環境條件，此處 之導電性略低之金屬例如是鎳。在此情況下，外層302可 提供電磁干擾遮蔽作用，亦可具有保護之功能。雖然第3 圖中係為兩層之結構，可了解的是，其他實施方式可包括 較多或較少膜層。 第4圖繪示依照本發明之另一實施例之晶圓級半導 體裝置封裝件400之剖面圖。如第4圖所示，封裝件4〇〇 包括封裝體414、重新分配單元424、電性接點444a、444b、 444c及444d與電磁干擾遮蔽454。部份之封裝件4〇〇與 如述之第1圖中之封裝件1 〇〇相似，因此不重複敘述。 請參照第4圖，封裝件400係為多裝置配置，並包括 多個半導體裝置402a、402b及402c。在圖示之實施例中， 半導體裝置402a及402c係為半導體晶片，且半導體裝置 402b為被動元件，例如是電阻器、電容器或 第4圖包括三個半導體裝置，可了解的是，其^施= 可包括較多或較少半導體裝置。 請繼續參照第4圖，重新分配單元424包括電性連接 部446a及446b。電性連接部446a係電性連接於半導體裝 置402a之接觸墊412a與電性接點444a。電性連接部446b 係電性連接半導體裝置402a、402b與402c之接地之接觸 墊412b、412c及412d至電性接點444d’且電性接點444d 係為接地之電性接點。更具體地說，電性連接部446b包 201118994 . , 1W3 zoisr 括導孔448b、448c與448d與電性走線450b、45〇c及45〇d。 導孔448b、448c與448d係分別電性連接至接觸墊412b、 412c及412d。電性走線450b係於導孔448b及448c間延 伸’並電性連接導孔448b及448c。電性走線450c係於導 孔448c及448d間延伸，並電性連接導孔448c及448d。 電性走線450d係於導孔448d及接地部份452間延伸’並 電性連接導孔448d及接地部份452。此外，電性走線450d 亦電性連接至接地之電性接點444d。 • 圖示之實施例中，接地部份邾2圍繞至少一部份之重 新分配單元424之邊緣而延伸。更具體地來說，依照後述 之製造程序，接地部份452係為接地環或一組接地條。請 參照第4圖，接地部份452包括連接表面S1，及S2，。連接 表面S1及S2係為背向封裳件4〇〇之内部之側表面且實質 上從重新分配單元424暴露出來。藉由環繞部份或全部之 重新分配單元424之邊緣，接地部份452提供面積較大的 連接表面81’及S2’’進而提升用以減少電磁干擾之電性連 接部的可靠度及效率。然而，可了解的是，在其他的實施 方式中，％繞重新分配單元424之邊緣之接地部份之範圍 可為不同。 第5圖繪示依照本發明之另一實施例之晶圓級半導 體裝置封裝件500之剖面圖。如第5圖所示，封裝件5〇〇 包括半導體裝置502、封裴體514、重新分配單元524、電 性接點544a及544b與電磁干擾遮蔽554。部份之封裝件 500係與上述之第1圖至第3圖中之封裝件1〇〇相似因 此不再重複敘述。 201118994The TW5768F layer 300 may be formed of a metal having germanium conductivity to provide electromagnetic interference shielding. Here, the conductive metal is, for example, ingot, copper, gold or silver. Alternatively, outer layer 302 may be formed of a metal having a slightly lower conductivity to protect inner layer 300 from oxidation, humidity, and other environmental conditions, such as nickel having a slightly lower conductivity. In this case, the outer layer 302 can provide electromagnetic interference shielding and can also have a protective function. Although the structure of the two layers is shown in Fig. 3, it will be appreciated that other embodiments may include more or fewer layers. 4 is a cross-sectional view of a wafer level semiconductor device package 400 in accordance with another embodiment of the present invention. As shown in FIG. 4, the package 4A includes a package 414, a redistribution unit 424, electrical contacts 444a, 444b, 444c, and 444d and an electromagnetic interference shield 454. A part of the package 4 is similar to the package 1 第 in Fig. 1 as described, and therefore the description will not be repeated. Referring to Figure 4, the package 400 is in a multi-device configuration and includes a plurality of semiconductor devices 402a, 402b, and 402c. In the illustrated embodiment, the semiconductor devices 402a and 402c are semiconductor wafers, and the semiconductor device 402b is a passive component, such as a resistor, a capacitor, or the fourth figure includes three semiconductor devices. It can be understood that = may include more or fewer semiconductor devices. Referring to Figure 4, the redistribution unit 424 includes electrical connections 446a and 446b. The electrical connection portion 446a is electrically connected to the contact pad 412a of the semiconductor device 402a and the electrical contact 444a. The electrical connection portion 446b is electrically connected to the ground contact pads 412b, 412c, and 412d of the semiconductor devices 402a, 402b, and 402c to the electrical contacts 444d', and the electrical contacts 444d are grounded electrical contacts. More specifically, the electrical connection portion 446b includes 201118994 . The 1W3 zoisr includes via holes 448b, 448c, and 448d and electrical traces 450b, 45〇c, and 45〇d. The via holes 448b, 448c, and 448d are electrically connected to the contact pads 412b, 412c, and 412d, respectively. The electrical trace 450b extends between the vias 448b and 448c and electrically connects the vias 448b and 448c. The electrical trace 450c extends between the vias 448c and 448d and is electrically connected to the vias 448c and 448d. The electrical trace 450d extends between the via 448d and the ground portion 452 and electrically connects the via 448d and the ground portion 452. In addition, the electrical trace 450d is also electrically connected to the grounded electrical contact 444d. • In the illustrated embodiment, the ground portion 邾2 extends around the edge of at least a portion of the redistribution unit 424. More specifically, the ground portion 452 is a grounding ring or a set of grounding strips in accordance with the manufacturing procedure described later. Referring to Figure 4, the ground portion 452 includes connection surfaces S1, and S2. The joining surfaces S1 and S2 are the side surfaces facing away from the inside of the sealing member 4'' and are substantially exposed from the redistribution unit 424. By surrounding some or all of the edges of the redistribution unit 424, the ground portion 452 provides a larger area of connection surfaces 81' and S2'' to enhance the reliability and efficiency of the electrical connections for reducing electromagnetic interference. However, it will be appreciated that in other embodiments, the range of the ground portion of the edge around the redistribution unit 424 may vary. Figure 5 is a cross-sectional view of a wafer level semiconductor device package 500 in accordance with another embodiment of the present invention. As shown in FIG. 5, the package 5A includes a semiconductor device 502, a package body 514, a redistribution unit 524, electrical contacts 544a and 544b, and an electromagnetic interference shield 554. A part of the package 500 is similar to the package 1 of the above Figs. 1 to 3 and will not be described again. 201118994

TW5768F 請參照第5圖，重新分配單元524包括 遍及渴。電性連接部遍係電性連接半導體 之接觸墊512a至電性接點544a。電性連 、 接於半導體梦署⑽ 电厂逆得。P 546b電性連 ^ 之接地之接觸塾⑽及電性接點 毛接點54仆係為接地之電性接點。更具體 〜兒，電性連接部5畅包括導孔5儀及電性走— 導孔渴電性連接至接地之接觸塾⑽。電性走。 於導孔54扑及接地部份552間延伸，並電性連孔％ 及接地部㈣。此外，電性走線亦電 之電性接點544b。 电f運接至接地 圖示之實施例中’接地部份552 具體地說，依照後述之製造程序，接地部份55^。更 之導孔之殘留部。接地部份552係配置於=為接地 524之介電層536所定義之開口 560中。社參昭^配單元 接地部份552係由導電材料所形成’且導i材料二圖， 填滿開口 ，並實質上垂直地貫穿介貫質上 度。然而，可了解的是，在曰 的整個厚 552之範圍可為不同，他' 實’接地部份 ，地條，取代接地 用。請繼續參照第5圖，接地 二^ h 552並 連接表面S2’’係為背向封裳件5:。内:的：面表面S2，，。 上於重新分配單元524之邊緣暴露出 且^ 二接地部份552提供面積鼓 二物進= 升用以降低電磁干擾之電性 進而提 些實施方式中，接地部份55=可靠度及效率。在某 丨物H2之尚度H及寬度w可介約 20 201118994TW5768F Referring to Figure 5, the redistribution unit 524 includes thirst. The electrical connection portion is electrically connected to the contact pad 512a of the semiconductor to the electrical contact 544a. Electrical connection, connected to the semiconductor dream plant (10) power plant reversed. P 546b Electrical connection ^ Ground contact 塾 (10) and electrical contacts The bristles 54 are grounded electrical contacts. More specifically, the electrical connection portion 5 includes a guide hole 5 and an electrical walking-guide hole that is electrically connected to the ground contact 塾 (10). Electric walk. The guide hole 54 extends between the grounding portion 552 and electrically connects the hole % and the ground portion (4). In addition, the electrical traces are also electrically connected to the contacts 544b. The electric f is transported to the ground. In the illustrated embodiment, the grounding portion 552 is specifically grounded in accordance with the manufacturing procedure described later. The remaining part of the guide hole. The ground portion 552 is disposed in the opening 560 defined by the dielectric layer 536 of the ground 524. The grounding portion 552 is formed of a conductive material and the second material is filled, and the opening is filled and penetrates substantially perpendicularly. However, it can be understood that the range of the entire thickness 552 of the crucible can be different, and the 'real' grounding portion and the ground strip are used instead of the grounding. Continuing to refer to Fig. 5, the grounding surface ^2 552 and the connecting surface S2'' are the back side sealing members 5:. Inside: Surface surface S2,,. The upper portion of the redistribution unit 524 is exposed and the second ground portion 552 provides the area of the drum to reduce the electrical interference of the electromagnetic interference. In some embodiments, the ground portion 55 = reliability and efficiency. The degree H and the width w of a certain object H2 can be about 20 201118994

' TW5768F 於2微米至24微米之間，例如是介於約5微米至i5微米 之間’或介於約8微米至12微米之間。 第6圖綠示依照本發明之另一實施例之晶圓級半導 體裝置封裝件600之剖面圖。如第6圖所示，封裝件6〇〇 包括封裝體614、重新分配單元624、電性接點64軺、6441)、 644c及644d與電磁干擾遮蔽654。部份之封裝 〇〇盥 上述之第1圖至第3圖中之封裝件100以及第5圖之封裝 件500相似，因此不重複敘述。 • 請參照第6圖，封裝件600係為多層結構並包括數個 半導體裝置602a、602及602c。圖示之實施例中，半導體 裝置602a及602c係為半導體晶片，而半導體裝置⑼^ 為被動元件，例如是電阻器、電容器或電感器。雖然第6 圖中包括三個半導體裝置，可了解的是，其他之實施方式 可包括較多或較少半導體裝置。 凊繼續參照第6圖，重新分配單元624包括電性連接 部646a及646b。電性連接部646a電性連接於半導體裝置 籲 602a之接觸墊612a及電性接點644a。電性連接部646b 係電性連接半導體裝置602a、602b及602c之接地之接觸 墊612b、612c及612d至電性接點644d，且電性接點644d 係為接地之電性接點。更具體地來說’電性連接部646b 包括導孔648b、648c及648d與電性走線650b、650c、 650d。導孔648b、648c及648d係分別電性連接至接地之 接觸墊612b、612c及612d。電性走線650b於導孔648b 與648c之間延伸並電性連接於導孔648b及648c。電性走 線650c於導孔648c與648d之間延伸，並電性連接導孔，'TW5768F is between 2 microns and 24 microns, for example between about 5 microns and i5 microns' or between about 8 microns and 12 microns. Figure 6 is a cross-sectional view of a wafer level semiconductor device package 600 in accordance with another embodiment of the present invention. As shown in FIG. 6, the package 6A includes a package body 614, a redistribution unit 624, electrical contacts 64A, 6441), 644c and 644d, and an electromagnetic interference shield 654. Part of the package 〇〇盥 The package 100 in the above Figs. 1 to 3 and the package 500 in Fig. 5 are similar, and therefore the description will not be repeated. • Referring to Figure 6, the package 600 is of a multi-layer structure and includes a plurality of semiconductor devices 602a, 602, and 602c. In the illustrated embodiment, semiconductor devices 602a and 602c are semiconductor wafers, and semiconductor devices (9) are passive components such as resistors, capacitors or inductors. Although three semiconductor devices are included in Fig. 6, it will be appreciated that other embodiments may include more or fewer semiconductor devices. Referring to Figure 6, the redistribution unit 624 includes electrical connections 646a and 646b. The electrical connection portion 646a is electrically connected to the contact pad 612a and the electrical contact 644a of the semiconductor device 602a. The electrical connection portion 646b electrically connects the ground contact pads 612b, 612c, and 612d of the semiconductor devices 602a, 602b, and 602c to the electrical contacts 644d, and the electrical contacts 644d are grounded electrical contacts. More specifically, the electrical connection portion 646b includes vias 648b, 648c, and 648d and electrical traces 650b, 650c, 650d. The via holes 648b, 648c, and 648d are electrically connected to the ground contact pads 612b, 612c, and 612d, respectively. The electrical traces 650b extend between the vias 648b and 648c and are electrically connected to the vias 648b and 648c. The electrical trace 650c extends between the via holes 648c and 648d and is electrically connected to the via hole.

L 21 201118994L 21 201118994

TW5768F 648c及續。電性走線65〇d於導孔6彻與接 ’ 之間延伸並電性連接於導孔648d及接地部份652。切 線650d亦電性連接至接地之電性接點64二。電性走 例中，接地部份652係為接地之導孔。更且辨貝她 尺丹體地來說，侬 照後述之製造程序，接地部份652係為接地之導孔 部。請參照第ό圖，接地部份652包括連接表面s2”，戔= 接表面S2’”係為背向封裝件600之内部之側表面， 析 上於重新分配單元624之處暴露出來或無遮蔽物。^貝 地，接地部份652提供面積較大之連接表面S2 ”，，進^提 升用以降低電磁干擾之電互連接之可靠度及效率。 第7A圖至第7K圖繪示依照本發明之實施例之晶圓 級半導體封裝件之製造方法。為了方便說明，後述之製造 方法係參照第1圖至第3圖而說明。然而，可了解的^， 製造方法亦可形成其他之半導體裝置封裝件，例如是第4 圖之封裝件400。 請參照第7A圖，提供載具700，且膠帶7〇2係鄰近 於載具700之上表面704而配置。膠帶7〇2可為單面或雙 鲁 面膠帶。膠帶702用以固定一元件’使該元件彼此分隔適 當之距離並使接續之製造程序彳於鄰近於載具700之元件 上進行。 當提供载具700之後，數個半導體裝置可配置於鄰近 膠帶702之處，使得部份之製造程序可快速地平行或連續 進行。半導體裝置包括半導體裝置102及鄰近之半導體裝 置102’。半導體裝置1〇2及102’係於晶圓中形成並彼此相 隔特定之距離，之後對晶圓進行分割程序以分離半導體裝 22 201118994TW5768F 648c and continued. The electrical trace 65 〇d extends between the via 6 and the ground and is electrically connected to the via 648d and the ground portion 652. The tangential line 650d is also electrically connected to the grounded electrical contact 64. In the electrical example, the grounding portion 652 is a grounding via. In addition, it is said that the grounding part 652 is a grounding guide hole according to the manufacturing procedure described later. Referring to the second drawing, the grounding portion 652 includes a connecting surface s2", and the 戋 = connecting surface S2'" is a side surface facing away from the inside of the package 600, exposed or unshielded at the redistribution unit 624. Things. ^Bei, the grounding portion 652 provides a large connecting surface S2", which improves the reliability and efficiency of the electrical interconnection for reducing electromagnetic interference. Figures 7A through 7K illustrate the invention according to the present invention. A method of manufacturing a wafer-level semiconductor package of an embodiment. For convenience of description, a manufacturing method to be described later is described with reference to FIGS. 1 to 3. However, it can be understood that the manufacturing method can also form other semiconductor device packages. The article is, for example, the package 400 of Figure 4. Referring to Figure 7A, the carrier 700 is provided, and the tape 7〇2 is disposed adjacent to the upper surface 704 of the carrier 700. The tape 7〇2 can be single-sided or Double-faced tape. The tape 702 is used to secure an element 'to separate the elements from each other by an appropriate distance and to splicing the subsequent manufacturing process to the component adjacent to the carrier 700. After the carrier 700 is provided, several semiconductor devices It can be disposed adjacent to the tape 702 such that part of the manufacturing process can be performed in parallel or continuously. The semiconductor device includes the semiconductor device 102 and the adjacent semiconductor device 102'. The semiconductor device 1〇2 and 102' Formed and spaced from each other with a certain distance in the wafer, then the wafer is divided to separate the semiconductor device program 22,201,118,994

' · 1W5768F 置102及102’。半導體裝置l〇2及1〇2’與其他的半導體裝 置可以陣列之方式排列於膠帶702上，數個半導體裝置係 以二維之方式排列。或者，數個半導體裝置可為條狀配 置，亦即半導體裝置係線性地連續排列。圖示之實施例 中’與半導體裝置在晶圓中的最鄰近間距（nearest-neighbor spacing)相較，半導體裝置102及102,於載具700上之排 列使半導體裝置彼此間具有較大之最鄰近間距，促使製成 之封裝件可形成扇出配置。然而，可了解的是，其它的實 # 施方式中’半導體裝置102及102’之間距可為不同。為了 方便說明，後述之製造程序係主要地參照半導體裝置1 〇2 及相關元件而敘述。然而，製造程序亦可用以製造其他半 導體裝置及相關元件。 接著，如第7B圖所示，封膠材料7〇6係塗佈於載具 700上，藉以實質上覆蓋或包覆半導體裝置1〇2及1〇2，。 由於半導體裝置102及102’係排列於膠帶7〇2上，封膠材 料706可實質上暴露半導體裝置102及1〇2，之主動表面 鲁104及104’。舉例來說，封膠材料706可包括酚醛基樹脂 (Novolac-based resin)、環氧基樹脂（ep〇xy_based 、 石夕基樹脂（silicone-based resin)或其他適當之包覆劑。封 膠材料706亦可包括適當之填充劑，例如是粉狀之二氧化 石夕。可利用數種封裝技術塗佈封膠材料，例如是壓縮 成型（compression molding )、注射成型（injecti〇n m〇Ming) 或轉注成型（transfer molding)。當塗佈封膠材料7〇6之 後，封膠材料706係被硬化或固化，例如是藉由降低溫度 至封膠材料706之熔點之下，藉以形成封膠結構708。鱗 23 201118994' · 1W5768F sets 102 and 102'. The semiconductor devices 102 and 1'2 and other semiconductor devices may be arranged in an array on the tape 702, and a plurality of semiconductor devices are arranged in two dimensions. Alternatively, the plurality of semiconductor devices may be in a strip configuration, that is, the semiconductor devices are linearly arranged in series. In the illustrated embodiment, the arrangement of the semiconductor devices 102 and 102 on the carrier 700 is such that the semiconductor devices are larger than each other in comparison with the nearest-neighbor spacing of the semiconductor device in the wafer. Adjacent spacing allows the resulting package to form a fan-out configuration. However, it will be appreciated that the distance between the semiconductor devices 102 and 102' may be different in other embodiments. For convenience of explanation, the manufacturing procedure described later is mainly described with reference to the semiconductor device 1 〇 2 and related elements. However, the manufacturing process can also be used to fabricate other semiconductor devices and related components. Next, as shown in Fig. 7B, a sealant material 7〇6 is applied to the carrier 700 to substantially cover or coat the semiconductor devices 1〇2 and 1〇2. Since the semiconductor devices 102 and 102' are arranged on the tape 7〇2, the sealing material 706 can substantially expose the active surfaces Lu 104 and 104' of the semiconductor devices 102 and 1 . For example, the encapsulating material 706 may include a novola-based resin, an epoxy resin (ep〇xy_based, a silicone-based resin, or other suitable coating agent. 706 may also include suitable fillers, such as powdered sulphur dioxide. The encapsulant may be applied by several packaging techniques, such as compression molding, injection molding (injecti 〇 nm 〇 Ming) or Transfer molding. After coating the sealant material 7〇6, the sealant material 706 is hardened or cured, for example, by lowering the temperature below the melting point of the sealant material 706, thereby forming a sealant structure 708. Scales 23 201118994

TW5768F 參照第7B圖，封膠錄構708及被包覆之半導體裝置102 及102’可彼此適當地分隔，促使封裝件形成扇出配置。在 後續的分割程序中，為了使得封膠結構708得以適當地配 置，可於封膠結構708中形成基準標誌（fiducial marks )， 例如是使用雷射標記。 當封膠結構708形成後，封膠結構708及被包覆之半 導體裝置102及102,係與膠帶702分離，並如第7C圖所 示地重新定位至一直立之方位。圖示之實施例中，封膠結 構708 (沿著直立之方位）之上表面710係實質上對齊於 半導體裝置102及102’之主動表面104及104’，或與主動 表面104及104’共平面。雖然未繪示於第7C圖中，可了 解的是，在後續之製造過程中，可使用膠帶固定封膠結構 708 (沿著直立之方位）之下表面712。膠帶可為單面或雙 面膠帶。 之後，於鄰近封膠結構708之上表面710及半導體裝 置102及102’之主動表面104及104’形成一組重新分配 層。請參照第7D圖，利用數種塗佈技術之一種以塗佈介 電材料714，該些塗佈技術例如是印刷（printing )、旋塗 (spinning)或喷塗（spraying)。之後，將介電材料714 圖案化以形成介電層716。圖案化之步驟後，介電層716 具有對齊於主動表面104及104’之開口。開口 140a及140b 之位置及尺寸用以暴露出半導體裝置102之至少部份之接 觸墊112a及112b。介電材料714之圖案化之步驟可以數 種不同之方式完成’例如是微影製程（photolithography )、 化學ϋ 刻（chemical etching)、雷射鑽孔（laser drilling) 24 201118994TW5768F Referring to Figure 7B, the encapsulation recording 708 and the coated semiconductor devices 102 and 102' can be suitably spaced from each other to cause the package to form a fan-out configuration. In a subsequent segmentation procedure, in order for the encapsulation structure 708 to be properly configured, fiducial marks may be formed in the encapsulation structure 708, such as using laser markers. When the encapsulation structure 708 is formed, the encapsulation structure 708 and the coated semiconductor devices 102 and 102 are separated from the tape 702 and repositioned to the upright orientation as shown in Figure 7C. In the illustrated embodiment, the top surface 710 of the encapsulation structure 708 (along the upright orientation) is substantially aligned with the active surfaces 104 and 104' of the semiconductor devices 102 and 102', or with the active surfaces 104 and 104'. flat. Although not shown in Figure 7C, it will be appreciated that in a subsequent manufacturing process, the lower surface 712 of the sealant structure 708 (along the upright orientation) may be secured using tape. The tape can be single or double sided tape. Thereafter, a set of redistribution layers are formed adjacent the upper surface 710 of the encapsulation structure 708 and the active surfaces 104 and 104' of the semiconductor devices 102 and 102'. Referring to Figure 7D, a dielectric material 714 is applied using one of several coating techniques, such as printing, spinning, or spraying. Thereafter, dielectric material 714 is patterned to form dielectric layer 716. After the patterning step, dielectric layer 716 has openings that are aligned with active surfaces 104 and 104'. The openings 140a and 140b are positioned and sized to expose at least a portion of the contact pads 112a and 112b of the semiconductor device 102. The step of patterning the dielectric material 714 can be accomplished in a number of different ways', such as photolithography, chemical etching, laser drilling 24 201118994

‘ 1 TW5768F 或機械鑽孔（mechanical drilling)，因此可形成多種形狀 的開口。開口之形狀包括柱狀或非柱狀’柱狀例如是圓柱 狀、糖圓柱狀、方形柱狀或矩形柱狀’非柱狀例如是圓錐 狀、漏斗狀或其他漸縮之形狀。可了解的是，形成之開口 之側向邊界可為彎曲狀或為粗链之材質。 然後’如第7E圖及第7F圖所示，導電材料718可藉 由數種塗佈技術而塗佈於介電層716並填入由介電層716 定義之開口中’例如是利用化學氣相沈積、無電鍍法 • ( electroless plating )、電解電鍍（eiectr〇lytic plating )、印 刷、旋塗、喷塗、滅鍍（sputtering )或真空沈積法（vacuum deposition)。接著，圖案化導電材料718以形成導電層 720。由圖案化步驟形成之導電層720具有電性連接部。 彼此分離之電性連接部係沿著介電層716之特定部份延 伸，且電性連接部係暴露出介電層716之其他部份。將導 電材料718圖案化之步驟可藉由數種方式完成，例如是微 影製程、化學蝕刻、雷射鑽孔或機械鑽孔。 鲁 第7G圖及第7H圖繪示於圖案化之步驟之後之導電 層720之兩種實施方式之上視圖。第7G圖繪示格狀之導 電層720。導電層720包括一組實質上平行之條狀物與另 一組實質上垂直之平行條狀物，且兩組條狀物係為相交。 第7H圖繪示平行柱狀之導電層720。導電層720包括一 組實質上平行之條狀物。第7G圖及第7H圖中之虛線722 代表將於後續切割程序中形成之切割狹縫的方位及位 置。可了解的是，第7G圖及第7H圖中所繪示之導電層 720之特定的實施方式僅作為範例之用，其他之實施方汽 25 201118994‘ 1 TW5768F or mechanical drilling, thus forming openings of various shapes. The shape of the opening includes a columnar or non-columnar column shape such as a columnar shape, a sugar column shape, a square column shape or a rectangular column shape. The non-columnar shape is, for example, a conical shape, a funnel shape or other tapered shape. It will be appreciated that the lateral boundaries of the formed openings may be curved or of a thick chain. Then, as shown in FIGS. 7E and 7F, the conductive material 718 can be applied to the dielectric layer 716 and filled into the opening defined by the dielectric layer 716 by a plurality of coating techniques, for example, using chemical gas. Electrodeposition, electroless plating, eiectr〇lytic plating, printing, spin coating, spray coating, sputtering or vacuum deposition. Next, conductive material 718 is patterned to form conductive layer 720. The conductive layer 720 formed by the patterning step has an electrical connection. The electrical connections that are separated from each other extend along a particular portion of the dielectric layer 716, and the electrical connections expose other portions of the dielectric layer 716. The step of patterning the conductive material 718 can be accomplished in a number of ways, such as lithography, chemical etching, laser drilling, or mechanical drilling. Lu 7G and 7H illustrate top views of two embodiments of conductive layer 720 after the step of patterning. Fig. 7G shows a grid-shaped conductive layer 720. Conductive layer 720 includes a set of substantially parallel strips and another set of substantially perpendicular parallel strips, and the two sets of strips are intersecting. FIG. 7H illustrates a parallel columnar conductive layer 720. Conductive layer 720 includes a set of substantially parallel strips. The dotted line 722 in Fig. 7G and Fig. 7H represents the orientation and position of the slit slit to be formed in the subsequent cutting process. It can be understood that the specific embodiment of the conductive layer 720 illustrated in the 7G and 7H diagrams is only used as an example, and other implementations of the square steam 25 201118994

TW5768F 中可包括不同之形式。 請參照第71圖，介電材料724可應用數種塗佈技術 之一種塗佈於導電層720及介電層716之暴露之部份，該 些塗佈技術例如是印刷、旋塗或喷塗。接著，圖案化介電 材料724以形成介電層726。由圖案化之步驟形成之介電 層726具有對齊於導電層720之開口。開口 142a及142b 之位置係用以暴露出至少部份之導電層720，且其尺寸係 用以容納銲料凸塊。圖案化介電材料724之步驟可以數種 方式完成，例如是微影製程、化學蝕刻、雷射鑽孔或機械 鑽孔。形成之開口可為數種形狀，包括柱狀及非柱狀。柱 狀可例如是圓柱壯、橢圓柱狀、方形柱狀或矩形柱狀。非 柱狀例如是圓錐狀、漏斗狀或其他漸縮之形狀。可了解的 是，形成之開口之側向邊界可為彎曲狀或粗糙之材質。請 參照第71圖，介電層726、導電層720及介電層716可稱 為重新分配結構728。重新分配結構728係鄰近於封膠結 構708之上表面710而配置，並沿著封膠結構708之上表 面710及半導體裝置102之主動表面104及104’而延伸。 之後，沿著虛線722切割，如第7J圖所示。圖示之 實施例係使用刀具730進行切割，而形成切割狹縫732。 可在切割步驟中使用基準標示輔助對齊刀具730。如此一 來，當形成切割狹縫732時，刀具730得以正確地定位。 具體地來說，切割狹縫732係完全穿過封膠結構708及重 新分配結構728.，藉以將封膠結構708及重新分配結構728 分割為分離單元，此分離單元包括封裝體114及重新分配 單元124。請繼續參照第7J圖，刀具730係側向地放置並 26 201118994Different forms can be included in the TW5768F. Referring to FIG. 71, the dielectric material 724 can be applied to the exposed portions of the conductive layer 720 and the dielectric layer 716 using a plurality of coating techniques such as printing, spin coating or spraying. . Next, dielectric material 724 is patterned to form dielectric layer 726. The dielectric layer 726 formed by the patterning step has openings that are aligned with the conductive layer 720. The openings 142a and 142b are positioned to expose at least a portion of the conductive layer 720 and are sized to receive the solder bumps. The step of patterning the dielectric material 724 can be accomplished in a number of ways, such as lithography, chemical etching, laser drilling, or mechanical drilling. The openings formed can be in a variety of shapes, including columnar and non-columnar. The columnar shape may be, for example, a cylindrical column, an elliptical column, a square column or a rectangular column. The non-columnar shape is, for example, a conical shape, a funnel shape or other tapered shape. It will be appreciated that the lateral boundaries of the formed openings may be curved or rough. Referring to Figure 71, dielectric layer 726, conductive layer 720, and dielectric layer 716 may be referred to as redistribution structure 728. The redistribution structure 728 is disposed adjacent to the upper surface 710 of the encapsulation structure 708 and extends along the surface 710 above the encapsulation structure 708 and the active surfaces 104 and 104' of the semiconductor device 102. Thereafter, it is cut along the broken line 722 as shown in Fig. 7J. The illustrated embodiment uses a cutter 730 for cutting to form a cutting slit 732. The reference mark assisted alignment tool 730 can be used in the cutting step. As such, when the cutting slit 732 is formed, the cutter 730 is properly positioned. In particular, the cutting slit 732 completely passes through the encapsulation structure 708 and the redistribution structure 728. thereby dividing the encapsulation structure 708 and the redistribution structure 728 into separate units, the separation unit including the package 114 and redistribution Unit 124. Please continue to refer to Figure 7J, the cutter 730 is placed laterally and 26 201118994

• ' TW5768F 對齊重新分配結構128,使得電性連接部M6b可做為接地 元件，且連接表面S1及S2係從重新分配單元124之邊緣 暴路出來。在第7G圖之格狀結構的情況下，連接表面S1 f S2係為接地環之側表面。在第7H圖之平行柱狀結構的 f月況下連接表面S1及S2係分別為接地條之側表面。 ^接著，如第7K圖所示，電磁干擾塗層734係鄰近暴 路出的表面而形成，该些暴露出的表面包括封裝體〖Μ之 外部表面、連接表面S1及S2與重新分配單元124之侧表 面130及132。電磁干擾塗層734可使用數種塗佈技術而 =成’例如疋化學氣相沈積、無電鑛法、電解電鍍、印刷、 旋塗噴塗、或真空沈積法。舉例來說，電磁干擾塗 =:34可包括應用無電鑛法形成且材料為鎳之單一膜層， ^厚，至少約5微米’例如是介於約5微米至％微米之 塗/73^:二於約5微米至1〇微米之間。當電磁干擾 你二'件/夕曰結構時’不同膜層可使用相同或不同之塗 佈技術形成。舉例來1 &丄 不忒内層可由銅並使用無電鍍法形 並使用無電鍍法或電解電鍍形成。在另-個例子中，内層Γ # r為土層之用）可由銅並使用濺鍍或無 為抗氧化芦之：：於約1微米至1〇微米之間。外層（做 成，j：严^約 可由不鏽鋼 '鎳或鋼並使用濺鍍法形 战’具知度約不大於】舛 子中，可在電磁干擾塗^^0·1微米之間。在此些例 序，有助於内層及外層：布：表面進行預先處理程 之形成。舉例來說，此些預先處珲, 27 201118994• The 'TW5768F aligns the redistribution structure 128 such that the electrical connection M6b acts as a grounding element and the connection surfaces S1 and S2 emanate from the edge of the redistribution unit 124. In the case of the lattice structure of the 7Gth diagram, the joint surface S1 f S2 is the side surface of the ground loop. The connecting surfaces S1 and S2 are respectively the side surfaces of the grounding strips in the case of the parallel columnar structure of Fig. 7H. Then, as shown in FIG. 7K, the electromagnetic interference coating 734 is formed adjacent to the surface of the storm path, and the exposed surfaces include the outer surface of the package, the connection surfaces S1 and S2, and the redistribution unit 124. Side surfaces 130 and 132. The electromagnetic interference coating 734 can be formed using several coating techniques such as 疋 chemical vapor deposition, electroless plating, electrolytic plating, printing, spin coating, or vacuum deposition. For example, the electromagnetic interference coating =: 34 may comprise a single film layer formed using a non-ferrous mineralization process and having a material of nickel, ^ thick, at least about 5 microns 'eg, between about 5 microns to a few microns of coating / 73 ^: Two between about 5 microns and 1 inch. When electromagnetic interference interferes with your two 'pieces/when's structure', different layers can be formed using the same or different coating techniques. For example, 1 & 丄 The inner layer can be formed of copper and using an electroless plating method and using electroless plating or electrolytic plating. In another example, the inner layer r # r is used for the soil layer) may be copper and may be sputtered or non-oxidized: between about 1 micron and 1 micron. The outer layer (made, j: strict can be made of stainless steel 'nickel or steel and using the sputtering method to shape the warfare' with a degree of knowledge of not more than 舛 中 , , , , 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁These examples help the inner and outer layers: cloth: the surface is pre-processed. For example, these pre-existing, 27 201118994

TW5768F 程序可包括表面粗糙化，例如透過化學蝕刻或機械磨蝕 法，或形成晶種層（seed layer )。將重新分配單元124及 相關元件由膠帶736及載具738分離，例如是使用撿放技 術（pick-and-place technique)，藉以形成包括電磁干擾遮 蔽154之封裝件100。 第8A圖及第8B圖繪示依照本發明之另一實施例之 晶圓級半導體裝置封裝件之製造方法。為了方便說明，後 述之製造程序係參考第5圖之封裝件500而敘述。然而， 可了解的是，此製造程序亦可類似地用以形成其他的半導 體裝置封裝件，例如是第6圖之封裝件600。此外，部份 之製造程序係與上述中第7A圖至第7K圖之製造程序相 同，因而不重複敘述。 請參照第8A圖，介電材料800係塗佈於封膠結構804 之上表面802以及半導體裝置502及鄰近之半導體裝置 502’之主動表面806及806’。之後，圖案化介電材料800 以形成介電層808。經過圖案化之後，介電層808具有對 齊於主動表面806及806’之開口。開口 810a及810b之位 置及尺寸係用以暴露半導體裝置502之至少部份之接觸墊 512a及512b。圖示之實施例中，介電層808亦具有位於 兩相鄰之半導體裝置間之開口，包括開口 810c。開口 810a、810b及810c可為數種形狀，包括柱狀及非柱狀。 柱狀例如是圓柱壯、橢圓柱狀、方形柱狀或矩形柱狀。非 柱狀例如是圓錐狀、漏斗狀或其他漸縮之形狀。可了解的 是，開口 810a、810b及810c之側向邊界可為彎曲狀或為 粗糙材質。 28 201118994The TW5768F program may include surface roughening, such as by chemical etching or mechanical abrasion, or by forming a seed layer. The redistribution unit 124 and associated components are separated by a tape 736 and a carrier 738, such as by using a pick-and-place technique, to form a package 100 that includes an electromagnetic interference shield 154. 8A and 8B illustrate a method of fabricating a wafer level semiconductor device package in accordance with another embodiment of the present invention. For convenience of explanation, the manufacturing procedure described later is described with reference to the package 500 of Fig. 5. However, it will be appreciated that this fabrication process can similarly be used to form other semiconductor device packages, such as package 600 of Figure 6. Further, part of the manufacturing procedure is the same as the manufacturing procedure of Figs. 7A to 7K described above, and thus the description will not be repeated. Referring to FIG. 8A, a dielectric material 800 is applied to the upper surface 802 of the encapsulation structure 804 and the active surfaces 806 and 806' of the semiconductor device 502 and the adjacent semiconductor device 502'. Thereafter, dielectric material 800 is patterned to form dielectric layer 808. After patterning, dielectric layer 808 has openings that align with active surfaces 806 and 806'. The openings 810a and 810b are positioned and sized to expose at least a portion of the contact pads 512a and 512b of the semiconductor device 502. In the illustrated embodiment, dielectric layer 808 also has openings between two adjacent semiconductor devices, including openings 810c. The openings 810a, 810b, and 810c can be in a variety of shapes, including columnar and non-columnar. The columnar shape is, for example, a cylindrical strong, an elliptical column, a square column or a rectangular column. The non-columnar shape is, for example, a conical shape, a funnel shape or other tapered shape. It will be appreciated that the lateral boundaries of the openings 810a, 810b and 810c may be curved or of a rough material. 28 201118994

' · TW5768F 然後，如第8B圖所示，導電材料812塗佈於介電層 808上並填入由介電層808所定義之開口 810a、810b及 810c中。接著，圖案化導電材料812以形成導電層814。 經過圖案化之步驟後，導電層814具有電性連接部及間 隙。電性連接部係沿著介電層808之某些部份延伸。間隙 係介於暴露介電層808之其他部份之電性連接部之間。圖 示之實施例中，導電材料812係被引入開口 810c中，藉 以填入開口 810c中，因而形成接地之導孔816。開口 810c • 之填充可促使連接表面具有較大之面積，進而提升用以減 少電磁干擾之電性連接之可靠度及效率。請繼續參照第8B 圖，接著，沿著虛線818進行分割，使得產生之切割狹縫 移除部份之接地導孔816，形成具有暴露之連接表面的接 地元件。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明。本發明所屬技術領域中具有通 常知識者，在不脫離本發明之精神和範圍内，當可作各種 • 之更動與潤飾。因此，本發明之保護範圍當視後附之申請 專利範圍所界定者為準。此外，為了應用於特定之條件、 材料、物質成分、方法或程序，亦可對於本發明之目的、 精神及範圍作各種更動與潤飾。本發明之保護範圍當包括 此些更動與潤飾。文中揭露之方法係按照特定之順序而敘 述。然而，可了解的是，此些步驟可被合併、分割或重新 排列，以在不脫離本發明之精神下形成等價之方法。除非 特別說明，此些步驟之順序或群組不可視為本發明之限 制。 [ 29 201118994TW5768F Then, as shown in FIG. 8B, conductive material 812 is applied over dielectric layer 808 and filled into openings 810a, 810b, and 810c defined by dielectric layer 808. Next, conductive material 812 is patterned to form conductive layer 814. After the patterning step, the conductive layer 814 has electrical connections and gaps. The electrical connections extend along portions of the dielectric layer 808. The gap is between the electrical connections of the other portions of the exposed dielectric layer 808. In the illustrated embodiment, conductive material 812 is introduced into opening 810c to fill opening 810c, thereby forming grounded vias 816. The filling of the opening 810c can promote a large area of the connecting surface, thereby improving the reliability and efficiency of the electrical connection for reducing electromagnetic interference. Continuing to refer to Figure 8B, then, along the dashed line 818, the resulting slits are removed to remove portions of the ground vias 816 to form ground features having exposed connecting surfaces. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. Those skilled in the art having the knowledge of the present invention can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. In addition, various modifications and refinements may be made to the purpose, spirit, and scope of the present invention in order to apply to particular conditions, materials, compositions, methods or procedures. The scope of protection of the present invention includes such modifiers and retouching. The methods disclosed herein are described in a particular order. However, it is to be understood that the steps may be combined, divided, or rearranged to form an equivalent method without departing from the spirit of the invention. The order or group of such steps is not to be construed as limiting the invention, unless otherwise stated. [ 29 201118994

TW5768F 【圖式簡單說明】 第1圖係繪示依照本發明之實施例之晶圓級半導體 裝置封裝件之立體圖； 第2圖係繪示第1圖之封裝件沿著A-A線之剖面圖； 第3圖繪示第1圖之封裝件之部份放大剖面圖； 第4圖繪示依照本發明之另一實施例之晶圓級半導 體裝置封裝件之剖面圖； 第5圖繪示依照本發明之另一實施例之晶圓級半導 體裝置封裝件之剖面圖； 第6圖繪示依照本發明之另一實施例之晶圓級半導 體裝置封裝件之剖面圖； 第7A圖至第7K圖繪示依照本發明之實施例之晶圓 級半導體封裝件之製造方法；及 第8A圖及第8B圖繪示依照本發明之另一實施例之 第5圖之封裝件之製造方法。 【主要元件符號說明】 100、400、500、600 :半導體裝置封裝件 102、402a、402b、402c ' 502、602a、602 ' 602c : 半導體裝置 104 :半導體裝置之下表面 106 :半導體裝置之上表面 108、110 :半導體裝置之側表面 112a、112b、412a、412b、412c、412d、512a、512b、 30 201118994BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a wafer-level semiconductor device package according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of the package of FIG. 1 taken along line AA; 3 is a partial enlarged cross-sectional view of the package of FIG. 1; FIG. 4 is a cross-sectional view of a wafer-level semiconductor device package according to another embodiment of the present invention; FIG. 6 is a cross-sectional view showing a wafer level semiconductor device package according to another embodiment of the present invention; FIGS. 7A to 7K. A method of fabricating a wafer level semiconductor package in accordance with an embodiment of the present invention; and FIGS. 8A and 8B illustrate a method of fabricating a package according to FIG. 5 of another embodiment of the present invention. [Main component symbol description] 100, 400, 500, 600: semiconductor device package 102, 402a, 402b, 402c '502, 602a, 602' 602c: semiconductor device 104: semiconductor device lower surface 106: semiconductor device upper surface 108, 110: side surfaces 112a, 112b, 412a, 412b, 412c, 412d, 512a, 512b, 30 of the semiconductor device 201118994

' 'TW5768F 612b、612c、612d :接觸塾 114、414、514、614 :封裝體 116 :封裝體之下表面 118 :封裝體之上表面 120、122 :封裝體之側表面 124、424、524、624 :重新分配單元 126:重新分配單元之下表面 128 :重新分配單元之上表面 # 13〇、I32 :重新分配單元之側表面 134、136、536、716、726、808 :介電層 138、720、814 :導電層 140a、140b、142a、142b、560、810a、810b、810c : 介電層之開口 144a、144b ' 444a、444b、444c、444d、544a、544b、 644a、644b、644c、644d :電性接點 146a、146b、446a、446b、546a、546b、646a、646b : ®電性連接部 148a、148、448b、448c、448d、548b、648b、648c、 648d、816 :導孔 150a、150、450b、450c、450d、550b、650b、650c、 650d :電性走線 152、452、552、652 :接地部份 154、454、554、654 :電磁干擾遮蔽 156 :電磁干擾遮蔽之上部 158 :電磁干擾遮蔽之側部 i 31 201118994'TW5768F 612b, 612c, 612d: contact pads 114, 414, 514, 614: package 116: package lower surface 118: package upper surface 120, 122: package side surfaces 124, 424, 524, 624: redistribution unit 126: redistribution unit lower surface 128: redistribution unit upper surface #13〇, I32: redistribution unit side surface 134, 136, 536, 716, 726, 808: dielectric layer 138, 720, 814: conductive layers 140a, 140b, 142a, 142b, 560, 810a, 810b, 810c: openings 144a, 144b' 444a, 444b, 444c, 444d, 544a, 544b, 644a, 644b, 644c, 644d of the dielectric layer Electrical contacts 146a, 146b, 446a, 446b, 546a, 546b, 646a, 646b: ® electrical connections 148a, 148, 448b, 448c, 448d, 548b, 648b, 648c, 648d, 816: vias 150a, 150, 450b, 450c, 450d, 550b, 650b, 650c, 650d: electrical traces 152, 452, 552, 652: ground portion 154, 454, 554, 654: electromagnetic interference shielding 156: electromagnetic interference shielding upper portion 158 : side of electromagnetic interference shielding i 31 201118994

TW5768F 300:電磁干擾遮蔽之内層 302 :電磁干擾遮蔽之外層 700、738 :載具 702、736 :膠帶 704 :載具之上表面 706 :封膠材料 708、804 :封膠結構 710、802 :封膠結構之上表面TW5768F 300: EMI shielding inner layer 302: electromagnetic interference shielding outer layer 700, 738: carrier 702, 736: tape 704: carrier upper surface 706: sealing material 708, 804: sealing structure 710, 802: sealing Glue structure

712 :封膠結構之下表面 714、800 :介電材料 718、724、812 :導電材料 722、818 :虛線 728 ： 重新分配結構 730 ： 刀具 732 ： 切割狹缝 734 ： 電磁干擾塗層 806、 806’ ：主動表面712: encapsulation structure lower surface 714, 800: dielectric material 718, 724, 812: conductive material 722, 818: dashed line 728: redistribution structure 730: cutter 732: cutting slit 734: electromagnetic interference coating 806, 806 ' : Active surface

SI、S2、SI’、S2’、S2，，，：連接表面 32SI, S2, SI', S2', S2,,,: connection surface 32

Claims (1)

201118994 · , ί W^/OiSt- 七、申請專利範圍： 1. 一種半導體裝置封裝件，包括： 一半導體裝置，具有一下表面及複數個側表面並包括 一接觸塾（contact pad )，該些側表面係鄰近該半導體裝置 之一邊緣（periphery)而配置，且該接觸塾係鄰近於該半 導體裝置之該下表面而配置； 一封裝體，覆蓋該半導體裝置之該些側表面，該封裝 體具有一上表面、一下表面及複數個側表面，該封裝體之 φ 該些側表面係鄰近於該封裝體之一邊緣而配置，且該封裝 體之該下表面及該半導體裝置之該下表面定義一前表面； 一組重新分配層（redistribution layer)，鄰近於該前 表面而配置，該組重新分配層具有複數個側表面並包括一 接地元件，該組重新分配層之該些側表面係鄰近於該重新 分配層之一邊緣而配置，且該接地元件包括一連接表面， 該連接表面係從鄰近該組重新分配層之該些側表面中至 少一者暴露出，以作為電性連接之用；以及 φ 一 電磁干擾遮蔽（electromagnetic interference shield)，鄰近於該封裝體之該上表面及該封裝體之該些側 表面配置，該電磁干擾遮蔽電性連接於該接地元件之該連 接表面； 其中，該接地元件提供一電性路徑（electrical pathway )，以將發生在該電磁干擾遮蔽的電磁放射放電至 接地端。 2. 如申請專利範圍第1項所述之半導體裝置封裝 件，其中該接地元件係延伸於該半導體裝置之該接觸墊與 33 201118994 TW5768F /、’且重新勺配層之該些側表面中至少一者之間。 3.如申請專利範圍第2項所述之半導體裝置封裝 '、中”亥組重新分配層更具有一下表面，該半導體^ 封裝件更包括一電性接點（electrical contact )，該气接 點係鄰近於㈣重新分配層而之該下表面而配置， 地元件係t性連触該祕接點。 且雜 4·如申請專利範圍第3項所述之半導體裝置封裝 ^其中5亥電性接點係側向地配置於該半導體裝置之該邊 緣。 w逆 5.如申請專利範圍第^所述之半導體農置封 牛，其中該接地元件包括一第一部份及一第二 ^ 性連接於該半導體裝置之該接觸塾，而該第= 重新分配層之該邊緣配置且該第二部份包括 件 件 件 6·如申請專利範圍第5項所述之半導體裝置封裝 Λ第一邛伤係為一接地環（grounding ring ) 〇 二如申請專利範圍第5項所述之半導體褒置封裝 X第一0戸伤係為一接地條（grounding strip ) 〇 】· Μ請專利範圍第5項所述之半導體裝置封裝 -该第二部份係為一接地導孔之一殘留部 (remnant)。 株I由如申請專利範圍第1項所述之半導體裝置封裝 前表面分配層包括一介電層’該介電層鄰近該 刚表面配置’且該接地元件包括—電性走線（electrical )，該電性走線係沿著該介電層延伸。 34 201118994 ' * TW5768F 申明專利靶圍第1項所述之半導體 件’其中該電磁干擾遮益句拓一 置封褒 靳八Μ括—側卩，關部沿著該組重 新刀配層之該些側表面延伸。 瓜Γ由如申請專利範圍第1〇項所述之半導體裝置封裝 件2中該組重新分配層具有一下表面，該侧部之；端 係只貝上對齊於該組重新分配層之該下表面。 12.半導體裝置封裝件，包括： 一半導體裝置，包括一主動表面； 封H覆蓋該半導體裝置並使該半導體裝置之該 主動表面暴露出，㈣為電性連接之用， 複數個外料面； 括 7重新分配單元’包括-介電層、-電性走線及一接 i =件4介電層㈣於該半導體裝置之社動表面配置 並定義複數個開口’該些開σ對齊於該半導體裝置之該主 動f面’該電性走線沿著該介電層延伸並透過由該介電層 所定義之該些開口中之—者電性連接於該半導财置之9 該主動表面，該接地元件沿著該介電層延伸且包括一側表 面，該接地元件之該側表面鄰近該重新分配單元之 配置；以及 瓊緣 一電磁干擾遮蔽，鄰近於該封裝體之該些外部表面配 置並電性連接於該接地元件之該側表面； 其中，該接地元件提供一電性路徑，以將發生在該電 磁干擾遮蔽的電磁放射放電至接地端。 13.如申凊專利範圍第12項所述之半導體裝置封裝 件’其令該接地元件包括-縣，該部份係鄰近該重新命 35 201118994 TW5768F 邊Γ配置’該部份包括該側表面且該部份為 者接柄、—接地條與-接地導孔之一殘留部中至^ 14.如申請專利範圍第12項 件，❹該接地元件透過由該介電層所定義導之 之另-者電性連接於該半導題裝置之該主開4 15·如申請專利範圍f 12項所述之半 =其h電軒㈣蔽之厚度介 Μ.如申請專利範圍第12項所述之半 件’其中該_分配單元之厚度介於14微米至^^裝 且該接地元件之厚度介於2微米至6微米。 勺括Π.-種半導體裝置封裝件之製造方法，該製造方法 和:供具有一主動表面之一半導體裝置； 塗佈一封膠材料以形成覆蓋該半導體裝置之一封膠201118994 · , ί W^/OiSt- VII. Patent application scope: 1. A semiconductor device package comprising: a semiconductor device having a lower surface and a plurality of side surfaces and including a contact pad, the sides The surface is disposed adjacent to a peripheral of the semiconductor device, and the contact is disposed adjacent to the lower surface of the semiconductor device; a package covering the side surfaces of the semiconductor device, the package having An upper surface, a lower surface, and a plurality of side surfaces, wherein the side surfaces of the package are disposed adjacent to an edge of the package, and the lower surface of the package and the lower surface of the semiconductor device are defined a front surface; a set of redistribution layers disposed adjacent to the front surface, the set of redistribution layers having a plurality of side surfaces and including a grounding member, the side surfaces of the set of redistribution layers being adjacent Arranging at one edge of the redistribution layer, and the grounding element includes a connection surface that is redistributed from adjacent to the group At least one of the side surfaces is exposed for electrical connection; and φ an electromagnetic interference shield adjacent to the upper surface of the package and the side surfaces of the package The electromagnetic interference shielding is electrically connected to the connecting surface of the grounding component; wherein the grounding component provides an electrical pathway to discharge electromagnetic radiation generated by the electromagnetic interference shielding to the grounding end. 2. The semiconductor device package of claim 1, wherein the grounding component extends from the contact pad of the semiconductor device and at least 33 of the side surfaces of the re-spraying layer Between one. 3. The semiconductor device package of the invention of claim 2, wherein the central group redistribution layer further has a lower surface, the semiconductor package further comprising an electrical contact, the gas contact The device is disposed adjacent to the (4) redistribution layer and the lower surface is connected to the contact point. The semiconductor device package of the third aspect of the patent application is as follows: The contact is laterally disposed on the edge of the semiconductor device. The semiconductor device of the semiconductor device of the invention, wherein the grounding component comprises a first portion and a second portion. Connected to the contact port of the semiconductor device, and the edge portion of the first redistribution layer is disposed and the second portion includes the device member. 6. The semiconductor device package as described in claim 5 is first. The injury system is a grounding ring. The second type of semiconductor package is as described in the fifth paragraph of the patent application. The first zero flaw is a grounding strip. Μ Semiconductor package The package-the second portion is a remnant of a ground via hole. The semiconductor device package front surface distribution layer according to claim 1 includes a dielectric layer 'the dielectric The layer is disposed adjacent to the rigid surface and the grounding element includes an electrical electrical line extending along the dielectric layer. 34 201118994 ' * TW5768F Declaring the patent target as described in item 1 In the semiconductor device, wherein the electromagnetic interference is covered by the 句 Μ — — 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩The set of redistribution layers in the semiconductor device package 2 has a lower surface, and the end portions are aligned on the lower surface of the set of redistribution layers. 12. The semiconductor device package comprises: a semiconductor device comprising an active surface; a cover H covering the semiconductor device and exposing the active surface of the semiconductor device, (4) for electrical connection, a plurality of external materials; 7 re-distribution unit a layer, an electrical trace, and an i = 4 dielectric layer (4) disposed on the social surface of the semiconductor device and defining a plurality of openings 'the open σ is aligned with the active f-plane of the semiconductor device' The active trace extends along the dielectric layer and is electrically connected to the active surface of the semiconductor via the dielectric layer defined by the dielectric layer. The ground element is along the dielectric The layer extends and includes a side surface, the side surface of the grounding member is adjacent to the redistribution unit; and the rim is shielded by electromagnetic interference, and the external surfaces adjacent to the package are disposed and electrically connected to the ground element The side surface; wherein the grounding element provides an electrical path to discharge electromagnetic radiation that is shielded by the electromagnetic interference to the ground. 13. The semiconductor device package of claim 12, wherein the grounding component comprises a county, the portion is adjacent to the re-orientation 35 201118994 TW5768F edge configuration "the portion includes the side surface and The portion is in the residual portion of the grounding strip, the grounding strip and the grounding via hole, and is in accordance with item 12 of the patent application scope, wherein the grounding element is guided by the dielectric layer. - the main opening of the semi-guided device is electrically connected to the semi-guided device 4 15 · as described in the patent claim f 12 half of the thickness = its thickness of the second (four) cover. As described in claim 12 The half piece 'where the thickness of the distribution unit is between 14 micrometers and the thickness of the grounding element is between 2 micrometers and 6 micrometers. a method of manufacturing a semiconductor device package, the method of manufacturing: and a semiconductor device having an active surface; coating an adhesive material to form an adhesive covering the semiconductor device 結構’該半導體裝置之該主動表面中至少―部份係從該封 膠材料中暴露出； 形成一重新分配結構於鄰近該半導體裝置之該主動 表面之處，該重新分配結構包括一電性連接部（electHcai mterx0nnect) ’該電性連接部係側向地延伸於該重新分配 結構中； 形成複數個切割狹縫’該些切割狹縫係穿過該封膠結 構及該重新分配結構，該些切割狹縫對齊於該重新分配結 構’用以分割該重新分配結構以形成一重新分配單元、用 36 201118994 1 * TW5768F 以分割該封膠結構以形成包括複數個外部表面之一封裝 體以及使該電性連接部之一殘留部對應至一接地元件，該 接地元件具有被暴露之一連接表面；以及 塗佈一電磁干擾塗層於該封裝體之該些外部表面及 該接地元件之該連接表面，以形成一電磁干擾遮蔽。At least a portion of the active surface of the semiconductor device is exposed from the encapsulant; a redistribution structure is formed adjacent the active surface of the semiconductor device, the redistribution structure including an electrical connection The portion (electHcai mterx0nnect) 'the electrical connection portion extends laterally in the redistribution structure; forming a plurality of cutting slits' through which the cutting slits pass through the sealing structure and the redistribution structure a cutting slit aligned with the redistribution structure for dividing the redistribution structure to form a redistribution unit, using 36 201118994 1 * TW5768F to divide the encapsulation structure to form a package comprising a plurality of external surfaces and to One of the remaining portions of the electrical connection portion corresponds to a grounding member having a contact surface exposed; and an electromagnetic interference coating is applied to the outer surface of the package and the connecting surface of the ground member To form an electromagnetic interference shield. 3737
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TWI409921B (en) 2013-09-21

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