201115705 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種無核心層封裝基板及其製法，尤指 一種提升電性連接品質之封裝基板及其製法。 【先前技術】 為滿足半導體封装件高積集度（Integration)以及微型 化(Miniaturization)的封裝要求，以提供給多數主被動元件 及線路連接用之封裝基板，逐漸由單層板演變成多層板， 參以在有限的空間下，藉由層間連接技術（Interlayer connection)擴大電路板上可利用的佈線面積，且能配合高 電子密度之積體電路(Integrated circuit)需求。 習知技術之多層電路板係由一核心板及對稱形成於 其兩側之線路增層結構所組成，但因使用核心板將導致導 線長度及整體結構厚度增加，故而難以滿足電子產品功能 不斷提昇且體積卻不斷縮小的使用需求，遂發展出無核心 φ 層（coreless)結構之電路板，以符合縮短導線長度及降低整 體結構厚度、及符合高頻化、微小化的趨勢要求。 而習知無核心層封裝基板之製法，係於一整版面承載 板之相對兩表面上分別形成金屬層、具有打線墊的嵌土里，線 路層、與線路增層結構，然後，將該承載板與其兩表面上 之結構分離，並蝕刻移除該金屬層以外露出該打線塾，、 同時形成兩個整版面封裝基板；最後，將整版面封裂基& 切割，即完成多數之無核心層封裝基板。當該無核心居_ 裝基板應用於承載半導體晶片之封裝時，並以導線電性連 3 ： U1365 201115705 接該打線墊與半導體晶片。 惟，習知無核心層封裝基板之製法中，該具有打線墊 的嵌埋線路層係直接形成於該金屬層上，因而於最終蝕刻 移除該金屬層之步驟中，由於若要將該金屬層完全钱刻移 除，則必須稍微過度蝕刻（over etch)，則部分該嵌埋線路層 (包含打線墊）將同時遭受蝕刻之影響而使得厚度變薄， 且由於外露之受蝕刻面積愈大則蝕刻之速率愈快，最終將 導致部分該嵌埋線路層之厚度過薄，形成該嵌埋線路層之 厚度不均、及表面粗糙度不均等現象，進而容易造成該打 線墊於後續連接導線時電性連接品質不良或失效等問題。 因此，如何避免習知技術中上述之種種問題，實已成 目前亟欲解決的課題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之一目的係提 供一種能有效提升打線墊電性連接品質之無核心層封裝基 板及其製法。 本發明之另一目的係提供一種能有效控制各該打線 墊厚度之無核心層封裝基板及其製法。 為達上述及其他目的，本發明係揭露一種無核心層封 裝基板，係包括：初始構成單元，係具有第一介電層及第 一線路層，該第一介電層具有相對之第一表面及第二表 面，且該第一線路層設於該第一介電層之第一表面上並具 有複數設於該第一介電層中之第一導電盲孔；增層結構， 係設於該第一介電層之第一表面及第一線路層上，該增層 4 111365 201115705 結構具有至少H電層、設於該第二介電層上之第二 •線路層、及設於該第二介電層中且電性連接該第一與第二 .線路層之複數第二導電盲孔；以及喪埋線路層，係嵌設於 g亥第-介電層之第二表面中並電性連接該等第一導電盲 孔，該喪埋線路層具有複數打線墊及複數導電跡線，且各 該打線墊之表面低於該第一介電層之第二表面。 #述之無核4封裝基板復包括第—絕緣保護層，係 設於該第一介電層之第二表面及嵌埋線路層上，且該第一 Φ絕緣保護層具有複數第一絕緣保護層開孔，以令該等打線 蟄之表面對應外露於各該第一絕緣保護層開孔。 刖述之無核心層封裝基板復包括表面處理層，係設於 各該打線墊上，且形成該表面處理層之材料係選自由化學 鍍錄/金、化錄浸金（ENIG)、化鎳鈀浸金（ENEpiG)及 化學鍍錫（JmmersicmTin)所組成之群組中之其中一者。 前述之無核心層封裝基板中，該增層結構最外層之第 _二線路層具有複數植球塾，⑽無核心層封裝基板復包括 設於該增層結構上之第二絕緣保護層，該第二絕 具有複數第二絕緣保護層開孔’以令各該植球塾對應外露 於各該第二絕緣保護層開孔。 本發明復揭露一種無核心層封裝基板之製法，係包 括：-種無核心層封裝基板之製法，係包括：提供—承載 板’係由具有相對兩表面之核心層、分別形成於該核心層 之兩表面的離形膜、及形成於該離形膜上之金屬層所構 成，並於各該金屬層上定義出有效區；於該金屬^依序 111365 5 201115705 形成阻障層及嵌埋線路層，該嵌埋線路層具有複數打線墊 及導電跡線；於該金屬層及嵌埋線路層上形成初始構成單 元，該初始構成單元係具有第一介電層及第一線路層，且 該第一介電層具有相對之第一表面及第二表面，令該嵌埋 線路層嵌設於該第一介電層之第二表面中，且該金屬層設 於該第二表面上，而令該第一線路層設於該第一介電層之 第一表面上，該第一線路層並具有複數設於該第一介電層 中且電性連接該嵌埋線路層之第一導電盲孔；於該第一介 電層之第一表面及第一線路層上形成增層結構，且該增層 結構具有至少一第二介電層、設於該第二介電層上之第二 線路層、及設於該第二介電層中且電性連接該第一與第二 線路層之複數第二導電盲孔；移除各該有效區以外之部 分；移除該離形膜及核心層，以外露出該金屬層，俾形成 初始整版面封裝基板；移除該金屬層及阻障層，以外露出 該第一介電層及嵌埋線路層，俾形成整版面封裝基板，且 各該打線墊之表面低於該第一介電層之第二表面；以及裁 切該整版面封裝基板，以分離成複數無核心層封裝基板。 前述之製法中，該核心層與金屬層之面積係大於該離 形膜之面積，且該離形膜對應該有效區；其中，該金屬層 並包覆該離形膜；或該核心層上復包括黏著材且圍繞該離 形膜，而該金屬層係形成於該離形膜與黏著材上。 前述之製法中，該嵌埋線路層之製法係包括：於該金 屬層上形成阻層，且該阻層中形成複數開口區，以令該金 屬層之部分表面外露於該等開口區；於各該開口區中依序 6 111365 201115705 形成該阻障層及嵌埋線路層；以及移除該阻層。 前述之製法中，該初始構成單元之製法係包括：於該 金屬層及嵌埋線路層上形成該第一介電層；於該第一介電 層形成複數連通該嵌埋線路層之盲孔；以及於該第一介電 層之第一表面上形成該第一線路層，且於各該盲孔中形成 第一導電盲孔，以令該第一線路層藉由該等第一導電盲孔 電性連接至該嵌埋線路層。 前述之製法中，移除該有效區以外之部分係藉由切割 _方式。 前述之製法中，移除該金屬層及阻障層之方式係藉由 蝕刻方式，令該製法復包括於蝕刻該金屬層及阻障層之 前，先於該增層結構上形成防蝕層；以及於蝕刻移除該金 屬層及阻障層之後，移除該防蝕層。 前述之製法復包括於裁切該整版面封裝基板之前，於 該第一介電層之第二表面及嵌埋線路層上形成第一絕緣保 Φ 護層，該第一絕緣保護層並形成複數第一絕緣保護層開 孔，以令該等打線墊之表面對應外露於各該第一絕緣保護 層開孔。 前述之製法復包括於裁切該整版面封裝基板之前，於 各該打線墊上形成表面處理層。 前述之製法復包括於該阻層之開口區中形成該嵌埋 線路層之前，於該阻障層上形成表面處理層，以令該表面 處理層設於該嵌埋線路層與該阻障層之間，當移除該金屬 層及阻障層之後，係外露出該嵌埋線路層上之表面處理層 7 Π1365 201115705 及5亥苐一介蕾a 後，該等 層，且於形成各該第一絕緣保護層開孔之 痛7線墊上之表面處理層對應外露出各該第一絕緣 保護層開孔。 前述之製法中，該增層結構最外層之第二線路層復且 =數植料’又該製法復包括於裁切該整版面封裝基板 续^㈢層結構上形成第二絕緣保護層，且該第二絕 ㈣2具有複數第二絕緣保護層開孔，以令各該植球塾 …卜路於各該第二絕緣保護層開孔。 居 了★本發明係藉由在該阻層之開口區中的金屬 =先形成阻障層後，再形絲埋線路層（包含打線塾及 中良）以使該阻障層於後續蝕刻移除該金屬層的製 ^保護該嵌埋線路層*受烟之影響，俾能有效控制該 ^埋線路層之厚度、厚度均勻性、及表面婦度均勾性， 進而能有效提升該打線墊之電性連接品質。 【貫施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，热悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 凊芩閱第1Α至1J圖，係為本發明所揭露之一種無核 心層封裴基板之製法。 ”" 如第1Α圖所示’提供一承載板20，係由具有相對兩 表面之核心層200、分別形成於該核心層2〇〇之兩表面的 離％暝20卜及形成於該離形膜201上並包覆該離形膜2〇】 的金屬層202所構成’並於各該金屬層202上定義出有效 111365 8 201115705 區A。該承載板20之另一實施態樣，係為具有相對兩表面 之核心層200、分別形成於該核心層200之兩表面的離形 膜201、形成於該核心層200上並圍繞該離形膜2〇1之黏 著材203、及形成於該離形膜201與黏著材2〇3上之金屬 層202所構成，又該離形膜201對應該有欵區A。201115705 VI. Description of the Invention: [Technical Field] The present invention relates to a coreless package substrate and a method for fabricating the same, and more particularly to a package substrate for improving electrical connection quality and a method for fabricating the same. [Prior Art] In order to meet the packaging requirements of semiconductor package high integration and miniaturization, package substrates for most active and passive components and line connections are gradually evolved from single-layer boards to multi-layer boards. In the limited space, the interlayer area available on the board can be expanded by Interlayer connection, and it can meet the requirements of integrated circuits with high electron density. The multi-layer circuit board of the prior art is composed of a core board and a circuit-added structure symmetrically formed on both sides thereof, but the use of the core board will result in an increase in the length of the wire and the thickness of the overall structure, so that it is difficult to meet the continuous improvement of the functions of the electronic products. With the ever-shrinking use of the volume, a circuit board with no core φ layer (coreless) structure has been developed to meet the trend of shortening the wire length and reducing the overall structure thickness, and meeting the trend of high frequency and miniaturization. The conventional method for manufacturing a core-free package substrate is formed by forming a metal layer, a grounding layer with a wire pad, a circuit layer, and a line-adding structure on opposite surfaces of a full-page carrier plate, and then carrying the carrier The plate is separated from the structure on both surfaces thereof, and the metal layer is etched away to expose the wire 塾, and at the same time, two full-face package substrates are formed; finally, the whole plate sealing base & cutting is completed, that is, most of the coreless Layer package substrate. When the coreless package substrate is applied to a package carrying a semiconductor wafer, the wire pad and the semiconductor wafer are connected by a wire electrically connected 3: U1365 201115705. However, in the conventional method for manufacturing a core-free package substrate, the buried wiring layer having the bonding pad is directly formed on the metal layer, so in the step of finally etching to remove the metal layer, since the metal is to be If the layer is completely removed, it must be slightly over-etched, and part of the embedded circuit layer (including the wire pad) will be affected by the etching to make the thickness thinner, and the exposed area is larger due to the exposure. The faster the etching rate, the result is that the thickness of part of the embedded circuit layer is too thin, the thickness of the embedded circuit layer is uneven, and the surface roughness is uneven, and the wire bonding pad is easily caused to be connected to the subsequent connecting wire. Problems such as poor quality or failure of electrical connections. Therefore, how to avoid the above-mentioned various problems in the prior art has become a problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above various deficiencies of the prior art, it is an object of the present invention to provide a coreless package substrate capable of effectively improving the electrical connection quality of a wire bonding pad and a method of fabricating the same. Another object of the present invention is to provide a coreless package substrate capable of effectively controlling the thickness of each of the wire bonding pads and a method of fabricating the same. To achieve the above and other objects, the present invention discloses a coreless package substrate, comprising: an initial constituent unit having a first dielectric layer and a first circuit layer, the first dielectric layer having a first surface opposite to the first surface And a second surface, the first circuit layer is disposed on the first surface of the first dielectric layer and has a plurality of first conductive blind holes disposed in the first dielectric layer; The first surface of the first dielectric layer and the first circuit layer, the build-up layer 4 111365 201115705 structure has at least an H electric layer, a second circuit layer disposed on the second dielectric layer, and a plurality of second conductive blind vias electrically connected to the first and second circuit layers in the second dielectric layer; and a buried circuit layer embedded in the second surface of the ghai-dielectric layer The first conductive via is electrically connected to the buried wiring layer, and the buried wiring layer has a plurality of wire pads and a plurality of conductive traces, and a surface of each of the wire pads is lower than a second surface of the first dielectric layer. The non-core 4 package substrate includes a first insulating protective layer disposed on the second surface of the first dielectric layer and the embedded circuit layer, and the first Φ insulating protective layer has a plurality of first insulating protection layers The layers are opened such that the surfaces of the wires are exposed to the openings of the first insulating protective layer. The non-core layer package substrate includes a surface treatment layer, which is disposed on each of the wire bonding pads, and the material forming the surface treatment layer is selected from the group consisting of electroless plating/gold, chemical immersion gold (ENIG), and nickel-palladium. One of a group consisting of ENEpiG and JmmersicmTin. In the foregoing coreless package substrate, the second to fourth circuit layer of the outermost layer of the buildup structure has a plurality of ball bumps, and (10) the coreless package substrate comprises a second insulating protective layer disposed on the buildup structure. The second device has a plurality of second insulating protective layer openings </ RTI> so that each of the ball slabs is correspondingly exposed to each of the second insulating protective layer openings. The invention discloses a method for manufacturing a coreless package substrate, comprising: a method for manufacturing a coreless package substrate, comprising: providing a carrier layer comprising a core layer having opposite surfaces, respectively formed on the core layer a release film on both surfaces and a metal layer formed on the release film, and defining an effective region on each of the metal layers; forming a barrier layer and embedding the metal layer in the order of 111365 5 201115705 a circuit layer, the embedded circuit layer has a plurality of wire pads and conductive traces; forming an initial constituent unit on the metal layer and the embedded circuit layer, the initial constituent unit having a first dielectric layer and a first circuit layer, and The first dielectric layer has opposite first and second surfaces, and the embedded circuit layer is embedded in the second surface of the first dielectric layer, and the metal layer is disposed on the second surface. The first circuit layer is disposed on the first surface of the first dielectric layer, and the first circuit layer has a plurality of first plurality of dielectric layers disposed in the first dielectric layer and electrically connected to the embedded circuit layer. Conductive blind via; in the first dielectric layer Forming a build-up structure on a surface and the first circuit layer, and the build-up structure has at least one second dielectric layer, a second circuit layer disposed on the second dielectric layer, and the second dielectric layer And electrically connecting the plurality of second conductive blind vias of the first and second circuit layers; removing portions other than the active regions; removing the release film and the core layer, exposing the metal layer, forming a germanium layer An initial surface of the package substrate; removing the metal layer and the barrier layer, exposing the first dielectric layer and the embedded circuit layer, forming a full-surface package substrate, and each of the wire pads has a surface lower than the first dielectric layer a second surface of the electrical layer; and cutting the full-face package substrate to separate into a plurality of coreless package substrates. In the above method, the area of the core layer and the metal layer is larger than the area of the release film, and the release film corresponds to an effective area; wherein the metal layer covers the release film; or the core layer The adhesive material is included and surrounds the release film, and the metal layer is formed on the release film and the adhesive. In the above method, the method for manufacturing the embedded circuit layer comprises: forming a resist layer on the metal layer, and forming a plurality of open regions in the resist layer to expose a portion of the surface of the metal layer to the open regions; The barrier layer and the buried wiring layer are formed in each of the opening regions in sequence 6 111365 201115705; and the resist layer is removed. In the above method, the method for fabricating the initial constituent unit includes: forming the first dielectric layer on the metal layer and the buried wiring layer; and forming a plurality of blind vias connecting the buried wiring layer to the first dielectric layer And forming the first circuit layer on the first surface of the first dielectric layer, and forming a first conductive blind hole in each of the blind holes, so that the first circuit layer is blinded by the first conductive The holes are electrically connected to the embedded circuit layer. In the above method, the portion other than the effective area is removed by the cutting method. In the above method, the metal layer and the barrier layer are removed by etching, and the method is formed to form an anti-corrosion layer on the build-up structure before etching the metal layer and the barrier layer; After the metal layer and the barrier layer are removed by etching, the anti-corrosion layer is removed. The foregoing method further includes forming a first insulating Shield layer on the second surface of the first dielectric layer and the embedded circuit layer before cutting the full-surface package substrate, and forming the first insulating protective layer and forming a plurality The first insulating protective layer is opened to expose the surface of the wire bonding pads to the openings of the first insulating protective layers. The foregoing method further includes forming a surface treatment layer on each of the wire bonding pads before cutting the full-face package substrate. The method further comprises forming a surface treatment layer on the barrier layer before forming the buried circuit layer in the open region of the resist layer, so that the surface treatment layer is disposed on the embedded circuit layer and the barrier layer After removing the metal layer and the barrier layer, the surface treatment layer 7 Π 1365 201115705 and 5 苐 介 介 蕾 a on the embedded circuit layer are exposed, and the layers are formed. The surface treatment layer on the 7-line pad of the insulating layer is correspondingly exposed to expose the openings of the first insulating protection layer. In the above method, the second circuit layer of the outermost layer of the buildup structure is complex and the number of the implants is further formed by forming a second insulating protective layer on the continuous (three) layer structure of the entire surface of the package substrate, and The second permanent (four) 2 has a plurality of second insulating protective layer openings, so that each of the ball slabs is opened in each of the second insulating protective layers. In the present invention, after the metal in the open region of the resist layer is formed, the barrier layer is formed first, and then the wiring layer is buried (including the wire bond and the middle wire) to cause the barrier layer to be subsequently etched. In addition to the protection of the metal layer, the embedded circuit layer* is affected by the smoke, and the thickness of the buried circuit layer, the uniformity of the thickness, and the uniformity of the surface degree are effectively controlled, thereby effectively improving the wire bonding pad. The quality of the electrical connection. [Brief Description] The following describes the embodiments of the present invention by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure herein. Referring to Figures 1 to 1J, the invention is a method for manufacturing a coreless core-sealing substrate disclosed in the present invention. " as shown in Fig. 1 'providing a carrier plate 20 formed by the core layer 200 having opposite surfaces, respectively formed on the surface of the core layer 2, and formed on the Forming a metal layer 202 on the film 201 and covering the release film 2 and defining an effective 111365 8 201115705 area A on each of the metal layers 202. Another embodiment of the carrier 20 is a core film 200 having opposite surfaces, a release film 201 respectively formed on both surfaces of the core layer 200, an adhesive member 203 formed on the core layer 200 and surrounding the release film 2〇, and formed on The release film 201 is formed of a metal layer 202 on the adhesive material 2〇3, and the release film 201 corresponds to the crotch region A.
^ 如第1B圖所示，於該金屬層202上形成阻層21，且 X阻層21中形成複數開口區210’令該金屬層2q2之部分 表面外！於該些開口區2! 〇。所述之阻層21係為一例如： 棋或液‘％光阻等光阻材料(ph_esist)，其係利用印刷、旋 塗或貼合等方式分別形成於該金屬層202上，再藉由曝 影等方式加以圖案化’以於該阻層21中形成圖案化 蝎口區210，而露出部份之金屬層202。 居22mCf所^，於各關° ^ 21°中依序形成阻障 i 23! 23 ’且触埋線路層23具有複數打線 塾231及導電跡線230。As shown in Fig. 1B, a resist layer 21 is formed on the metal layer 202, and a plurality of open regions 210' are formed in the X resist layer 21 so that portions of the metal layer 2q2 are outside the surface! In the open areas 2! 〇. The resist layer 21 is a photoresist material (ph_esist) such as a chess or liquid '% photoresist, which is formed on the metal layer 202 by printing, spin coating or lamination, respectively. The patterning is performed by exposure or the like to form a patterned mask region 210 in the resist layer 21 to expose a portion of the metal layer 202. At 22 mCf, a barrier i 23! 23 ' is sequentially formed in each of the ^^21° and the buried wiring layer 23 has a plurality of wires 231 and conductive traces 230.
弟1D圖所示，移除該阻層 路層23及金屬層202 开)成圖所示，於該金屬層地及嵌埋線路層2 二：:二層240 ;再於該第-介電層240上形成4 二:成里ΓΤ3之盲孔2401;最後於該第， 盲孔二=41，並於該第-介電… 層川藉㈣i第/—導電盲孔冰，以令該第一差 層23，俾使; 電盲孔242電性連接至該細 俾使_ —介電層、第1路層241及第- 111365 9 201115705 電盲孔242構成一初始構成單元％。 24卜 所述之第一介電層240具有相對之第-表面24〇a及 第二表面240b，令該嵌埋線路層23 |設於該第一介電層 240之第二表面24Gb中’且令該金屬層2〇2設於該第二表 面24〇b上，又令該第一線路層241設於該第一介電層24〇 之第-表面24Ga上，又該些第一導電盲孔242係設於該第 介電層240中且電性連接該嵌埋線路層23與第一線路層 如第1F圖所示，於該第-介電層240之第一表面24〇a 及第一線路層241切成增層結構25，且該增層結構25 具有至少一第二介電層250、設於該第二介電層250上之 第二線路層251、及設於該第二介電層250中且電性連接 該第-與第二線路層241,251之複數第二導電盲孔况， 又該增層結構25最外層之第二線路層251具有複數植球塾 253。 依上述之製法中，於形成該第一與第二線路層 241，251時，係先於該第一及第二介電層240,250上及其盲 孔中瓜成導電層’ 由該導電層作爲後續電鑛金屬材料之 電流傳導路徑，而轉電層可*金屬、合金或沉積數層金 屬層所構成如選自鋼、錫、鎳、路、鈦、銅絡合金或錫 !σ σ金^所構成切紐之其巾—者触成，並㈣鑛、蒸 鍵：Ί錢及化學沈積之一者形成；或可使用例如聚乙 炔、聚笨胺或有機硫聚合物等導電高分子材料，而以旋轉 塗佈（SPinC〇atlng)、喷墨印刷（ink-jet printing)或壓印 1Π365 10 201115705 (imprinting )等方式形成該導電層。 如第1G圖所示，藉由切割方式，沿著如第1F圖所示 之切割假想線S，先移除各該有效區A以外之部分；接著， 移除該離形膜201及核心層200,以外露出該金屬層202， 俾形成初始整版面封裝基板2a。 如第1H圖所示，先於該增層結構25上形成防蝕層 30，再移除該金屬層202及阻障層22，以外露出該第一介 電層240之第二表面240b及嵌埋線路層23，且各該打線 Φ 墊231之表面231a低於該第一介電層240之第二表面 240b，最後移除該防蝕層30,俾以形成整版面封裝基板2b。 如第II圖所示，先於該第一介電層240之第二表面 240b及嵌埋線路層23上形成第一絕緣保護層26a，該第一 絕緣保護層26a中並形成複數第一絕緣保護層開孔260a， 以令該些打線墊231之表面231a對應外露於各該第一絕緣 保護層開孔260a，且於該增層結構25上形成第二絕緣保 I 護層26b，該第二絕緣保護層26b中形成複數第二絕緣保 護層開孔260b，以令各該植球墊253對應外露於各該第二 絕緣保護層開孔260b ;接著，再於各該打線墊231上形成 表面處理層27。 如第1J與1Γ圖所示，其中，第1Γ圖係為第1J圖之 俯視圖，藉由切割方式，沿著如第II圖所示之切割假想線 L，裁切該整版面封裝基板2b，以分離成複數無核心層封 裝基板2 ;由第1Γ圖可知，該些打線墊231之表面對應外 露於各該第一絕緣保護層開孔260a。 11 1Π365 201115705 睛參閱第ικ圖，係於該 晶片31;如圖所示，該半^裝基版2上接置—半導體 面3U及非作用面3lb，且曰曰片31係具有相對之作用 墊3H)，藉由導線32電性連接^乍用面313上具有複數電極 連接遠打線墊231與電極墊310, 而該非作用面3ib係固設於該第一絕緣保護層施上，再 於該第一絕緣保護層26a上形成封裝材％，以包覆該半導 體晶片31、導線32及打線墊231。又可於該植球墊253 上形成焊球34，以供接置於一外部電路板上。 本發明係藉由在該阻層21之開口區21〇中形成阻障 層22及嵌埋線路層23’以令該嵌埋線路層23表面與該阻 層21表面齊平，相較於習知技術，本發明可有效 ㈣線路層23之打線塾卻之厚度；再者，藉由切成= 阻障層22再形成該嵌埋線路層23，以於移除該阻障層u 時，各該打線墊231之表面23la係低於該第一介電層曰24 之第二表® 2機’故相較於習知技術之打線墊：於曰介24電0 層，本發明易於控制各該打線墊231之表面粗縫度，而处 有效提升後續該導線32之電性連接品質。 ％ 另請參閱第1C，及1J”圖，於另一實施例中，於各气 開口區2H)中形成該嵌埋線路層23之前，先於該阻障層乂 22上形成表面處理層27’，以令該表面處理層27,設於，二 埋線路層23與阻障層22之間，如第1C，圖张；.人、 m不，於後續 移除該金屬層202及阻障層22之後’於該外露出之山土、 路層23上之表面處理層27及該第一介電層mo上开γ成a 一絕緣保護層26a ,並於該第一絕緣保護層26a中^成^ Π1365 12 201115705 些第一絕緣保護層開孔260a之後，以令各該打線墊231 上之表面處理層27’對應外露於各該第一絕緣保護層開孔 260a，如第1Γ圖所示。本實施例係藉由於各該開口區210 中形成該嵌埋線路層23之前，先於該阻障層22上形成表 面處理層27’，以於移除該阻障層22後，即完成表面粗糙 化作業，令各該打線墊231之表面粗糙度有更佳之均勻 性，俾能有效提升後續該導線32之電性連接品質。 本發明復揭露一種無核心層封裝基板2,如第1J圖所 • 示，係包括初始構成單元24、增層結構25以及嵌埋線路 層23。 所述之初始構成單元24係具有第一介電層240及第 一線路層241，該第一介電層240具有相對之第一表面240a 及第二表面240b，且該第一線路層241設於該第一介電層 240之第一表面240a上並具有複數設於該第一介電層240 中之第一導電盲孔242。 φ 所述之增層結構25係設於該第一介電層240之第一 表面240a及第一線路層241上，該增層結構25具有至少 一第二介電層250、設於該第二介電層250上之第二線路 層251、及設於該第二介電層250中且電性連接該第一與 第二線路層241,251之複數第二導電盲孔252。又該增層 結構25最外層之第二線路層251具有複數植球墊253。 所述之嵌埋線路層23係嵌設於該第一介電層240之 第二表面240b中並電性連接該些第一導電盲孔242,且該 嵌埋線路層23具有複數打線墊231及複數導電跡線230， 13 111365 201115705 又該些打線塾231及導電跡線23〇之表面231&低於該第一 介電層240之第二表面24〇b。 所述之無核心層封裝基板2復包括第一絕緣保護層 26a ’係設於該第一介電層24〇之第二表面24〇b及嵌埋線 路層23上’且遠第一絕緣保護層26a具有複數第一絕緣保 4層開孔260a ’以令該些打線墊231之表面231a對應外 露於各該第一絕緣保護層開孔2 6 〇 a。 所述之無核心層封裝基板2復包括表面處理層 27,27’ ’係設於各該打線墊231上，且形成該表面處理層 27’27’之材料係選自由化學錄錄/金、化錄浸金（ENIG)、 化錦把浸金（ENEHG)及化學鍍錫（I_ersi〇n Tin)所 組成之群組中之其中—者。 所述之無核心層封裝基板2復包括設於該增層結構 25上之第二絕緣保護層遍，且該第二絕緣保護層施具 有複數第二絕緣保護層開孔26Gb，以令各該植球塾253對 應外露於各該第二絕緣保護層開孔260b。 綜上所述’本發明係藉由在該阻層之開口區中的金屬 形，層後’再形成嵌埋線路層（包含打線塾） 埋線於後續餘刻移除該金屬層的製程中保護該嵌 厚卢、;二刻之影響’俾能有效控制該嵌埋線路層之 效，❹例μ說明本發明之原理及其功 制本發明。任何㈣此項技藝之人士均可 Π1365 201115705 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1A至1J圖係為本發明無核心層封裝基板之製法之 示意圖；其中，第1C’及1J”圖係為本發明另一實施例之示 意圖，第1Γ圖係第1J圖之俯視圖；以及1D, the removal of the barrier layer 23 and the metal layer 202 are shown in the figure, in the metal layer and the embedded layer 2 2:: 2 layer 240; and then the first dielectric Forming layer 4 on the layer 240: the blind hole 2401 of the ΓΤ ΓΤ 3; finally in the first, the blind hole two = 41, and in the first - dielectric ... layer Chuan (4) i / / conductive blind hole ice, so that the first A differential layer 23 is electrically connected to the fine via 242, and the dielectric layer, the first via layer 241, and the -111365 9 201115705 electrical blind via 242 form an initial constituent unit %. The first dielectric layer 240 has a first surface 24a and a second surface 240b opposite to each other, and the buried circuit layer 23 is disposed in the second surface 24Gb of the first dielectric layer 240. And the metal layer 2〇2 is disposed on the second surface 24〇b, and the first circuit layer 241 is disposed on the first surface 24Ga of the first dielectric layer 24, and the first conductive The blind via 242 is disposed in the dielectric layer 240 and electrically connected to the buried wiring layer 23 and the first wiring layer as shown in FIG. 1F. The first surface 24 〇 a of the first dielectric layer 240 And the first circuit layer 241 is cut into the build-up structure 25, and the build-up structure 25 has at least one second dielectric layer 250, a second circuit layer 251 disposed on the second dielectric layer 250, and The second dielectric layer 250 is electrically connected to the plurality of second conductive blind vias of the first and second circuit layers 241, 251, and the second wiring layer 251 of the outermost layer of the buildup structure 25 has a plurality of ball bumps 253. In the above method, when the first and second circuit layers 241, 251 are formed, a conductive layer is formed on the first and second dielectric layers 240, 250 and in the blind vias thereof. The current conduction path of the subsequent metallurgical metal material, and the conductive layer can be composed of metal, alloy or deposited metal layers such as steel, tin, nickel, road, titanium, copper alloy or tin! σ σ gold ^ The towel that constitutes the cut-up is touched, and (4) mineral, steamed bonds: one of the money and chemical deposition; or a conductive polymer material such as polyacetylene, poly-amine or organic sulfur polymer, The conductive layer is formed by spin coating (ink-jet printing) or embossing 1Π365 10 201115705 (imprinting). As shown in FIG. 1G, by cutting the imaginary line S as shown in FIG. 1F, portions other than the effective area A are removed first; then, the release film 201 and the core layer are removed. 200, the metal layer 202 is exposed, and the initial full-surface package substrate 2a is formed. As shown in FIG. 1H, the anti-corrosion layer 30 is formed on the build-up structure 25, and the metal layer 202 and the barrier layer 22 are removed, and the second surface 240b of the first dielectric layer 240 is exposed and embedded. The circuit layer 23, and the surface 231a of each of the wire Φ pads 231 is lower than the second surface 240b of the first dielectric layer 240, and finally the etching resist 30 is removed to form a full-face package substrate 2b. As shown in FIG. 2, a first insulating protective layer 26a is formed on the second surface 240b of the first dielectric layer 240 and the embedded wiring layer 23, and a plurality of first insulating layers are formed in the first insulating protective layer 26a. a protective layer opening 260a, such that the surface 231a of the wire bonding pad 231 is exposed to each of the first insulating protective layer openings 260a, and a second insulating protective layer 26b is formed on the build-up structure 25, A plurality of second insulating protective layer openings 260b are formed in the second insulating protective layer 26b, so that the ball-fitting pads 253 are correspondingly exposed to the second insulating protective layer openings 260b; and then formed on each of the bonding pads 231. Surface treatment layer 27. As shown in FIG. 1J and FIG. 1 , wherein the first drawing is a top view of the first J-FIG., the entire surface-encapsulated substrate 2b is cut along the cutting imaginary line L as shown in FIG. The surface of the wire bonding pads 231 is exposed to the first insulating protective layer opening 260a. 11 1Π365 201115705 The reference to the ικ diagram is attached to the wafer 31; as shown in the figure, the half-mounted substrate 2 is connected to the semiconductor surface 3U and the non-active surface 3lb, and the cymbal 31 has a relative function. The pad 3H) is electrically connected to the wire 32. The surface 313 has a plurality of electrodes connected to the distal wire pad 231 and the electrode pad 310, and the non-active surface 3ib is fixed to the first insulating protective layer, and then A package material % is formed on the first insulating protective layer 26a to cover the semiconductor wafer 31, the wires 32, and the bonding pads 231. Solder balls 34 may be formed on the ball bumper 253 for attachment to an external circuit board. In the present invention, the barrier layer 22 and the buried wiring layer 23' are formed in the opening region 21 of the resist layer 21 so that the surface of the embedded wiring layer 23 is flush with the surface of the resist layer 21, compared with the According to the prior art, the present invention can effectively (4) the thickness of the wiring layer 23; further, the buried wiring layer 23 is formed by cutting into the barrier layer 22 to remove the barrier layer u. The surface 23la of each of the wire pads 231 is lower than the second surface of the first dielectric layer 曰24. Therefore, compared with the wire pad of the prior art: the layer is electrically and electrically, and the invention is easy to control. The surface of each of the wire mats 231 has a rough seam, and the electrical connection quality of the subsequent wires 32 is effectively improved. % See also FIGS. 1C, and 1J". In another embodiment, the surface treatment layer 27 is formed on the barrier layer 22 before the buried wiring layer 23 is formed in each of the gas opening regions 2H). ', so that the surface treatment layer 27 is disposed between the buried circuit layer 23 and the barrier layer 22, such as the 1C, the picture; the person, m not, the subsequent removal of the metal layer 202 and the barrier After the layer 22, the surface treatment layer 27 on the exposed surface, the surface treatment layer 27 on the road layer 23, and the first dielectric layer mo are opened to form an insulating protective layer 26a, and in the first insulating protective layer 26a. After the first insulating protective layer opening 260a is formed, the surface treatment layer 27' on each of the bonding pads 231 is exposed to each of the first insulating protective layer openings 260a, as shown in FIG. In this embodiment, the surface treatment layer 27' is formed on the barrier layer 22 before the buried layer 23 is formed in each of the open regions 210, so as to remove the barrier layer 22, that is, The surface roughening operation is completed, so that the surface roughness of each of the wire bonding pads 231 has better uniformity, and the electric power of the subsequent wire 32 can be effectively improved. The present invention recurs a coreless package substrate 2, as shown in Fig. 1J, including an initial constituent unit 24, a buildup structure 25, and an embedded circuit layer 23. The initial constituent unit 24 is The first dielectric layer 240 has a first surface 240a and a second surface 240b, and the first circuit layer 241 is disposed on the first dielectric layer 240. The first surface 240a has a plurality of first conductive vias 242 disposed in the first dielectric layer 240. The buildup structure 25 is disposed on the first surface 240a of the first dielectric layer 240. And the first circuit layer 241, the build-up structure 25 has at least one second dielectric layer 250, a second circuit layer 251 disposed on the second dielectric layer 250, and a second dielectric layer 250. And electrically connecting the plurality of second conductive blind vias 252 of the first and second circuit layers 241, 251. The second circuit layer 251 of the outermost layer of the buildup structure 25 has a plurality of ball pads 253. The layer 23 is embedded in the second surface 240b of the first dielectric layer 240 and electrically connected to the first conductive blind holes. 242, and the embedded circuit layer 23 has a plurality of wire pads 231 and a plurality of conductive traces 230, 13 111365 201115705, and the surface 231 & of the wire 231 and the conductive traces 23 低于 are lower than the first dielectric layer 240 The second surface 24 〇b. The core-free package substrate 2 includes a first insulating protective layer 26a' disposed on the second surface 24b of the first dielectric layer 24 and the embedded circuit layer 23. And the first first insulating protective layer 26a has a plurality of first insulating insulating layers 260a' so that the surface 231a of the bonding pads 231 are exposed to the first insulating protective layer openings 2 6 〇a. The core-free package substrate 2 further includes a surface treatment layer 27, 27'' is disposed on each of the wire bonding pads 231, and the material forming the surface treatment layer 27'27' is selected from the chemical recording/gold, Among the groups consisting of ENIG, enamel gold (ENEHG) and electroless tin plating (I_ersi〇n Tin). The core-free encapsulating substrate 2 includes a second insulating protective layer disposed on the build-up structure 25, and the second insulating protective layer has a plurality of second insulating protective layer openings 26Gb for The ball bump 253 is correspondingly exposed to each of the second insulating protective layer openings 260b. In summary, the present invention is formed by embedding an embedded circuit layer (including a wire bond) in a metal form in the open region of the resist layer, and then embedding the buried circuit layer (including wire bonding) in a subsequent process of removing the metal layer. Protecting the embedded thick layer; the effect of the second moment '俾 can effectively control the effect of the embedded circuit layer, and the example μ illustrates the principle of the present invention and the present invention. Any of the above-mentioned techniques may be modified by the person skilled in the art. 1365 201115705 The above embodiments may be modified without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1J are schematic views showing a method of fabricating a coreless package substrate of the present invention; wherein, the 1C' and 1J" diagrams are schematic views of another embodiment of the present invention, and the first diagram is a top view of the 1J chart;
第1K圖係為本發明無核心層封裝基板接置半導體晶 片之示意圖。 【主要元件符號說明】 2 無核心層封裝基板 2a 初始整版面封裝基板 2b 整版面封裝基板 20 承載板 200 核心層 201 離形膜 202 金屬層 203 黏著材 21 阻層 210 開口區 22 阻障層 23 嵌埋線路層 230 導電跡線 231 打線墊 111365 201115705 231a 表面 24 初始構成單元 240 第一介電層 240a 第一表面 240b 第二表面 2401 盲孑L 241 第一線路層 242 第一導電盲孔 25 增層結構 250 第二介電層 251 第二線路層 252 第二導電盲孔 253 植球墊 26a 第一絕緣保護層 26b 第二絕緣保護層 260a 第一絕緣保護層開孔 260b 第二絕緣保護層開孔 27,27, 表面處理層 30 防蝕層 31 半導體晶片 31a 作用面 31b 非作用面 310 電極墊 32 導線 16 111365 201115705Fig. 1K is a schematic view showing the attachment of a semiconductor wafer to the coreless package substrate of the present invention. [Main component symbol description] 2 Coreless package substrate 2a Initial full face package substrate 2b Full face package substrate 20 Carrier plate 200 Core layer 201 Release film 202 Metal layer 203 Adhesive material 21 Resistive layer 210 Open area 22 Barrier layer 23 Embedded circuit layer 230 conductive trace 231 wire pad 111365 201115705 231a surface 24 initial constituent unit 240 first dielectric layer 240a first surface 240b second surface 2401 blind 孑 L 241 first circuit layer 242 first conductive blind hole 25 Layer structure 250 second dielectric layer 251 second circuit layer 252 second conductive blind hole 253 ball pad 26a first insulating protective layer 26b second insulating protective layer 260a first insulating protective layer opening 260b second insulating protective layer Holes 27, 27, surface treatment layer 30 corrosion proof layer 31 semiconductor wafer 31a active surface 31b non-active surface 310 electrode pad 32 wire 16 111365 201115705
33 34 A33 34 A
L,S 封裝材 焊球 有效區 切割假想線L, S package material solder ball effective area cutting imaginary line