201106455 六、發明說明： 【發明所屬之技術領域】 本發明係有關-種封裝基板及其製法，尤指—種各打 線墊之間均有防護層作區隔之封裝基板及其製法。 【先前技術】 /、衣' 為符合半導體封裝件輕薄短小'多功能、高速度及高 頻化的開發方向’為此’用以承載半導體元件之封裝基板 已朝向細線路及小孔徑發展。 請參閱第^⑺圖，係為一種習知封裝基板；如 圖所示，係提供-具有相對第一及第二表面l〇a，i〇b之核 心板！〇’且該核心板1G係已完成内部線路（圖式中失表 不），於該第-及第二表面心⑽上設有係為銅材之線 路層lla，Ub，並於該核心板1()中具有導電通孔]〇〇以電 性連接該第一及第二表面1〇a，1〇b上之線路層山，爪；再 者，該第-表面K)a上之線路層lla具有複數打線塾u〇a， 而該第二表面H)b上之線路| llb係具有複數植球塾 ⑽’且該核心板1〇及線路層叫爪上設有防焊層 12M2b，於該第一表面1〇a上之防焊層na設有置晶區/， 並於該置晶d Μ 有複數開口丨施， 心又該第二表面⑽上之防焊層⑶具有減= POb ’以露出各該植球墊丨]〇b。 惟，習知防谭層12a之開口 I2〇a係呈長條狀，以令 早-開口 n〇a可外露出複數打線塾n〇a，導致各該打線 墊1心之間並無防焊層]2a作區隔，致使各該打線塾]]〇a Π1285 4 201106455 不僅容易吸濕，且於製作細間距（fine pitch )之線路時， 容易發生電性短路之現象。 再者，於後續製程中，當於該置晶區F上設置半導體 晶片且完成封裝製程後，該半導體裝置必需實施信賴性試 驗，而一般半導體裝置之信賴性評估的加速實驗包括有熱 循環實驗、溫度/濕度/偏壓加速實驗、以及高溫加速實驗， 俾藉由將半導體封裝基板安置在規定之環境條件之下，以 確認該半導體裝置能否正常動作。而在該溫度、濕度與壓 • 力偏高之實驗環境中，若在絕緣物（防焊層12a)與導體 (打線墊ll〇a)之表面形成水薄膜時，則構成該導體之金 屬容易在受到電壓變動影響下即被離子化而形成金屬離子 而溶解於水膜中，當該金屬離子被相鄰導體之電位所吸引 而移動時，一旦接觸到導體時即被還原成金屬，若此一離 子遷移現象持續進行，則該被還原之金屬會發展成樹枝狀 結晶（Dentrite)，最後相鄰的導體（打線墊110a)間將產生 φ 電性連接而造成短路現象。 又，於製作細線路及高密度之封裝基板時，該防焊層 12a,12b容易與銅材（線路層11a,lib)或後續製成之封裝 材（molding component)產生分層問題，導致可靠度不良； 另外，該防焊層12a，12b也不易有效填入該線路層lla5llb 之間的空隙，同樣容易導致可靠度不良。 因此，如何避免習知技術中上述之種種問題，實已成 目前亟欲解決的課題。 【發明内容】 5 ]]]285 201106455 鑑於上述習知技術之種種缺失，本發明之一目的係在 提供一種封裝基板及其製法，能避免習知打線墊容易吸濕 及短路等問題。 本發明之另一目的係在提供一種封裝基板及其製 法，能提升可靠度。 為達上述及其他目的，本發明揭露一種封裝基板，係 包括：基板本體，係由增層結構及設於該增層結構上之第 一防護層所構成，該第一防護層具有複數第一開孔，且該 增層結構具有至少一介電層；以及第一線路層，係設於該 基板本體内，且該第一線路層具有複數嵌設於該增層結構 之介電層中之導電跡線及複數對應設於各該第一開孔中之 打線墊，該導電跡線具有對應各該打線墊之端部，而各該 打線墊之上表面外露於各該第一開孔，且各該打線墊之上 表面低於該第一防護層之上表面，又各該打線墊電性連接 該導電跡線。 前述之封裝基板中，該第一防護層係可為感光或非感 光之介電材；該打線墊之周緣可小於或等於該導電跡線之 端部周緣。 前述之封裝基板中，該增層結構復可具有設於該介電 層上之第二線路層、及複數設於該介電層中且電性連接該 第一與第二線路層之導電盲孔，且最外層之第二線路層具 有複數電性接觸墊；復包括係為防·焊層之第二防護層，係 設於該增層結構上，且該第二防護層形成複數第二開孔， 以令各該電性接觸墊對應外露於各該第二開孔。 6 ]]]285 201106455 前述之封裝基板復可包括表面處理層，係設於各該電 性接觸墊上，且形成該表面處理層之材料係選自由化學鍍 鎳/金、化鎳浸金（ENIG)、化鎳鈀浸金（ENEPIG)、化 學鐘錫（Immersion Tin)及有機保焊劑（OSP)所組成之群 • 組中之其中一者。 本發明復揭露一種封裝基板之製法，係包括：提供一 承載板，係具有相對兩表面，該兩表面上具有離型層；於 該離型層上形成第一防護層，且於該第一防護層上形成複 鲁數第一開孔，以露出部分離型層表面；於各該第一開孔中 形成分離阻障層；於該第一防護層上電鍍形成第一線路 層，且該第一線路層具有複數導電跡線及位於對應各該分 離阻障層上之打線墊，該導電跡線具有對應各該打線墊之 端部；於該第一防護層及第一線路層上形成增層結構；移 除該承載板，以外露出該離型層；以及移除該離型層及分 離阻障層，以形成封裝基板，且各該打線墊之間具有該第 φ 一防護層，並且各該打線墊之上表面外露於各該第一開孔。 前述之製法中，該第一防護層係可為感光或非感光之 介電材；該打線墊之周緣可小於或等於該導電跡線之端部 周緣。 前述之製法中，該增層結構係可具有至少一介電層、 設於該介電層上之第二線路層、及複數設於該介電層中且 電性連接該第一與第二線路層之導電盲孔，且最外層之第 二線路層具有複數電性接觸墊。復包括於該增層結構上形 成第二防護層，且該第二防護層形成複數第二開孔，以令 7 Π1285 201106455 各該電性接觸墊對應外露於各該第二開孔。該第二防護層 係為防焊層。 前述之製法復可包括於各該電性接觸墊上形成表面 處理層，且形成該表面處理層之材料係選自由化學鍍錄/ 金、化鎳浸金（ENIG)、化鎳鈀浸金（ENEPIG)、化學 鍵錫（Immersion Tin )及有機保焊劑（OSP)所組成之群組 中之其中一者。 由上可知，本發明藉由各該打線墊之間均有該第一防 護層作區隔，可避免習知技術之打線墊容易吸濕及短路等 問題；再者，因該第一防護層可選擇與該第一線路層或後 續製成之封裝材具有較佳界面親和性之材質，而不會如習 知產生分層問題，且該第一線路層之導電跡線係嵌設於介 電層中，亦不會產生如習知防焊層不易有效填入線路層之 間的空隙的問題，俾提升可靠度，可利於製作細線路及高 密度之封裝基板。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2H圖，係為本發明所揭露之一種封 裝基板之製法。 如第2A圖所示，提供一承載板20，係具有相對兩表 面，於該兩表面上分別具有離型層2]。 如第2B圖所示，於該離型層21上形成第一防護層 8 ]]1285 201106455 22，且於該第— 出部分離型層21#\曰.形成複數第一開孔220，以露 或非感光之;電/。’其中’該第一防護層22係為感光 形成哕八離 早s 3亚未填滿整個第一開孔220，· 、^刀雜㈣23之材料係為錄㈤）或錫（Sn)， 更二刀離承载板2〇及離型層幻之製程。 程，且門㈣_不’於該第一防護層22上進行線路製 矛王且關方；線路製程之 方式製作線路，彳/並22多，以下係以半加成法_ 第-防護層22、第一=；2為0限’特此述明；首先，於該 汗1孔22〇之孔壁及分離阻障層23上 阻声（二S’再於該導電層2如上形成具有開口區之 铺表示）’接著於該開口區中電鑛形成係為 線路層24’最後再移除該阻層及其覆蓋之導電 所述之導電層24a ± φ α > 、 主要係作爲後續電鍍金屬材料所需 之電流傳導路徑，盆可由今戸尺 、了由i屬、合金或沉積數層金屬層所 構成’如選自銅、錫、锃、^ ’果1〇 '鈦、銅-鉻合金或錫-鉛合 金等所構成之群組之其中-者所組成，係以韻、蒸鑛、 無^電鑛及化學沈積之—者形成；或可使關如聚乙块、 聚苯胺或有機硫聚合物等導電高分子材料，而以旋轉塗佈 (spin coating )、賀墨印刷〇nk jet㈤她名）或壓印 (imprinting)等方式形成該導電層2如。 所述之阻層係為一例如乾膜或液態光阻等光阻層 】]】285 9 201106455 (Photoresist)，其係利用印刷、旋塗或貼合等方式分別形成 於該導電層24a上，再藉由曝光、顯影等方式加以圖案化， 於該阻層中形成圖案化開口區，以顯露部份之導電層24a。 所述之第一線路層24具有複數導電跡線240,240’及 位於對應各該分離阻障層23上之打線墊241，該導電跡線 240,240’具有對應各該打線墊241之端部240a,240a’，而各 該打線墊241係位於各該第一開孔220中，以令各該第一 開孔220中設有分離阻障層23及打線墊241，且令該第一 防護層22有效隔離各該打線墊241 ;其中，該打線墊241 之周緣等於其相對應位置的導電跡線240’之端部240a’周 緣，或該打線墊241之周緣小於其相對應位置的導電跡線 240之端部240a周緣。 如第2E圖所示，於該第一防護層22及第一線路層 24上形成增層結構25，該增層結構25係具有至少一介電 層250、設於該介電層250上之第二線路層251、及複數設 於該介電層250中且電性連接該第一與第二線路層24,251 之導電盲孔252，且最外層之第二線路層251具有複數電 性接觸墊253。 如第2F圖所示，移除該承載板20，以外露出該離型 層21。 如第2G及2G’圖所示，移除該離型層21、分離阻障 層23及其上之導電層24a，以形成基板本體2，且各該打 線墊241之間具有該第一防護層22，並且各該打線墊241 之上表面241a外露於各該第一開孔220 ;其中，該打線墊 10 111285 201106455 241之周緣等於其相對應位置的導電跡線240’之端部 240a’周緣，或該打線墊241之周緣小於其相對應位置的導 電跡線240之端部240a周緣。於本實施例中，該導電跡線 240,240’之端部240a，240a’周緣與該打線墊241之周緣呈 現不同之對應大小形式，係為便於說明；然，同一基板上 的導電跡線之端部周緣與該打線墊之周緣亦可為同樣對應 形式，即全部小於或全部等於；且於實際使用中，將依需 求，令該打線墊之周緣全部小於、全部等於或同時呈現小 • 於及等於其相對應位置的導電跡線之端部周緣。 由於該第一防護層22之各該第一開孔220係對應各 該打線墊241，以令單一第一開孔220外露單一打線墊 241，俾使各該打線墊241之間均有該第一防護層22作區 隔，以避免習知技術之打線墊容易吸濕、於製作細間距之 線路時易發生電性短路等問題。 再者，當進行半導體裝置之信賴性試驗時，因該第一 φ 防護層22設於各該打線墊241之間，以隔離各該打線墊 241，故有效避免相鄰的打線墊241間出現短路現象。 又，於製作細線路及高密度之封裝基板時，因該第一 防護層22係為感光或非感光之介電材，而可以曝光顯影或 雷射形成第一防護層22之第一開孔220。 另外，該些導電跡線240,240’係設於該第一防護層22 上，而各該打線墊241並填入於各該第一開孔220中，相 較於習知之防焊層填入線路層之間的空隙，本發明可改善 習知之可靠度不良之問題。 Π1285 201106455 因該第一防護層22可選擇與該第一線路層24或後續 製成之封裝材具有較佳界面親和性之材質，而不會如習知 防焊層易與封裝材產生分層問題，且該第一線路層24之導 電跡線240,240’係嵌設於介電層250中，亦不會產生如習 知防焊層不易有效填入線路層之間的空隙的問題，俾提升 可靠度，可利於製作細線路及高密度之封裝基板。 如第2H圖所示，於該增層結構25上形成第二防護層 26，且該第二防護層26形成複數第二開孔260，以令各該 電性接觸墊253對應外露於各該第二開孔260 ;其中，該 第二防護層26係為防焊層（solder mask)。 再者，於各該電性接觸墊253及打線墊241上形成表 面處理層2 7，且形成該表面處理層2 7之材料係選自由化 學鍍鎳/金、化鎳浸金（ENIG)、化鎳鈀浸金（ENEPIG)、 化學鍵錫（Immersion Tin )及有機保焊劑（0SP)所組成之 群組中之其中一者。 如第3圖所示，於後續製程中，該封裝基板復可於該 第一防護層22上設置具有作用面30a及非作用面30b之半 導體晶片30，該半導體晶片30之非作用面30b設於該第 一防護層22上，而該半導體晶片30之作用面30a復具有 複數電極墊301，而各該電極墊301藉由焊線31以電性連 接至各該打線墊241上之表面處理層27，並於該第一防護 層22上設有覆蓋該半導體晶片30、焊線31與表面處理層 27的封裝材料32。 本發明復揭露一種封裝基板，係包括基板本體2以及 1Π285 201106455 設於該基板本體2内之當 、 門之罘一線路層24。 構25上之2係由增層結構25及設於該增層結 t 防邊層22所構成，該第一防護拜22#為威 光或非感光之介電材且X層22¼為饮 , 具有複數第一開孔220，且嗜捭層 結構25具有至少一入 ZU丑為〜層 "电層250、設於該介電屌250上之第 二線路層251、》、-私 兒增上之弟 第一 Μ » 钹數设於該介電層250中且電性連接該 :線路Γ線路層24,251之導電盲孔252，且最外層之第 7 3 251具有複數電性接觸墊253。 之介恭圮之第一線路層24具有複數嵌設於該增層結構25 第二；層250中之導電跡線24〇,24〇,及複數對應設於各該 對廡各孔220中之打線墊241，該導電跡線240,240,具有 之:“丁線墊241之端部240a,240a’’而各該打線墊241 1上^^241a外露於各該第—開孔22〇,且各該打線墊241 墊24^ Ϊ 241&低於該第一防護層22之上表面，各該打線 ^ 電性連接該導電跡線240,24〇,，該打線墊241之周 =亚小於或等於該導電跡線240,240，之端部24〇七24〇&,周 所地之封裝基板復包括設於該增層結構25 -Ϊ1. β ^ ^ 工亚马防 曰 <卑二防護層26，且該第二防護層26中形成複數第 一開孔260，以令各該電性接觸墊253對應外露於各該第 一開孔260 ;較佳地，亦包括設於各該電性接觸墊253及 打線墊241上之表面處理層27，且形成該表面處理層27 之材料係選自由化學鍍鎳/金、化鎳浸金（]ENIg)、化鎳 鈀浸金（ENEPIG)、化學鍍錫（Immersi〇n 丁⑺）及有機 η Π1285 201106455 保焊劑（OSP)所組成之群組中之其中一者。 综上所述，本發明之封裝基板及其製法係藉由各該打 線墊之間均有該第一防護層作區隔，以避免習知技術之打 線墊容易吸濕及短路等問題；再者，因該第一防護層可選 擇與該第一線路層或後續製成之封裝材具有較佳界面親和 性之材質，而不會如習知產生分層問題，且該第一線路層 之導電跡線係嵌設於介電層中，亦不會產生如習知防焊層 不易有效填入線路層之間的空隙的問題，俾提升可靠度， 可利於製作細線路及高密度之封裝基板。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1A圖係為習知封裝基板之剖視示意圖； 第1B圖係為習知封裝基板之上視示意圖； 第2A至2H圖係為本發明封裝基板之製法之示意 圖； 其中 ，第2G’圖係為上視示意圖 ;以及 第3 圖係為本發明封裝基板與晶 片結合之示意圖 [主 要元件符號說明】 10 核心板 10a 第一表面 10b 第二表面 14 】]]285 201106455201106455 VI. Description of the Invention: [Technical Field] The present invention relates to a package substrate and a method for fabricating the same, and more particularly to a package substrate having a protective layer separated between each of the wire pads and a method for fabricating the same. [Prior Art] /, 'The clothing' is in line with the development trend of thin, short, multi-functional, high-speed and high-frequency semiconductor packages. The package substrate for carrying semiconductor components has been developed toward thin circuits and small apertures. Please refer to the figure (7), which is a conventional package substrate; as shown in the figure, it is provided with a core plate having opposite first and second surfaces l〇a, i〇b! 〇' and the core board 1G has completed the internal circuit (not shown in the figure), and the circuit layers 11a, Ub of the copper material are provided on the first and second surface cores (10), and the core board is 1 () has a conductive through hole 〇〇 electrically connected to the first and second surfaces 1 〇 a, 1 〇 b on the line layer mountain, claw; further, the line on the first surface K) a The layer 11a has a plurality of wires 塾u〇a, and the line on the second surface H)b has a plurality of ball rafts (10)' and the core plate 1 and the circuit layer are provided with a solder resist layer 12M2b. The solder resist layer na on the first surface 1a is provided with a crystallized area /, and the plurality of openings are applied to the seed crystal d, and the solder resist layer (3) on the second surface (10) has a subtraction = POb 'to expose each of the ball pads 〇b〇. However, the opening I2〇a of the conventional anti-tank layer 12a is elongated, so that the early-opening n〇a can expose the plurality of wires 塾n〇a, resulting in no soldering between the cores of the wire pads 1 The layer 2a is divided, so that each of the wires 塾]]〇a Π1285 4 201106455 is not only easy to absorb moisture, but also causes an electrical short circuit when making a fine pitch line. Furthermore, in the subsequent process, after the semiconductor wafer is disposed on the crystal-forming region F and the packaging process is completed, the semiconductor device must perform a reliability test, and the acceleration test of the reliability evaluation of the general semiconductor device includes a thermal cycle test. The temperature/humidity/bias acceleration test and the high temperature acceleration test are performed by placing the semiconductor package substrate under a predetermined environmental condition to confirm whether the semiconductor device can operate normally. In the experimental environment where the temperature, humidity, and pressure are high, if a water film is formed on the surface of the insulator (solder layer 12a) and the conductor (wire pad 11a), the metal constituting the conductor is easy. When it is affected by the voltage fluctuation, it is ionized to form metal ions and dissolves in the water film. When the metal ions are attracted by the potential of the adjacent conductor, they are reduced to metal when they are contacted with the conductor. When an ion migration phenomenon continues, the reduced metal will develop into dendrites, and finally the adjacent conductors (wire pads 110a) will be electrically connected to each other to cause a short circuit. Moreover, when the thin wiring and the high-density package substrate are fabricated, the solder resist layers 12a, 12b are liable to cause delamination problems with the copper material (the wiring layer 11a, lib) or the subsequently formed molding component, resulting in reliability. In addition, the solder resist layers 12a and 12b are not easily filled in the gap between the wiring layers 11a and 11b, and the reliability is also likely to be poor. Therefore, how to avoid the above-mentioned various problems in the prior art has become a problem that is currently being solved. SUMMARY OF THE INVENTION 5 ]]] 285 201106455 In view of the above-mentioned various deficiencies of the prior art, it is an object of the present invention to provide a package substrate and a method of manufacturing the same, which can avoid the problems of easy moisture absorption and short circuit of the conventional wire bonding pad. Another object of the present invention is to provide a package substrate and a method of manufacturing the same that can improve reliability. To achieve the above and other objects, the present invention discloses a package substrate, comprising: a substrate body, which is composed of a build-up structure and a first protective layer disposed on the build-up structure, the first protective layer having a plurality of first layers Opening the hole, and the layered structure has at least one dielectric layer; and the first circuit layer is disposed in the substrate body, and the first circuit layer has a plurality of dielectric layers embedded in the layered structure The conductive traces and the plurality of wire pads corresponding to the first openings, the conductive traces having ends corresponding to the wire pads, and the upper surfaces of the wire pads are exposed to the first openings, And the upper surface of each of the wire mats is lower than the upper surface of the first protective layer, and each of the wire pads is electrically connected to the conductive traces. In the foregoing package substrate, the first protective layer may be a photosensitive or non-photosensitive dielectric material; the circumference of the wire bonding pad may be less than or equal to the peripheral edge of the conductive trace. In the above package substrate, the build-up structure may have a second circuit layer disposed on the dielectric layer, and a plurality of conductive blinds disposed in the dielectric layer and electrically connected to the first and second circuit layers. The second circuit layer of the outer layer and the outermost layer has a plurality of electrical contact pads; the second protective layer comprising the anti-welding layer is disposed on the build-up structure, and the second protective layer forms a plurality of second layers Opening holes to expose each of the electrical contact pads to each of the second openings. 6]] 285 201106455 The foregoing package substrate may further comprise a surface treatment layer disposed on each of the electrical contact pads, and the material forming the surface treatment layer is selected from the group consisting of electroless nickel/gold and nickel immersion gold (ENIG) One of the group • group consisting of ENEPIG, Immersion Tin and Organic Preservative (OSP). The invention discloses a method for manufacturing a package substrate, comprising: providing a carrier plate having opposite surfaces, wherein the two surfaces have a release layer; forming a first protection layer on the release layer, and Forming a plurality of first openings in the protective layer to expose the surface of the separation layer; forming a separation barrier layer in each of the first openings; forming a first circuit layer on the first protection layer, and the The first circuit layer has a plurality of conductive traces and a wire pad corresponding to each of the separation barrier layers, the conductive traces having ends corresponding to the wire pads; forming on the first protection layer and the first circuit layer a layered structure; removing the carrier sheet to expose the release layer; and removing the release layer and the separation barrier layer to form a package substrate, and each of the wire pads has the first φ-protection layer And the upper surface of each of the wire mats is exposed to each of the first openings. In the above method, the first protective layer may be a photosensitive or non-photosensitive dielectric material; the circumference of the bonding pad may be less than or equal to the periphery of the end of the conductive trace. In the above method, the build-up structure may have at least one dielectric layer, a second circuit layer disposed on the dielectric layer, and a plurality of dielectric layers disposed in the dielectric layer and electrically connected to the first and second layers. The conductive layer has a conductive blind hole, and the outermost second circuit layer has a plurality of electrical contact pads. The second protective layer is formed on the layered structure, and the second protective layer forms a plurality of second openings, so that each of the electrical contact pads of the 7 Π 1285 201106455 is correspondingly exposed to each of the second openings. The second protective layer is a solder resist layer. The foregoing method may include forming a surface treatment layer on each of the electrical contact pads, and the material forming the surface treatment layer is selected from the group consisting of electroless plating/gold, nickel immersion gold (ENIG), and nickel-palladium immersion gold (ENEPIG). ), one of a group of chemical bond tin (Immersion Tin) and organic solder resist (OSP). It can be seen from the above that the first protective layer is separated between each of the wire mats, which can avoid the problem that the wire pad of the prior art is easy to absorb moisture and short circuit; further, because of the first protective layer A material having a better interface affinity with the first circuit layer or a subsequently fabricated package material may be selected without delamination problems as conventionally known, and the conductive traces of the first circuit layer are embedded in the dielectric layer. In the electric layer, there is no problem that the conventional solder resist layer is not easily filled into the gap between the circuit layers, and the reliability is improved, which can facilitate the fabrication of thin wiring and high-density package substrates. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure. Please refer to Figures 2A to 2H, which are a method of manufacturing a package substrate disclosed in the present invention. As shown in Fig. 2A, a carrier plate 20 is provided having opposite surfaces on each of which has a release layer 2]. As shown in FIG. 2B, a first protective layer 8]]1285 201106455 22 is formed on the release layer 21, and a plurality of first openings 220 are formed in the first-part separation type layer 21#\曰. Dew or non-photosensitive; electric /. 'Where the first protective layer 22 is formed by photosensitive sensation, the first s3 is not filled with the entire first opening 220, and the material of the knives (four) 23 is recorded (five) or tin (Sn), The second knife is separated from the carrier board 2 离 and the release layer illusion process. Cheng, and the door (four) _ not 'on the first protective layer 22 on the line to make the spear king and the side; line manufacturing method to make the line, 彳 / 22 more, the following is a semi-additive method _ first - protective layer 22, the first =; 2 is 0 limit 'specially stated here; first, the sound is blocked on the hole wall of the sweat hole 1 hole 22 and the separation barrier layer 23 (two S' and then the conductive layer 2 has an opening formed as above The tile of the zone indicates that 'the subsequent formation of the electric ore formation in the open area is the circuit layer 24' and finally removes the resistive layer and the conductive layer 24a of the conductive layer covered by the conductive layer 24a ± φ α > The current conduction path required for the metal material, the basin can be composed of the current genus, the alloy, or the deposition of several layers of metal layers, such as selected from the group consisting of copper, tin, tantalum, ^ '1' titanium, copper-chromium alloy Or a group consisting of tin-lead alloys, etc., formed by rhyme, steaming, non-electrical or chemical deposits; or polymerizing such as polystyrene, polyaniline or organic sulfur a conductive polymer material such as spin coating, 墨nk jet (5) her name) or embossing The conductive layer 2 is formed by, for example, imprinting. The resist layer is a photoresist layer such as a dry film or a liquid photoresist.] 285 9 201106455 (Photoresist), which is formed on the conductive layer 24a by printing, spin coating or lamination, respectively. Then, by patterning by exposure, development, etc., a patterned opening region is formed in the resist layer to expose a portion of the conductive layer 24a. The first circuit layer 24 has a plurality of conductive traces 240, 240' and a wire pad 241 corresponding to each of the separation barrier layers 23. The conductive traces 240, 240' have end portions 240a, 240a corresponding to the wire pads 241. And each of the wire pads 241 is disposed in each of the first openings 220, so that the first barrier 220 is provided with a separation barrier layer 23 and a wire pad 241, and the first protection layer 22 is effective. Each of the wire pads 241 is isolated; wherein the circumference of the wire pad 241 is equal to the circumference of the end 240a' of the conductive trace 240' at its corresponding position, or the circumference of the wire pad 241 is smaller than the corresponding position of the conductive trace 240 The periphery of the end portion 240a. As shown in FIG. 2E, a build-up structure 25 is formed on the first protection layer 22 and the first circuit layer 24. The build-up structure 25 has at least one dielectric layer 250 disposed on the dielectric layer 250. a second circuit layer 251, and a plurality of conductive vias 252 disposed in the dielectric layer 250 and electrically connected to the first and second circuit layers 24, 251, and the outermost second circuit layer 251 has a plurality of electrical contact pads 253. As shown in Fig. 2F, the carrier sheet 20 is removed and the release layer 21 is exposed. As shown in FIGS. 2G and 2G', the release layer 21, the separation barrier layer 23, and the conductive layer 24a thereon are removed to form the substrate body 2, and the first protection is provided between each of the wire pads 241. The upper surface 241a of the wire pad 241 is exposed to each of the first openings 220; wherein the periphery of the wire pad 10 111285 201106455 241 is equal to the end 240a of the conductive trace 240' at its corresponding position. The circumference, or the circumference of the wire pad 241, is smaller than the circumference of the end 240a of the conductive trace 240 of its corresponding position. In this embodiment, the circumferences of the ends 240a, 240a' of the conductive traces 240, 240' and the periphery of the wire pad 241 are in different corresponding sizes for convenience of explanation; however, the ends of the conductive traces on the same substrate The circumference of the circumference and the circumference of the wire mat may also be in the same corresponding form, that is, all are less than or equal to all; and in actual use, the circumference of the wire mat will be less than, all equal to or at the same time according to the demand. The end of the end of the conductive trace equal to its corresponding position. The first opening 220 of the first protective layer 22 corresponds to each of the wire bonding pads 241, so that the single first opening 220 exposes a single wire bonding pad 241, so that the wire bonding pads 241 have the same A protective layer 22 is partitioned to avoid the problem that the wire pad of the prior art is easy to absorb moisture and is susceptible to electrical short circuit when making fine pitch lines. Moreover, when the reliability test of the semiconductor device is performed, since the first φ protection layer 22 is disposed between each of the wire bonding pads 241 to isolate the wire bonding pads 241, the adjacent wire bonding pads 241 are effectively prevented from appearing. Short circuit phenomenon. Moreover, when the thin circuit and the high-density package substrate are fabricated, the first protection layer 22 is a photosensitive or non-photosensitive dielectric material, and the first opening of the first protection layer 22 can be formed by exposure development or laser irradiation. 220. In addition, the conductive traces 240, 240' are disposed on the first protective layer 22, and each of the bonding pads 241 is filled in each of the first openings 220, and is filled in with the solder resist layer. The present invention can improve the problem of poor reliability in the prior art. Π 1285 201106455 Because the first protective layer 22 can select a material having better interface affinity with the first circuit layer 24 or a subsequently formed package material, without the delamination of the solder resist layer from the package material as is conventional The problem is that the conductive traces 240, 240' of the first circuit layer 24 are embedded in the dielectric layer 250, and the problem that the conventional solder resist layer is not easily filled into the gap between the circuit layers is not caused. Reliability, which can be used to make thin circuits and high-density package substrates. As shown in FIG. 2H, a second protection layer 26 is formed on the build-up structure 25, and the second protection layer 26 forms a plurality of second openings 260, so that the electrical contact pads 253 are correspondingly exposed. a second opening 260; wherein the second protective layer 26 is a solder mask. Further, a surface treatment layer 27 is formed on each of the electrical contact pads 253 and the wire bonding pads 241, and the material forming the surface treatment layer 27 is selected from the group consisting of electroless nickel/gold, nickel immersion gold (ENIG), One of a group of nickel-palladium immersion gold (ENEPIG), chemical bond tin (Immersion Tin), and organic solder resist (0SP). As shown in FIG. 3, in the subsequent process, the package substrate is provided with a semiconductor wafer 30 having an active surface 30a and an inactive surface 30b. The non-active surface 30b of the semiconductor wafer 30 is provided. On the first protective layer 22, the active surface 30a of the semiconductor wafer 30 has a plurality of electrode pads 301, and each of the electrode pads 301 is electrically connected to the surface of each of the bonding pads 241 by bonding wires 31. The layer 27 is provided with an encapsulation material 32 covering the semiconductor wafer 30, the bonding wires 31 and the surface treatment layer 27 on the first protection layer 22. The present invention discloses a package substrate comprising a substrate body 2 and a circuit layer 24 disposed between the door and the substrate body 2 in the substrate body 2. The second structure of the structure 25 is composed of a build-up structure 25 and an anti-edge layer 22 disposed on the build-up layer, the first protective fence 22# being a light or non-photosensitive dielectric material and the X layer 221⁄4 being a drink having a plurality of first openings 220, and the osmotic layer structure 25 has at least one U-U ugly layer, a second layer 251, and a second layer 251 disposed on the dielectric cymbal 250. The first Μ Μ 钹 钹 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The first circuit layer 24 has a plurality of conductive traces 24, 24〇, and a plurality of corresponding conductive holes 220 in each of the pair of holes 220. The wire pad 241, the conductive traces 240, 240, have: "the end portions 240a, 240a" of the wire pad 241, and each of the wire pads 241 1 is exposed to each of the first opening 22, and each The wire pad 241 pads 24^ 241 & are lower than the upper surface of the first protective layer 22, and each of the wires is electrically connected to the conductive traces 240, 24〇, and the circumference of the wire pad 241 is less than or equal to The conductive traces 240, 240, the end portion 24 〇 24 24 〇 &, the surrounding package substrate is included in the build-up structure 25 - Ϊ 1. β ^ ^ Gong Yama 曰 卑 卑 second protective layer 26 And forming a plurality of first openings 260 in the second protective layer 26, so that the electrical contact pads 253 are correspondingly exposed to the first openings 260; preferably, the electrical contacts are also disposed in each of the electrical contacts. The surface treatment layer 27 on the pad 253 and the wire pad 241, and the material forming the surface treatment layer 27 is selected from the group consisting of electroless nickel/gold, nickel immersion gold (=ENIg), and nickel-palladium immersion gold (ENEPIG). One of a group consisting of electroless tin plating (Immersi〇n butyl (7)) and organic η Π 1285 201106455 solder resist (OSP). In summary, the package substrate of the present invention and the method of manufacturing the same are provided by each of the wires The first protective layer is partitioned between the pads to avoid problems such as moisture absorption and short circuit of the prior art wire bonding pad; further, since the first protective layer can be selected and the first circuit layer or subsequent system The encapsulating material has a material with better interface affinity, and does not cause delamination problems as in the prior art, and the conductive traces of the first circuit layer are embedded in the dielectric layer, and no conventional knowledge is generated. The solder resist layer is not easy to fill the gap between the circuit layers, and the reliability is improved, which can facilitate the fabrication of thin lines and high-density package substrates. The above embodiments are used to exemplarily illustrate the principles and effects of the present invention. Rather than limiting the invention, any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be as described below. BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1A] FIG. 1A is a schematic cross-sectional view of a conventional package substrate; FIG. 1B is a top view of a conventional package substrate; and FIGS. 2A to 2H are a method for manufacturing a package substrate of the present invention. FIG. 2 is a schematic view of the top view; and FIG. 3 is a schematic view showing the combination of the package substrate and the wafer of the present invention. [Main component symbol description] 10 core plate 10a first surface 10b second surface 14] ]285 201106455
100 導電通孔 11a,lib 線路層 110a 打線墊 110b 植球墊 12a,12b 防焊層 120a 開口 120b 開孔 2 基板本體 20 承載板 21 離型層 22 第一防護層 220 第一開孔 23 分離阻障層 24 第一線路層 24a 導電層 240,240， 導電跡線 240a,240a， 端部 241 打線墊 241a 上表面 25 增層結構 250 介電層 251 第二線路層 252 導電盲孔 253 電性接觸墊 201106455 26 第二防護層 260 第二開孔 27 表面處理層 30 半導體晶片 30a 作用面 30b 非作用面 301 電極墊 31 焊線 32 封裝材料 F 置晶區 16 1Π285100 conductive through hole 11a, lib circuit layer 110a wire pad 110b ball pad 12a, 12b solder resist layer 120a opening 120b opening 2 substrate body 20 carrier plate 21 release layer 22 first protective layer 220 first opening 23 separation resistance Barrier layer 24 first circuit layer 24a conductive layer 240, 240, conductive traces 240a, 240a, end portion 241 wire pad 241a upper surface 25 build-up structure 250 dielectric layer 251 second circuit layer 252 conductive blind hole 253 electrical contact pad 201106455 26 second protective layer 260 second opening 27 surface treatment layer 30 semiconductor wafer 30a active surface 30b non-active surface 301 electrode pad 31 bonding wire 32 packaging material F crystallizing area 16 1 Π 285