201027535 y /-υζ〇 j〇245twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體記憶體元件之測定方法， 且特別是有關於一種非揮發性記憶體之固有啟始電壓的測 定方法。 【先前技術】 典型的快閃記憶體係以掺雜的多晶石夕製作浮置閘極與 φ 控制閘極。當記憶體進行程式化(Program)時，適當之程式 化之電壓分別加到源極區、汲_極區與控制閘極上，電子將 由源極區經由通道流向没極區。在此過程中，將有部分的 電子會穿過多晶矽浮置閘極層下方的穿隧氧化層，進入並 且會均勻分布於整個多晶矽浮置閘極層之中。此種電子穿 越穿隧氧化層進入多晶矽浮置閘極層的現象，稱為穿隧效 應(Tunneling Effect)。穿隧效應可以分成兩種情況，—種 稱為通道熱電子注入(Channel Hot-Electron Injection)，另一 ❹ 種稱為Fowler-Nordheim穿隧(F-N Tunneling)。通常快閃記 憶體是以通道熱電子程式化，並且通過源極區旁邊或通道 區域以Fowler-Nordheim穿隧抹除。 一般而言，在快閃記憶體製作完畢後，由於每—記憶 胞可旎會受到製程影響，而具有不均勻的啟始電壓，使得 記憶體具有較大的啟始電壓分佈，而可能造成使用上的困 難。因此在出貨之前，通常會利用紫外光充分照射快閃記 憶體，使快閃記憶體的每個記憶胞處於低啟始電壓 (Low丨Vt | )狀態，而達到元件初始化之效果。其中記憶胞 201027535 >/-uz〇 j〇245twf.doc/n 經紫外光充分照射後，所維持的啟始電壓即稱為固有啟始 電壓(Native Threshold Voltage)。 ° 然而’在目前提高記紐元件集積度的趨勢下纪憶 胞的尺寸也相對縮小’而且在峨胞上通常覆蓋有高密度 的金屬層。在使用紫外光照射記憶體肖，紫外光受到金屬 層遮擋不易·至記.it胞，而紐使記憶體達到元件 初始化的效果。而且’由於紫外光無法充分照射記憶胞， 因此記憶胞無法處於时啟始電壓㈣，也無法得知該記 憶胞的固有啟始電壓。 【發明内容】 本發明提供一種非揮發性記憶體之固有啟始電壓的測 定方法’可以容㈣測定出非揮發性記憶體之时啟始電 —本發明提出-種非揮發性記憶體之固有啟始電壓的測 $法’包括下列步驟。首I提供具有控綱極、電荷201027535 y /-υζ〇j〇245twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a method for measuring a semiconductor memory device, and more particularly to a non-volatile memory A method for determining the inherent starting voltage. [Prior Art] A typical flash memory system uses a doped polycrystalline spine to make a floating gate and a φ control gate. When the memory is programmed, the appropriate programmed voltage is applied to the source region, the 汲-polar region, and the control gate, respectively, and the electrons flow from the source region to the immersion region via the channel. During this process, some of the electrons will pass through the tunneling oxide layer under the polysilicon floating gate layer, and will be evenly distributed throughout the polysilicon floating gate layer. This phenomenon of electrons passing through the tunneling oxide layer into the polysilicon floating gate layer is called the tunneling effect. The tunneling effect can be divided into two cases, namely, Channel Hot-Electron Injection and Fowler-Nordheim Tunneling (F-N Tunneling). Usually the flash memory is stylized by channel thermal electrons and is erased by Fowler-Nordheim tunneling alongside the source region or via the channel region. Generally speaking, after the flash memory is fabricated, since each memory cell can be affected by the process and has an uneven starting voltage, the memory has a large initial voltage distribution, which may cause use. Difficulties. Therefore, before shipment, the flash memory is usually irradiated with ultraviolet light, so that each memory cell of the flash memory is in a low start voltage (Low丨Vt | ) state, and the component initialization effect is achieved. Among them, the memory cell 201027535 >/-uz〇 j〇245twf.doc/n is fully called after the ultraviolet light, the starting voltage is called the native threshold voltage (Native Threshold Voltage). ° However, the size of the memory cells is also relatively reduced in the current trend of increasing the accumulation of elements, and the cells are usually covered with a high-density metal layer. When the ultraviolet light is used to illuminate the memory, the ultraviolet light is blocked by the metal layer and is difficult to be recorded, and the memory is brought into effect by the memory. Moreover, since the ultraviolet light cannot sufficiently illuminate the memory cell, the memory cell cannot be at the time start voltage (4), and the inherent starting voltage of the memory cell cannot be known. SUMMARY OF THE INVENTION The present invention provides a method for determining the intrinsic starting voltage of a non-volatile memory, which can accommodate (4) when the non-volatile memory is measured. The invention is based on the inherent non-volatile memory. The method of measuring the starting voltage 'includes the following steps. The first I provides a control pole and charge
儲存層、源極區與汲極區的記憶胞。然後，利用F_N穿隨 =應對記舰進行㈣化操作，以取得時晴啟始電壓的 ^式化曲線。在程式化操作中，於控制閘極施加第一電壓。 ^著’利終N穿隧效應對記憶胞進行抹除操作，以取得 時間對啟始電壓的抹除曲線。在抹除操作中，於控制間極 也加第二電壓，其中第二電壓與第—電壓的絕對值相同， $極性相反。之後，從程式化曲線與抹除曲線的交叉點 I出記憶胞的固有啟始電壓。 在本發明之-實施例中，上述第一電壓為8伏特〜2〇 201027535 j〇245twf.doc/n 伏特之間。 在本發明之-實施例中’上述第二電壓為_〇 伏特之間。 ^ 在本發明之-實施例中，在上述程式化操作中，使源 極區與没極區接地或接〇伏特電麗。 在本發明之-實施例中，在上述抹除操作令，使源極 區與汲極區接地或接〇伏特電壓。 參 φ f本發明之-實施射’上述記憶胞為1閃記憶胞。 基於上述，本發明之非揮發性記憶體之 壓 的測定方法，由於只需進行-次程式化操作^ ^ ;固==之方法可以容易的測定出非揮發性』 ^ 2 而且’即使記憶胞上覆蓋有高密度的金 屬層，也可以容易的敎出該記憶胞之固有啟始電壓。 為讓本剌之上述特徵和優職更職驗，下文 舉實施例’並配合所附圓式作詳細說明如下。 ， 【實施方式】 蚨广與-圖立^為分別緣示非揮發性記憶體的程式化及 憶體在程式化及抹_作_能帶示_。發 基底憶體例如是由 H)6、控_極⑽、;^ 存層⑽、閘間介電層 穿隨介電層102顧112所構成。 .f ea, 寬何儲存層104、間問介雷川6、 控1 f 5 1G8例如是依序設置於基底 100上。穿隨θ介電層 5 201027535 y/-U2(> i0245twf.doc/n 102的材質例如是氧化石夕。電荷儲存層1〇4 使電荷儲存於其中的材料’例如摻雜多晶料1間介電 層106的材質例如是氧化石夕或者氧化石夕/氮化石 源極區110與汲極區112例如是設置於閘極⑽兩侧的基 底100中。 請參照圖1A與圖2A，當程式化此記憶 參 ❹Memory cells in the storage, source and bungee regions. Then, using F_N wear and follow = to carry out the (four) operation of the record ship to obtain the normalized starting voltage curve. In a stylized operation, a first voltage is applied to the control gate. ^The end of the N tunneling effect on the memory cell erase operation to obtain the erasing curve of the starting voltage. In the erase operation, a second voltage is also applied to the control terminal, wherein the second voltage is the same as the absolute value of the first voltage, and the polarity is opposite. Thereafter, the intrinsic starting voltage of the memory cell is derived from the intersection of the stylized curve and the erased curve. In an embodiment of the invention, the first voltage is between 8 volts and 2 〇 201027535 j 〇 245 twf. doc / n volts. In the embodiment of the invention, the second voltage is between _ volts volts. In the embodiment of the present invention, in the above stylized operation, the source region and the non-polar region are grounded or connected to the volts. In an embodiment of the invention, in the above erase operation, the source region and the drain region are grounded or connected to a volt voltage. The above memory cell is a 1-flash memory cell. Based on the above, the method for measuring the pressure of the non-volatile memory of the present invention can be easily determined by the method of solid-==2 and the memory cell can be easily determined by the method of -==== The upper layer is covered with a high-density metal layer, and the inherent starting voltage of the memory cell can be easily extracted. In order to make the above features and superior functions of Benedict, the following embodiments will be described in detail with reference to the accompanying circular form as follows. [Embodiment] 蚨广和-图立^ are respectively stylized and non-volatile memory stylized and memorized in stylized and erased. The basal memory layer is composed of, for example, H) 6, a control electrode (10), a memory layer (10), and a gate dielectric layer traversing the dielectric layer 102. .f ea, the wide storage layer 104, the inter-discipline leichuan 6, and the control 1 f 5 1G8 are sequentially disposed on the substrate 100, for example. The material of the θ dielectric layer 5 201027535 y/-U2 (> i0245twf.doc/n 102 is, for example, oxidized oxide. The charge storage layer 1 〇 4 the material in which the charge is stored], for example, doped polycrystalline material 1 The material of the interlayer dielectric layer 106 is, for example, an oxide oxide or a oxidized oxide/nitride source region 110 and a drain region 112, for example, provided in the substrate 100 on both sides of the gate (10). Referring to FIG. 1A and FIG. 2A, When stylizing this memory
閘極與基底100之間具有8伏特至20伏特的電壓差 以引發 F-N 穿隧(F〇Wler-Nordheim tunndingM A m由基底獅進入電荷儲存層104卜舉例來^= 制閘極108施加+ VG之電壓(8伏特至2〇伏特），使^ 1〇〇、源極區110與汲極區112接地或施加Q伏特之電 以利用F-N穿隧效應程式化記憶胞。 睛參照圖1B與圖2B，當抹除此記憶體時，使基底1〇〇 與控制閘極108之間具有8伏特至2G雜的電壓差；'以引 發F-N穿隨效應，使電子114由電荷儲存層1〇4排至基底 1〇〇中。舉例來說，於控制閘極108施加-VG之電壓(胃8伏 特至_2〇伏特）’使基底1〇〇、源極區110與汲極區112接 地或施加G伏特之電壓，以_ F_N賴效應抹除記憶胞。 而且，如圖1A與圖1B所示，在程式化或抹除記憶胞 時’源極區與汲極區112是接地或施加〇伏特。 圖3為繪示施加於閘極的電壓(〇〜±20伏特)對F_N穿 ，電流之關係圖。實驗例1(符號◊)表示於閘極施加負電 壓’使源極區與汲極區接地；實驗例2(符號□)表示於閘極 施加正電塵，使源極區與汲極區接地；實驗例3(符號△) 201027535 97-026 30245twf.d〇c/n -加貞電壓，使源極區纽極區浮置；實驗例 罢。二m巾於間極施加正電I，使源極區與没極區浮 # - + m2中，橫座標以施加電壓的絕對值表示，縱座標 不甲丨電層檢測到之f_n穿隧電流。 ^ 3所7^ ’實驗例1-3的曲線，當於閘極施加電壓 mThere is a voltage difference between the gate and the substrate 100 of 8 volts to 20 volts to induce FN tunneling (F〇Wler-Nordheim tunndingM A m from the base lion into the charge storage layer 104. For example, ^= gate 108 is applied + VG The voltage (8 volts to 2 volts) is such that the source region 110 and the drain region 112 are grounded or Q volts are applied to program the memory cells using the FN tunneling effect. See Figure 1B and Figure 2B, when erasing the memory, the voltage difference between the substrate 1 and the control gate 108 is 8 volts to 2 G; 'to induce the FN wear-through effect, the electron 114 is made up of the charge storage layer 1 〇 4 Discharge into the substrate 1 . For example, applying a voltage of -VG to the control gate 108 (8 volts to 2 volts volts of the stomach) causes the substrate 1 , the source region 110 and the drain region 112 to be grounded or Applying a voltage of G volts, the memory cell is erased by the _F_N ray effect. Moreover, as shown in FIG. 1A and FIG. 1B, the source region and the drain region 112 are grounded or applied when the memory cell is programmed or erased. Fig. 3 is a graph showing the relationship between the voltage applied to the gate (〇~±20 volts) and F_N, and the current. Experimental example 1 (symbol ◊) indicates A negative voltage is applied to the gate to ground the source region and the drain region; Experimental Example 2 (symbol □) indicates that positive dust is applied to the gate to ground the source region and the drain region; Experimental Example 3 (symbol △) 201027535 97-026 30245twf.d〇c/n - The voltage is applied to make the source region of the neopolar region floating; experimental example. The second m towel applies a positive current I to the interpole, so that the source region and the nonpolar region float. # - + In m2, the abscissa is expressed by the absolute value of the applied voltage, and the ordinate is not the tunneling current of the f_n detected by the armor layer. ^ 3 of 7^ 'The curve of the experimental example 1-3, when applied to the gate Voltage m
、击描+伏特)時’隨著電堡的增加，F-N穿隧電流也會快 1#施加於難的電壓為±2()伏特時，實驗例Μ 電流可到達ο·1〜〇.01安培的程度。但是，如 的曲線所示，雖然、F_N親電流隨著施加於問極 垒而增加’但是增加的幅度很小。當施加於閘極的電 壓為广伏特的電壓時，實驗例4的賭穿隨電流只到達 :10〜1X1010安培的程度，無法產生大的F-N穿隧電 流。此結縣* ’純麵歧麵浮置，#闕極施加 =電壓時，將無法引發較多的電子，產生大的F_N穿隧電 流三因此，在本發明的非揮發性記憶體之固有啟始電壓的 須J疋方法中，在程式化操作與抹除操作時源極區與沒極 區較隹疋接地或處加0伏特。 圖4為繪示本發明之非揮發性記憶體之固有啟始電壓 的測定方法之一實施例的之步驟流程圖。 請參照圖4，首先提供記憶胞(步驟2〇〇)，此記憶胞例 如具有圖1A及圖1B所示的結構，包括控制閘極、電荷儲 存層、源極區與汲極區。記憶胞例如是快閃記憶胞。 然後’利用F-N穿隧效應對記憶胞進行程式化操作(步 肆202) ’以取得時間對啟始電壓的程式化曲線。在此程= 201027535 化操作中’如圖1A所示，於控制閘極施加電壓+vg，且 基底100、源極區110與汲極區112接地或施加〇伏特之 電壓。 接著，利用F-N穿隧效應對記憶胞進行抹除操作(步驟 204)’以取得時間對啟始電壓的抹除曲線《^在抹除操作中， 如圖1Β所示，於控制閘極施加電壓_VG ’且基底1〇〇、源 極區110與汲極區112接地或施加〇伏特之電壓。亦即， φ 在本發明的非揮發性記憶體之固有啟始電壓的測定方法 中，在程式化操作時施加於控制閘極的電壓與在抹除操作 時施加於控制閘極的電壓的絕對值必須相同，但是極性相 之後，從程式化曲線與抹除曲線的交又點即求出記憶 胞的固有啟始電壓(步驟204)。 t 接著根據實驗，以說明本發明之非揮發性記憶體之固 有啟始電壓的測定方法是有用的。 射後，所測得的電流電壓曲線圖When scanning + volts, 'With the increase of the electric castle, the FN tunneling current will be fast 1# applied to the difficult voltage of ±2 () volts, the experimental example 电流 current can reach ο·1~〇.01 The extent of amps. However, as shown by the curve, although the F_N pro-current increases as applied to the barrier, the magnitude of the increase is small. When the voltage applied to the gate was a wide volt, the gambling of Experimental Example 4 reached only 10 to 1 x 1010 amps with a current, and a large F-N tunneling current could not be generated. This Jiexian* 'pure surface is floating, #阙极 applied=voltage, it will not trigger more electrons, and generate large F_N tunneling current. Therefore, it is inherent in the non-volatile memory of the present invention. In the method of starting voltage, in the staging operation and the erasing operation, the source region and the gate region are grounded or 0 volts. Fig. 4 is a flow chart showing the steps of an embodiment of a method for measuring the inherent starting voltage of the non-volatile memory of the present invention. Referring to Fig. 4, a memory cell (step 2A) is first provided. The memory cell has, for example, the structure shown in Figs. 1A and 1B, including a control gate, a charge storage layer, a source region, and a drain region. The memory cell is, for example, a flash memory cell. Then, the memory cell is programmed (step 202) using the F-N tunneling effect to obtain a stylized curve of time versus starting voltage. In this process = 201027535, as shown in Fig. 1A, a voltage +vg is applied to the control gate, and the substrate 100, the source region 110 and the drain region 112 are grounded or a voltage of 〇V is applied. Then, the FN tunneling effect is used to erase the memory cell (step 204)' to obtain the erasing curve of the starting voltage. In the erasing operation, as shown in FIG. 1A, a voltage is applied to the control gate. _VG 'and the substrate 1 〇〇, the source region 110 and the drain region 112 are grounded or a voltage of 〇V is applied. That is, φ is a method of measuring the inherent starting voltage of the non-volatile memory of the present invention, the voltage applied to the control gate during the program operation and the absolute voltage applied to the control gate during the erasing operation. The values must be the same, but after the polar phase, the inherent starting voltage of the memory cell is obtained from the intersection of the stylized curve and the erased curve (step 204). t Next, according to experiments, it is useful to demonstrate the method for determining the onset voltage of the non-volatile memory of the present invention. After the shot, the measured current and voltage curve
w付的囡有啟始電壓約為2 5伏特。 圖5為繪示非揮發性記憶體在製造完成後經紫外光照 圖6所纷示為在不同的操作偏壓下進行程式化操作或The payout of w has a starting voltage of about 25 volts. FIG. 5 is a diagram showing that the non-volatile memory is subjected to ultraviolet light illumination after being manufactured, and is illustrated as being programmed under different operating biases or
201027535 y/-uzo j〇245twf.doc/n 操作條件如下： ·) f,電壓為+18伏特’程式化曲線(符號 = 伏特，抹除曲線(符號口）。 △);抹p/電2壓ίϋ電㈣+ 17伏特，程式化曲線(符號 )=電壓為-17伏特，抹除曲線(符號X)。 ▲);抹除電壓為+16伏特，程式化曲線(符號 )^除電壓為-16伏特，抹除曲線(符號〇)。 實驗例4 ’程式化雷厭么 ◊);抹㈣#A is⑶鶴為特’喊化轉(符號 ^ 為5伏特’抹除曲線(符號_)。 抹除曲實驗例1中，程式化曲線(符糊與 2.52、伏特。每^彳丨〇 乂又點A所對應的啟始電壓值約為 沪二’程式化曲線(符號△)與抹除曲線(符 Γ3中父=斤啟始電壓值約為伏特。實驗 c所厂（符號▲)與抹除曲線(符號〇)的交叉點 2·49伏特。實關4中，程式 啟始電的交叉點D所對應的 ，、2.5伏特、2.49伏特、2.5伏特)== = 電壓值(2.5伏特)非纽★ *机、捕朗固有啟始 可以容㈣測性^;知利用本發明之方法， 、 半赞性5己憶體之固有啟始電壓。 的判Γ 3述w本發明之非揮發性記憶體之固有啟始電壓 的測疋方法’利用㈣穿隨效應進行-次程式化操作與- 9 201027535 y7-026 3U245twf.d〇c/n =::2=程Ϊ化操作與抹除操作所得到的時 點即可輕易的測=體 次抹除操作 雖然:發記憶體之固有啟始電壓。 本發明，：Γ 實例揭露如上，然其並非用以限定 故本 本發明之浐技術領域中具有通常知識者，在不脫離 發範圍内，當可作些許之更動與潤飾，故 【圖式簡單二當視後附之申請專利範圍所界定者為準 抹除^非揮發性記⑽雜式化及 圖 抹除^=_非揮發性記憶體在程式化及 圖3為繪不施加於閘極的電壓對F _Ν穿隧電流之關係 ，4為緣不本發明之非揮發性記憶體之固有啟始電壓 的測疋方私—實關的之步魏程圖。 圖5為緣示非揮發性記憶體在製造完成後經紫外光照 ’所测得的電流電壓曲線圖。 ^ 6所緣示為在不同的操 化 ^操作時的時間與啟始電壓之關係圖。 L芏要凡件符號說明】 100 :基底 201027535 y /-υζο 3〇245twf.doc/n 102 :穿隧介電層 104 :電荷儲存層 106 :閘間介電層 108 :控制閘極 110 .源極區 112 .没極區 114 :電子 200、202、204、206 :步驟 A、B、C、D :交叉點201027535 y/-uzo j〇245twf.doc/n The operating conditions are as follows: ·) f, the voltage is +18 volts' stylized curve (symbol = volt, erase curve (symbol port). △); wipe p / electricity 2 Press ϋ ϋ (4) + 17 volts, stylized curve (symbol) = voltage is -17 volts, erase curve (symbol X). ▲); erase voltage is +16 volts, stylized curve (symbol) ^ divided voltage is -16 volts, erase curve (symbol 〇). Experimental Example 4 'Stylized Thunder ◊ ◊ ; ; ; ; ; 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四(Fuzzle with 2.52, volts. The starting voltage value corresponding to each point and point A is about the Shanghai 2' stylized curve (symbol △) and the erase curve (French 3 in the parent = kg starting voltage The value is approximately volts. The intersection of the experimental c factory (symbol ▲) and the erase curve (symbol 〇) is 2.49 volts. In the actual 4, the intersection of the program initiation power D corresponds to 2.5 volts. 2.49 volts, 2.5 volts) == = voltage value (2.5 volts) non-news ★ * machine, catching the intrinsic start can accommodate (four) testability ^; knowing to use the method of the invention, semi-dominant 5 The judgment of the starting voltage. The method of measuring the inherent starting voltage of the non-volatile memory of the present invention is carried out by using the (four) wear-through effect - the stylized operation with - 9 201027535 y7-026 3U245twf.d〇 c/n =::2=The time point obtained by the process and the erase operation can be easily measured = the volume erase operation is the same as the inherent start voltage of the memory. The example is disclosed above, but it is not intended to limit the general knowledge in the technical field of the present invention. When it is not out of the scope of the invention, when some changes and retouching can be made, the figure is simple. The scope defined in the patent application scope is the quasi-erasing ^non-volatile (10) hybridization and image erasure ^=_non-volatile memory in stylized and Figure 3 is the voltage pair F not applied to the gate. _ Ν Ν tunneling current relationship, 4 is not the edge of the inherent starting voltage of the non-volatile memory of the present invention - the real-time step of the Wei Cheng map. Figure 5 shows the non-volatile memory in the The current and voltage curves measured by UV illumination after fabrication are completed. ^ 6 is shown as the relationship between the time and the starting voltage in different operation operations. Substrate 201027535 y /-υζο 3〇245twf.doc/n 102: tunneling dielectric layer 104: charge storage layer 106: inter-gate dielectric layer 108: control gate 110. source region 112. gate region 114: electron 200, 202, 204, 206: Steps A, B, C, D: intersection
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