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TW201026914A - Silicon wafer and fabrication method thereof - Google Patents

Silicon wafer and fabrication method thereof Download PDF

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Publication number
TW201026914A
TW201026914A TW098130435A TW98130435A TW201026914A TW 201026914 A TW201026914 A TW 201026914A TW 098130435 A TW098130435 A TW 098130435A TW 98130435 A TW98130435 A TW 98130435A TW 201026914 A TW201026914 A TW 201026914A
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Taiwan
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wafer
approximately
temperature
annealing process
body region
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TW098130435A
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Chinese (zh)
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TWI395844B (en
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Jung-Goo Park
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Magnachip Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02469—Group 12/16 materials
    • H01L21/02472—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10% over the bulk area.

Description

201026914 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體製造技術，且更特定言之，係關於 矽晶圓及其製造方法。 本發明主張2008年9月29曰及2009年1月16曰向韓國智慧 財產局申請之韓國專利申請案第10-2008-0095462號及第 • 10-2009-0003 697號之優先權，該等專利申請案以引用之方 式併入本文中。 ® 【先前技術】 在諸如NMOS電晶體及PMOS電晶體之大多數高壓器件 中，通常自一基板之一表面形成一井至大致5微米至10微 米之深度。僅使用離子植入製程難以達成具有5微米至10 微米深度之井的摻雜分布。為此，在離子植入製程後應必 需使用高溫熱處理執行摻雜劑擴散過程。 然而，歸因於高溫熱處理，在矽本體中不能完全達成氧 析出。此引起在用於淺渠溝隔離（STI)之刻蝕製程後在矽基 ® 板中出現諸如環狀位錯之晶體缺陷。 此外，此等晶體缺陷降低生產良率，且亦惡化諸如高壓 器件之臨限電壓及靜態隨機存取記憶體（SRAM)之待用模 式期間的漏電流均一性之電參數特性。此外，此等晶體缺 ' 陷增加在雜質檢驗過程（其為製造半導體器件所必需執行 之過程）期間用以檢驗及分析大量缺陷的時間，從而導致 製造半導體器件之總處理時間的增加。 【發明内容】 142898.doc 201026914 本發明之實施例係針對一種用於藉由充分地增加吸氣位 點來防止晶體缺陷歸因於由後繼高溫熱處理製程引起之熱 預算而產生的石夕晶圓。 本發明之另一實施例係針對一種在本體區域中具有高且 均勻之本體微觀缺陷（BMD)密度之石夕晶圓。 本發明之另一實施例係針對一種用於製造藉由充分地增 加吸取位點來防止晶體缺陷歸因於由後繼高溫熱處理製程 引起之熱預算而產生的矽晶圓的方法。 本發明之另一實施例係針對一種用於製造在本體區域中 具有南且均勻之本體微觀缺陷（BMD)密度之矽晶圓的方 法。 本發明之另一實施例係針對一種藉由使用以上描述之矽 晶圓製造之半導體器件。 本發明之另一實施例係針對一種用於藉由使用以上描述 之用於製造石夕晶圓之方法製造半導體器件的方法。 根據本發明之一態樣，提供一種石夕晶圓，其包括：一第 一剝蝕區，其經形成具有始於該矽晶圓之一頂面的一預定 深度；及一本體區域，其形成於該第一剝蝕區與矽晶圓之 一背面之間，其中該第一剝蝕區經形成具有範圍為始於該 頂面的大致20微米至大致80微米之一深度，且其中本體區 域中乳之濃度遍及本體區域以1 〇%内之變化均勻分布。 根據本發明之又一態樣，提供一種用於製造一矽晶圓之 方法，其包括·•提供具有一制蝕區及一本體區域之矽晶 圓；在一第一溫度下對該矽晶圓執行第一退火製程以在本 142898.doc 201026914 :區域中補充產生氧析出物核及氧析出物；及在高於第一 溫度之第二溫度下對石夕晶圓執行第二退火製程以增大本體 區域中之氧析出物。 根據本發明之又一態樣，提供一種用於製造一石夕晶圓之 . 於去’其包括：提供該矽晶圓；在-裝載溫度下將矽晶圓 • I載至加熱裳置内部；執行-將石夕晶圓自裝載溫度加熱至 第-溫度之第一加熱製程；在該第一溫度下執行使該石夕晶 • ®退火之H火製㈣產生氧析出物；執行—將該石夕 曰曰曰圓自該第-溫度加熱至高於該第一溫度之一第二温度的 第加熱過程，在該第二溫度下執行使該矽晶圓退火之一 第一退火製程以增大氧析出物以用於增加其密度；執行一 將該石夕晶圓自該第二溫度冷卻至一卸載溫度之冷卻製程； 及將該矽晶圓自該加熱裝置卸載至外部。 本發明之其他目；^票及優點可藉由以下描述來理解，且參 考本發明之實施例變得顯而易見。又，本發明之目標及優 _ .點可藉由如所主張之構件及其組合實現對於熟悉本發明所 屬之相關技術者為顯然的。 【實施方式】 本發明之優點、特徵及態樣將自參看隨附圖式之下文所 闡述的實施例之以下描述變得顯而易見。 在諸圖中，4說明ί青楚，誇示層及區域之尺寸。亦應理 解，當一層（或膜）被稱為「在另一層或基板上」時，其可 直接在另-層或基板上，或亦可存在插人層。此外，應理 解，當一層被稱為「在另一層下方」時，其可直接在^一 142898.doc 201026914 合 且亦可存在一或多個插入層。此外，亦應理解， 層被稱為「在兩個層之間」時，其可為兩個層之間的 唯—層’或亦可存在—或多個插入層。 β本發明可藉由對晶圓矽使用兩步驟退火製程來實現本體 區域中同且均勻之BMD密度。結果，本發明可藉由充分地 增加吸取位點（gettering site)來防止晶體缺陷歸因於由後 繼高溫熱處理製程引起之熱預算而產生。 圖1為根據本發明之一實施例的矽晶圓之橫截面圖。 如圖1所展示，矽晶圓100包括：一第一剝蝕區DZ1，該 第剝钱區DZ1經形成具有始於該矽晶圓之一頂面1〇1的 預定深度；及一本體區域區塊，該本體區域Βκ形成於 該第一剝蝕區DZ1與一背面1 〇2之間。矽晶圓i00進一步包 括一第二剝钱區DZ2，該第二剝蝕區dZ2經形成具有自該 背面102朝向該頂面101之方向的預定深度。 經形成具有自頂面101朝向背面1〇2之方向的預定深度之 第一剝蝕區DZ1為無缺陷區域（DFZ)，其不存在諸如空位 及位錯之晶體缺陷。較佳地，第一剝蝕區DZ1經形成具有 自頂面101朝向背面102之方向的範圍為大致20微米至大致 80微米的深度。 第二剝餘區DZ2亦為DFZ且經形成具有自背面1〇2朝向頂 面101之方向的與第一剝蝕區DZ1之深度相同的深度，或根 據對背面102之拋光製程，第二剝蝕區DZ2經形成具有小 於第一剝蝕區DZ1之深度的深度。亦即，當對矽晶圓1〇〇 之頂面101及背面102兩者無差別地進行鏡面拋光時，相同 142898.doc 201026914 深度形成具有相同深度的第一剝蝕區DZ1及第二剝蝕區 DZ2。相反，當對頂面1〇1進行鏡面拋光且不對背面1〇2進 行鏡面拋光時，形成具有小於第—剝蝕區DZ1深度之深度 的第二剝蝕區DZ2 ’因為根據背面1〇2之粗糙度緊接於背 面102形成氧析出物。 在第一剝蝕區DZ1與第二剝蝕區dZ2之間形成的本體區 域BK包括本體微觀缺陷（BMD)l〇3。BMD 103在整個本體 區域中保持均勻。BMD 103包括析出物及本體疊差。此 外，可控制本體區域BK中之BMD 103以具有足夠密度，藉 此吸取經由後繼高溫熱處理製程或熱製程待在矽晶圓之表 面上擴散之金屬污染物。本體區域Βκ中之BMD 103較佳可 保持自大致lxlO5 ea/cm2至大致ixi〇7 ea/cm2之密度’且更 佳自大致lxlO6 ea/cm2至lxlO7 ea/cm2。本體區域Βκ中氧之 濃度（以下稱為「氧濃度」）與氧析出物緊密相關，且氧濃 度較佳遍及本體區域BK以10%内之變化分布且保持自大致 10.5至大致13 PPMA(原子百萬分率）。 圖2為說明根據本發明之第一實施例的用於製造矽晶圓 之方法的橫截面圖。 參看圖2 ’製備矽晶圓200。此時，矽晶圓200可為裸晶 圓。可按照以下步驟形成矽晶圓200。首先，在成長單晶 碎後’將單晶石夕切割成晶圓形狀。在執行刻领製程以钮刻 經切割晶圓之表面或使經切割晶圓之侧面變圓之後，對石夕 晶圓200之頂面201及背面202進行鏡面拋光。此時，使用 柴氏（Czochralski，CZ)晶體成長法來使單晶矽成長。此 142898.doc ^ 201026914 外’可在後續熱製程後執行對矽晶圓200之鏡面拋光製 程。 執行對矽晶圓200之第一熱製程，使得矽晶圓2〇〇之頂面 201與背面202之間的氧化物元素203向内部擴散。結果， 形成第一剝姓區DZ1及第二剝姓區DZ2以及本體區域BK。 第一熱製程可為RTP(快速熱製程）或使用爐裝置之退火製 程。較佳地，第一熱製程包括RTP。 為快速擴散矽晶圓200之頂面201及背面202中之氧化物 兀素203，使用氬（Ar)氣、氮（NO氣、氨（NH3)氣或其組合 在高溫下執行第一熱製程。當第一熱製程為尺丁卩時，在範 圍為1050°C至大致115〇t之溫度下執行第一熱製程歷時大 致10秒至大致30秒。當第一熱製程為退火製程時，在範圍 為1050C至大致1150C之溫度下執行第一熱製程歷時大致 1〇〇分鐘至大致300分鐘。 接著，執行對矽晶圓200之第二熱製程，使得本體區域 BK中之氧化物凡素2〇3結合。結果，產生氧析出物核 204。與第一熱製程類似，第二熱製程可為RTp或使用爐裝 置之退火製程。第二熱製程較佳包括RTp。 為易於形成氧析出物核204，使用氬（Ar)氣、氮（n2)氣、 氨（NH3)氣或其組合在低於第一熱製程之溫度的溫度下執 行第二熱製程。當第二熱製程為RTp時，在範圍為大致 950 C至大致1000 C之溫度下執行第二熱製程歷時大致⑺ 私至大致3G秒。當第三熱製程為退火製程時，在範圍為大 致950°C至大致l〇0(TC之溫度下執行第二熱製程歷時大致 142898.doc 201026914 100分鐘至大致200分鐘。 隨後，在完成第二熱製程後對矽晶圓2〇〇執行第一退火 製程。使用爐裝置執行第一退火製程。藉由在低於第二熱 製程之溫度的預定溫度下加熱矽晶圓2〇〇，補充產生本體 區域BK中之氧析出物核2〇4，且同時，產生氧析出物 205A。較佳地，在範圍為大致75〇它至大致之溫度下 執行第一退火製程歷時大致i 〇〇分鐘至大致18〇分鐘。此 外，在氧（〇2)氣氛圍.下執行第一退火製程。 在完成第一退火製程後對矽晶圓200執行第二退火製 程。亦使用爐裝置執行第二退火製程。藉由在高於第一退 火製程之溫度的預定溫度下加熱矽晶圓2〇〇，增大氧析出 物205A。結果，產生經增大之氧析出物2〇5b。較佳地， 在範圍為大致l〇〇〇°C至大致115〇。(：之溫度下執行第二退火 製程歷時大致1〇〇分鐘至大致分鐘。此外，在氧（〇2)氣 氛圍下執行第二退火製程。 在下文中，詳細描述第一退火製程及第二退火製程。在 下文中，將第一退火製程及第二退火製程稱為兩步驟退火 製程。 圖ό為說明根據本發明之一實施例的兩步驟退火製程之 曲線圖。 參看圖6’使用爐裝置之退火製程包括使用氧（〇2)氣在 第一溫度下使矽晶圓200退火之第一退火製程（Π)及在高於 第一溫度之第二溫度下執行使矽晶圓2〇〇退火的第二退火 製程（IV)。執行第一退火製程（II)及第二退火製程（IV)中之 142898.doc 201026914 每一者歷時大致100分鐘至大 里王；ISO分鐘。第一退火製程 (II)之第一溫度的範圍為女 祀固馮大致75〇C至大致8〇〇t，且第二 退火製程（IV)之第二溫磨沾益一 乐酿度的範圍為大致1000°c至大致 1150〇c。 為^良氧化製程及熱處理製程之效應，在第—退火製程 (Π)前，根據本發明之實施例的兩步驟退火製程可進一步 匕括將夕曰曰圓200裝載至爐裝置内部且接著將矽晶圓細保 持至裝載溫度歷時—預定持續時間的裝載過程⑹。又， 在^二退火製程（IV)後，根據本發明之實施例的兩步驟退 火製程可進—步包括在將梦晶圓細卸載至爐裝置外部前 將梦明圓2GG保持至卸載溫度歷時__預定持續時間的卸载 過程（UL)。 裝載過程（L)之裝載溫度低於第一溫度❶較佳地，裝栽 溫度之範圍為大致600〇c至大致7〇〇t。在裝載過程（以期 間=將氧氣供應至爐裝置中。結果，在裝載過程（l)期間 矽晶圓200未受到氧化。卸載過程（UL)之卸載溫度大體上 等於第一溫度。較佳地，卸載溫度之範圍為大致75〇<t至 大致800。(： ^在卸載過程（UL)期間，不供應氧氣而僅供應 氣氣。氮氣之流動速率的範圍為大致9slm至大致u slm。 此外’根據本發明之實施例的兩步驟退火製程可進一步 包括在裝載過程（L)與第一退火製程（II)之間的用於將裝載 溫度加熱至第一溫度的第一加熱製程（I)及在第一退火製程 (II)與第二退火製程（IV)之間的用於將第一溫度加熱至第二 溫度的第二加熱製程（111)。當在第一加熱製程⑴及第二加 142898.doc 201026914 熱製程（III)期間每分鐘升溫速率過高時，晶圓結構可能變 形因此，可將第一加熱製程⑴及帛二加熱製程（即中之 升溫速率設定為大致5t/分鐘至大致8〇c/分鐘之範圍。 又根據本發明之實施例的兩步驟退火製程可進一步包 括在第二退火製程（IV)與卸載過程（UL)之間的用於將第二 溫度冷卻至卸載溫度的冷卻製程（v)。冷卻製程之降溫 速率的範圍可為大致2。〔〕/分鐘至大致4t:/分鐘。 在根據本發明之實施例的兩步驟退火製程中，矽晶圓 200之退火大體上主要在第一退火製程及第二退火製程 (Π、IV)期間達成，因為僅在此等製程期間供應氧氣。第 一退火製程及第二退火製程（11、IV)期間所供應之氧氣之 流動速率的範圍可為大致5〇 sccm至大致12〇 sccm。可執行 第一退火製程及第二退火製程（II、IV)中之每一者歷時大 致100分鐘至大致180分鐘。 如圖6中描述之兩步驟退火製程可應用於圖3至圖$中展 示之根據本發明之以下實施例的用於製造矽晶圓之方法的 第一退火製程及第二退火製程。 圖3為說明根據本發明之第二實施例的用於製造石夕晶圓 之方法的橫截面圖。 參看圖3，執行對矽晶圓300之熱製程，使得矽晶圓3〇〇 之頂面301與背面302之間的氧化物元素303向内部擴散。 結果’形成第一剝蝕區DZ1及第二剝蝕區DZ2以及本體區 域ΒΚ。熱製程可為RTP或使用爐裝置之退火製程。較佳 地，第一熱製程包括RTP。 142898.doc -11 - 201026914 為快速擴散矽晶圓300之頂面301及背面302之氧化物元 素303，在高溫下執行熱製程。當熱製程為RTp時，在範圍 為1050 C至大致1150°C之溫度下執行熱製程歷時大致1〇秒 至大致30秒。當熱製程為退火製程時，在範圍為1〇5〇χ：至 大致1150C之溫度下執行熱製程歷時大致1〇〇分鐘至大致 200分鐘。 隨後，對矽晶圓300執行第一退火製程，使得本體區域 BK中之氧化物疋素203結合。結果’形成氧析出物核 304。在低於熱製程之溫度的預定溫度下使用爐裴置執行 第一退火製程。較佳地，在範圍為大致？“^至大致8〇〇t 之溫度下執行第一退火製程歷時大致1〇〇分鐘至大致18〇分 鐘。此外，在氧（〇2)氣氛圍下執行第一退火製程。 對矽晶圓300執行第二退火製程。亦使用爐裝置執行第 一退火製程。藉由在高於第一退火製程之溫度的預定溫度 下加熱矽晶圓300，產生氧析出物3〇5。較佳地，在範圍為 大致100(TC至大致115(TC之溫度下執行第二退火製程歷時 大致1〇〇分鐘至大致180分鐘。此外，在氧（〇2)氣氛圍下執 行第二退火製程。 圖4為說明根據本發明之第三實施例的用於製造矽晶圓 之方法的橫截面圖。 在圖4中，在低於圖3之熱製程之溫度的溫度下執行第一 退火製程之前的熱製程。 參看圖4,在低於圖3之熱製程之溫度的溫度下執行對矽 晶圓400之熱製程。因此，產生氧析出物核4〇4因為在低 142898.doc •12- 201026914 溫下執行熱製程，所以在第一剝蝕區DZ1及第二剝蝕區 DZ2以及本體區域BK中形成氧析出物核404。熱製程可為 RTP或退火製程。較佳地，第一熱製程包括RTP。當熱製 程為RTP時，在範圍為大致95(TC至大致1〇〇〇。(：之溫度下執 行熱製程歷時大致10秒至大致30秒。當熱製程為退火製程 時’在範圍為大致950°C至大致1〇〇〇。(3之溫度下執行熱製 程歷時大致100分鐘至大致200分鐘。 隨後，對矽晶圓400順序地執行第一退火製程及第二退 火製程’使得產生氧析出物核4〇4及氧析出物4〇5a。在與 圖3之第一退火製程及第二退火製程之彼等條件相同的條 件下執行第一退火製程及第二退火製程。 圖5為說明根據本發明之第四實施例的用於製造矽晶圓 之方法的橫截面圖。 參看圖5，與圖2至圖4中展示之退火製程不同，根據本 一退火製程及第二退201026914 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to semiconductor manufacturing technology, and more particularly to a germanium wafer and a method of fabricating the same. The present invention claims the priority of Korean Patent Application No. 10-2008-0095462 and No. 10-2009-0003 697, filed on Sep. 29, 2008, and January 16, 2009, to the Korean Intellectual Property Office. The patent application is incorporated herein by reference. ® [Prior Art] In most high voltage devices such as NMOS transistors and PMOS transistors, a well is typically formed from the surface of one of the substrates to a depth of approximately 5 microns to 10 microns. It is difficult to achieve a doping profile of a well having a depth of 5 microns to 10 microns using only an ion implantation process. For this reason, it is necessary to perform a dopant diffusion process using a high temperature heat treatment after the ion implantation process. However, due to the high temperature heat treatment, oxygen evolution cannot be completely achieved in the crucible body. This causes crystal defects such as ring dislocations to occur in the ruthenium ® plate after the etching process for shallow trench isolation (STI). In addition, such crystal defects reduce production yield and also deteriorate electrical parameter characteristics such as the threshold voltage of the high voltage device and the leakage current uniformity during the standby mode of the static random access memory (SRAM). Moreover, such crystal defects increase the time to inspect and analyze a large number of defects during the impurity inspection process, which is a process that must be performed to fabricate a semiconductor device, resulting in an increase in the total processing time for fabricating a semiconductor device. SUMMARY OF THE INVENTION 142898.doc 201026914 Embodiments of the present invention are directed to a Shihwa wafer for preventing crystal defects from being caused by a thermal budget caused by a subsequent high-temperature heat treatment process by sufficiently increasing a gettering site . Another embodiment of the present invention is directed to a stone wafer having a high and uniform bulk microscopic defect (BMD) density in the body region. Another embodiment of the present invention is directed to a method for fabricating a tantalum wafer which is produced by sufficiently increasing the gettering sites to prevent crystal defects from being attributed to the thermal budget caused by subsequent high temperature heat treatment processes. Another embodiment of the present invention is directed to a method for fabricating a tantalum wafer having a south and uniform bulk microscopic defect (BMD) density in the body region. Another embodiment of the present invention is directed to a semiconductor device fabricated by using the above described wafer. Another embodiment of the present invention is directed to a method for fabricating a semiconductor device by using the above-described method for fabricating a lithographic wafer. According to an aspect of the present invention, a lithographic wafer is provided, comprising: a first ablation region formed to have a predetermined depth starting from a top surface of the germanium wafer; and a body region formed Between the first ablation region and a back surface of one of the germanium wafers, wherein the first ablation region is formed to have a depth ranging from approximately 20 micrometers to approximately 80 micrometers from the top surface, and wherein the body region is milked The concentration is evenly distributed throughout the body region within 1 〇%. According to still another aspect of the present invention, a method for fabricating a germanium wafer is provided, comprising: providing a germanium wafer having an erosion region and a body region; the twin crystal at a first temperature Performing a first annealing process to supplement the generation of oxygen precipitate cores and oxygen precipitates in the region of the 142898.doc 201026914: and performing a second annealing process on the Shihua wafer at a second temperature higher than the first temperature Increase the oxygen precipitates in the body region. According to still another aspect of the present invention, there is provided a method for manufacturing a silicon wafer. The method comprises: providing the germanium wafer; loading the germanium wafer I to the inside of the heating skirt at a loading temperature; Executing - heating the Shi Xi wafer from the loading temperature to a first heating process of the first temperature; performing, at the first temperature, performing H-fire (4) to generate oxygen precipitates; The first heating process of heating the first temperature to a second temperature higher than the first temperature, and performing a first annealing process for annealing the germanium wafer to increase at the second temperature An oxygen precipitate for increasing the density thereof; performing a cooling process for cooling the Shihua wafer from the second temperature to an unloading temperature; and unloading the tantalum wafer from the heating device to the outside. Other objects and advantages of the present invention will be understood from the following description, and the embodiments of the present invention will become apparent. Further, it is apparent that the objects and advantages of the present invention can be realized by those skilled in the art to which the present invention pertains. The advantages, features, and aspects of the present invention will become apparent from the following description of the embodiments illustrated in the appended claims. In the figures, 4 illustrates ί青楚, exaggerating the dimensions of layers and regions. It should also be understood that when a layer (or film) is referred to as being "on another layer or substrate," it can be directly on another layer or substrate, or an intervening layer can also be present. In addition, it should be understood that when a layer is referred to as "below another layer," it can be directly in the singularity of one or more intervening layers. In addition, it should also be understood that when a layer is referred to as "between two layers," it can be a "layer" or a plurality of intervening layers between two layers. The present invention achieves the same and uniform BMD density in the body region by using a two-step annealing process for the wafer crucible. As a result, the present invention can prevent crystal defects from being generated due to the thermal budget caused by the subsequent high-temperature heat treatment process by sufficiently increasing the gettering site. 1 is a cross-sectional view of a tantalum wafer in accordance with an embodiment of the present invention. As shown in FIG. 1 , the germanium wafer 100 includes: a first ablation region DZ1 formed to have a predetermined depth starting from a top surface 1〇1 of the germanium wafer; and a body region region The body region Βκ is formed between the first ablation region DZ1 and a back surface 1 〇2. The wafer i00 further includes a second stripping region DZ2 formed to have a predetermined depth from the back surface 102 toward the top surface 101. The first ablation region DZ1 formed to have a predetermined depth from the top surface 101 toward the back surface 1〇2 is a defect-free region (DFZ) which does not have crystal defects such as vacancies and dislocations. Preferably, the first ablation zone DZ1 is formed to have a depth ranging from about 20 micrometers to about 80 micrometers from the direction of the top surface 101 toward the back surface 102. The second stripping zone DZ2 is also DFZ and is formed to have the same depth as the depth of the first ablation zone DZ1 from the back surface 1〇2 toward the top surface 101, or according to the polishing process for the back surface 102, the second ablation zone DZ2 is formed to have a depth smaller than the depth of the first ablation region DZ1. That is, when the top surface 101 and the back surface 102 of the wafer 1 are mirror-polished without difference, the same 142898.doc 201026914 depth forms the first ablation region DZ1 and the second ablation region DZ2 having the same depth. . On the contrary, when the top surface 1〇1 is mirror-polished and the back surface 1〇2 is not mirror-polished, the second ablation region DZ2′ having a depth smaller than the depth of the first ablation region DZ1 is formed because of the roughness according to the back surface 1〇2 An oxygen precipitate is formed next to the back surface 102. The body region BK formed between the first ablation zone DZ1 and the second ablation zone dZ2 includes a bulk microscopic defect (BMD) 103. The BMD 103 remains uniform throughout the body area. BMD 103 includes precipitates and bulk stacks. In addition, the BMD 103 in the body region BK can be controlled to have a sufficient density to absorb metal contaminants to be diffused on the surface of the wafer via subsequent high temperature heat treatment processes or thermal processes. The BMD 103 in the body region Βκ is preferably maintained from a density of approximately lxlO5 ea/cm2 to approximately ixi〇7 ea/cm2 and more preferably from approximately lxlO6 ea/cm2 to lxlO7 ea/cm2. The concentration of oxygen in the bulk region Βκ (hereinafter referred to as "oxygen concentration") is closely related to the oxygen precipitate, and the oxygen concentration is preferably distributed throughout the body region BK within 10% and is maintained from approximately 10.5 to approximately 13 PPMA (atoms) Parts per million). 2 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a first embodiment of the present invention. Referring to Figure 2, a germanium wafer 200 is prepared. At this time, the germanium wafer 200 may be a bare die. The germanium wafer 200 can be formed in the following steps. First, after the single crystal is grown, the single crystal stone is cut into a wafer shape. The top surface 201 and the back surface 202 of the Shixi wafer 200 are mirror-polished after performing the engraving process to scribe the surface of the wafer or round the side of the diced wafer. At this time, a single crystal crucible was grown using a Czochralski (CZ) crystal growth method. This 142898.doc ^ 201026914 outer can perform a mirror polishing process on the wafer 200 after the subsequent thermal process. The first thermal process of the wafer 200 is performed such that the oxide element 203 between the top surface 201 and the back surface 202 of the germanium wafer 2 is diffused internally. As a result, the first stripping area DZ1 and the second stripping area DZ2 and the body area BK are formed. The first thermal process can be an RTP (rapid thermal process) or an annealing process using a furnace apparatus. Preferably, the first thermal process comprises RTP. In order to rapidly diffuse the top surface 201 of the tantalum wafer 200 and the oxide halogen 203 in the back surface 202, the first thermal process is performed at a high temperature using argon (Ar) gas, nitrogen (NO gas, ammonia (NH 3 ) gas, or a combination thereof). When the first thermal process is a ruler, the first thermal process is performed at a temperature ranging from 1050 ° C to approximately 115 〇t for about 10 seconds to about 30 seconds. When the first thermal process is an annealing process, Performing the first thermal process for a period of approximately 1 minute to approximately 300 minutes at a temperature ranging from 1050 C to approximately 1150 C. Next, performing a second thermal process on the germanium wafer 200 such that the oxide in the body region BK 2〇3 combination. As a result, an oxygen precipitate core 204 is produced. Similar to the first thermal process, the second thermal process may be RTp or an annealing process using a furnace apparatus. The second thermal process preferably includes RTp. The core 204 is subjected to a second thermal process at a temperature lower than the temperature of the first thermal process using argon (Ar) gas, nitrogen (n 2 ) gas, ammonia (NH 3 ) gas, or a combination thereof. When the second thermal process is RTp Performing a second heat at a temperature ranging from approximately 950 C to approximately 1000 C The process time is roughly (7) private to approximately 3G seconds. When the third thermal process is an annealing process, the second thermal process is performed at a temperature ranging from approximately 950 ° C to approximately 10 ° (the temperature of TC is approximately 142898.doc 201026914 100 minutes) Up to approximately 200 minutes. Subsequently, a first annealing process is performed on the germanium wafer 2 after the second thermal process is completed. The first annealing process is performed using the furnace device. By a predetermined temperature lower than the temperature of the second thermal process The ruthenium wafer 2 is heated down to replenish the oxygen precipitate core 2〇4 in the body region BK, and at the same time, the oxygen precipitate 205A is generated. Preferably, it is performed at a temperature ranging from approximately 75 〇 to approximately temperature. The first annealing process lasts from approximately 1 minute to approximately 18 minutes. Further, the first annealing process is performed under an oxygen (〇2) gas atmosphere. The second annealing is performed on the germanium wafer 200 after the first annealing process is completed. The second annealing process is also performed using the furnace apparatus. The oxygen precipitates 205A are enlarged by heating the tantalum wafer 2 at a predetermined temperature higher than the temperature of the first annealing process. As a result, an increased oxygen is generated. Precipitates 2〇5b. Preferably, the range is from about 10 ° C to about 115 〇. (: The temperature of the second annealing process is performed for approximately 1 minute to approximately minutes. In addition, the atmosphere is performed under an oxygen (〇2) atmosphere. The second annealing process. Hereinafter, the first annealing process and the second annealing process are described in detail. Hereinafter, the first annealing process and the second annealing process are referred to as a two-step annealing process. A two-step annealing process diagram of an example. Referring to Figure 6, an annealing process using a furnace apparatus includes a first annealing process (Π) and a high temperature of annealing the tantalum wafer 200 at a first temperature using an oxygen (〇2) gas. A second annealing process (IV) for annealing the tantalum wafer 2 is performed at a second temperature of the first temperature. Each of the first annealing process (II) and the second annealing process (IV) is carried out for 142898.doc 201026914 each of which lasts approximately 100 minutes to the king of Daly; ISO minutes. The first annealing process (II) has a first temperature range of approximately 75 〇C to approximately 8 〇〇t, and a second annealing process (IV) of the second tempering range It is approximately 1000 ° c to approximately 1150 ° c. For the effect of the oxidation process and the heat treatment process, before the first annealing process, the two-step annealing process according to an embodiment of the present invention may further include loading the wafer 200 into the furnace device and then The wafer is held fine to the loading temperature for a predetermined duration of loading (6). Moreover, after the two-annealing process (IV), the two-step annealing process according to an embodiment of the present invention may further include maintaining the dream ring 2GG to the unloading temperature duration before finely unloading the dream wafer to the outside of the furnace device. __Uninstallation process (UL) for a predetermined duration. The loading temperature of the loading process (L) is lower than the first temperature. Preferably, the loading temperature ranges from about 600 〇c to about 7 〇〇t. During the loading process (during period = supplying oxygen into the furnace device. As a result, the wafer 200 is not subjected to oxidation during the loading process (1). The unloading temperature of the unloading process (UL) is substantially equal to the first temperature. Preferably The unloading temperature ranges from approximately 75 〇 < t to approximately 800. (: ^ During the unloading process (UL), no oxygen is supplied and only gas is supplied. The flow rate of nitrogen ranges from approximately 9 slm to approximately u slm. Further, the two-step annealing process according to an embodiment of the present invention may further include a first heating process for heating the loading temperature to the first temperature between the loading process (L) and the first annealing process (II) (I And a second heating process (111) for heating the first temperature to the second temperature between the first annealing process (II) and the second annealing process (IV). When in the first heating process (1) and Two plus 142898.doc 201026914 When the heating rate per minute during the hot process (III) is too high, the wafer structure may be deformed. Therefore, the first heating process (1) and the second heating process (ie, the heating rate in the middle can be set to approximately 5t/ Minutes to approximately 8〇c/ Further, the two-step annealing process according to an embodiment of the present invention may further include a cooling process for cooling the second temperature to the unloading temperature between the second annealing process (IV) and the unloading process (UL) ( v) The cooling rate of the cooling process may range from approximately 2. [] / minute to approximately 4 t: / minute. In the two-step annealing process according to an embodiment of the present invention, the annealing of the germanium wafer 200 is substantially The first annealing process and the second annealing process (Π, IV) are achieved because oxygen is supplied only during such processes. The flow rate of oxygen supplied during the first annealing process and the second annealing process (11, IV) The range may be from about 5 〇sccm to about 12 〇sccm. Each of the first annealing process and the second annealing process (II, IV) may be performed for approximately 100 minutes to approximately 180 minutes. The step annealing process can be applied to the first annealing process and the second annealing process of the method for manufacturing a germanium wafer according to the following embodiments of the present invention shown in FIG. 3 to FIG. $. FIG. 3 is a diagram illustrating the first embodiment of the present invention. two A cross-sectional view of a method for fabricating a Shihua wafer of an embodiment. Referring to FIG. 3, a thermal process for the tantalum wafer 300 is performed such that an oxide between the top surface 301 and the back surface 302 of the tantalum wafer 3 is formed. The element 303 diffuses internally. The result 'forms the first ablation zone DZ1 and the second ablation zone DZ2 and the body zone ΒΚ. The thermal process may be RTP or an annealing process using a furnace device. Preferably, the first thermal process includes RTP. 142898 .doc -11 - 201026914 The thermal process is performed at a high temperature for rapidly diffusing the top surface 301 of the tantalum wafer 300 and the oxide element 303 of the back surface 302. When the thermal process is RTp, the range is from 1050 C to approximately 1150 ° C. The hot process is performed at a temperature of approximately 1 second to approximately 30 seconds. When the thermal process is an annealing process, the hot process is performed at a temperature ranging from 1 〇 5 〇χ to approximately 1150 C for approximately 1 minute to approximately 200 minutes. Subsequently, a first annealing process is performed on the germanium wafer 300 such that the oxide halogen 203 in the body region BK is bonded. As a result, an oxygen precipitate core 304 is formed. The first annealing process is performed using a furnace set at a predetermined temperature lower than the temperature of the hot process. Preferably, the scope is approximate? The first annealing process is performed at a temperature of approximately 8 〇〇t for approximately 1 minute to approximately 18 minutes. Further, the first annealing process is performed under an oxygen (〇2) atmosphere. The second annealing process is performed. The first annealing process is also performed using the furnace device. The oxygen precipitates 3〇5 are generated by heating the tantalum wafer 300 at a predetermined temperature higher than the temperature of the first annealing process. Preferably, The range is approximately 100 (TC to approximately 115 (the second annealing process is performed at a temperature of TC for approximately 1 minute to approximately 180 minutes. Further, the second annealing process is performed under an oxygen (〇2) gas atmosphere. A cross-sectional view of a method for fabricating a germanium wafer according to a third embodiment of the present invention is illustrated. In FIG. 4, a thermal process prior to the first annealing process is performed at a temperature lower than the temperature of the thermal process of FIG. Referring to Fig. 4, the thermal process for the germanium wafer 400 is performed at a temperature lower than the temperature of the thermal process of Fig. 3. Therefore, the oxygen precipitate core 4 is generated because it is at a low temperature of 142898.doc •12-201026914 Perform a thermal process, so in the first ablation zone DZ1 and second An oxygen precipitate core 404 is formed in the ablation zone DZ2 and the body region BK. The thermal process may be an RTP or an annealing process. Preferably, the first thermal process includes RTP. When the thermal process is RTP, the range is approximately 95 (TC to Approximately 1 〇〇〇. (: The temperature is performed at a temperature of approximately 10 seconds to approximately 30 seconds. When the thermal process is an annealing process, the range is approximately 950 ° C to approximately 1 〇〇〇. (3 temperature The thermal process is performed for approximately 100 minutes to approximately 200 minutes. Subsequently, the first annealing process and the second annealing process are sequentially performed on the silicon wafer 400 to generate the oxygen precipitate core 4〇4 and the oxygen precipitate 4〇5a. The first annealing process and the second annealing process are performed under the same conditions as those of the first annealing process and the second annealing process of FIG. 3. FIG. 5 is a view for explaining the use of the twin crystal according to the fourth embodiment of the present invention. Cross-sectional view of the round method. Referring to Figure 5, unlike the annealing process shown in Figures 2 to 4, according to the present annealing process and the second retreat

退火製程。 發明之第四實施例的退火製程無需第 火製程之前的額外熱製程。亦即，提 500 ’且對矽晶圓500順戽地铀#银_Annealing process. The annealing process of the fourth embodiment of the invention does not require an additional thermal process prior to the first fire process. That is, raise 500' and 矽 矽 500 500 500 500 # # # # #

表示氧析出物且「505B 表示經增大之氧析出物。 142898.doc -13· 201026914 如上文所描述，參看圖2至圖5描述根據本發明之用於製 造矽晶圓之方法。如先前所述，在圖2至圖4所展示之第一 至第三實施例中，RTp偏好在第一退火製程及第二退火製 程之前使用熱製程。 矽明圓中之氧析出物或空隙缺陷之内部缺陷可在成長單 日曰矽期間文到控制，或在成長單晶矽後藉由熱製程控制。 如上文所描述，熱製程可包括使用鹵素燈之RTP及使用爐 裝置之退火製程。 在氬（Ar)氣或氫（HD氣氛圍下於高於大致1〇〇〇它之高溫 下執行使用爐裝置之退火製程歷時多於大致1〇〇分鐘之長 時間。經由此退火製程引起之矽晶圓中氧化物元素之擴散 及矽重排，在矽晶圓之頂面的一部分中形成器件理想區 (亦即，無缺陷區（DFZ))。然而，隨著矽晶圓之大小增 加此退火製程難以控制歸因於高溫熱處理之石夕晶圓之污 染或滑動位錯。 因此，RTP獲得優於退火製程的矽晶圓特性。然而，當 使用各種缺陷偵測方法評估由RTp製造之矽晶圓時僅控 制氧析出物在自頂面大致3微米至大致1〇微米之深度内。 此外，當藉由僅執行RTP —次或兩次來製造矽晶圓時，存 在對實現本體區域内高BMD密度之限制。更具體言之，當 藉由執行RTP—次來製造矽晶圓時，BMD密度經確定在自 ixlO6 ea/cm2至3χ1〇6 ea/cm2之範圍内，且難以使ΒΜβ密度 超出該範圍。 在本發明之實施例中，如圖2至圖4所展示，在熱製程後 142898.doc •14· 201026914 執行兩步驟退火製程，藉此移除靠近矽晶圓之頂面的空隙 缺陷及氧析出物。結果，本發明可確保無缺陷區（DFZ)且 增加BMD密度（包括本體區域中之本體堆疊缺陷及氧析出 物），藉此藉由增加本體區域中之吸取位點來改良吸取效 • 應。 在下文中，參看表1及表2詳細描述由本發明之實施例製 造之矽晶圓之特性。 [表1]Indicates an oxygen precipitate and "505B represents an enlarged oxygen precipitate. 142898.doc -13· 201026914 As described above, a method for manufacturing a tantalum wafer according to the present invention will be described with reference to FIGS. 2 through 5. In the first to third embodiments shown in FIGS. 2 to 4, RTp prefers to use a thermal process before the first annealing process and the second annealing process. Oxygen precipitates or void defects in the circle Internal defects can be controlled during the growth of a single day, or by thermal process after the growth of a single crystal. As described above, the thermal process can include the RTP using a halogen lamp and the annealing process using a furnace device. Argon (Ar) gas or hydrogen (the annealing process using the furnace apparatus is performed for more than about 1 minute in a high-temperature atmosphere at a temperature higher than approximately 1 Torr. The anneal caused by the annealing process The diffusion of the oxide elements in the wafer and the rearrangement of the germanium form a desired region of the device (ie, a defect free region (DFZ)) in a portion of the top surface of the germanium wafer. However, as the size of the germanium wafer increases Annealing process is difficult to control due to Therefore, RTP obtains the characteristics of the germanium wafer superior to the annealing process. However, when using various defect detection methods to evaluate the silicon wafer fabricated by RTp, only oxygen is controlled. The precipitates are in a depth of from about 3 micrometers to about 1 micrometer from the top surface. Furthermore, when germanium wafers are fabricated by performing only RTP-times or twice, there is a limit to achieving high BMD density in the body region. More specifically, when the germanium wafer is manufactured by performing RTP-times, the BMD density is determined to be in the range from ixlO6 ea/cm2 to 3χ1〇6 ea/cm2, and it is difficult to make the ΒΜβ density exceed the range. In the embodiment of the present invention, as shown in FIG. 2 to FIG. 4, a two-step annealing process is performed after the thermal process 142898.doc •14·201026914, thereby removing void defects and oxygen deposition near the top surface of the germanium wafer. As a result, the present invention can ensure a defect-free zone (DFZ) and increase BMD density (including bulk stack defects and oxygen precipitates in the body region), thereby improving the absorption efficiency by increasing the suction sites in the body region. Should be. Below , Characteristic of the silicon wafer described in detail with reference to Table 1 and Table 2 by the embodiment of the present invention made in Example prepared. [Table 1]

條件1 條件2 條件3 條件4 南溫RTP 1050〇C~1150〇C 1050〇C~1150〇C 省略 省略 低溫RTP 950°C 〜l〇〇〇°C 省略 950〇C~1〇〇〇〇C 省略 低溫退火製程 750〇C~800〇C 750〇C~800〇C 750〇C~800〇C 750°C~B00°C 高溫退火製程 1000°C~1150°C 1000°C〜1150°C 1000°C~1150°C 1000°C~1150°CCondition 1 Condition 2 Condition 3 Condition 4 South temperature RTP 1050〇C~1150〇C 1050〇C~1150〇C Omit the omission of low temperature RTP 950°C ~l〇〇〇°C Omit 950〇C~1〇〇〇〇C Omit the low-temperature annealing process 750〇C~800〇C 750〇C~800〇C 750〇C~800〇C 750°C~B00°C High temperature annealing process 1000°C~1150°C 1000°C~1150°C 1000 °C~1150°C 1000°C~1150°C

[表2] 條件1 條件2 條件3 條件4 Oi (PPMA) 10.3 11.6 12.7 10.3 11.6 12.7 10.3 11.6 12.7 10.3 11.6 12.7 BMD密度 (ea/cm2) 3.03x 106 5.43χ ΙΟ6 8.85χ ΙΟ6 4.32χ ΙΟ5 9.35χ ΙΟ5 2.35χ ΙΟ6 2.12χ ΙΟ5 7.12χ ΙΟ5 1.25χ ΙΟ6 3.85χ ΙΟ5 5.12χ ΙΟ5 9.50χ ΙΟ5 DZ深度 (微米） 38.5 28.7 24.5 36.5 29.01 24.7 52.9 42.10 34.6 57.6 40.3 32.5[Table 2] Condition 1 Condition 2 Condition 3 Condition 4 Oi (PPMA) 10.3 11.6 12.7 10.3 11.6 12.7 10.3 11.6 12.7 10.3 11.6 12.7 BMD density (ea/cm2) 3.03x 106 5.43χ ΙΟ6 8.85χ ΙΟ6 4.32χ ΙΟ5 9.35χ ΙΟ5 2.35χ ΙΟ6 2.12χ ΙΟ5 7.12χ ΙΟ5 1.25χ ΙΟ6 3.85χ ΙΟ5 5.12χ ΙΟ5 9.50χ ΙΟ5 DZ depth (micron) 38.5 28.7 24.5 36.5 29.01 24.7 52.9 42.10 34.6 57.6 40.3 32.5

在表1中，使用氬（Ar)氣、氮（N2)氣、氨（NH3)氣或其組 合在快速熱處理下執行「高溫RTP」及「低溫RTP」歷時 大致10秒至大致30秒。使用氧（02)氣執行「低溫退火製 程」及「高溫退火製程」歷時大致100分鐘至大致180分 鐘。 在表1及表2中，「條件1」表示圖2中展示之第一實施 例，「條件2」表示圖3中展示之第二實施例，「條件3」表 142898.doc -15- 201026914 示圖4中展示之第三實施例且「條件4」表示圖5中展示之 第四實施例。表2展示根據每—條件中之氧濃度（〇〇之 BMD密度及剝蝕區（DZ)深度。 圖7至圖12為展示表1及表2之參數的曲線圖。詳言之， 圖7為說明關於每一條件之BMD密度之曲線圖。圖8為說明 關於每一條件之DZ深度之曲線圖。圖9至圖12為說明關於 . 每一條件之本體區域中氧濃度之曲線圖。 ， 參看表2及圖7，在所有條件下獲得大於1χ1〇5 ea/cm2之 BMD密度。特定言之，在條件丨下獲得大於1χ1〇6 ea/cm2之⑬ BMD密度（與氧濃度無關）。儘管未呈現關於藉由僅執行 RTP—次或兩次而製造之矽晶圓之BMD密度的資料，但可 預測該BMD密度與以上條件下之BMD密度相比將顯著較 低。 如先前所述，藉由吸取BMD來控制金屬污染物。然而， 因為在高溫製程期間BMD密度傾向於降低，所以在製造矽 晶圓期間需要確保高BMD密度。一般而言，半導體器件需 要在高壓環境下操作之高壓器件。為製造此高壓器件，必〇 需執行重度離子植入製程及高溫退火製程，此係因為需要 具有深分布之接合區域（亦即，摻雜區域）。當bmd密度在 高溫退火製程期間降低時，不僅歸㈣缺陷評估而且歸目* 於低吸取此力’在後繼淺渠溝隔離（sti)後出現環狀位錯。. 作f量測BMD密度之結果，當BMD密度為大致2.5X105 ea/cn^時部分出現環狀位錯，但當bmd密度為大致 m時不出現環狀位錯。因此，需要控制BMD密度大於 142898.doc • 16 - 201026914 至少1x10 ea/cm。在本實施例中，與製造矽晶圓期間之 習知熱製程無關，另外執行兩步驟退火製程以用於製造半 導體器件之初始製程。初始製程包括在用於形成一井之離 子植入之前執行的氧化製程。氧化製程對應於在用於形成 • 一井之離子植入（在下文中，稱為井離子植入）期間用於形 成遮蔽氧化物層之製程。 參看表2及圖8，展示根據每一條件之Dz深度。DZ深度 與BMD畨度及氧濃度緊密相關。隨著BMD密度及氧濃度 增加，DZ深度變得減小。#氧濃度在每一條件下相同（例 如，表2中之11.6)時，條件丨及條件2下之BMD密度高於條 件3及條件4下之BMD密度，但條件丨及條件2下之DZ深度 低於條件3及條件4下之DZ深度。因此，〇2深度可為bmd 密度之量測。 參看表2及圖9至圖12，展示每一條件下根據氧濃度之 BMD密度及DZ深度。隨著氧濃度（〇i)增加，bmd密度變 • 得增加但DZ深度變得減小。因此，氧濃度（〇〇亦為βμ〇密 度之量測。亦即，可藉由量測Dz深度及氧濃度（〇i)來計算 本體區域中之BMD密度。 圖13及圖14為石夕晶圓之橫截面圖。 詳言之，圖13展示藉由僅執行RTp但無兩步驟退火製程 而製造之碎晶圓之橫截面圖，且圖u展示藉由執行根據本 發明之-實施例的兩步驟退火製程製造之石夕晶圓之橫截面 圖。 如所展示，在圖之石夕晶圓中出現複數個梦位錯，但在 142898.doc 17 201026914 圖14之矽晶圓中不存在矽位錯。此外，當藉由使用磊晶成 長形成磊晶層時，矽晶圓之本體區域（其中形成磊晶層）中 之晶體缺陷顯著得以減少。 圖15及圖16說明石夕晶圓中本體區域（其中形成蠢晶層）之 晶體缺陷圖。使用由KLA公司製造之檢驗裝置執行此檢 驗。 如圖15所展示，在執行不具有兩步驟退火製程之氧化製 程時，大量晶體缺陷分布於圖中。在本文中，氧化製程在 井離子植入期間形成遮蔽氧化物層。相反，如圖16所展 示’在執行具有本發明之兩步驟退火製程之氧化製程時， 晶體缺陷顯著減少。 在下文中，將參看圖17A至圖17D詳細描述用於製造具 有用於尚壓器件之井之半導體器件的方法，該方法包括根 據本發明之一實施例的兩步驟退火製程。 圖17A至圖17D為說明根據本發明之實施例的用於製造 半導體器件之方法。 參看圖17A，使用圖6中展示之兩步驟退火製程在矽晶圓 600上形成遮蔽氧化物層6〇1。矽晶圓6〇〇可為如圖2至圖4 中所描述之對其應用RTP—次或兩次的晶圓，或為如圖5中 所描述之不對其應用RTP之裸晶圓。遮蔽氧化物層6〇丨可為 氧化秒層，且形成至範圍為大致10〇 A至大致14〇 A之厚 參看圖17B，在矽晶圓600中形成井602至一預定深度。 視高壓器件之導電類型而定，井6〇2可具有p型或n型導電 142898.doc •18· 201026914 類型。 經由離子植入製程及擴散過程形成井6〇2。僅使用離子 植入製程難以形成用於高壓器件之井。因此，應在完成離 子植入製程後另外執行擴散過程以及離子植入製程，以便 . 形成具有圖17B之摻雜分布之井602。使用諸如爐之高溫加 . 熱裝置經由退火製程執行擴散過程歷時長時間。較佳地， 僅使用氮（NO氣在範圍為大致11〇〇。〇至大致〖250=^之溫度 下執行擴散過程歷時大致6小時至大致1 〇小時。 參看圖17C，充當硬式光罩之襯墊氮化物層（未圖示）形 成於遮蔽氧化物層601上，或襯墊氮化物層形成於緩衝層 (未圖示）上，該緩衝層係藉由在移除遮蔽氧化物層601後執 打額外氧化製程而形成。移除遮蔽氧化物層6〇1之原因為 遮蔽氧化物層601不適合於緩衝層，因為遮蔽氧化物層6〇1 在離子植入製程期間受到損壞。接著在襯墊氮化物層上形 成用於形成STI渠溝之光阻圖案604。 φ 可經由低壓化學氣相沈積（LPCVD)製程形成襯墊氮化物 層以便在沈積製程期間藉由最小化施加至碎晶圓6〇〇之 應力而防止矽晶圓600受到損壞。襯墊氮化物層可由氮化 矽形成。可形成襯墊氮化物層至範圍為大致14〇〇 A至大致 2000 A之厚度。 使用光阻圖案604作為钮刻遮罩來按順序部分地姓刻襯 墊氮化物層、遮蔽氧化物層6〇1及矽晶圓6〇〇，藉此形成襯 墊氮化物圖案603、遮蔽氧化物圖案601A、矽晶圓6〇〇A及 井602A。結果，在矽晶圓6〇〇A中形成具有預定深度及傾 142898.doc •19- 201026914 角之渠溝605。 參看圖17D，形成填充渠溝6〇5之器件隔離結構6〇6，且 隨後移除襯墊氮化物圖案6〇3及遮蔽氧化物圖案6〇ia。器 件隔離結構606可由具有優良間隙填充性質之高密度電漿 (HDP)層形成。 在比較本發明之方法與比較性實例的同時，下文將描述 本發明之以上實施例之有利效應。本發明之方法包括經由 使用兩步驟退火製程之氧化製程形成遮蔽氧化物層而比 較性實例包括經由使用一步退火製程之氧化製程形成遮蔽 氧化物層。在此比較性實例之氧化製程中’使用濕式氧化 製程在範圍為800 C至850°C之單一溫度下氧化矽晶圓。 圖18至圖21說明由比較性實例之氧化製程製備之矽晶圓 中的缺陷。 詳言之，圖1 8說明在由比較性實例之氧化製程製備之矽 晶圓中經由STI製程形成一渠溝後由KLa公司所製造之檢 驗裝置所檢驗之晶體缺陷之圖資料。如圖18所展示，可觀 察到大多數缺陷晶圓中存在諸如環狀矽位錯之晶體缺陷。 圖19及圖20為由KLA公司所製造之檢驗裝置所獲取的矽 晶圓之掃描電子顯微鏡微觀（SEM)圖片。 具體而言，圖19為展示矽晶圓之戴面之SEM影像，且圖 20為平面傾斜STM影像。如圖19及圖2〇所展示，可觀察到 存在晶體缺陷及位錯。 圖21為展示對具有環狀缺陷之矽晶圓進行之本體微觀缺 陷（BMD)密度分析的顯微照片。 142898.doc -20- 201026914 如圖21所展示，可觀察到大多數bmd緊靠矽晶圓之頂面 形成’但少數BMD形成於矽晶圓之中央部分中，亦即，形 成於本體區域中。亦即，本體區域之BMD密度顯著低於矽 晶圓之頂面之BMD密度。 圖22至圖24為藉由使用根據本發明之實施例的兩步驟退 火製程之氧化製程製備的矽晶圓中晶體缺陷之檢驗結果。 使用由KL A公司製造之檢驗裝置執行此檢驗。 詳言之’圖22說明在於藉由使用本發明之兩步驟退火製 程之氧化製程製備的矽晶圓中經由STI製程形成渠溝後矽 晶圓之晶體缺陷的檢驗結果。如圖22所展示，可觀察到晶 體缺陷經移除且僅偵測到一些微粒或粉塵。 圖23為由KLA公司所製造之檢驗裝置所獲取的矽晶圓之 平面傾斜STM影像。與圖22之結果類似，可觀察到僅偵測 到一些微粒。 圖24為展示對藉由使用本發明之兩步驟退火製程之氧化 製程製備的石夕晶圓進行BMD密度分析之顯微照片。如圖24 所展不’可觀察到遍及矽晶圓均勻形成BMD。 圖25為說明靜態隨機存取記憶體（SRAM)之待用模式期 間漏電流之比較結果的曲線圖。在圖25中’左視圖展示藉 由使用本發明之兩步驟退火製程之氧化製程製備的高壓器 牛之樣本’且右視圖展示比較性實例之高壓器件之樣本。 « ____ 圖25所展示’可觀察到與藉由比較性實例之氧化製程製 備之樣本相比’藉由本發明之氧化製程製備之樣本呈現均 勻漏電流特徵。 142898.doc -21 - 201026914 圖26為說明生產良率之比較結果的曲線圖。在圖26中， 左視圖展示藉由使用本發明之兩步驟退火製程之氧化製程 製備的高壓器件之樣本，且右視圖展示比較性實例之高壓 器件之樣本。如圖26所展示，與比較性實例之樣本相比’ 藉由本發明之氧化製程製備之樣本的生產良率高大致5%_ 9%。 - 根據本發明，首先，可藉由在不同溫度下執行兩步驟退 _ 火製程而在矽晶圓中充分地產生吸取位點。此使得可能防 止晶體缺陷歸因於由後繼高溫熱處理製程引起之熱預算而 籲 產生。 其次，本發明可藉由在不同溫度下執行兩步驟退火製程 來提供在本體區域中具有高且均勻之BMD密度之矽晶圓。 第三，根據本發明，在於不同溫度下對矽晶圓執行兩步 驟退火製程後，使用蟲晶成長在破晶圓上形成蠢晶層。結 果，本發明可提供形成有具優良特性之磊晶層的半導體器 件。 第四’根據本發日月，在藉由在不同溫度下對石夕晶圓執行❿ 兩步驟退火製程來在碎晶圓上形成遮蔽氧化物層後，藉由 使用遮蔽氧化物層作為離子遮罩執行離子植入製程來在矽 明圓中形成一井。結果’本發明可在硬晶圓中充分地逢生 吸取位點以藉此防止晶體缺陷歸因於由後繼高溫熱處理冑 程引起之熱預算而產生。 儘管已關於特定實施例描述了本發明，但熟習此項技術 者將顯而易見可在不偏離由以下申請專利範圍定義之本發 142898.doc •22· 201026914 明的精神及範疇的情況下做出各種改變及修改。 【圖式簡單說明】 圖1為根據本發明之一實施例的矽晶圓之橫截面圖； 圖2為說明根據本發明之第一實施例的用於製造一碎晶 圓之方法的橫截面圖； 圖3為說明根據本發明之第二實施例的用於製造一矽晶 圓之方法的橫截面圖； 圖4為說明根據本發明之第三實施例的用於製造一矽晶 圓之方法的橫截面圖； 圖5為說明根據本發明之第四實施例的用於製造一矽晶 圓之方法的橫截面圖； 圖ό為說明根據本發明之一實施例的兩步驟退火製程方 法之曲線圖； 圖7為說明在各種條件下bmd密度之曲線圖； 圖8為說明在各種條件下剝蝕區之深度之曲線圖； 圖9至圖12為說明在各種條件下根據氧濃度之BMD密度 及剝姓區之深度之曲線圖； 圖13為根據比較性實例製造之矽晶圓之橫截面圖； 圖14為根據本發明之實施例製造之矽晶圓之橫截面圖； 圖15說明根據比較性實例製造之矽晶圓中本體區域之晶 體缺陷圖； 圖16說明使用根據本發明之一實施例的兩步驟退火製程 製造之矽晶圓中本體區域之晶體缺陷圖； 圖17A至圖17D為說明根據本發明之一實施例的用於製 142898.doc -23- 201026914 造半導體器件之方法； 圖18說明根據比較性實例製備之矽晶圓中之晶體缺陷的 檢驗結果； 圖19為藉由比較性實例之氧化製程製備的矽晶圓之掃描 電子顯微鏡（SEM)圖像； 圖20為藉由比較性實例之氧化製程製備的矽晶圓之平面 影像； 圖21為展示對藉由比較性實例之氧化製程製備的矽晶圓 進行之BMD密度分析的微觀圖像； 圖22說明根據本發明之一實施例之矽晶圓的晶體缺陷之 檢驗結果； 圖23為根據本發明之一實施例之石夕晶圓的平面影像· 圖24為展示對根據本發明之一實施例的石夕晶圓進 BMD密度分析的顯微照片； 用模式 期 圖25為說明在靜態隨機存取記憶體（SRam)之待 間漏電流之比較結果的曲線圖；及 圖26為說明生產良率之比較結果之曲線圖。 【主要元件符號說明】 100 碎晶圓 101 頂面 102 背面 103 本體微觀缺陷（BMD) 200 碎晶圓 201 頂面 142898.doc • 24· 201026914In Table 1, "high temperature RTP" and "low temperature RTP" are performed under rapid thermal processing using argon (Ar) gas, nitrogen (N2) gas, ammonia (NH3) gas or a combination thereof for about 10 seconds to about 30 seconds. The "low temperature annealing process" and the "high temperature annealing process" are performed using oxygen (02) gas for approximately 100 minutes to approximately 180 minutes. In Tables 1 and 2, "Condition 1" indicates the first embodiment shown in FIG. 2, and "Condition 2" indicates the second embodiment shown in FIG. 3, and "Condition 3" Table 142898.doc -15-201026914 The third embodiment shown in FIG. 4 and "Condition 4" represent the fourth embodiment shown in FIG. Table 2 shows the oxygen concentration (BMD density and the ablation zone (DZ) depth in each of the conditions. Figures 7 to 12 are graphs showing the parameters of Tables 1 and 2. In detail, Figure 7 shows A graph showing the BMD density for each condition is shown in Fig. 8. Fig. 8 is a graph illustrating the DZ depth for each condition. Fig. 9 to Fig. 12 are graphs illustrating the oxygen concentration in the body region of each condition. Referring to Table 2 and Figure 7, BMD densities greater than 1 χ 1 〇 5 ea/cm 2 were obtained under all conditions. In particular, 13 BMD densities greater than 1 χ 1 〇 6 ea/cm 2 were obtained under conditions ( (independent of oxygen concentration). Although no data is presented regarding the BMD density of a germanium wafer fabricated by performing only RTP-times or twice, it is predicted that the BMD density will be significantly lower than the BMD density under the above conditions. Controlling metal contaminants by drawing BMD. However, because BMD density tends to decrease during high temperature processing, high BMD density needs to be ensured during the fabrication of germanium wafers. In general, semiconductor devices need to operate in a high voltage environment. High voltage device. For manufacturing For high-voltage devices, it is necessary to perform a heavy ion implantation process and a high-temperature annealing process because it requires a deep-distributed bonding region (ie, a doped region). When the bmd density is lowered during the high-temperature annealing process, not only (4) Defect assessment and attribution * Low absorption of this force 'After the shallow trench isolation (sti), a circular dislocation occurs. The result of measuring the BMD density by f, when the BMD density is approximately 2.5X105 ea/cn^ Some annular dislocations occur, but no annular dislocations occur when the bmd density is approximately m. Therefore, it is necessary to control the BMD density to be greater than 142898.doc • 16 - 201026914 at least 1x10 ea/cm. In this embodiment, and manufacturing Regardless of the conventional thermal process during the wafer, a two-step annealing process is additionally performed for the initial process of fabricating the semiconductor device. The initial process includes an oxidation process performed prior to ion implantation for forming a well. The oxidation process corresponds to The process for forming a masking oxide layer during ion implantation for forming a well (hereinafter, referred to as well ion implantation). Referring to Table 2 and Figure 8, showing each Dz depth. DZ depth is closely related to BMD mobility and oxygen concentration. As BMD density and oxygen concentration increase, DZ depth becomes smaller. #Oxygen concentration is the same under each condition (for example, 11.6 in Table 2) The BMD density under conditions 丨 and 2 is higher than the BMD density under conditions 3 and 4, but the DZ depth under conditions 丨 and 2 is lower than the DZ depth under conditions 3 and 4. Therefore, 〇2 depth It can be measured by bmd density. See Table 2 and Figure 9 to Figure 12 for the BMD density and DZ depth according to the oxygen concentration under each condition. As the oxygen concentration (〇i) increases, the bmd density changes. The DZ depth becomes smaller. Therefore, the oxygen concentration (〇〇 is also measured as the βμ〇 density. That is, the BMD density in the body region can be calculated by measuring the Dz depth and the oxygen concentration (〇i). Fig. 13 and Fig. 14 are Shi Xi Cross-sectional view of a wafer. In detail, Figure 13 shows a cross-sectional view of a shredded wafer fabricated by performing only RTp but without a two-step annealing process, and Figure u shows an embodiment in accordance with the present invention. A cross-sectional view of the Si Xi wafer fabricated by the two-step annealing process. As shown, a plurality of dream dislocations appear in the Shi Xi wafer of the figure, but not in the wafer of 142898.doc 17 201026914 In addition, when an epitaxial layer is formed by epitaxial growth, crystal defects in the bulk region of the germanium wafer in which the epitaxial layer is formed are remarkably reduced. FIGS. 15 and 16 illustrate Shi Xijing. A crystal defect map of a central body region in which a stray layer is formed. This inspection is performed using an inspection device manufactured by KLA Corporation. As shown in Fig. 15, a large number of crystal defects are observed in an oxidation process without a two-step annealing process. Distributed in the figure. In this article, The oxidation process forms a masking oxide layer during well ion implantation. Conversely, as shown in Figure 16, 'the crystal defects are significantly reduced when performing the two-step annealing process with the present invention. In the following, reference will be made to Figure 17A. Figure 17D details a method for fabricating a semiconductor device having a well for a device under pressure, the method comprising a two-step annealing process in accordance with an embodiment of the present invention. Figures 17A through 17D illustrate an embodiment in accordance with the present invention. A method for fabricating a semiconductor device. Referring to FIG. 17A, a mask oxide layer 6〇1 is formed on a germanium wafer 600 using the two-step annealing process shown in FIG. 6. The germanium wafer 6 can be as shown in FIG. The wafers to which RTP is applied once or twice as described in Figure 4, or bare wafers to which RTP is not applied as described in Figure 5. The masking oxide layer 6 can be an oxidized second layer, And forming a thickness ranging from approximately 10 A to approximately 14 A. Referring to FIG. 17B, a well 602 is formed in the tantalum wafer 600 to a predetermined depth. Depending on the conductivity type of the high voltage device, the well 6〇2 may have p Type or n type conductive 14289 8.doc •18· 201026914 Type. Wells are formed through ion implantation processes and diffusion processes. It is difficult to form wells for high voltage devices using only ion implantation processes. Therefore, it should be performed after completion of the ion implantation process. The diffusion process and the ion implantation process are such that a well 602 having the doping profile of Fig. 17B is formed. The diffusion process is performed for a long period of time via an annealing process using a high temperature heating device such as a furnace. Preferably, only nitrogen is used (NO The gas is in the range of approximately 11 〇〇. The diffusion process is performed at a temperature of approximately 250 = ^ for approximately 6 hours to approximately 1 hour. Referring to Figure 17C, a pad nitride layer serving as a hard mask (not shown) ) is formed on the mask oxide layer 601, or a pad nitride layer is formed on a buffer layer (not shown) formed by performing an additional oxidation process after removing the mask oxide layer 601. The reason for removing the masking oxide layer 6〇1 is that the masking oxide layer 601 is not suitable for the buffer layer because the masking oxide layer 6〇1 is damaged during the ion implantation process. A photoresist pattern 604 for forming an STI trench is then formed over the pad nitride layer. φ The pad nitride layer can be formed via a low pressure chemical vapor deposition (LPCVD) process to prevent damage to the germanium wafer 600 during the deposition process by minimizing stress applied to the broken wafer. The pad nitride layer may be formed of tantalum nitride. A pad nitride layer can be formed to a thickness ranging from approximately 14 Å to approximately 2000 Å. The photoresist pattern 604 is used as a button mask to partially etch the pad nitride layer, the mask oxide layer 6〇1, and the germanium wafer 6〇〇 in order, thereby forming a pad nitride pattern 603, masking oxidation. The pattern 601A, the wafer 6A, and the well 602A. As a result, a trench 605 having a predetermined depth and a slope of 142898.doc • 19 - 201026914 is formed in the germanium wafer 6A. Referring to Fig. 17D, a device isolation structure 6?6 filling the trenches 6?5 is formed, and then the pad nitride pattern 6?3 and the mask oxide pattern 6?ia are removed. The device isolation structure 606 can be formed from a high density plasma (HDP) layer having excellent gap fill properties. While comparing the method of the present invention with a comparative example, the advantageous effects of the above embodiments of the present invention will be described below. The method of the present invention comprises forming a masking oxide layer via an oxidation process using a two-step annealing process, and a comparative example includes forming a masking oxide layer via an oxidation process using a one-step annealing process. In the oxidation process of this comparative example, a tantalum wafer was oxidized using a wet oxidation process at a single temperature ranging from 800 C to 850 °C. 18 to 21 illustrate defects in a germanium wafer prepared by the oxidation process of the comparative example. In particular, Fig. 18 illustrates a graph of crystal defects examined by a testing apparatus manufactured by KLa Corporation after forming a trench through a STI process in a wafer prepared by a comparative example oxidation process. As shown in Fig. 18, it is observed that crystal defects such as ring-shaped defects are present in most defective wafers. 19 and 20 are scanning electron microscope microscopic (SEM) images of a ruthenium wafer obtained by an inspection apparatus manufactured by KLA Corporation. Specifically, Fig. 19 is a SEM image showing the wearing surface of the enamel wafer, and Fig. 20 is a plane tilt STM image. As shown in Fig. 19 and Fig. 2, crystal defects and dislocations were observed. Figure 21 is a photomicrograph showing the bulk microscopic defect (BMD) density analysis of a germanium wafer with a ring defect. 142898.doc -20- 201026914 As shown in Figure 21, it can be observed that most of the bmd forms close to the top surface of the wafer. However, a small number of BMDs are formed in the central portion of the germanium wafer, that is, formed in the body region. . That is, the BMD density of the body region is significantly lower than the BMD density of the top surface of the wafer. 22 to 24 are test results of crystal defects in a germanium wafer prepared by an oxidation process using a two-step annealing process according to an embodiment of the present invention. This test was performed using an inspection device manufactured by KL A. DETAILED DESCRIPTION OF THE INVENTION Fig. 22 illustrates the results of inspection of crystal defects of a germanium wafer after formation of a trench through an STI process in a germanium wafer prepared by an oxidation process using the two-step annealing process of the present invention. As shown in Figure 22, it was observed that the crystal defects were removed and only some particles or dust were detected. Figure 23 is a plan view of a tilted STM image of a germanium wafer taken by an inspection apparatus manufactured by KLA Corporation. Similar to the results of Figure 22, it was observed that only some of the particles were detected. Figure 24 is a photomicrograph showing the BMD density analysis of a Shihua wafer prepared by an oxidation process using the two-step annealing process of the present invention. As shown in Fig. 24, it is observed that BMD is uniformly formed throughout the wafer. Fig. 25 is a graph showing the comparison result of the leakage current during the standby mode of the static random access memory (SRAM). In Fig. 25, the 'left side view shows a sample of a high pressure vessel prepared by an oxidation process using the two-step annealing process of the present invention' and the right side view shows a sample of a high voltage device of a comparative example. « ____ shown in Figure 25, it can be observed that the sample prepared by the oxidation process of the present invention exhibits a uniform leakage current characteristic as compared with the sample prepared by the oxidation process of the comparative example. 142898.doc -21 - 201026914 Figure 26 is a graph illustrating the comparison of production yield. In Fig. 26, a left side view shows a sample of a high voltage device prepared by an oxidation process using the two-step annealing process of the present invention, and a right side view shows a sample of a high voltage device of a comparative example. As shown in Fig. 26, the yield of the sample prepared by the oxidation process of the present invention was as high as about 5% to 9% as compared with the sample of the comparative example. - According to the present invention, first, the sucking sites can be sufficiently generated in the germanium wafer by performing a two-step annealing process at different temperatures. This makes it possible to prevent crystal defects from being attributed to the thermal budget caused by the subsequent high temperature heat treatment process. Second, the present invention provides a germanium wafer having a high and uniform BMD density in the body region by performing a two-step annealing process at different temperatures. Third, according to the present invention, after the two-step annealing process is performed on the germanium wafer at different temperatures, the insect crystal growth is used to form a stray layer on the broken wafer. As a result, the present invention can provide a semiconductor device in which an epitaxial layer having excellent characteristics is formed. Fourth, according to the date of the present invention, after the masking oxide layer is formed on the broken wafer by performing a two-step annealing process on the Shixi wafer at different temperatures, the masking oxide layer is used as the ion mask. The hood performs an ion implantation process to form a well in the circle. As a result, the present invention can sufficiently absorb the sites in the hard wafer to thereby prevent crystal defects from being generated due to the thermal budget caused by the subsequent high temperature heat treatment process. Although the invention has been described in terms of specific embodiments, it will be apparent to those skilled in the art that the invention can be made without departing from the spirit and scope of the invention, which is defined by the scope of the following claims. Change and modify. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a germanium wafer according to an embodiment of the present invention; FIG. 2 is a cross section illustrating a method for fabricating a wafer according to a first embodiment of the present invention. Figure 3 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a second embodiment of the present invention; and Figure 4 is a view for fabricating a germanium wafer in accordance with a third embodiment of the present invention; FIG. 5 is a cross-sectional view illustrating a method for fabricating a germanium wafer in accordance with a fourth embodiment of the present invention; FIG. 5 is a view illustrating a two-step annealing process in accordance with an embodiment of the present invention; Figure 7 is a graph illustrating the bmd density under various conditions; Figure 8 is a graph illustrating the depth of the ablation zone under various conditions; and Figures 9 through 12 are BMD illustrating the oxygen concentration under various conditions. FIG. 13 is a cross-sectional view of a germanium wafer fabricated according to a comparative example; FIG. 14 is a cross-sectional view of a germanium wafer fabricated in accordance with an embodiment of the present invention; FIG. Manufactured according to comparative examples A crystal defect map of a body region in a circle; FIG. 16 illustrates a crystal defect pattern of a body region in a germanium wafer fabricated using a two-step annealing process according to an embodiment of the present invention; FIGS. 17A to 17D are diagrams illustrating one of the present invention The method for fabricating a semiconductor device of the embodiment 142898.doc -23-201026914; FIG. 18 illustrates the inspection result of the crystal defect in the germanium wafer prepared according to the comparative example; FIG. 19 is an oxidation process by a comparative example Scanning electron microscope (SEM) image of the prepared tantalum wafer; FIG. 20 is a plan view of a tantalum wafer prepared by the oxidation process of the comparative example; FIG. 21 is a view showing the preparation of an oxidation process by a comparative example. A microscopic image of a BMD density analysis performed on a germanium wafer; FIG. 22 illustrates a test result of a crystal defect of a germanium wafer according to an embodiment of the present invention; FIG. 23 is a view of a silicon wafer according to an embodiment of the present invention. Plane Image · Figure 24 is a photomicrograph showing BMD density analysis of a Shihua wafer according to an embodiment of the present invention; (SRam) A graph of the comparison result of the leakage current; and Fig. 26 is a graph illustrating the comparison result of the production yield. [Main component symbol description] 100 Broken wafer 101 Top surface 102 Back surface 103 Body micro defect (BMD) 200 Broken wafer 201 Top surface 142898.doc • 24· 201026914

202 背面 203 氧化物元素 204 氧析出物核 205A 氧析出物 205B 經增大之氧析出物 300 破晶0 301 頂面 302 背面 303 氧化物元素 304 氧析出物核 305 氧析出物 400 碎晶圓 401 頂面 402 背面 403 氧化物元素 404 氧析出物核 405A 氧析出物 405B 經增大之氧析出物 500 碎晶圓 501 頂面 502 背面 503 氧化物元素 504 氧析出物核 505A 氧析出物 142898.doc -25- 201026914 505B 經增大之氧析出物 600 碎晶圓 600A 矽晶圓 601 遮蔽氧化物層 601A 遮蔽氧化物圖案 602 井 602A 井 603 襯墊氮化物圖案 604 光阻圖案 605 渠溝 606 器件隔離結構 BK 本體區域 DZ1 第一剝蝕區 DZ2 第二剝蝕區 142898.doc -26-202 Back surface 203 Oxide element 204 Oxygen precipitate core 205A Oxygen precipitate 205B Increased oxygen precipitate 300 Crystallization 0 301 Top surface 302 Back surface 303 Oxide element 304 Oxygen precipitate core 305 Oxygen precipitate 400 Broken wafer 401 Top surface 402 Back surface 403 Oxide element 404 Oxygen precipitate core 405A Oxygen precipitate 405B Increased oxygen precipitate 500 Crushed wafer 501 Top surface 502 Back surface 503 Oxide element 504 Oxygen precipitate core 505A Oxygen precipitate 142898.doc -25- 201026914 505B Increased Oxygen Precipitate 600 Crushed Wafer 600A 矽 Wafer 601 Masking Oxide Layer 601A Masking Oxide Pattern 602 Well 602A Well 603 Pad Nitride Pattern 604 Photoresist Pattern 605 Trench 606 Device Isolation Structure BK body region DZ1 first ablation zone DZ2 second ablation zone 142898.doc -26-

Claims (1)

201026914 七 、申請專利範圍·· 一種矽晶圓，其包含·· 一 ^_區，其經形成具有始於料 的一預定深度；及 只田 :本體區域，其形成於該第—剝钱區與該之一 背面之間， ❹ 2. 其中該第一剝蝕區經形成呈右 —大致8。微米之-深度有範:為始於該頂面的大 其中該本體區域巾氧之—濃度遍及該本龍域以在 10/〇内之一變化均勻分布。 ^睛求項1之⑦晶圓’其中該本體區域中—本體微觀缺 D)之'密度的範圍為大致Ixl。1 2 3 4 5 eaW至大致lx 10 ea/cm2 〇 142898.doc 1 ·如請求項1之石m其中該本體區域中氧之-濃度的 圍為大致10.5 PPMA至大致13 ppma(原子百萬分率）。 • 4.如：求们之矽晶圓’其進一步包含一遙晶層該蟲晶 2 層經由一磊晶成長而形成在該矽晶圓之該頂面上。 請长項1之矽晶圓，其進一步包含一第二剝蝕區，該 3 第一剝蝕區經形成於該本體區域下方且具有自該背面朝 向該頂面之方向的一預定深度。 4 6·如請求項5之矽晶圓，其中該第二剝蝕區經形成具有範 圍為始於該背面的大致20微米至大致80微米之一深度。 5 . 一種用於製造一矽晶圓之方法，其包含： 提供具有一剥蚀區及一本體區域之該矽晶圓； 201026914 在—第一溫度下對該矽晶圓執行一第一退火製程以在 該本體區域中補充產生氧析出物核及氧析出物；及 8. 9. 10. 11. 12. 13. 14. 在阿於該第-溫度之一第二溫度下對該石夕晶圓執行一 第退火製程以增大該本體區域中之該等氧析出物。 如喷求項7之方法’其中該第一退火製程係在範圍 致75〇。(：至大致8〇〇它之一溫度下執行。 如請求項7之方法，其中該第二退火製程係在範圍 致100〇t至大致115〇t之一溫度下執行。 如凊求項7之方法，其中該提供該矽晶圓包括： 在等於或低於該第二溫度之一第三溫度下對該石夕晶圓 行第熱製程以形成該剝钱區及該本體區域；及 在高於該第一溫度且低於該第1溫度之一第四溫度下 對該石夕晶圓執行-第二熱製程以在該本體區域中形成該 專氧析出物核。 請求項10之方法，其中該第一熱製程及該第二熱製程 係藉由—快速熱製程（RTP)或一退火製程執行。 青求項10之方法，其中該第一熱製程係在範圍為大致 1050 C至大致⑴代之―溫度下執行且該第二熱製程 係在範圍為大致95G°C至大致刪。(：之-溫度下執行。 青求項10之方法，其中該第一熱製程及該第二熱製程 使用ι(Αι°氣、氣⑽氣、氨（NH3)氣或其之一組合。 如請求項7之方法，其中該提供該矽晶圓包括： f等於或低於該第二溫度之一第三溫度下對該矽晶圓 執行—熱製程以形成該剝蝕區及該本體區域。 142898.doc 201026914 ΐ5·如請求項14之方法，其中該熱製程係在範圍為大致 1050°c至大致115〇t之一溫度下執行。 16.如吻求項7之方法，其中該提供該石夕晶圓包括： 在高於該第一溫度且低於該第二溫度的一第三溫度下 對該石夕晶圓執行-熱製程以形成該剝餘區及該本體區 域。 17. 如吻求項16之方法，其中該熱製程係在範圍為大致 950°C至大致1〇〇(rc之一溫度下執行。 18. 如請求項7之方法’其中該第-退火製程及該第二退火 製私係在氧（〇2)氣氛圍下執行。 :求項7之方法，其中該第一退火製程及該第二退火 製程中之每一者執行歷時大致1〇〇分鐘至大致⑽分鐘。 2 0.如請求jg 7 #古、土 ^ 法，其中該剝蝕區經形成具有範圍為始 ;§"石夕晶81之—頂面的大致職米至大致8G微米之-深201026914 VII. Patent application scope · A germanium wafer, comprising: a ^_ region formed by a predetermined depth starting from the material; and a field only: a body region formed in the first stripping area Between the back side of the one, ❹ 2. wherein the first ablation zone is formed to be right-about 8. The micrometer-depth has a range: a large one starting from the top surface, wherein the concentration of the oxygen in the body region is uniformly distributed throughout the local domain to change within one of 10/〇. The 'density' of the 7th wafer of the item 1 in which the body microscopically lacks D is approximately Ixl. 1 2 3 4 5 eaW to approximately lx 10 ea/cm2 〇 142898.doc 1 • The stone m of claim 1 wherein the oxygen-concentration in the body region is approximately 10.5 PPMA to approximately 13 ppma (atomic million rate). • 4. For example, the wafer of the 'the wafer' further includes a telecrystal layer. The crystal 2 layer is formed on the top surface of the germanium wafer by epitaxial growth. The wafer of length 1 further includes a second ablation zone formed over the body region and having a predetermined depth from the back toward the top surface. 4 6. The wafer of claim 5, wherein the second ablation zone is formed to have a depth ranging from about 20 microns to about 80 microns starting from the back side. 5. A method for fabricating a germanium wafer, comprising: providing the germanium wafer having a denuded region and a body region; 201026914 performing a first annealing process on the germanium wafer at a first temperature Supplementing the oxygen precipitate core and the oxygen precipitate in the body region; and 8. 9. 10. 11. 12. 13. 14. at the second temperature of the first temperature An annealing process is performed to increase the oxygen precipitates in the body region. The method of claim 7, wherein the first annealing process is in the range of 75 Å. The method of claim 7, wherein the second annealing process is performed at a temperature ranging from 100 〇t to approximately 115 〇t. The method, wherein the providing the germanium wafer comprises: performing a thermal process on the Shihua wafer at a third temperature equal to or lower than the second temperature to form the stripping area and the body region; Performing a second thermal process on the Shihua wafer above the first temperature and below the fourth temperature of the first temperature to form the oxygen-rich precipitate core in the body region. The method of claim 10 The first thermal process and the second thermal process are performed by a rapid thermal process (RTP) or an annealing process. The method of claim 10, wherein the first thermal process is in a range of approximately 1050 C to Substantially (1) is performed at a temperature - and the second thermal process is performed in a range of approximately 95 G ° C to approximately 5%. The method of claim 10, wherein the first thermal process and the first The two-heat process uses ι (Αι° gas, gas (10) gas, ammonia (NH3) gas or a combination thereof The method of claim 7, wherein the providing the germanium wafer comprises: f is performed at a third temperature equal to or lower than the second temperature to perform a thermal process on the germanium wafer to form the ablated region and the body region. The method of claim 14, wherein the thermal process is performed at a temperature ranging from approximately 1050 ° C to approximately 115 ° t. 16. The method of claim 7, wherein the providing The Shixi wafer includes: performing a heat process on the Shihua wafer at a third temperature higher than the first temperature and lower than the second temperature to form the stripping region and the body region. The method of claim 16, wherein the thermal process is performed at a temperature ranging from approximately 950 ° C to approximately 1 〇〇 (a method of claim 7) wherein the first annealing process and the first The method of claim 7, wherein the first annealing process and the second annealing process are performed for about 1 minute to approximately (10). Min. 2 0. If request jg 7 #古,土^ method, where the erosion zone Formed with a range from the beginning; § " Shi Xijing 81 - top surface of the general job to roughly 8G micron - deep 21. 如請求項7之方法 本體區域中包括該 之一密度經控制到 的範圍。 ，其中在執行該第二退火製程後，該 等氧析出物之一本體微觀缺陷（BMd) 大致 lxl〇5 ea/cm2 至大致 ixi〇7 ea/cm2 22. 如清求項7之方法， 本體區域中氧之—：執打該第二退火製程後，該 ;度經控制為遍及該本體區域以1 〇〇/0 内之—變化均勻分布。 23. 如請求項7之古 本體區域中氧之二t :在執行該第二退火製程後’該 濃度經控制到大致10.5至大致13 142898.doc 201026914 PPMA的範圍。 頂面上形 24.如請求項7之方法，其進一步包含： 移除在該第二退火製程期 成之一層氧化物層；及 經由，成長形成一蟲晶層，該蟲晶 矽晶圓之該頂面上。 …攻在4 25.如請求項7之方法，其進一步包含： 藉由使f層氧化物層作為—緩衝層在該以圓中形 二：：Γ該氧化物層係在該第二退火製程期間形成 在該石夕晶圓之一頂面上。 成長一單晶 26·如請求項7之方法，其中該提供該石夕晶圓包括 矽 將該經成長之單晶石夕切割為一晶圓形狀；及 士執行-㈣製程錢刻該經切割之々晶圓之表面或使 »亥經切割之矽晶圓之側面變圓。 27. -種用於製造一矽晶圓之方法其包含 提供該矽晶圓； 在:裝載溫度下將該石夕晶圓裝載至-加熱裝置内部； 執仃將該梦晶圓自該裝载溫度加熱至一第—溫度之一 第一加熱製程； 在該第一温度下執行使該矽晶圓退火之一第一退火製 程以產生氧析出物； 執仃將該石夕晶圓自該第—溫度加熱至高於該第一溫度 之一第二溫度的—第二加熱製程； 142898.doc -4- 201026914 在該第二溫度下執行使該碎晶圓退火之一第二退火製 程以增大該等氧析出物以用於增加其之一密度； 執行將該石夕晶圓自該第二溫度冷卻至一卸^溫度之一 冷卻製程；及 將該矽晶圓自該加熱裝置卸載至外部。 28. 如请求項27之方法，其中該提供該⑦晶圓包括： 藉由對該石夕M圓執行一熱製程而在該石夕晶圓中形成一 剝钮區及一本體區域。 29. 如請求項27之方法，社士 > # & 方法其中该裝載溫度之範圍為大致 6〇〇°C 至大致 7〇〇°c。 3〇·如请求項27之方法，其中該第一加熱製程之一升溫速率 的範圍為大致5°C/分鐘至大致8°C/分鐘。 31. 如請求項27之方法，其中該第一溫度之範圍為大致 750°C至大致8〇〇乞。 32. 如請求項27之方法，其中該第二加熱製程之一升溫速率 的範圍為大致5°C/分鐘至大致8〇c/分鐘。 33. 如請求項27之方法，其中該第二溫度之範圍為大致 1000 C 至大致 ii5〇°c。 34. 如請求項27之方法，其中該冷卻製程之一降溫速率的範 圍為大致2°C/分鐘至大致4。(:/分鐘。 35·如請求項27之方法’其中該卸載溫度之範圍為大致 75〇°C至大致8〇〇。匚。 36.如請求項27之方法，其中該卸載該矽晶圓係使用氮（N2) 氣執行^ 142898.doc 201026914 3 7.如請求項27之方法，其中該第一退火製程及該第二退火 製程係使用氧（〇2)氣執行。21. The method of claim 7 wherein the body region includes a range to which the density is controlled. , wherein after performing the second annealing process, one of the oxygen precipitates has a bulk microscopic defect (BMd) of approximately lxl 〇 5 ea/cm 2 to approximately ixi 〇 7 ea/cm 2 . Oxygen in the region—after the second annealing process is performed, the degree is controlled to be evenly distributed throughout the body region within 1 〇〇/0. 23. The second oxygen in the bulk region of claim 7 is: after performing the second annealing process, the concentration is controlled to a range of approximately 10.5 to approximately 13 142898.doc 201026914 PPMA. The method of claim 7, further comprising: removing one of the oxide layers during the second annealing process; and growing to form a worm layer, the worm wafer On the top surface. The method of claim 7, further comprising: forming the oxide layer in the second annealing process by using the f-layer oxide layer as a buffer layer The period is formed on one of the top surfaces of the Shi Xi wafer. The method of claim 7, wherein the providing the silicon wafer comprises: cutting the grown single crystal into a wafer shape; and performing the - (4) process cutting the cut The surface of the wafer is then rounded to the side of the wafer. 27. A method for fabricating a wafer comprising: providing the wafer; loading the Shihua wafer into the interior of the heating device at a loading temperature; and executing the loading of the wafer from the wafer Heating the temperature to a temperature-first temperature heating process; performing a first annealing process for annealing the germanium wafer to generate oxygen precipitates at the first temperature; a second heating process for heating the temperature to a second temperature higher than the first temperature; 142898.doc -4- 201026914 performing a second annealing process for annealing the chip at the second temperature to increase The oxygen precipitates are used to increase a density thereof; performing a cooling process for cooling the Shihua wafer from the second temperature to a temperature; and unloading the tantalum wafer from the heating device to the outside . 28. The method of claim 27, wherein the providing the 7 wafer comprises: forming a stripping region and a body region in the Shishi wafer by performing a thermal process on the Shishi M circle. 29. The method of claim 27, the socialist >#& method wherein the loading temperature ranges from approximately 6 〇〇 ° C to approximately 7 〇〇 ° c. The method of claim 27, wherein the temperature increase rate of one of the first heating processes ranges from approximately 5 ° C/min to approximately 8 ° C/min. 31. The method of claim 27, wherein the first temperature ranges from approximately 750 ° C to approximately 8 〇〇乞. 32. The method of claim 27, wherein the rate of temperature rise of the second heating process ranges from approximately 5 ° C/minute to approximately 8 ° C/minute. 33. The method of claim 27, wherein the second temperature ranges from approximately 1000 C to approximately ii5 〇 °c. 34. The method of claim 27, wherein the cooling rate of one of the cooling processes ranges from approximately 2 ° C/minute to approximately 4. (:/min. 35. The method of claim 27, wherein the unloading temperature ranges from approximately 75 〇 ° C to approximately 8 〇〇. 36. The method of claim 27, wherein the unloading the wafer The method of claim 27, wherein the first annealing process and the second annealing process are performed using oxygen (〇2) gas. The method of claim 27, wherein the first annealing process and the second annealing process are performed using a nitrogen (N2) gas. 142898.doc -6-142898.doc -6-
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