TW201007845A - AC/DC converters and methods of manufacturing same - Google Patents

Abstract

The present invention discloses AC/DC converters and methods of manufacturing the same. The method includes providing a substrate; forming an oxide layer on a top surface of the substrate; applying a photo-resist layer on the oxide layer to define a well region; performing an ion-implantation in the well region using a dopant; and driving in atoms of the dopant to a depth in the well region through a thermal treatment, wherein the driving in process provides a concentration profile of the dopant in the well region such that the semiconductor structure has a high breakdown voltage.

Description

201007845 IX. Invention Description: [Refer to the relevant patent application] This application is about and advocates the 2nd and 8th of February, ^ gram, Su Ji, Natali, Wang Shunyi and Cai Chenhui Hui ^ people Kolo flow converter BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC/DC converter and a method of manufacturing the same. [Prior technology] It is often necessary to have a double _ 湳鲭 湳鲭 51 51, the daily poverty, c to produce a customary pressure exchange, turn ====== ίϊϊΐ ί, also said that the completion of the structure is more complicated, and the stomach. ^ Furthermore, the custom design of the integrated singular scale changer, = low voltage pulse width modulation (PWM) controller and external components, such as start 2 MOS half field effect transistor _SFET) and so on. The AC_DC converter can include the PWM controller and the high voltage input mosfet. However, the size of the conventional integrated AC/DC converter is still large. Integrating many non-components into many complex processes leads to increased costs. Accordingly, the art requires an integrated unit 11' having more components and simplified circuitry to reduce final volume and reduce production costs. 5 201007845 Furthermore, when the conventional AC-DC converter component is activated, under ideal conditions, overcharge voltage will be avoided. Figure 16 is a block diagram of a conventional AC-to-DC converter that utilizes a soft start block (e.g., block 320) to reduce the rate of rise of the output voltage' to avoid damage based on the rapid rise of the output voltage. The conventional solution for soft start is to charge the external capacitor css by an internal current source (block 303 in Figure 16) and sense the voltage in the capacitor to limit the duty cycle until the output voltage reaches a specific one. The value is up. In addition to the soft start scheme, the AC-DC converter typically includes a phase compensation block (not shown) to synchronize the phase of the parent current. Therefore, what is needed in the art is a simplified solution. The integration of an external capacitor with a small current source allows the internal capacitor to be used for both soft start and phase compensation. SUMMARY OF THE INVENTION One aspect of the present invention is directed to a method of fabricating a semiconductor structure. The method comprises: providing a substrate, forming an oxide layer on a top surface of the substrate; applying a photoresist layer on the oxide layer to define a well region; using a dopant in the well region, , an ion implantation; and through the heat treatment technology, the molecules of the dopant are driven into the depth of the ^ region, wherein the driving process provides - a thicker to the light intermediate dopants - making the semiconductor structure highly resistant The characteristics of the pressure. The method of manufacturing a semiconductor structure is provided by the other. The present invention comprises a substrate provided with a substrate having a -part portion and a second portion; a top surface of the substrate forming a -first oxide layer; a first oxygen region in the first oxygen barrier layer defining the first well region; In the well zone, the first-permeate molecule is used in the second well region, and the first [middle-y-th degree, wherein the heat treatment system is at least Celsius Calitude • Hours, No. 201007845 A depth system greater than 5.5 microns and a second depth system greater than 3 microns. Another aspect of the present invention provides a method of manufacturing by the above method. The integrated circuit includes an integrated start source and supply voltage - a single voltage control H; and a single-start and supply voltage control (four) electric flute, which is responsible for converting high input voltage to single-start and supply voltage Internal supply voltage, wherein the first electro-crystalline system (DM 〇 S) taaalt 〇 金 氧 + 导体 导体 导体 导体 导体 导体 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟 熟Facing.

[Embodiment] The details of the various aspects of the present invention will be described in detail below, with the accompanying drawings of the examples of the embodiments. In the specification, the touch marks represent similar elements. A ^ (four) off towel, money _ money view secret - sewing money · DC converter, can be made with only 11 lithography masks. According to a preferred embodiment of the present invention, the method produces a high voltage double diffused N-type gold oxide (NLDMOS) and high voltage N-type gold oxide semiconductor (HVNM〇s) structure. Oh, need

Yes, this process can be used to fabricate other structures such as low voltage complementary metal oxide (CMOS) transistors, bipolar transistors, and passive components. Figure M1 is a cross-sectional view showing a method of fabricating an AC-DC converter in accordance with a preferred embodiment of the present invention. Referring to Figure 丨, the method forms an N-type well. As shown in FIG. 1, a substrate 1 〇 2 (preferably, but not limited to a p-type substrate) may have two portions, one portion forming an NLDMOS 11 〇 and the other portion forming a hvnm 〇 s 120 ° at - In the preferred embodiment, a plurality of n-type wells, 121, 122 can be formed in the substrate 1〇2. According to the present invention, in order to form an N-type well, first, a thin oxide layer can be formed on the top surface of the substrate 1〇2. Next, a layer of photoresist is applied and the position at which the N material is to be formed is defined using lithography. Then, the green can be transmitted through, for example, 嶙 7 201007845

As a dopant, the N-well is implanted at an appropriate concentration and energy. After the completion of the implantation process, the plasma chemical treatment and the photoresist stripping can be separately performed, and then the photoresist layer can be removed from the top surface of the substrate. Then, after heat treatment, the dopant phosphorus atoms can be driven into a desired depth. . Since the depth of the N-well junction will also increase as the applied thermal energy increases, the total temperature applied during the heat treatment can be at least 6,000 degrees Celsius. In a preferred embodiment of the invention, the N-well drive process provides a concentration characteristic to the dopant in the N-type well such that the final MOS structure has a high withstand voltage

= sex. For example, in operation, the ideal high withstand voltage can be 700V. In Figure 1, the junction depth 1 of the N-wells 112, 121, 122 can be greater than 5.5 microns after the drive-in process is completed. The method utilizes conventional techniques to remove the oxide layer during the drive-in process. Referring to Figure 2', the green method forms a p-type well. As shown in Fig. 2, a plurality of p-type wells 123, 125 can be formed in the substrate 2. Similar to the formation of the N-type well, the step of forming a first step can form a thin oxidation on the top surface of the substrate 102.

= This connector is in the coating-layer photoresist layer and uses lithography to define the position at which the P is to be formed. Next, P-type well implantation can be carried out at a suitable concentration by, for example, using boron as a dopant. After the implantation process is completed, the photoresist layer can be removed from the substrate and the 'through heat treatment' dopant can be driven into the ideal ride. As the applied heat energy increases, the P-type well junction, = will also deepen, so the total heat treatment _ job plus at least 6000 degrees · hour. Ingenuity - better thin +, p cake drive to provide - the concentration of the dopant in the well-type well makes the final M〇s structure with high resistance to waste, in the operation, the ideal high resistance &gt ;1 can be 7G0V. In Fig. 2, after the 0.00:: process, the junction depth of the p-wells 123, 125 can be greater than 3 and a half. The joint depth dl of the Fr., and the +-type wells 112, 121, and 122 may be greater than 5.5 micrometers. The oxide layer may be stripped after the drive-in process by conventional techniques. 201007845 Figure 3 illustrates the formation of an active area. First, the method can form a thin oxide layer 13 on the top surface of the substrate 1〇2 (then, a layer of Sl3N4 is deposited on the oxide layer 13〇. Then the method can apply a light on the Si3N4 layer 132. a resist layer (not shown). Then the 'active region can be defined by lithography, and the portion of the Si3N4 layer 132 that is not covered by the photoresist pattern is etched to expose the active region. Then, the method can strip the remaining light The pattern is blocked, leaving the structure shown in Figure 3.

In view of the present invention, a plurality of P-fields can be formed in the P-type well to increase the parasitic threshold voltage of the final structure. To form a p-type field, firstly, the method can form a photoresist layer having a predetermined pattern by using a conventional lithography technique, wherein the predetermined pattern only exposes a region where a P-type field is to be formed, and the method can be performed, for example, by deleting the cloth. Planting: To implement P-type field planting. After the implantation process is completed, the photoresist layer can be removed. = After 'P-field flooding process' This method drives boron ions into deeper layers in the substrate. As shown in FIG. 4, after driving into the process, the depth of the p-type field 126 can be, for example, greater than 3 microns. Next, a conventional heat treatment can be used to form a Weihua structure (F〇x) in a region not covered by the private team layer 132. After the field/structure is formed, Si3N4>f 132 can be stripped. Figure 4 shows the resulting structure of these processes, and two p-type fields 126 are formed in the p-well 125. Refer to Figure 5. According to the present invention, the p-type base region can be formed by conventional photo-resistance techniques. Next, the method can perform P-type base region implantation, f-stripping, and drive the base rotor. Preferred Embodiment = After the completion of the driving process, the depth d4 of the P-type base region 116 may be, for example, greater than 3 μm. Figure 5 shows the structure after completion of the above procedure, in which NLDMOS 110 on both sides of the N-type well ΐ2 can be formed. Two p-type base regions 116. According to the present invention, a gate electrode can be formed. After oxidation, the Tusk structure can be first deposited with a layer of sand. Then, the polycrystalline (tetra) can be oxidized. Know the lithography technology, carry out the lithography process to determine the _ pole. With the ^ isotropic galvanic _. The lion photoresist layer is shown in Figure 6. As shown in Figure 6, NL_S m has two 9 201007845 and HVNMOS 120 has two gate structures 161. As shown in Figure 7, the present invention can then form a p+ region in the P-type base region of nldmOS 110 and the p-type well of HVNMOS 120. These germanium regions and subsequently formed N+ regions The contact wires can be connected to NLDM〇s and hvnM〇s. This method can be formed by conventional lithography techniques and implanting procedures. +. Figure 7 shows the structure formed by these processes, in which two p+ regions 117 are formed in the p-type base region 116 of NLDM〇s, and two P+ regions 127 are formed in the p-type base region 125 of HVNM〇s. Referring to Figure 8, the present invention forms an n+ region in the P-type base region of the NLDMOS and in the N-type base region of the NLDMOS and HVNMOS. As described above, the present invention can form such a conventional lithography and implantation process. N+ zone to connect the contact wires. Furthermore, because the ions used in the N+ and P+ zones are large, in an ideal case, an additional drive-in procedure is required to drive the ions to the desired depth. 8 shows a structure formed by the equal process, in which the N+ region 118 is formed in the P-type base region 116 of the NLDMOS, and the N-well 112 in the NLDMOS 110 and the N-wells 121 and 122 in the HVNMOS 120 respectively form N+. Zones 119, 128, 129. According to the present invention, contact points can be formed, and then holes are formed to fill the holes with conductive materials, thereby providing an electrical connection between the NLDMOS/HVNMOS and an external circuit. Referring to Figure 9, The structure after the contact point is formed. Figure 8 = No layer can be deposited on the structure A vapor-deposited (CVD) film 14 〇. Next, the present invention can form contact holes 142 in the CVD film 14 by conventional lithography and etching techniques. As shown in FIG. 9, these contact holes 142 are preferably formed in Corresponding to the N+ or p+ region, which is the N+ or P+ region previously opened in the P-base, p-type or n-type well in the NLDMOS/HVNMOS. ^ According to the invention, the contact hole The top surface of CVD film 140 and CVD film 140 can be metallized to provide suitable electrical connections in such MOS devices. Only 10 201007845 This material can withstand the conventional process and at the same time achieve the desired electrical and physical properties. The present invention does not limit the metallized material. a According to the embodiment, metallization is first performed by metal sputtering to form a metal layer (not shown) on the CVD thin film 140. Next, the present invention can perform a lithography process on a metal layer to define an appropriate metal line pattern. Each contact hole 142 in FIG. 9 is now filled by metal 144 as shown in FIGS. 9 and 1B. ❹

According to the present invention, a PAD layer can be selectively implemented. First, a top surface of the structure shown in FIG. 1A can form a passivation layer 150. Then, the method can define and open some areas through the lithography process for subsequent packaging. Figure u shows the structure formed by these processes. In addition to the novel NLDMOS/HVNMOS structure and its method of fabrication, the present invention also provides a novel ic material for the startup and internal voltage regulation of an AC-DC converter. A true AC-DC converter has a smaller PCB footprint, which in turn provides smaller product size and lower cost. Figure 12 is a block diagram of an AC-DC converter of the present invention. As shown in Fig. 12, the internal design of ic includes a dashed box 300 in which the starting current source 3〇1 can be connected to the supply unit 3〇2, which can then be connected to the current reference unit 303. The ramp generator 304 can then be connected to the voltage and current reference unit 3. The DMOS transistor μ as in the above figure can be used as an output power switch. Since the HVNM〇s (ie, the high-voltage NLDMOS (ie, DMOS) in the wafer integration start-up circuit is turned on', the volume of the die is still relatively large: - the preferred embodiment - the AC-DC converter - a crime In the (4) of the present, through the start-up and supply pressure, 31 (which may include the start source 3 (1) and the feed dust 302 shown in Figure 12) 'DMOS transistor M1 in Figure 13 - The same operation, and thus reduced grain size. The other functions shown in Figure 12, DMOS transistor M2, operate in the same way. According to the invention, the high input voltage is converted into the internal supply voltage of the controller 312. In this novel design, the input high voltage MOSFET can be replaced by the same more efficient DMOS as the output DM 〇s transistor M2. Since the transistor is more efficient than conventional MOSFETs, this replacement would ideally be made. This design can further reduce the overall wafer volume. Therefore, the invention can not only reduce the manufacturing cost of the wafer, but also the product is more competitive, because the smaller 1C diaphragm volume can have more applications. , Figure 1^ The block 310 in ' preferably includes the design shown in Fig. 14. In another embodiment of the present invention, the output DM 〇 SM2 in Fig. 13 can be disposed outside the AC-DC converter 1C to further reduce the IC Volume, ® is shown in Figure 15. This embodiment can be applied in many applications, like a large current/high power 1C design. ^ In yet another embodiment of the invention, a parent flow enabling a soft start function is disclosed - DC Converter. Referring to Figure 17, an example of an AC-DC converter in accordance with one embodiment of the present invention is shown. Referring to Figure 17, in a startup sequence, logic block 330 is enabled to turn off the error amplifier (transistor). M3), and switch to the current source (II). The current source can then be supplied to the capacitor Ci, and the voltage in the capacitor ci can gradually increase as the conversion duty cycle increases. When the voltage on the feedback (FB) pin reaches When required, the 'start logic block 33' can then enable the error amplifier M3 and switch to the load resistor ri. In this case, the capacitor ci can be used as a phase compensation unit. The advantage of this novel 1C design is that Inside Capacitor ci, because = no external capacitor is required for soft start. In other words, no additional capacitor is needed. Furthermore, the internal soft start block 33 can be replaced with a phase compensation unit to reduce the components required in the wafer design. The present invention has been described in detail with reference to the preferred embodiments of the present invention, which are intended to illustrate the preferred embodiments of the present invention and are not intended to limit the invention. The scope of the invention is based on the scope of the application of the present invention. 12 201007845 = equalization & modification and modification, etc., should still be covered by the scope of the present invention [simplified description of the drawings] 'which shows the manufacture of the preferred embodiment of the invention A method of a parent current-to-DC converter; FIG. 12 is a block diagram showing an example of an AC current converter according to a preferred embodiment of the present invention;

Figure 13 is a block diagram showing an example of an AC-DC converter according to a preferred embodiment of the present invention; Figure 14 is a circuit diagram showing an example of an AC-DC converter according to a preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 16 is a block diagram of an exemplary AC-DC converter; FIG. 16 is a block diagram of a conventional AC-DC converter; and FIG. 17 is a preferred embodiment of the present invention. A block diagram of an example of an AC-DC converter. [Main component symbol description] 102 substrate 110 double diffused germanium type MOS semiconductor 112, 121, 122 Ν type well 116 基 type base region 117, 127 Ρ + region 118 Ν + region 119, 128, 129 Ν + region 13 201007845 120 high pressure N-type gold Oxygen semiconductor 123, 125 P-well 126 P-type field 130 oxide layer 132Si3N4 layer 140 CVD film 142 contact hole 144 metal 150 passivation layer 160, 161 gate structure 300 dashed box 301 start current source 302 supply voltage unit 303 voltage and current reference Unit 304 ramp generator 310 activates and supplies voltage controller 312 other functional blocks 320 soft start block 330 start logic block

14

Claims (2)

201007845 X. Application for patents: L The method of semiconductor structure, which comprises: = forming an oxide layer on the top surface of the board; coating the photoresist layer on the emulsion layer to define a well area. a dopant, an ion cloth and a direct "factory process" to drive the molecules of the dopant into the well region, and the ❹r process provides a concentration characteristic to the dopant in the well region, The oblique conductor structure has the characteristics of high fuel pressure. 2. The method described in Item 1 is: the heat treatment is at least Celsius 〇 · · 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 3. 3. 3. 3. 3. 3. 3. 3. 3. 3. The method of claim 3, wherein the hybrid system is greater than 55 micrometers. 5. The method of claim 3, wherein the well region is a well region 6. The method of claim 1, wherein the depth is greater than 3 microns. 7. The method of claim 6 wherein the blending relationship is rotten. 8. The method of claim 6 Wherein the well region is a 井-type well region. 9. A method of fabricating a semiconductor structure, the method comprising: lifting, a substrate, The substrate has a first portion and a second portion; a first oxide layer is formed on the top surface of the substrate; and a first photoresist layer is coated on the first oxide layer to define a first well region; 201007845 In the first well area, using the first inspection secret 10, through-heat treatment technology, & performing - the first ion implantation; the molecular enthalpy of the m 帛 _ is stripped of the first well region a first oxide layer; a second oxide is formed on the top surface of the substrate; and a second layer is coated on the first oxide layer to form a first well region, in the first well region & utilized-second doping. Through the heat treatment technique, a second depth of the first-to-fth f-f, a molecule of the first dopant, is driven into the second well region Wherein the heat treatment is at least 摄 〇 5.5 μm and the second depth is greater than 3 μm. The method of claim 9, further comprising: forming a third oxide layer on the top surface of the substrate; depositing a nitriding stone on the a second oxide layer. f the nitriding coating - the third photoresist is a part of the ;; and after the shadowing process, the third photoresist layer is uncovered, the gasification 'extracts one of the third photoresist layers The remaining portion is formed to form the active region. The method of claim 10, further comprising: forming a fourth photoresist layer having a predetermined pattern; exposing a portion to form a field region; using a second dopant Planting for a planting; driving the molecules of the second dopant of the second phase into the field region - the third product; the nitride-uncovered region forming a field oxide structure; stripping The gas phase forms the field in the first and second zones. 12. The method of claim η, further comprising: 16 201007845 forming a base region; driving the base region into a fourth depth in the first portion of the substrate on both sides of the first well region; The first and second portions of the substrate form a gate structure; a first ion region is formed in the base region of the first portion of the substrate and the second well region of the second portion; Forming a second ion region in the base region of the first portion and the first well region of the first portion and the second portion; corresponding to the first ion in a CVD film deposited on the substrate A contact hole is formed at the region or the second ion region of the 3H, and the contact hole is filled with a metal to provide electrical connection between the first portion and the second portion of the substrate. 13. The method of claim 12, further comprising: forming a purification layer on the top surface of the substrate; and defining additional regions in the passivation layer. 14. The method of claim 11, wherein the third depth system is greater than 3 microns. 15. The method of claim 12, wherein the fourth depth system is greater than 3 microns. 16. An integrated circuit manufactured by the method of any one of claims 1 to 15, the integrated circuit comprising: a single start-up and voltage controller for integrating a start source and a supply voltage; a transistor electrically coupled to the single start-up and supply voltage controller to convert the high input voltage to an internal supply voltage of the single start-up and supply voltage controller, wherein the first electro-crystalline system has a double diffused gold oxide Semiconductor (DMOS) transistor. 17 201007845 17. The integrated circuit of claim 16 further comprising: a controller 1; the DC controller is electrically connected to the single start and supply surface control crystal is electrically connected to the AC/DC controller, , , δ 第二 second second crystal system, a DMOS transistor. 18. SC two-body circuit 'where the second electro-crystalline system is in the product 19. The integrated circuit of claim π, further comprising: a startup logic selectively enabling an error amplifier based on a demand value achieved by a feedback (FB) pin; and an internal capacitor When the enable logic enables the error amplifier, it acts as a phase compensation unit to synchronize one phase of an alternating current. The method of claim 1, wherein the high withstand voltage system 700V 〇 during operation