200930202 九、發明說明： 【發明所屬之技術領域】 ' 本發明涉及電路板製作技術，尤其涉及一種電路板製 *作方法及用該方法製作之電路板。 【先前技術】 隨著電子產品往小型化、高速化方向之發展，電路板 亦從單面電路板、雙面電路板往多層高密度電路板方向發 ❹展。多層高密度電路板是指具有多層導電線路之電路板， 其具有較多佈線面積、較高互連密度，因而得到廣泛應用， 請參見Takahashi，A.等人於1992年發表於IEEE Trans, on Components, Packaging, and Manufacturing Technology 之 文獻 High density multilayer printed circuit board for HITAC M-880。 多層高密度電路板之各層導電線路之間通過導孔實現 電連接。該導孔係指穿透各層導電線路之間之樹脂層，且 _孔壁具有一定厚度之可導電鍍銅層用於電連接各層導電線 路之通孔、盲孔或埋孔。多層電路板中導孔之品質十分重 要，其會影響電路板各層導電線路之間之電連接效果，進 而影響多層電路板之工作性能。 多層高密度電路板製作過程中導孔通常通過如下方法 製作。首先，於覆銅基板（Copper Clad Laminate，CCL) 之預定位置鑽孔，該覆銅基板係指包括銅箔及樹脂層之板 狀基材。其次，進行鍍銅工序，於所鑽孔之孔壁及覆銅基 200930202 ==表面依次形成化學銅層與電鑛銅層，以便後續進 f電線路之製作，再次，進行填孔（塞孔）工序，利用 -油墨等填孔材料將鍍鋼後之導孔填充，使得覆銅 平整。為製作成多層高密度電路板，通常還會於 =成WL與導電線路之覆銅基板外表_合其他覆銅基 ==於壓合之其他覆銅基板上進行鑽孔、鑛銅、線路 衣作專步驟以實現增層之目的。 ❹料為用習知製作方法進行導孔填孔時，由於填孔材 ♦^ #用或填充材料中溶劑揮發等原因，容易於導孔 处生填孔凹陷110,如圖！所示。由於填孔凹陷η〇之產 生’習知填孔技術並不能滿足多層高密度電路板導孔製作 =要，特別無法適應高階盲孔或埋孔之製作需求，會影 板之品f。例如，填孔凹陷no如果存在於多層高 密度電路板產品訊號線路上，可能會影響訊號之傳輸；填 孔凹陷110如果存在於高階導孔（如二階盲孔）位置，可 ❹能會影響高階導孔之製作精度。此外，出現填空凹陷還會 造成覆銅基板表面不平整’從而導致表面之銅層厚度不 均，不利於導電線路之製作。 有鑑於此’提供一種電路板製作方法及用該方法製作 之電路板，以有效去除填孔時產生之填孔凹陷，進而提高 多層尚密度電路板之製作品質實屬必要。 【發明内容】 以下將以實施例說明—種電路板製作方法及用該方法 8 200930202 製作之電路板。 該電路板製作方法，其包括以下步驟：提供具有至少 ，-導孔之覆銅基材，導孔之導電層與覆銅基材表面之銅層 相連；於導孔中填充填孔材料；於覆銅基材表面之銅層設 置導孔撞片，使導孔擋片完全遮蓋填充填孔材料之導孔； 微㈣位於導孔擔片之外區域之覆銅基材表面之銅層，從 而形成位於填充填孔材料之導孔處之凸出部；去除凸出 部’從而使得填孔材料之表面及位於覆銅基材表面之銅層 ❹之表面處於同一平面。 該電路板，其包括至少一導孔，該導孔中填充有填孔 材料，填孔材料之表面及與導孔之導電層相連之銅層之表 面處於同一平面。 本技術方案之電路板製作方法及用該方法製作之電路 板具有如下優點：首先’於覆銅基材表面之銅層設置導孔 擋片，微蝕刻去除位於導孔擋片之外區域之覆銅基材表面 ⑩之銅層，從而降低了覆銅基材表面之銅層之厚度，有利於 高密度細線路之製作；其次，於微蝕刻銅層之後，形成位 於填充填孔材料之導孔處之凸出部，填孔凹陷同時會凸出 於覆銅基材表面銅層之表面，去除凸出部可有效消除導孔 填孔過程中可能存在之填孔凹陷，進而平整覆銅基板表 面’使得填孔材料之表面與位於覆銅基材表面之銅層之表 面位於同一平面，同時於覆銅基板之表面形成厚度均勻之 銅層’利於高階導孔以及後續電路板增層之製作。 9 200930202 【實施方式】 下面將結合附圖及實施例，對本技術方案提供之電路 板製作方法及用該方法製作之電路板作進一步之詳細說 明。 請參閱圖2,本技術方案實施方式提供之電路板製作方 法包括以下步驟： 第一步，提供具有至少一導孔20之覆銅基材10。 該覆銅基材10具有至少兩層銅層及至少一層位於該至 ❹少兩層銅層之間之樹脂層，因此該覆銅基材10可為單層雙 面覆銅線路基板，亦可為已完成内部線路製作、尚未進行 表面線路製作之多層線路基板。請參閱圖2，本實施例中， 覆銅基材10為多層線路基板，該覆銅基材10包括第一基 材11以及壓合於第一基材11之第二基材12。該第一基材 11包括第一銅層111及第一樹脂層112，該第二基材12包 括第二銅層121及基板層122。其中，該第二銅層121已形 &成為導電線路，該基板層122可為多層線路基板，亦可為 〇 單層樹脂層。該第一樹脂層112壓合於第二銅層121，從而 形成多層結構之覆銅基材10。當然，如果覆銅基材10不包 括基板層122時，該覆銅基材10即可視為單層雙面覆銅基 材，此時該第二銅層121可先不形成導電線路。 該覆銅基材10具有一個或複數導孔20。該導孔20係 指於覆銅基材10形成之導通孔或盲孔，該導通孔或盲孔之 内壁已形成有鍍銅層以實現不同銅層之間之電連接。本實 施例中，以覆銅基材10具有一個導孔20為例進行填孔方 200930202 法之說明。該導孔20為貫穿第一銅層m、第一樹脂層ι12 ,之盲孔，且該導孔20内壁形成有鍍銅層23a作為導電層， 用於第一銅層111與第二銅層121之間之電連接，而在位 於導孔20中第二銅層121表面亦會相應形成鍍銅層23a。 即’導孔20之一端通過内壁之鍍銅層23a與第一銅層m 相連，導孔20之另一端通過内壁之鍍銅層23a與第二銅層 121相連’而第二銅層121位於基板層122，並由此被第一 銅層111與基板層122封閉，從而形成盲孔結構。鍍銅層 〇 23a可採用化學鍍銅或電鍍銅之方法形成，因此於該第一銅 層111之表面會形成鍍銅層23b，鍍銅層23b成為表面銅 層，從而導致表面銅層厚度增加。當然，如果覆銅基材10 不包括基板層122時’此時導孔20可為電連接第一銅層ill 及第二銅層121之導通孔結構’此時導孔20之兩端均為開 放狀態。且鑛銅層23b會同時形成於該第一銅層ill與第 二銅層121之表面，成為表面銅層，從而導致表面銅層厚 度增加。當然，亦可採用其他方法製作導孔20，使得鍍銅 〇 層不會形成於第一銅層111之表面，從而使得覆統基材10 表面銅層之厚度不會額外增加。 該第一樹脂層112及基板層122可為硬性樹脂層，如 環氧樹脂、玻纖布等，亦可柔性樹脂層，如聚醯亞胺 (Polyimide，PI)、聚乙烯對苯二曱酸乙二醇醋（Polyethylene Terephtalate, PET)、聚四 I 乙烯（Teflon)、聚硫胺 (Polyamide)、聚曱基丙稀酸曱酉旨（Polymethylmethacrylate)、 聚碳酸酯（Polycarbonate)或聚醯亞胺-聚乙烯-對苯二甲酯共 11 200930202 聚物（Polyamide polyethylene-terephthalate copolymer)等。 另外，第一銅層111與第一樹脂層112之間、第二銅層121 與基板層122之間還可具有黏膠層，以使得第一銅層111 •與第一樹脂層112、第二銅層121與基板層122之間具有較 大之黏結力。 第二步，於導孔20中填充填孔材料25。 為了便於後續高階導孔之製作以及增層製作，採用填 孔材料25填充導孔20，如圖3所示。該填孔材料25可為 ❹導電膏或有機樹脂等，優選為導電膏。填孔材料25可採用 網版印刷之方法填充到導孔20中。具體地，採用具有與導 孔20位置相對應之網印圖案之印刷網版，使其設置於覆銅 基材10表面銅層之表面，即鐘銅層23b之表面，然後利用 刮刀將填充材料25擠壓通過印刷網版之網印圖案，從而填 充到導孔20中。填充材料25填充到導孔20中後，經固化 即可牢固之存在於導孔20中。但，由於固化過程中填充材 _料25中溶劑揮發以及重力作用之影響，可能於導孔20中 靠近第一銅層111與鍍銅層23b之一端形成填孔凹陷251， 從而導致覆銅基材10表面不平整。當然，根據填充材料25 之選擇，填孔凹陷251可能並不十分明顯，填孔凹陷251 之深度小於第一銅層111與鍍銅層23b厚度之和，但可能 大於、等於或小於鍍銅層23b之厚度。 第三步，於覆銅基材10表面銅層之表面設置導孔擋片 30，使導孔擋片30完全遮蓋填充填孔材料25之導孔20。 本實施例中，由於導孔20為盲孔結構，鍍銅層23b形 12 200930202 成於第一銅層111表面而成為覆銅基材10之表面之銅層， 因此僅需要於導孔20所對應之鍍銅層23b之表面設置導孔 擋片30。該導孔擋片30可採用幹膜光阻或液態光阻製作而 >成。本實施例中，採用幹膜光阻製作導孔擋片30，即選用 與導孔20尺寸相應之幹膜光阻直接壓合貼附於鍍銅層23b 表面，使得幹膜光阻完全遮蓋導孔20,即覆蓋導孔20周邊 之鍍銅層23b材料以及填充於導孔20中之填孔材料，並露 出導孔20周邊之外之鑛銅層23b材料，如圖4所示。當然， ©如果採用液態光阻製作導孔擋片30，可利用點塗之方式或 網版印刷之方式進行塗佈，使得液態光阻完全遮蓋導孔 20，即覆蓋導孔20周邊之鍍銅層23b材料以及填充於導孔 20中之填孔材料，並露出導孔20周邊之外之鍍銅層23b 材料，然後再將液態光阻進行固化。設置於導孔20處之導 孔擋片30可保護導孔20，以使得位於導孔20周邊之銅層 材料以及填充於導孔20中之填孔材料於後續之微蝕刻步驟 中不會被钱刻掉。 當然，如果覆銅基材10不包括基板層122時，該導孔 20為電連接第一銅層111與第二銅層121之導通孔時，由 於導孔20之兩端均為開放狀態，故亦可於覆銅基材10相 對兩表面之銅層同時設置導孔20之導孔擋片30,即於形成 於第一銅層111表面與第二銅層121表面之鍍銅層23b同 時設置導孔20之導孔擋片30，以使得位於導孔20周邊之 銅層材料以及填充於導孔20中之填孔材料於後續之微蝕刻 步驟中不會被蝕刻掉。 13 200930202 第四步，微蝕刻位於導孔擋片30之外區域之覆銅基材 .10表面之銅層’從而形成位於導孔20處之凸出部32。 . 利用銅蝕刻液對位於導孔擋片30之外區域之覆銅基材 10表面之銅層進行微蝕刻，以減小覆銅基材1〇表面銅層之 厚度，從而形成凸出於覆銅基材表面銅層之表面之凸出 部32，較薄之表面銅層厚度有利於製作高密度細線路。微 蝕刻銅層之厚度應當大於或等於填孔凹陷251之深度，以 使得填孔凹陷251可凸出於覆銅基材1〇表面銅層之表面。 本實施例中，利用銅蝕刻液恰好微蝕刻位於導孔擋片 30之外區域之覆銅基材1〇表面之鍍銅層23b及部分厚度第 一銅層in,從而留下厚度較薄第一銅層llla成為表2銅 層，使得填孔凹陷251可全部凸出於第一銅層llu之表 面。該銅蝕刻液可為硫酸-雙氧水、過硫酸銨_硫酸、過硫酸 鈉-硫酸、過硫酸鉀-硫酸、氣化銅-硫酸等混合微蝕體系。 該銅蝕刻液蝕刻銅層之速度跟銅蝕刻液之成分、濃度、蝕 ❿刻溫度、處理方法均密切相關。適當控制覆銅基板1〇之蝕 刻速度以及蝕刻時間即可恰好除去鍍銅層2扑或鍍銅層 23b及。卩为厚度之第一銅層lu。舉例來說，以喷霧式處理 法將硫酸-雙氧水系微蝕液於38攝氏度環境下以i 3kg/m2 之喷壓喷淋至走板速度為2.im/min之電路板表面時，微蝕 速度約為Ι/zm/min，若第一銅層ιη與鍍銅層2补之厚度 之和為1.4〜l.6mil (即35·56〜復64//m)，則約需餘刻^ 刀鐘，即可恰好除去厚度為〇 4〜〇 6恤（即 鍍銅層23b及部分厚度第一銅層lu，從而留下厚度較薄第 200930202 銅層Ilia成為表面銅層，盆 此時，導孔2。及= '二護於Γ —刻祕刻，從而與導孔擋二 =出於第一銅層11U表面之凸出部％， 匕括導孔擔片3〇、部分鑛銅層2 材料H “ 科、部分鍍銅層23a 所L刀第一銅層111材料及部分填充材料25,如圖5 ❹23b 如^真孔凹陷251深度較小，例如小於錢銅層 23^ ^微韻刻位於導孔撐片3〇之外區域之錄 銅層现，而第一銅層m不被 =Γ:第—銅層111表面，凸⑷^ 部^充材料^鐘銅層现材料、部分鑛銅層-材料及 声之除導孔20處突出於覆銅基材1〇表面之銅 二面二 得填孔材料25之表面及位於覆銅基材 ®表面平整。5層之表面處於同—平面’從而使得覆銅基材10 i f實知例中’當鍍銅層23b被微钱刻後，較薄第一銅 :一广為覆銅基材10表面之銅層，因此凸出部％突出於 9ίΓ走層llU之表面。本實施例中，採用磨刷方法去除導 銅A材1=於覆銅基材1〇表面之銅層之凸出部32進行覆 銅基材10表面之平整。苦杰 — 導孔20處凸出於第一二進：第-磨刷工序，以去除 銅基材H)表面平整，3 6 32’使得覆 十 如圖6所不。本實施例中，第一磨刷 15 200930202 70Π 1 磨刷輪進行磨刷。具體地，採用磨刷精度為 I: 之陶曼磨刷輪對覆銅基材10表面進行磨刷，由 陶免具有硬度’當陶究磨刷輪與凸出於第-銅層 ?la表面之凸出部32碰撞時，凸出部32即可被削去，使 侍填孔材料25之表面及第-銅層Ula之表面位於同一平 面，從而使得覆銅基材10表面平整，填孔材料乃之表面 與第一銅層UU之表面具有相同之粗輪度。如圖6所示。200930202 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a circuit board manufacturing technology, and more particularly to a circuit board manufacturing method and a circuit board manufactured by the method. [Prior Art] With the development of electronic products in the direction of miniaturization and high speed, the circuit board has also been developed from a single-sided circuit board and a double-sided circuit board to a multi-layer high-density circuit board. A multi-layer high-density circuit board refers to a circuit board having a plurality of layers of conductive lines, which has a large wiring area and a high interconnect density, and thus is widely used. See Takahashi, A. et al., 1992, IEEE Trans, on Components, Packaging, and Manufacturing Technology. High density multilayer printed circuit board for HITAC M-880. Electrical connections are made between the conductive lines of the layers of the multilayer high-density circuit board through the via holes. The via hole refers to a resin layer penetrating between the conductive lines of each layer, and the conductive copper plated layer having a certain thickness of the hole wall is used for electrically connecting the through holes, blind holes or buried holes of the conductive lines of the respective layers. The quality of the vias in a multilayer circuit board is very important, which affects the electrical connection between the conductive traces of the various layers of the board, which in turn affects the performance of the multilayer board. The via holes in the fabrication of a multilayer high-density circuit board are usually fabricated as follows. First, a hole is drilled at a predetermined position of a copper clad laminate (CCL), which is a plate-like substrate including a copper foil and a resin layer. Secondly, the copper plating process is carried out, and a chemical copper layer and an electric ore copper layer are sequentially formed on the hole wall and the copper-clad base 200930202 == surface of the hole for subsequent fabrication of the electric circuit, and again, the hole is filled (plug hole) In the process, the via hole after the steel plating is filled with a hole-filling material such as ink, so that the copper plating is flat. In order to make a multi-layer high-density circuit board, it is usually used for the surface of the copper-clad substrate with WL and conductive lines. _Other copper-clad substrates are used for drilling, copper, and line clothing on other copper-clad substrates that are pressed together. Take special steps to achieve the purpose of adding layers. When the material is filled in the hole by the conventional manufacturing method, it is easy to fill the hole depression 110 at the guide hole due to the evaporation of the solvent in the filling material or the filling material, as shown in the figure! Shown. Due to the production of 填 填 填 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 多层 多层 多层 多层 多层 多层 多层 多层For example, if the hole filling recess no exists on the multi-layer high-density circuit board product signal line, it may affect the signal transmission; if the hole filling recess 110 exists in the high-order guiding hole (such as the second-order blind hole), the high-order can be affected. The precision of the guide hole. In addition, the occurrence of void-filled depressions may also cause the surface of the copper-clad substrate to be uneven, resulting in uneven thickness of the copper layer on the surface, which is disadvantageous for the fabrication of the conductive traces. In view of the above, it is necessary to provide a circuit board manufacturing method and a circuit board produced by the method to effectively remove the hole-filling recesses generated during the filling of the holes, thereby improving the manufacturing quality of the multilayer-density circuit board. SUMMARY OF THE INVENTION Hereinafter, a circuit board manufacturing method and a circuit board manufactured by the method 8 200930202 will be described by way of embodiments. The circuit board manufacturing method comprises the steps of: providing a copper-clad substrate having at least a via hole, wherein the conductive layer of the via hole is connected to the copper layer on the surface of the copper-clad substrate; filling the hole-filling material in the via hole; The copper layer on the surface of the copper-clad substrate is provided with a guide hole striker, so that the guide hole cover completely covers the guide hole filled with the hole-filling material; and micro (4) the copper layer on the surface of the copper-clad substrate located outside the guide hole-supporting piece, thereby Forming a protrusion at the via hole filling the hole-filling material; removing the protrusion portion such that the surface of the hole-filling material and the surface of the copper layer on the surface of the copper-clad substrate are in the same plane. The circuit board includes at least one via hole filled with a hole-filling material, and the surface of the hole-filling material and the surface of the copper layer connected to the conductive layer of the via hole are in the same plane. The circuit board manufacturing method of the technical solution and the circuit board produced by the method have the following advantages: firstly, a via hole stopper is disposed on the copper layer on the surface of the copper-clad substrate, and the micro-etching removes the region outside the via hole blocking sheet. The copper layer on the surface 10 of the copper substrate reduces the thickness of the copper layer on the surface of the copper-clad substrate, which is favorable for the fabrication of high-density fine lines. Secondly, after the micro-etching of the copper layer, a via hole is formed in the filled hole-filling material. At the protruding portion, the filling hole depression will protrude from the surface of the copper layer on the surface of the copper-clad substrate, and the removal of the protruding portion can effectively eliminate the filling hole depression which may exist during the hole-filling process of the guiding hole, thereby flattening the surface of the copper-clad substrate. 'The surface of the hole-filling material is in the same plane as the surface of the copper layer on the surface of the copper-clad substrate, and a copper layer of uniform thickness is formed on the surface of the copper-clad substrate' to facilitate the fabrication of the higher-order via holes and the subsequent circuit board build-up. 9 200930202 [Embodiment] Hereinafter, a circuit board manufacturing method and a circuit board manufactured by the method provided by the present technical solution will be further described in detail with reference to the accompanying drawings and embodiments. Referring to FIG. 2, the circuit board manufacturing method provided by the embodiment of the present technical solution includes the following steps: In the first step, a copper clad substrate 10 having at least one via hole 20 is provided. The copper-clad substrate 10 has at least two copper layers and at least one resin layer between the two copper layers. Therefore, the copper-clad substrate 10 can be a single-layer double-sided copper-clad circuit substrate. It is a multilayer circuit board that has completed internal circuit fabrication and has not been surface-surfaced. Referring to FIG. 2, in the present embodiment, the copper-clad substrate 10 is a multilayer circuit substrate including a first substrate 11 and a second substrate 12 pressed against the first substrate 11. The first substrate 11 includes a first copper layer 111 and a first resin layer 112, and the second substrate 12 includes a second copper layer 121 and a substrate layer 122. The second copper layer 121 has a shape and a conductive line. The substrate layer 122 can be a multilayer circuit substrate or a single-layer resin layer. The first resin layer 112 is pressed against the second copper layer 121, thereby forming a copper clad base material 10 having a multilayer structure. Of course, if the copper-clad substrate 10 does not include the substrate layer 122, the copper-clad substrate 10 can be regarded as a single-layer double-sided copper-clad substrate, and the second copper layer 121 can be formed without a conductive line. The copper clad substrate 10 has one or a plurality of via holes 20. The via hole 20 refers to a via hole or a blind via formed in the copper clad substrate 10, and the inner wall of the via hole or the blind via has been formed with a copper plating layer to realize electrical connection between different copper layers. In the present embodiment, the copper-clad substrate 10 has a via hole 20 as an example, and the method of filling the hole is explained in the method of 200930202. The via hole 20 is a blind via hole penetrating the first copper layer m and the first resin layer ι12, and the inner wall of the via hole 20 is formed with a copper plating layer 23a as a conductive layer for the first copper layer 111 and the second copper layer. The electrical connection between the electrodes 121, and the copper plating layer 23a is formed correspondingly on the surface of the second copper layer 121 in the via hole 20. That is, one end of the via hole 20 is connected to the first copper layer m through the copper plating layer 23a of the inner wall, and the other end of the via hole 20 is connected to the second copper layer 121 through the copper plating layer 23a of the inner wall' while the second copper layer 121 is located The substrate layer 122 is thereby closed by the first copper layer 111 and the substrate layer 122, thereby forming a blind via structure. The copper plating layer 23a can be formed by electroless copper plating or copper plating. Therefore, a copper plating layer 23b is formed on the surface of the first copper layer 111, and the copper plating layer 23b becomes a surface copper layer, thereby causing an increase in the thickness of the surface copper layer. . Of course, if the copper-clad substrate 10 does not include the substrate layer 122, the conductive via 20 can be electrically connected to the via structure of the first copper layer ill and the second copper layer 121. Open state. The ore layer 23b is simultaneously formed on the surface of the first copper layer ill and the second copper layer 121 to form a surface copper layer, thereby causing an increase in the thickness of the surface copper layer. Of course, the via holes 20 may be formed by other methods so that the copper plated layer is not formed on the surface of the first copper layer 111, so that the thickness of the copper layer on the surface of the substrate 10 is not additionally increased. The first resin layer 112 and the substrate layer 122 may be a hard resin layer such as an epoxy resin, a fiberglass cloth, or the like, or a flexible resin layer such as polyimide (PI) or polyethylene terephthalic acid. Polyethylene Terephtalate (PET), Polytetraethylene (Teflon), Polyamide, Polymethylmethacrylate, Polycarbonate or Polyimine - Polyethylene-terephthalate copolymer, etc., polyethylene terephthalate. In addition, an adhesive layer may be further disposed between the first copper layer 111 and the first resin layer 112 and between the second copper layer 121 and the substrate layer 122, so that the first copper layer 111 and the first resin layer 112, The copper layer 121 has a large bonding force with the substrate layer 122. In the second step, the hole-filling material 25 is filled in the guide hole 20. In order to facilitate the fabrication of subsequent higher-order vias and build-up, the vias 20 are filled with a via material 25, as shown in FIG. The hole-filling material 25 may be a conductive paste or an organic resin or the like, and is preferably a conductive paste. The hole-filling material 25 can be filled into the guide holes 20 by screen printing. Specifically, a printing screen having a screen printing pattern corresponding to the position of the guide hole 20 is used, which is disposed on the surface of the copper layer on the surface of the copper-clad substrate 10, that is, the surface of the copper layer 23b, and then the filler is used by the doctor blade. 25 is extruded through the screen printing pattern of the printing screen to be filled into the guide holes 20. After the filling material 25 is filled into the guide holes 20, it is solidified and is present in the guide holes 20. However, due to the influence of solvent volatilization and gravity in the filler material 25 during the curing process, a hole-filling recess 251 may be formed in the via hole 20 near one end of the first copper layer 111 and the copper plating layer 23b, thereby causing a copper-clad base. The surface of the material 10 is not flat. Of course, depending on the choice of the filling material 25, the filling recess 251 may not be very obvious, and the depth of the filling recess 251 is smaller than the sum of the thicknesses of the first copper layer 111 and the copper plating layer 23b, but may be greater than, equal to, or less than the copper plating layer. The thickness of 23b. In the third step, the via hole stopper 30 is disposed on the surface of the copper layer on the surface of the copper-clad substrate 10, so that the via-hole 30 completely covers the via hole 20 filling the hole-filling material 25. In this embodiment, since the via hole 20 is a blind via structure, the copper plating layer 23b shape 12 200930202 is formed on the surface of the first copper layer 111 to form a copper layer on the surface of the copper clad substrate 10, and therefore only needs to be in the via hole 20 A via stopper 30 is provided on the surface of the corresponding copper plating layer 23b. The via shield 30 can be fabricated using a dry film photoresist or a liquid photoresist. In this embodiment, the via mask 30 is formed by dry film photoresist, that is, the dry film photoresist corresponding to the size of the via 20 is directly bonded and attached to the surface of the copper plating layer 23b, so that the dry film photoresist is completely covered. The hole 20, that is, the material of the copper plating layer 23b covering the periphery of the via hole 20 and the hole filling material filled in the via hole 20, and exposing the material of the ore layer 23b outside the periphery of the via hole 20, as shown in FIG. Of course, if the via shield 30 is formed by using a liquid photoresist, the coating can be performed by means of dot coating or screen printing, so that the liquid photoresist completely covers the via hole 20, that is, the copper plating covering the periphery of the via hole 20. The layer 23b material and the hole-filling material filled in the via hole 20 expose the material of the copper plating layer 23b outside the periphery of the via hole 20, and then the liquid photoresist is cured. The via shield 30 disposed at the via 20 can protect the via 20 such that the copper layer material located around the via 20 and the fill material filled in the via 20 are not subjected to subsequent microetching steps. The money is carved away. Of course, if the copper-clad substrate 10 does not include the substrate layer 122, when the via hole 20 is electrically connected to the via hole of the first copper layer 111 and the second copper layer 121, since both ends of the via hole 20 are open, Therefore, the via hole stopper 30 of the via hole 20 may be simultaneously disposed on the copper layer of the copper-clad substrate 10 opposite to the two surfaces, that is, at the same time as the copper plating layer 23b formed on the surface of the first copper layer 111 and the surface of the second copper layer 121. The via spacers 30 of the via holes 20 are disposed such that the copper layer material located around the via holes 20 and the hole-filling material filled in the via holes 20 are not etched away in the subsequent micro-etching step. 13 200930202 In the fourth step, the copper layer of the surface of the copper-clad substrate .10 on the outer surface of the via-hole 30 is microetched to form a projection 32 at the via hole 20. The copper layer on the surface of the copper-clad substrate 10 located outside the via shield 30 is microetched with a copper etching solution to reduce the thickness of the copper layer on the surface of the copper-clad substrate 1 to form a convex coating. The convex portion 32 of the surface of the copper layer on the surface of the copper substrate, the thickness of the thin copper layer on the surface is favorable for making a high-density fine line. The thickness of the micro-etched copper layer should be greater than or equal to the depth of the hole-filling recess 251 so that the hole-filling recess 251 can protrude from the surface of the copper layer on the surface of the copper-clad substrate 1 . In this embodiment, the copper etching layer is used to micro-etch the copper plating layer 23b on the surface of the copper-clad substrate 1 outside the via-hole 30 and a portion of the first copper layer in, thereby leaving a thinner thickness. A copper layer 111a becomes the copper layer of Table 2, so that the hole-filling recesses 251 may all protrude from the surface of the first copper layer 11u. The copper etching solution may be a mixed micro-etching system such as sulfuric acid-hydrogen peroxide, ammonium persulfate-sulfuric acid, sodium persulfate-sulfuric acid, potassium persulfate-sulfuric acid, and vaporized copper-sulfuric acid. The speed at which the copper etching solution etches the copper layer is closely related to the composition, concentration, etching temperature and processing method of the copper etching solution. The copper plating layer 2 or the copper plating layer 23b can be removed just by appropriately controlling the etching speed of the copper-clad substrate 1 and the etching time.卩 is the thickness of the first copper layer lu. For example, when the sulfuric acid-hydrogen peroxide micro-etching solution is sprayed by a spray treatment at a temperature of 38 ° C under a spray pressure of 3 kg/m 2 to a surface of a board having a running speed of 2. im/min, micro The etch rate is about Ι/zm/min. If the sum of the thickness of the first copper layer ιη and the copper plating layer 2 is 1.4~l.6mil (ie 35·56~64×/m), it will take a moment. ^ Knife clock, you can just remove the thickness of 〇 4 ~ 〇 6 shirt (ie copper plated layer 23b and part of the thickness of the first copper layer lu, leaving a thinner thickness of the 200930202 copper layer Ilia becomes the surface copper layer, the basin at this time , Guide hole 2 and = '二护于Γ - engraved secret, and the guide hole block 2 = out of the convex portion of the surface of the first copper layer 11U, including the guide hole 3 〇, part of the copper Layer 2 Material H " Section, part of the copper plating layer 23a L knife first copper layer 111 material and part of the filling material 25, as shown in Figure 5 ❹ 23b such as ^ true hole depression 251 depth is small, such as less than the copper layer 23 ^ ^ micro The copper layer is located in the area outside the via rib 3, and the first copper layer m is not replaced by the surface of the first copper layer 111, the convex (4) ^ portion of the material, the copper layer of the material, Partial copper layer - material and sound Except for the surface of the copper two-sided two-hole filling material 25 protruding from the surface of the copper-clad substrate 1 at the guiding hole 20 and the surface of the copper-clad substrate® are flat. The surface of the five layers is in the same plane-thickness In the case of the material 10, if the copper plating layer 23b is micro-etched, the first copper is thin: the copper layer on the surface of the copper-clad substrate 10 is wide, so the protruding portion protrudes from the 9 Γ layer In the present embodiment, the copper-plated substrate A is removed by a brushing method. The convex portion 32 of the copper layer on the surface of the copper-clad substrate 1 is flattened on the surface of the copper-clad substrate 10. Bitter-guide hole 20 The first two advances: the first-grinding process to remove the copper substrate H) the surface is flat, 3 6 32' so that the cover 10 is as shown in Fig. 6. In this embodiment, the first brush 15 200930202 70Π 1 The grinding wheel is used for the grinding. Specifically, the surface of the copper-clad substrate 10 is polished by the Taoman grinding wheel with the grinding precision of I: the hardness of the ceramic-free grinding wheel and the convexity When the protruding portion 32 of the surface of the first copper layer is collided, the protruding portion 32 can be cut off so that the surface of the hole-filling material 25 and the surface of the first copper layer Ula are located at the same Surface, so that the copper surface roughness of the substrate 10, the hole filling material is the same surface of the rough surface of the first wheel of the copper layer UU shown in Figure 6.
其次，為了進一步確保較好之表面平整度與粗糙度， 可選擇性之進行第二磨刷工序，該第二磨刷卫序之磨刷精 度大於第一磨刷工序之磨刷精度。本實施例中，第二磨刷 工序採用採用不織布磨刷輪進行磨刷，當然亦可採用尼龍 磨刷輪進行磨刷。具體地’採用磨刷精度為11〇〇〜13〇〇目 之不織布磨刷輪對覆銅基材10表面進行磨刷，不織布磨刷 輪與覆銅基材10之第一銅層llla表面以及去除凸出部32 後填充於導孔20之填充材料25之表面進行磨刷，以細小 之凸起及毛刺，從而進一步提高覆銅基材1〇表面之平整度 與粗糙度。 之後，該完成填孔之覆銅基材1〇，可進行導電線路之 製作，亦可進一步壓合其他覆銅基材進行多層電路板之製 作。由於使用本技術方案之填孔方法，微蝕刻工序之後， 會形成位於填充填孔材料之導孔處之凸出部32，填孔凹陷 251同時會全部四出於覆銅基材1〇表面之銅層，去除凸出 部32 ’不僅可有效消除了導孔20於填孔過程中可能存在之 填孔凹陷251 ’破保覆銅基板1〇表面之平整性，提升了多 16 200930202 層兩密度電路板製作之良率；而且由於微姓刻工序還可同 時降低了覆銅基材10之表面銅層之厚度，以於覆銅基材1〇 ，表面形成厚度較薄且均勻之銅層’有利於高密度細線路之 製作’以及後續高階導孔以及後續電路板增層製作。 可理解，採用上述方法製作之電路板，其包括至少— 導孔20，導孔20中填充有填孔材料25，填孔材料25之表 面及與導孔20導電層相連之銅層之表面處於同一平面。本 實知例中，如圖6所示，鑛銅層23a為導孔20之導電層， ❹其與第一銅層111a相連，因此，填孔材料25之表面與第 一銅層Ilia之表面處於同一平面。此外，由於採用磨刷工 序去除凸出部32，填孔材料25之表面及第一銅層llla之 表面可具有相同之表面粗糖度。 綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案 ❾技藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係現有之填孔技術填孔後於導孔處產生之填孔凹 陷之示意圖。 圖2係本技術方案實施方式提供之覆銅基材之示意圖。 —圖3係本技術方案實施方式提供之覆銅基材填孔後之 示意圖。 圖4係本技術方案實施方式提供之填孔後之覆銅基材 17 200930202 表面銅層設置導孔擋片之示意圖。 圖5係本技術方案實施方式提供之設置導孔擋片之填 孔後之覆銅基材表面銅層微蝕刻之示意圖。 圖6係本技術方案實施方式提供之覆銅基材表面磨刷 後之示意圖。 【主要元件符號說明】 覆銅基材 10 ❹ 第一基材 11 第二基材 12 第一銅層 111 > 111a 第一樹脂層 112 第二銅層 121 基板層 122 導孔 20 ❹ 鐘銅層 23a > 23b 導孔擔片 30 凸出部 32 填孔材料 25 填孔凹陷 110 ， 251 18Secondly, in order to further ensure a good surface flatness and roughness, a second brushing step can be selectively performed, and the second brushing step has a higher grinding accuracy than the first brushing step. In this embodiment, the second brushing process is performed by using a non-woven brush wheel, and of course, a nylon brush wheel can be used for the brushing. Specifically, the surface of the copper-clad substrate 10 is polished by a non-woven abrasive wheel having a rubbing precision of 11 〇〇 to 13 〇〇, and the surface of the first copper layer 111a of the non-woven brush wheel and the copper-clad substrate 10 is After the protrusions 32 are removed, the surface of the filling material 25 filled in the via holes 20 is polished to make fine protrusions and burrs, thereby further improving the flatness and roughness of the surface of the copper-clad substrate 1 . Thereafter, the copper-clad substrate 1 is filled, and the conductive wiring can be fabricated, and the other copper-clad substrate can be further pressed to perform the multilayer circuit board. Since the hole filling method of the present technical solution is used, after the micro-etching process, the protruding portion 32 at the guiding hole of the filling hole-filling material is formed, and the filling hole recess 251 is all at the same time as the surface of the copper-clad substrate 1 The copper layer and the removal of the protruding portion 32' can not only effectively eliminate the flatness of the surface of the hole-filled recess 251, which may exist in the hole-filling process of the via hole 20, and improve the two layers of the layer of 200930202 The yield of the circuit board is produced; and the thickness of the copper layer on the surface of the copper-clad substrate 10 can be simultaneously reduced by the micro-inscription process, so that the copper-clad substrate is formed on the surface, and a thin and uniform copper layer is formed on the surface. Conducive to the production of high-density fine lines' and subsequent high-order vias and subsequent circuit board build-up. It can be understood that the circuit board manufactured by the above method comprises at least a guide hole 20 filled with a hole-filling material 25, and the surface of the hole-filling material 25 and the surface of the copper layer connected to the conductive layer of the guide hole 20 are at same plane. In the present embodiment, as shown in FIG. 6, the mineralized copper layer 23a is a conductive layer of the via hole 20, and is connected to the first copper layer 111a. Therefore, the surface of the hole-filling material 25 and the surface of the first copper layer Ilia In the same plane. Further, since the projections 32 are removed by the rubbing process, the surface of the hole-filling material 25 and the surface of the first copper layer 111a may have the same surface roughness. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art and in the spirit of the present invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a hole-filling recess formed at a guide hole after filling a hole by a conventional hole filling technique. 2 is a schematic view of a copper-clad substrate provided by an embodiment of the present technical solution. - Figure 3 is a schematic view of the copper-clad substrate provided by the embodiment of the present technical solution after filling holes. 4 is a schematic diagram of a copper-clad substrate after filling holes provided by an embodiment of the present invention. FIG. 5 is a schematic view showing the copper layer micro-etching on the surface of the copper-clad substrate after the hole-filling of the via-hole is provided by the embodiment of the present invention. FIG. 6 is a schematic view showing the surface of the copper-clad substrate provided by the embodiment of the present technical solution after being brushed. [Description of main component symbols] Copper-clad substrate 10 ❹ First substrate 11 Second substrate 12 First copper layer 111 > 111a First resin layer 112 Second copper layer 121 Substrate layer 122 Guide hole 20 钟 Clock copper layer 23a > 23b guide hole sheet 30 projection 32 hole filling material 25 hole filling recess 110, 251 18