[go: up one dir, main page]

TW200929409A - A semiconductor device testing system and testing method thereof - Google Patents

A semiconductor device testing system and testing method thereof Download PDF

Info

Publication number
TW200929409A
TW200929409A TW96149075A TW96149075A TW200929409A TW 200929409 A TW200929409 A TW 200929409A TW 96149075 A TW96149075 A TW 96149075A TW 96149075 A TW96149075 A TW 96149075A TW 200929409 A TW200929409 A TW 200929409A
Authority
TW
Taiwan
Prior art keywords
boundary
unit
test
semiconductor component
semiconductor
Prior art date
Application number
TW96149075A
Other languages
Chinese (zh)
Other versions
TWI372432B (en
Inventor
Ming-Tsong Lee
Original Assignee
King Yuan Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by King Yuan Electronics Co Ltd filed Critical King Yuan Electronics Co Ltd
Priority to TW096149075A priority Critical patent/TWI372432B/en
Publication of TW200929409A publication Critical patent/TW200929409A/en
Application granted granted Critical
Publication of TWI372432B publication Critical patent/TWI372432B/en

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A semiconductor device testing method includes at least a semiconductor device that having a plurality of units, and each units with its status respectively. Then, the semiconductor device is provided for testing to define the boundary unit of the semiconductor device according to the testing result. The status of the boundary unit is compared with the pre-setting value to determine the message that is sent to remind the operator that the map could be shifted.

Description

200929409 九、發明說明: 【發明所屬之技術領域】 本創作係有關於一種半導體元件的測試方法與系統,特別是有關於一種在 晶圓針測(chipprobe)過程中發生地圖偏移情形的判斷方法與系統。 【先前技術】200929409 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method and system for testing a semiconductor component, and more particularly to a method for judging the occurrence of a map offset in a wafer probe process With the system. [Prior Art]

積體電路(1C,integrated circuit)的生產流程係多層級的分工架構,包括了 積體電路設計(IC design)、晶圓製造(wafer manufacturing)、晶圓針測(circuk probing)、封裝(assembling)以及最終測試(finai testing)。前述的生產分工中,晶 圓針測與最終測試兩道檢測程序,都是碟保產品品質的重要關卡。 一片晶圓上含有許多單元,這些單元通常被稱為晶粒(die)但是並非所有的 晶粒皆具有良好品質,因此晶圓針測的方法,係以很細的探針卡❻阳心cM) 或微小探針(fme-P〇int needle)測試晶圓上的每一個晶粒,接著在不良的晶粒上 標示記號或留存測試圖(mapping file),用以分類良品與不良品。縣進行晶圓 針測,直接在晶圓製造完成後進行_與雜,則不良品騎裝成本是非必要 的浪費》因此晶圓針測這個步驟可以分類晶圓上的良品與不良品以降低封裝 與後續測試的成本。 — 晶圓針測中 诔以機槭視覺設備偵測到起測點(firstdie),再依循預先設定 的測試範圍對晶粒逐-進行齡在上述的方法中,若起測點未被正確找到, 則測試範圍會偏移,造朗試結果的錯誤,稱之為地_移(娜趣)。 ^前可以使用人工判斷來解決此問題,以人工判斷有否地圖偏移現象,將 每-個的圓以人工目視的方法進行檢查,此方法可以全面性的進行檢查,需要 有經驗的技術人員方能有效操作,並且無法提出證據說明。 知的方法是預先設定記號晶粒—η8也)’此記號晶粒具有已 知的朗粒㈣’㈣號晶粒之職結果與已知_試結果相異時删斷起測 5 200929409 點錯誤’發生地圖偏移的問題。但此方法必須每項測試前預先設定記號晶板, 步驟增加的結果也會浪費時間,並且難以全面實施。 有鑒於以上缺失,本發明所提供之半導體元件的測試方法與系統,乃針 先前技術加以改良者。 【發明内容】 基於解決上耻前技術之缺失,本發明所提供之半導體元件的測試方法益 需預先设S己號晶粒’可增加測試效率。 … 本發明之-目的在於提供—半導體元件_試方法與祕㈣判 體7C件的測試過程中是否有地圖偏移的現象。 本發明之目的在於提供—半導趙元件的職方法與祕,可 力需求,減少時間並增加效率。 降低人 本發明之再-目的在於提供—半導體树的測試方法與系統,在地圖偏移 的情況發生時,發出訊號以提示操作人員。 少-目首缺供—種半導體元件的測試方法,係提供至 Ο 離;接著it行半導雜、!上具有複數辦元,每解元財各自單元狀 i界Ϊ 結衫義轉體元件的邊界單元, 設定值進行比較,決定是否發出訊息,用以提示操作人員。 尹選擇极的早心再彻運算裝置敏衫發出^ 【實施方式j 由 於本發明係—種半導趙元件_試方法與系統, 其尹所利用到的一些基 200929409 •本原理,屬_倾具有通常知識之人顿驗易理解者,林再贅述。而以 .,係表達與本發明特徵相關之示意,並未亦不需要«實 際尺寸兀整繪製,闔先敘明0 首先’請參考帛1圖所示,係根據本發明之一較佳實施例之示意圖。如第 二先提供—半導體兀件此半導體元件在本實施例中為晶圓100,晶 所包含的複數個單柳為晶粒⑽。接著,以測試裝置對晶圓ι〇〇進 ^時,當起測點偏移而使測量 1 示,職圖112中的數字代表晶嶋,其中晶_ ❹似。、日日,晶粒狀態3代表晶粒短路(sh〇rt),晶粒狀態4代表晶粒開 般情況下,會先進行晶粒1〇2之缺陷測試,#晶粒脱之測試 ==時,可統稱為錯誤;或者當晶粒1〇2之測試狀態與預期狀態 不同時,亦可稱為錯誤。 接著’如第2圖所示,係本發明用以判斷邊界晶粒之示意务在本實施例 小==晶粒X最多具有8個相鄰晶粒’當測試結果中的某一晶粒ι〇2具有 ^於8個相鄰晶粒時,則定義裝置會判斷此晶粒為邊界晶粒γ。 圖。請參考第3 ^ ’係斷地圖偏移之另—難實施例示意 〇的^^日減所不,當域*邊界晶粒¥後,利用選擇裝置選擇部分(或全部) 的邊界B0粒賴的晶粒W,_運算裝置計算標的晶粒γ 如第t ’4參考第4圖係本發明判斷地圖偏移之再—較佳實施例示意圖。 位’當定義出邊界晶粒¥後’利用分類裝置將邊界晶粒y依所在 以2 ^、A3、A4等喃邊界單元群組,運算裝置計算一個 ^如元群組中鳴瞻量,跑邊界單元群組㈣些晶粒狀 i算m路或無代表獨電性的晶錄態)數量_預先設定值時, ⑴運算裝置會發出-訊號’表示可能有地圖偏移的情形。 7 200929409 根據本發明-較佳實施例,當定義料界晶粒γ後,辟 # γϋ轉侧職嶋冑算標示。如 第^1除,第5a圖係將邊界晶粒γ分為左右兩個相對群組第兄圖係 晶粒γ分為上下兩個相對群組、第5e _將邊界晶粒左 下兩個相對群組、第5d _將邊界晶粒Y分為左上與右下兩個相對群ϋ -:界晶粒可以屬於多個不同的群組。接著使用一咖 相對群組進行錯誤率的比較,當錯誤率的差異到達一預先設定值時,發出一訊 ❹The integrated circuit (1C) integrated circuit is a multi-level division of labor architecture, including IC design, wafer manufacturing, circuk probing, and assembly. ) and final testing (finai testing). In the above-mentioned production division, the two rounds of testing for the round needle test and the final test are important points for the quality of the disc warranty. A wafer contains many cells. These cells are often called dies, but not all dies have good quality. Therefore, the method of wafer pinning is based on a very thin probe card. Or a small probe (fme-P〇int needle) tests each die on the wafer, and then marks or retains a mapping file on the defective die to classify good and defective products. In the county, wafer needle testing is performed directly after the wafer fabrication is completed, and the cost of defective products is unnecessary waste. Therefore, the wafer needle measurement step can classify the good and defective products on the wafer to reduce the package. Cost with subsequent testing. — In the wafer needle test, the machine is used to detect the first die, and then according to the preset test range, the die is aged in the above method. If the starting point is not found correctly. , the test range will be offset, and the error of the test result will be called the ground_shift (Na fun). Before you can use manual judgment to solve this problem, manually judge whether there is a map offset phenomenon, and check each circle by manual visual inspection. This method can be comprehensively checked and requires experienced technicians. It can operate effectively and cannot provide evidence. The known method is to pre-set the mark grain - η8 also) 'This mark grain has a known granule (4) '(4) grain position result is different from the known _ test result when the test starts 5 200929409 point error 'The problem of map offset occurred. However, this method must be pre-set the crystal plate before each test, and the added result of the step will also waste time and is difficult to fully implement. In view of the above, the test method and system for the semiconductor device provided by the present invention have been improved by the prior art. SUMMARY OF THE INVENTION Based on the solution to the shortcomings of the prior art, the test method of the semiconductor device provided by the present invention needs to pre-set the S-grain granules to increase the test efficiency. The object of the present invention is to provide a phenomenon in which a semiconductor device _ test method and a secret (4) judged that there is a map offset during the test of the 7C device. SUMMARY OF THE INVENTION The object of the present invention is to provide a method and a secret for the semi-guided component, reducing the time and increasing efficiency. Reducing the Human Body A further object of the present invention is to provide a test method and system for a semiconductor tree that emits a signal to alert the operator when a map offset occurs. Less-head-of-the-head supply--a test method for semiconductor components is provided to the Ο-off; then it is semi-conducting, and has a complex number of elements, each of which has its own cell-like i-boundary boundary. The unit, the set value is compared, and a message is sent to prompt the operator. Yin's choice of the early heart and then the operation of the device to send the shirt ^ [Embodiment j because the invention is a semi-conductive Zhao element _ test method and system, some of the base used by Yin 200929409 • The principle, belongs to the _ Those who have the usual knowledge are easy to understand, and Lin repeats. However, the expressions relating to the features of the present invention are not required to be drawn by the actual size. First, the first description is shown in FIG. 1 , which is a preferred embodiment of the present invention. A schematic diagram of an example. As the second first provides, the semiconductor device is a wafer 100 in this embodiment, and the plurality of single crystals contained in the crystal are grains (10). Next, when the test device is used to align the wafer, the measurement is shown when the measurement point is offset, and the number in the job map 112 represents the wafer, wherein the crystal ❹ is similar. On the day of the day, the grain state 3 represents the grain short circuit (sh〇rt), and the grain state 4 represents the grain opening. In the case of the grain opening, the defect test of the grain 1〇2 is performed first, and the # die removal test == When it is collectively referred to as an error; or when the test state of the die 1〇2 is different from the expected state, it may also be referred to as an error. Then, as shown in FIG. 2, the schematic of the present invention for judging the boundary grain is small in this embodiment == the grain X has a maximum of 8 adjacent grains'. When 〇2 has 8 adjacent grains, the device determines that the grain is the boundary grain γ. Figure. Please refer to the 3^'s another section of the map offset. The hard-to-implement example shows the ^^ day minus. When the domain *boundary grain is ¥, use the selection device to select the partial (or all) boundary B0. The grain W, the _ computing device calculates the target γ, as shown in the t'4 reference to Fig. 4 is a schematic diagram of the preferred embodiment of the present invention for determining the map offset. Bit 'When defining the boundary grain ¥¥', using the classification device to divide the boundary grain y according to the group of 2 ^, A3, A4 and other boundary cells, the arithmetic device calculates a sounding quantity in the group Boundary unit group (4) Some grain-like i-calculated m-path or non-representative crystal-recorded state) _ Pre-set value, (1) The arithmetic device will issue a -signal indicating that there may be a map offset. 7 200929409 According to the present invention - the preferred embodiment, when the grain boundary γ of the material boundary is defined, the #γϋ turns the side job calculation index. For example, in addition to ^1, the 5a figure divides the boundary grain γ into two left and right relative groups. The γ of the figure is divided into two upper and lower relative groups, and the fifth _ _ the boundary grain is lower left and opposite The group, 5d _ divides the boundary grain Y into two upper and lower right groups - the boundary grain can belong to a plurality of different groups. Then use a coffee relative group to compare the error rate. When the difference of the error rate reaches a preset value, a message is sent.

號,此訊號傳❹警示裝置,警示裝置會形化資訊顯示,肋提醒操作人 員可能有地圖偏移的情形。 綜上所述’本發明提供了一種半導體元件的測試方法與系統,此方法可以 用來判斷半賴讀的顺過財是偏移的狀,可崎所有進行測 試的半導趙元件進行判斷,並且無須增加人力負擔。當系統判斷出可能有地圖 偏移的現象時,可以進-步發出峨,提示操作人員檢查起測點。 顯然地’依照上面實施例中的财,本發明可能有許多的修正與差異。因 此需要在其附加的權利要求項之範圍内加以理解,除了上餅細的描述外,本 發明還可以廣泛地在其他的實施例中施行。上述僅為本發明之較佳實施例而 已’並非用以限定本發明之申請專利範圍;凡其它未脫離本發明所揭示之精神 下所完成的等效改變或修飾,均應包含在下述申請專利範圍内。 【圖式簡單說明】 第1圖係本發明之起測偏移示意圖 第2圖係本發明一較佳實施例之邊界單元定義示意圖 第3圖係本發明一較佳實施例之判斷地圖偏移示意圖 第4圖係本發明一較佳實施例之判斷地圖偏移示意圖 第5a-5d圖係本發明一較佳實施例之判斷地圖偏移示意囷 8 200929409 【主要元件符號說明】 1 晶粒狀態(可用) 3 晶粒狀態(短路) 4 晶粒狀態(開路) 100 晶圓 102 晶粒 110 測量範圍 112 測試圖 Y 邊界晶粒 Y1 標的晶粒 A1-A4 邊界單元群組No., this signal transmits the warning device, the warning device will shape the information display, and the rib reminds the operator that there may be a map offset. In summary, the present invention provides a test method and system for a semiconductor component, which can be used to determine the offset of a half-reading readout, and can be judged by all the semi-conductive components that are tested. And there is no need to increase the manpower burden. When the system determines that there may be a phenomenon of map offset, you can step forward to prompt the operator to check the starting point. Obviously, the present invention may have many modifications and differences in accordance with the above embodiments. It is therefore to be understood that within the scope of the appended claims, the invention may be The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following claims. Within the scope. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a start-up offset of the present invention. FIG. 2 is a schematic diagram of a boundary element definition according to a preferred embodiment of the present invention. FIG. 3 is a diagram for determining a map offset according to a preferred embodiment of the present invention. FIG. 4 is a schematic diagram of determining a map offset according to a preferred embodiment of the present invention. FIG. 5a-5d is a schematic diagram of a map offset of a preferred embodiment of the present invention. 20098 200929409 [Description of main component symbols] 1 Grain state (Available) 3 Grain state (short circuit) 4 Grain state (open circuit) 100 Wafer 102 Grain 110 Measurement range 112 Test pattern Y boundary grain Y1 mark grain A1-A4 boundary cell group

Claims (1)

200929409 、申請專利範圍 l -種半導體元件的測試方法,酬試方法包含· 提供至少—辨綠元件,辭導體树Μ«個單元· 測試該半導體元件上的該些單元; 皁兀, ^該半雜元狀料單元,龜據解導批狀顺絲定義出邊界 Ο ❹ 選擇複數個邊界單元為標的單元;以及 =比較順,姆標幅輸 2.=請專利範圍第丨雜之測試方法,其中該半導體元件為晶圓。 .如申請專利範圍第i項所述之測試方法,其中該些單元為晶粒。 4.=申物_第1項所㈣m方法,其巾該標的單元包含所有邊界單 =申清專利範@第1項所述之測試方法,其巾該標的單元包含部分邊界單 6·—種半導體元件的測試方法,該測試方法包含: 提供至;—辨賴讀,該半導航件包含複油私触單元具有 自的單元狀態; 測試該半導體元件上的該些單元; ,義該半導體元件之邊界單元,係根據辭導體元件之麟結果定義出邊界 單元; 執行一分類程序,係將該些邊界單元分類為複數個邊界單元群組;以及 執行一比較判斷,當至少一邊界單元群組的至少一單元狀態到達一預先設定 值時,發出一訊號。 7 ji .如申請專利範圍第ό項所述之測試方法,係依據邊界單元所在位置將該些邊 200929409 界單元分類為複數個邊界單元群組。 8· -種半導體元件酬試方法,酬試方法包含: 提供至y-個半導體元件,該半導體元件包含複數個單元; 測試該半導體元件上的該些單元; 疋義該半導體疋件之邊界單元,係根據該半導體元件之測試結果定義出至少 一側無相鄰單元的單元為邊界單元; 標示該邊界單元,係以至少一方向標記來標示該邊界單元; ❹ Ο 執行刀類程序’餘财向將該麵界單元分麟複脑邊元群組; 以及 ,行-比較躺’當具有姆方向之邊界單元的錯誤比繼異到達一預先設 疋值時,發出一訊號。 2申π專利範圍第8項所述之測試方法,其中單一邊界單元可具有複數個方 向,可包含於複數個邊界單元群組中。 達^請專概圍第8項所述之職方法,其中該方向標示步驟係由電蹈運算 圍第自8項所述之測試方法,另提供一警示裝置用以接收該訊 唬’且發出警示訊息。 12. -種半導體元件的測試系統,該測試系統包含: ㈣m半導體元件,其中辭導體元件包含複數個單元; 裝置’係根據該測試裝置之測試結果定義出該半導體元件之至少一邊 一運算裝置’當該些標的單元的錯 13. 如申請專利範圍第12項所示 f達到-預先設定值時,發出一訊號。 收該訊號,且發出警示訊t系統,其中另包含一警示裝置,用以接 14. 一種半導體元件的測試系統,包含: 200929409 一測試裝置,用以測試一半導艚开杜i 些單元具有各自的單元狀態;’該半導體元件包含複數個單元’該 二置之測試結果定義出該半導體元件之至少一 一=,:將T界單元分類為複數個邊界單元群組;以及 群組之至少―單被態的數制達一預先設 疋值時,發出一訊號。 15. 如申請專_,4衛示之職纽,糾另 ❹200929409, the patent application scope l - a test method for a semiconductor component, the compensation method includes: providing at least - a green component, a conductor tree Μ «units · testing the cells on the semiconductor component; saponin, ^ the half In the impurity element unit, the turtle defines the boundary Ο according to the demodulation batch shape Ο ❹ selects a plurality of boundary elements as the target unit; and = is relatively smooth, and the metric size is 2. 2. Please ask the test method of the patent range. Wherein the semiconductor component is a wafer. The test method of claim i, wherein the units are grains. 4.=Application _ Item 1 (4) m method, the unit of the label contains all the boundary sheets = the test method described in the patent paragraph @1, and the unit of the label contains a part of the boundary sheet. a test method for a semiconductor device, the test method comprising: providing a read-to-read, the semi-navigation member includes a unit state in which the re-oiling private touch unit has a self-test; testing the plurality of units on the semiconductor element; a boundary unit, which defines a boundary unit according to a result of a lining of the conductor element; performing a classification procedure, classifying the boundary units into a plurality of boundary element groups; and performing a comparison judgment, when at least one boundary unit group A signal is sent when at least one of the unit states reaches a predetermined value. 7 ji. The test method described in the scope of claim patent section classifies the edge 200929409 boundary elements into a plurality of boundary element groups according to the location of the boundary unit. 8. A semiconductor component compensation method, the method comprising: providing to y-semiconductor components, the semiconductor component comprising a plurality of cells; testing the cells on the semiconductor component; constituting a boundary cell of the semiconductor component According to the test result of the semiconductor component, a cell having at least one side without adjacent cells is defined as a boundary cell; the boundary cell is marked with at least one direction mark to mark the boundary cell; ❹ Ο executing a knife program The signal is sent to the boundary unit; and the line-comparison is issued when the error of the boundary unit having the um direction reaches a preset value. The test method of claim 8, wherein a single boundary unit may have a plurality of directions and may be included in a plurality of boundary element groups. Please refer to the method described in item 8 in which the direction marking step is performed by the test method described in item 8 and a warning device is provided to receive the message. Warning message. 12. A test system for a semiconductor component, the test system comprising: (4) an m-semiconductor component, wherein the re-conductor component comprises a plurality of cells; and the device 'defines at least one side of the semiconductor component based on the test result of the test device' When the target unit is in error 13. When the f reaches the pre-set value as shown in item 12 of the patent application, a signal is sent. Receiving the signal and issuing a warning t system, which further includes a warning device for connecting 14. A test system for a semiconductor component, comprising: 200929409 A test device for testing half of the lead-opening The unit state; 'the semiconductor component includes a plurality of cells'. The test results of the two sets define at least one of the semiconductor components =, the T boundary cells are classified into a plurality of boundary cell groups; and at least one of the groups A signal is sent when the number of states of the single state reaches a preset value. 15. If you apply for a special _, 4 Guardian's job, correct the other ❹ 收該訊號,且發出警示訊息。 詈丁聚置用乂接 16. 種半導體元件的測試系統,該測試系統包含: -=裝置,⑽職半導體元件,其巾辭導體元 ^義裝置,係根據測試結果,“具有至少—側無相鄰單元的單二邊界 -標示裝置’用以於該邊界單元標示至少-無相鄰單福方向· 以及 -分類裝置,霞方向職料界單元錢騎數料 細㈣―曝㈣㈣先· 其中另包含一警示裝置,用以接 其中該警示訊息係以圖像顯示。 17. 如申請專利範圍第16項所示之測試系統 收該訊號,且發出警示訊息。 18. 如申請專利範圍第16項所示之測試系統 12Receive the signal and send a warning message. The tester system of the semiconductor component is connected to the semiconductor device. The test system comprises: -= device, (10) semiconductor component, and the device of the conductor element, according to the test result, "having at least - side without The single-two boundary-marking device of the adjacent unit is used to mark at least the adjacent single-blessing direction and the sorting device in the boundary unit, and the number of the riding units in the Xia direction-feeding unit is fine (four)-exposure (four) (four) first · In addition, a warning device is provided for receiving the warning message as an image. 17. The test system shown in claim 16 of the patent application receives the signal and issues a warning message. Test system 12 shown
TW096149075A 2007-12-20 2007-12-20 A semiconductor device testing system and tseting method thereof TWI372432B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW096149075A TWI372432B (en) 2007-12-20 2007-12-20 A semiconductor device testing system and tseting method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096149075A TWI372432B (en) 2007-12-20 2007-12-20 A semiconductor device testing system and tseting method thereof

Publications (2)

Publication Number Publication Date
TW200929409A true TW200929409A (en) 2009-07-01
TWI372432B TWI372432B (en) 2012-09-11

Family

ID=44864473

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096149075A TWI372432B (en) 2007-12-20 2007-12-20 A semiconductor device testing system and tseting method thereof

Country Status (1)

Country Link
TW (1) TWI372432B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112683210A (en) * 2020-12-28 2021-04-20 上海利扬创芯片测试有限公司 MAP graph offset detection method for wafer test

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102019127214B4 (en) 2019-05-15 2023-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. border cell
US11062074B2 (en) 2019-05-15 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Boundary cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112683210A (en) * 2020-12-28 2021-04-20 上海利扬创芯片测试有限公司 MAP graph offset detection method for wafer test

Also Published As

Publication number Publication date
TWI372432B (en) 2012-09-11

Similar Documents

Publication Publication Date Title
CN100390554C (en) Chip test solution reduced at wafer level
JP6997428B2 (en) Systems and methods for electronic die-inking after automatic visual defect inspection
TW442880B (en) Method for automatically classifying the wafer with failure mode
TWI591503B (en) System and method to diagnose integrated circuit
US9435847B2 (en) Method for testing special pattern and probe card defect in wafer testing
TW201528189A (en) Method of using test data for performing quality control
TW200929409A (en) A semiconductor device testing system and testing method thereof
JP2004047542A (en) Chip quality determining method, chip quality determining program, marking mechanism using the program, and fault generation analyzing method of wafer
CN101493494B (en) Wafer testing method and system
US6872582B2 (en) Selective trim and wafer testing of integrated circuits
US6939727B1 (en) Method for performing statistical post processing in semiconductor manufacturing using ID cells
CN110931382B (en) A method for detecting optoelectronic properties of LED die
CN111044878A (en) Integrated circuit testing and monitoring method based on ATE system
CN202361941U (en) A fuel cell bipolar plate flatness detection device
TW201009891A (en) The method for forecasting wafer overlay error and critical dimension
CN116046789A (en) Method and system for detecting quality of square wafer crystal particles
US7271609B2 (en) Method of automatically creating a semiconductor processing prober device file
JP3550525B2 (en) Automatic Classification Method of Test Wafer with Failure Mode
CN102789998A (en) Detection method and detection device
US20070280541A1 (en) Pattern shape evaluation apparatus, pattern shape evaluation method, semiconductor device manufacturing method, and program
JPH08147369A (en) Method for discriminating nondefective semiconductor element
US6975945B2 (en) System and method for indication of fuse defects based upon analysis of fuse test data
JP2002184819A (en) Wafer-testing device and method
CN114548070B (en) A method for adding a map to a SITE MAP
CN114545205A (en) A Method to Prevent MAP Offset Error