200929409 九、發明說明: 【發明所屬之技術領域】 本創作係有關於一種半導體元件的測試方法與系統,特別是有關於一種在 晶圓針測(chipprobe)過程中發生地圖偏移情形的判斷方法與系統。 【先前技術】200929409 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method and system for testing a semiconductor component, and more particularly to a method for judging the occurrence of a map offset in a wafer probe process With the system. [Prior Art]
積體電路(1C,integrated circuit)的生產流程係多層級的分工架構,包括了 積體電路設計(IC design)、晶圓製造(wafer manufacturing)、晶圓針測(circuk probing)、封裝(assembling)以及最終測試(finai testing)。前述的生產分工中,晶 圓針測與最終測試兩道檢測程序,都是碟保產品品質的重要關卡。 一片晶圓上含有許多單元,這些單元通常被稱為晶粒(die)但是並非所有的 晶粒皆具有良好品質,因此晶圓針測的方法,係以很細的探針卡❻阳心cM) 或微小探針(fme-P〇int needle)測試晶圓上的每一個晶粒,接著在不良的晶粒上 標示記號或留存測試圖(mapping file),用以分類良品與不良品。縣進行晶圓 針測,直接在晶圓製造完成後進行_與雜,則不良品騎裝成本是非必要 的浪費》因此晶圓針測這個步驟可以分類晶圓上的良品與不良品以降低封裝 與後續測試的成本。 — 晶圓針測中 诔以機槭視覺設備偵測到起測點(firstdie),再依循預先設定 的測試範圍對晶粒逐-進行齡在上述的方法中,若起測點未被正確找到, 則測試範圍會偏移,造朗試結果的錯誤,稱之為地_移(娜趣)。 ^前可以使用人工判斷來解決此問題,以人工判斷有否地圖偏移現象,將 每-個的圓以人工目視的方法進行檢查,此方法可以全面性的進行檢查,需要 有經驗的技術人員方能有效操作,並且無法提出證據說明。 知的方法是預先設定記號晶粒—η8也)’此記號晶粒具有已 知的朗粒㈣’㈣號晶粒之職結果與已知_試結果相異時删斷起測 5 200929409 點錯誤’發生地圖偏移的問題。但此方法必須每項測試前預先設定記號晶板, 步驟增加的結果也會浪費時間,並且難以全面實施。 有鑒於以上缺失,本發明所提供之半導體元件的測試方法與系統,乃針 先前技術加以改良者。 【發明内容】 基於解決上耻前技術之缺失,本發明所提供之半導體元件的測試方法益 需預先设S己號晶粒’可增加測試效率。 … 本發明之-目的在於提供—半導體元件_試方法與祕㈣判 體7C件的測試過程中是否有地圖偏移的現象。 本發明之目的在於提供—半導趙元件的職方法與祕,可 力需求,減少時間並增加效率。 降低人 本發明之再-目的在於提供—半導體树的測試方法與系統,在地圖偏移 的情況發生時,發出訊號以提示操作人員。 少-目首缺供—種半導體元件的測試方法,係提供至 Ο 離;接著it行半導雜、!上具有複數辦元,每解元財各自單元狀 i界Ϊ 結衫義轉體元件的邊界單元, 設定值進行比較,決定是否發出訊息,用以提示操作人員。 尹選擇极的早心再彻運算裝置敏衫發出^ 【實施方式j 由 於本發明係—種半導趙元件_試方法與系統, 其尹所利用到的一些基 200929409 •本原理,屬_倾具有通常知識之人顿驗易理解者,林再贅述。而以 .,係表達與本發明特徵相關之示意,並未亦不需要«實 際尺寸兀整繪製,闔先敘明0 首先’請參考帛1圖所示,係根據本發明之一較佳實施例之示意圖。如第 二先提供—半導體兀件此半導體元件在本實施例中為晶圓100,晶 所包含的複數個單柳為晶粒⑽。接著,以測試裝置對晶圓ι〇〇進 ^時,當起測點偏移而使測量 1 示,職圖112中的數字代表晶嶋,其中晶_ ❹似。、日日,晶粒狀態3代表晶粒短路(sh〇rt),晶粒狀態4代表晶粒開 般情況下,會先進行晶粒1〇2之缺陷測試,#晶粒脱之測試 ==時,可統稱為錯誤;或者當晶粒1〇2之測試狀態與預期狀態 不同時,亦可稱為錯誤。 接著’如第2圖所示,係本發明用以判斷邊界晶粒之示意务在本實施例 小==晶粒X最多具有8個相鄰晶粒’當測試結果中的某一晶粒ι〇2具有 ^於8個相鄰晶粒時,則定義裝置會判斷此晶粒為邊界晶粒γ。 圖。請參考第3 ^ ’係斷地圖偏移之另—難實施例示意 〇的^^日減所不,當域*邊界晶粒¥後,利用選擇裝置選擇部分(或全部) 的邊界B0粒賴的晶粒W,_運算裝置計算標的晶粒γ 如第t ’4參考第4圖係本發明判斷地圖偏移之再—較佳實施例示意圖。 位’當定義出邊界晶粒¥後’利用分類裝置將邊界晶粒y依所在 以2 ^、A3、A4等喃邊界單元群組,運算裝置計算一個 ^如元群組中鳴瞻量,跑邊界單元群組㈣些晶粒狀 i算m路或無代表獨電性的晶錄態)數量_預先設定值時, ⑴運算裝置會發出-訊號’表示可能有地圖偏移的情形。 7 200929409 根據本發明-較佳實施例,當定義料界晶粒γ後,辟 # γϋ轉侧職嶋冑算標示。如 第^1除,第5a圖係將邊界晶粒γ分為左右兩個相對群組第兄圖係 晶粒γ分為上下兩個相對群組、第5e _將邊界晶粒左 下兩個相對群組、第5d _將邊界晶粒Y分為左上與右下兩個相對群ϋ -:界晶粒可以屬於多個不同的群組。接著使用一咖 相對群組進行錯誤率的比較,當錯誤率的差異到達一預先設定值時,發出一訊 ❹The integrated circuit (1C) integrated circuit is a multi-level division of labor architecture, including IC design, wafer manufacturing, circuk probing, and assembly. ) and final testing (finai testing). In the above-mentioned production division, the two rounds of testing for the round needle test and the final test are important points for the quality of the disc warranty. A wafer contains many cells. These cells are often called dies, but not all dies have good quality. Therefore, the method of wafer pinning is based on a very thin probe card. Or a small probe (fme-P〇int needle) tests each die on the wafer, and then marks or retains a mapping file on the defective die to classify good and defective products. In the county, wafer needle testing is performed directly after the wafer fabrication is completed, and the cost of defective products is unnecessary waste. Therefore, the wafer needle measurement step can classify the good and defective products on the wafer to reduce the package. Cost with subsequent testing. — In the wafer needle test, the machine is used to detect the first die, and then according to the preset test range, the die is aged in the above method. If the starting point is not found correctly. , the test range will be offset, and the error of the test result will be called the ground_shift (Na fun). Before you can use manual judgment to solve this problem, manually judge whether there is a map offset phenomenon, and check each circle by manual visual inspection. This method can be comprehensively checked and requires experienced technicians. It can operate effectively and cannot provide evidence. The known method is to pre-set the mark grain - η8 also) 'This mark grain has a known granule (4) '(4) grain position result is different from the known _ test result when the test starts 5 200929409 point error 'The problem of map offset occurred. However, this method must be pre-set the crystal plate before each test, and the added result of the step will also waste time and is difficult to fully implement. In view of the above, the test method and system for the semiconductor device provided by the present invention have been improved by the prior art. SUMMARY OF THE INVENTION Based on the solution to the shortcomings of the prior art, the test method of the semiconductor device provided by the present invention needs to pre-set the S-grain granules to increase the test efficiency. The object of the present invention is to provide a phenomenon in which a semiconductor device _ test method and a secret (4) judged that there is a map offset during the test of the 7C device. SUMMARY OF THE INVENTION The object of the present invention is to provide a method and a secret for the semi-guided component, reducing the time and increasing efficiency. Reducing the Human Body A further object of the present invention is to provide a test method and system for a semiconductor tree that emits a signal to alert the operator when a map offset occurs. Less-head-of-the-head supply--a test method for semiconductor components is provided to the Ο-off; then it is semi-conducting, and has a complex number of elements, each of which has its own cell-like i-boundary boundary. The unit, the set value is compared, and a message is sent to prompt the operator. Yin's choice of the early heart and then the operation of the device to send the shirt ^ [Embodiment j because the invention is a semi-conductive Zhao element _ test method and system, some of the base used by Yin 200929409 • The principle, belongs to the _ Those who have the usual knowledge are easy to understand, and Lin repeats. However, the expressions relating to the features of the present invention are not required to be drawn by the actual size. First, the first description is shown in FIG. 1 , which is a preferred embodiment of the present invention. A schematic diagram of an example. As the second first provides, the semiconductor device is a wafer 100 in this embodiment, and the plurality of single crystals contained in the crystal are grains (10). Next, when the test device is used to align the wafer, the measurement is shown when the measurement point is offset, and the number in the job map 112 represents the wafer, wherein the crystal ❹ is similar. On the day of the day, the grain state 3 represents the grain short circuit (sh〇rt), and the grain state 4 represents the grain opening. In the case of the grain opening, the defect test of the grain 1〇2 is performed first, and the # die removal test == When it is collectively referred to as an error; or when the test state of the die 1〇2 is different from the expected state, it may also be referred to as an error. Then, as shown in FIG. 2, the schematic of the present invention for judging the boundary grain is small in this embodiment == the grain X has a maximum of 8 adjacent grains'. When 〇2 has 8 adjacent grains, the device determines that the grain is the boundary grain γ. Figure. Please refer to the 3^'s another section of the map offset. The hard-to-implement example shows the ^^ day minus. When the domain *boundary grain is ¥, use the selection device to select the partial (or all) boundary B0. The grain W, the _ computing device calculates the target γ, as shown in the t'4 reference to Fig. 4 is a schematic diagram of the preferred embodiment of the present invention for determining the map offset. Bit 'When defining the boundary grain ¥¥', using the classification device to divide the boundary grain y according to the group of 2 ^, A3, A4 and other boundary cells, the arithmetic device calculates a sounding quantity in the group Boundary unit group (4) Some grain-like i-calculated m-path or non-representative crystal-recorded state) _ Pre-set value, (1) The arithmetic device will issue a -signal indicating that there may be a map offset. 7 200929409 According to the present invention - the preferred embodiment, when the grain boundary γ of the material boundary is defined, the #γϋ turns the side job calculation index. For example, in addition to ^1, the 5a figure divides the boundary grain γ into two left and right relative groups. The γ of the figure is divided into two upper and lower relative groups, and the fifth _ _ the boundary grain is lower left and opposite The group, 5d _ divides the boundary grain Y into two upper and lower right groups - the boundary grain can belong to a plurality of different groups. Then use a coffee relative group to compare the error rate. When the difference of the error rate reaches a preset value, a message is sent.
號,此訊號傳❹警示裝置,警示裝置會形化資訊顯示,肋提醒操作人 員可能有地圖偏移的情形。 綜上所述’本發明提供了一種半導體元件的測試方法與系統,此方法可以 用來判斷半賴讀的顺過財是偏移的狀,可崎所有進行測 試的半導趙元件進行判斷,並且無須增加人力負擔。當系統判斷出可能有地圖 偏移的現象時,可以進-步發出峨,提示操作人員檢查起測點。 顯然地’依照上面實施例中的财,本發明可能有許多的修正與差異。因 此需要在其附加的權利要求項之範圍内加以理解,除了上餅細的描述外,本 發明還可以廣泛地在其他的實施例中施行。上述僅為本發明之較佳實施例而 已’並非用以限定本發明之申請專利範圍;凡其它未脫離本發明所揭示之精神 下所完成的等效改變或修飾,均應包含在下述申請專利範圍内。 【圖式簡單說明】 第1圖係本發明之起測偏移示意圖 第2圖係本發明一較佳實施例之邊界單元定義示意圖 第3圖係本發明一較佳實施例之判斷地圖偏移示意圖 第4圖係本發明一較佳實施例之判斷地圖偏移示意圖 第5a-5d圖係本發明一較佳實施例之判斷地圖偏移示意囷 8 200929409 【主要元件符號說明】 1 晶粒狀態(可用) 3 晶粒狀態(短路) 4 晶粒狀態(開路) 100 晶圓 102 晶粒 110 測量範圍 112 測試圖 Y 邊界晶粒 Y1 標的晶粒 A1-A4 邊界單元群組No., this signal transmits the warning device, the warning device will shape the information display, and the rib reminds the operator that there may be a map offset. In summary, the present invention provides a test method and system for a semiconductor component, which can be used to determine the offset of a half-reading readout, and can be judged by all the semi-conductive components that are tested. And there is no need to increase the manpower burden. When the system determines that there may be a phenomenon of map offset, you can step forward to prompt the operator to check the starting point. Obviously, the present invention may have many modifications and differences in accordance with the above embodiments. It is therefore to be understood that within the scope of the appended claims, the invention may be The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following claims. Within the scope. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a start-up offset of the present invention. FIG. 2 is a schematic diagram of a boundary element definition according to a preferred embodiment of the present invention. FIG. 3 is a diagram for determining a map offset according to a preferred embodiment of the present invention. FIG. 4 is a schematic diagram of determining a map offset according to a preferred embodiment of the present invention. FIG. 5a-5d is a schematic diagram of a map offset of a preferred embodiment of the present invention. 20098 200929409 [Description of main component symbols] 1 Grain state (Available) 3 Grain state (short circuit) 4 Grain state (open circuit) 100 Wafer 102 Grain 110 Measurement range 112 Test pattern Y boundary grain Y1 mark grain A1-A4 boundary cell group