200926378 .九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝基板及封裝結構，尤指一種 具電性埤接結構之封裝基板及其半導體封裝結構。 【先前技術】 在現行覆晶（Flip Chip)技術中，於積體電路（ic)之 半導體晶片的作用面上具有電極墊，而有機電路板亦具有 相對應該電極墊之電性連接墊，於該半導體晶片之電極塾 電路板之電性連接墊之間形成焊錫結#或其他導電點 著材料，該焊錫結構或導電黏著材料提供該半導體晶片以 及電路板之間的電性連接以及機械性的連接，相關技術如 第1A至1G圖所示。首先提供一基板本體1〇，係具有内 層線2 ιοί及複數電性連接墊103,該電性連接墊ι〇3位 於覆蓋該内層線路101之介電層1〇2表面上，且該些電性 連接墊103以導電盲孔104電性連接該内層線路ι〇ι，如 〇第1A @所示；接著’於該介電層m表面上形成一係如 防焊層之絕緣保護層u，於該絕緣保護層u中形成複數 相對應該電性連接墊1〇3之開孔11〇，如帛iB圖所示； 之後於該絕緣保護層11上表面、該開孔110側表面及顯 露於該開孔110之電性連接墊103上表面形成一導電層 12’然後於該導電f 12上表面形成一阻層13，於該阻層 13中形成複數開口 13〇以對應顯露該開孔I"及電性連 接塾103表面上的導電層12,如第1C圖所示；藉由該導 電層12作為電鑛之電流傳導路徑以於該阻層13之開口 110478 5 200926378 …·:30中電鍍形成係如焊錫之導電材 .係電性連接該電性連接墊1〇3， =電材们4 除該阻層U及其所覆蓋之= = ^ = 之後，經〜 電材枓14融熔成—係如錫球之 -封褒基板1，如第1F圖所示。電…4，俾以完成 ο 二=閱第1G圖’該封裝基板1具有第-表面la及第 I:緣二：該第一表面1a具有該絕緣保護層11，且於 1中具有該外露之導電元件14、-半導 體晶片2具有一作用等 廄兮道餘 該作用面2a具有複數相對 應以導電7L件14,之導電凸塊21 焊製程以包覆該導雷1導電兀件14經迴 、鱼μ 乂 俾將該半導體晶>5 2電性 Π,基板^且於該封裝基板1與半導體晶片2之 蚵真充有底Dp填勝（underfiU)23。 ❹ ，該導電凡件14,係採用凸出於該絕緣保護層η 2上表面’使該半導體晶片2之導電凸塊21經迴谭而接 間的間隔較大，使得二裝:4=與封裝基板〗之 小封裝之目的。體间度無法降低，而無法達到薄 卜該導電元件14’係形成於該平直之電性連接塾 ⑽表面，使該導電元件】4，與電性連接墊⑽之間的接 觸面積較小，因此該導電元件14，與電性連接墊ι〇3之 間的結合力較弱’導致該導以件14，容易產生脫落的情 110478 6 200926378 者二?？板1之導電元件14,凸出於該絕緣保 護層11表面且為球狀，使該半導體晶片2之導電凸塊21 與導電兀件14,對接並經迴烊而接置後 = 於融溶狀態下因互相接觸而發生導致短路::接 導電元件14,之間必須保持較大的間距， 因此無法達到細間距以達增 接點數之目的。 s力輸出/輸入（I聊t/〇utput) Ο 此夕二：導電材料14經印刷及迴烊而形成導電元件 =之=Γ14’之高度共面性不佳，使該半導邀晶 片2之V電凸塊21與導電元件14,迴焊而對接後，因應 力分佈不均而導致該封裝體之接點斷裂或接觸不良，因 降低可靠度，而影響產品的品質。 因此，如何提供一種得縮小封裝基板與半導體晶片之 間的間隔以達到薄小封裝、避免導電元件脫落、並且縮小 電性連接墊之間的間距以供細間距之應用、以及避免該導 ❹ 面性不佳所致之應力分佈不均，已成為業 界之重要課題。 【發明内容】 鑑於上述習知技術之缺失，轉明之一目的係在於 提供-種具電性連接結構之封裝基板及其半導體封裝結 構，得降低封裝體高度以達薄小化之封裝結構。 本發明又一目的係在於提供一種具電性連接結構之 封裝基板及其半導體封裝結構’得增加電性連接整與焊接 材料之間的結合性’以避免該焊接材料產生脫落，俾提高 110478 200926378 ，可靠度。 本發明再一目的係在於提供一種具電性 封裝基板及其半導體封#_ 接、、、〇構之 致短路，、構’㈣免辉接材料溢流而導 短路進而侍縮小電性連接墊之間的間距。 ，發明另—目的係在於提供—種具電性連接結 此面生反及其半導體封裝結構，得以避免桿接材料之高产 ，、面性不佳而致應力分佈不均的情況。 q又 ο 為達上述及其他目的，本菸 _ a ^ 構之封梦甚k η 種具電性連接結 I之封裝基板，係包括：基板本體，其至少—表The invention relates to a package substrate and a package structure, and more particularly to a package substrate having an electrical splicing structure and a semiconductor package structure thereof. [Prior Art] In the current Flip Chip technology, an electrode pad is provided on the active surface of the semiconductor wafer of the integrated circuit (ic), and the organic circuit board also has an electrical connection pad corresponding to the electrode pad. A solder joint # or other conductive material is formed between the electrode pads of the semiconductor chip and the electrical connection pads of the circuit board, the solder structure or the conductive adhesive material provides electrical connection between the semiconductor wafer and the circuit board, and mechanical Connection, related art is shown in Figures 1A to 1G. Firstly, a substrate body 1 is provided, which has an inner layer 2 ιοί and a plurality of electrical connection pads 103. The electrical connection pads 10 are located on the surface of the dielectric layer 1 覆盖 2 covering the inner layer 101, and the electricity is The connection pad 103 is electrically connected to the inner layer line ι〇ι by a conductive blind hole 104, as shown in FIG. 1A@; then, an insulating protection layer u such as a solder resist layer is formed on the surface of the dielectric layer m. Forming a plurality of openings 11 相对 corresponding to the electrical connection pads 1 〇 3 in the insulating protective layer u, as shown in FIG. 2B; then, the upper surface of the insulating protective layer 11 and the side surface of the opening 110 are exposed A conductive layer 12 ′ is formed on the upper surface of the electrical connection pad 103 of the opening 110 , and then a resist layer 13 is formed on the upper surface of the conductive layer 12 , and a plurality of openings 13 形成 are formed in the resist layer 13 to correspondingly expose the opening I" And electrically connecting the conductive layer 12 on the surface of the crucible 103, as shown in FIG. 1C; by using the conductive layer 12 as a current conduction path of the electric ore to the opening of the resist layer 13 110478 5 200926378 ...::30 Electroplating is formed into a conductive material such as solder. The electrical connection pad is electrically connected to the electrical connection pad 1〇3, = electrical materials 4 After the resist layer U and its covered == ^ =, it is melted through the electrical material 枓 14 into a solder ball substrate 1 as shown in Fig. 1F. The first substrate 1 has a first surface 1a and a first surface 2: the first surface 1a has the insulating protective layer 11 and has the exposed portion 1 in FIG. The conductive element 14 and the semiconductor wafer 2 have an action and the like. The active surface 2a has a plurality of corresponding conductive 7L members 14 , and the conductive bumps 21 are soldered to cover the conductive conductive elements 14 . The semiconductor crystal is electrically entangled, and the substrate is filled with the bottom surface Dp of the package substrate 1 and the semiconductor wafer 2. ❹ , the conductive member 14 is protruded from the upper surface of the insulating protective layer η 2 to make the interval between the conductive bumps 21 of the semiconductor wafer 2 to be tanned, so that the second mounting: 4 = and The purpose of the small package of the package substrate. The inter-body degree cannot be reduced, and the conductive element 14' is formed on the surface of the flat electrical connection port (10), so that the contact area between the conductive element 4 and the electrical connection pad (10) is small. Therefore, the bonding force between the conductive member 14 and the electrical connection pad ι〇3 is weak, which results in the guide member 14, which is prone to fall off. 110478 6 200926378 The conductive member 14 of the board 1 protrudes from the surface of the insulating protective layer 11 and is spherical, so that the conductive bump 21 of the semiconductor wafer 2 and the conductive member 14 are butted and connected after being replaced. In the state, the short circuit occurs due to mutual contact: the conductive elements 14 are connected, and a large spacing must be maintained, so that the fine pitch cannot be achieved to achieve the purpose of increasing the number of joints. s force output / input (I chat t / 〇 utput) Ο 夕 : : : : : 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电After the V-electrode bump 21 and the conductive element 14 are butt-welded, the joint of the package is broken or the contact is poor due to uneven stress distribution, and the reliability is deteriorated, thereby affecting the quality of the product. Therefore, how to provide a method for reducing the spacing between the package substrate and the semiconductor wafer to achieve a thin package, avoiding the dropping of the conductive member, and reducing the spacing between the electrical connection pads for fine pitch, and avoiding the guiding surface The uneven distribution of stress caused by poor sex has become an important issue in the industry. SUMMARY OF THE INVENTION In view of the above-mentioned deficiencies of the prior art, one of the objectives of the invention is to provide a package substrate having an electrical connection structure and a semiconductor package structure thereof, and to reduce the height of the package to achieve a thin package structure. Another object of the present invention is to provide a package substrate having an electrical connection structure and a semiconductor package structure thereof to increase the bond between the electrical connection and the solder material to prevent the solder material from falling off, and improve 110478 200926378 , reliability. A further object of the present invention is to provide an electrical package substrate and a semiconductor package thereof, which are connected to each other, and a short circuit caused by the structure, and the structure of the (4) free-graft material overflows and leads to a short circuit, thereby reducing the electrical connection pad. The spacing between them. The invention is also aimed at providing a kind of electrical connection junction, which is opposite to the semiconductor package structure, so as to avoid the high yield of the rod-joining material and the uneven surface distribution, resulting in uneven stress distribution. q又 ο For the above and other purposes, the present invention is a package substrate having an electrical connection I, comprising: a substrate body, at least -
=層及設於其中之複數電性連接墊，該些電性連接墊之I 部且未高於該介電層；焊接材料，係設於各 電層及焊接材料上，且具有㈣心蔓層’係“又於該介 材料。 叶上且具有複數開孔以對應顯露該些焊接 〇 於冓’該絕緣保護層之開孔尺寸係小於或大 寸；復包括表面處理層’係設於該電性 = 之凹陷部與該谭接材料之間；該表面處理 金0^Au)、鎖/纪/金（Ni/Pd/Au)、^Ag)及金（㈢ >中-者；該辉接材料復延伸至該絕緣保護層之開孔 於卞工^ 表或者，該焊接材料高度係高 於、背平及低於該介電層上表面 絕緣保護層之上表面。 f且未同於該 包括本其發提供另一種具電性連接結構之封裝基板，係 ^ 體，其至少一表面具有介電層及設於其令之 110478 8 200926378 #複數電性連接墊與線路，該些電性連接墊之上表面具有凹 陷部且未高於該介電層’該些線路之上表面係未高於該： 電層；焊接材料，係設於該些電性連接墊之凹陷部中；^以 及絕緣保護層，係設於該基板本體表面之線路區域並霜= 該些線路之上表面。 狐 依上述之結構，復包括表面處理層，係設於該電性連 接墊之凹陷部與該焊接材料之間；該表面處理層係為鎳/a layer and a plurality of electrical connection pads disposed therein, the I of the electrical connection pads is not higher than the dielectric layer; the solder material is disposed on each of the electrical layers and the solder material, and has (four) heart The layer 'system' is further on the material. The leaf has a plurality of openings to correspondingly expose the solder joints. The opening size of the insulating protective layer is less than or large; the surface layer including the surface treatment layer is The electrical resistance = between the recessed portion and the tantalum material; the surface treatment of gold 0^Au), lock/Ji/Gold (Ni/Pd/Au), ^Ag) and gold ((3) > The fused material is extended to the opening of the insulating protective layer or the height of the soldering material is higher than, flatter and lower than the upper surface of the insulating protective layer on the upper surface of the dielectric layer. In addition, the package substrate includes another dielectric connection structure, and at least one surface thereof has a dielectric layer and is disposed on the 110478 8 200926378 #plural electrical connection pads and lines. The upper surface of the electrical connection pads has a recess and is not higher than the dielectric layer. The electric layer; the solder material is disposed in the recessed portion of the electrical connection pads; and the insulating protective layer is disposed on the line region of the surface of the substrate body and frost = the upper surface of the lines. The structure includes a surface treatment layer disposed between the recessed portion of the electrical connection pad and the solder material; the surface treatment layer is nickel/
金（Ni/Au)、鎳/鈀/金（Ni/Pd/Au)、銀（Ag)及金（Au)之其 中一者。 八 本發明復提供一種半導體封裝結構，係包括：封裝基 板，係於基板本體之至少一表面設有介電層，且於該介電 層中a有複數電性連接墊，該些電性連接塾之上表面並形 成凹陷部且未高於該介電層，於該凹陷部中設有焊接材 料又該；I電層及焊接材料上設有絕緣保護層，該絕緣保 ”蒦層中具有複數開孔以對應顯露該焊接材料；半導體晶 ©片，係具有一作用面，該作用面具有複數導電凸塊，並藉 由該焊接材料以對應電性連接該封裝基板之電性連接墊 與半導體晶片之導電凸塊；以及底部填膠（underfill)， 係設於該絕緣保護層及該半導體晶片之間。 依上述之結構，該絕緣保護層之開孔尺寸係小於及大 於該電性連接墊尺寸之其中一者；復包括表面處理層，係 叹於該電性連接墊之凹陷部與該焊接材料之間；該表面 處理層係為鎳/金（Ni/Au)、鎳/鈀/金（Ni/Pd/Au)、銀（Ag) 及金（Au)之其中一者。 θ 110478 200926378 本發明復提供一種半導體封裝結構，係包括：封裝基 板，係於基板本體之至少一表面設有介電層，且於該介電 層中設有複數電性連接墊與線路，該些電性連接墊之上表 面具有凹陷部且未高於該介電層，該些線路之上表面係未 高於該介電層，且該些電性連接墊之凹陷部中設有焊接材 料，又該介電層上之線路區域設有絕緣保護層，以覆蓋在 β亥些線路上，半導體晶片，係具有一作用面，該作用面具 有複數導電凸塊’並藉由該焊接材料以對應電性連接該封 〇裝基板之電性連接墊與半導體晶片之導電凸塊；以及底 部填膠（underfill)，係設於該介電層及該半導體晶片之 間。 依上述之結構，復包括表面處理層，係設於該電性連 接墊之凹陷部與該焊接材料之間；該表面處理層係為錄/ 金W/Au)、錄/把/金（Ni/pd/Au)、銀（Ag)及金（Au)之其 中一者。 ❹ 本發明之具電性連接結構之封裝基板及其半導體封 裝°構中該電性連接墊之上表面具有凹陷部，使該半導 U之導電凸塊對接在該凹陷部時得以縮小封装體高 度’且該凹陷部與焊接材料之間具有較大的接觸面積，俾 以增加該電性連接墊與焊接材料之間的結合性，以避免該 =接材料產生脫落；又該焊接材料可不高於該絕緣^ 曰曰^開孔’使該焊接材料經迴焊製㈣電性連接該半導體 1導電凸塊得避免該焊接材料溢流而導致短路，進而 、J電欧連接塾之間的間距；此外，可免除習知結構之 110478 10 200926378 •V電元件的间度共面性不佳導致應力分佈不均的情況， 況，俾減少封裝體中晶片端之凸塊承受來自基板絕緣保護 層之應力’故本發明得提高可靠度，避免影響產品的 【實施方式】 '以下係藉由特定的具體實例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容_ 瞭解本發明之其他優點與功效。 Λ [第一實施例] 請參閱第2Α至2F圖’係詳細說明本發明之具電性連 接結構之封裝基板及其半導體封裝結構之第一實施例的 製法剖面示意圖。 如第2Α圖所示，首先提供具有内層線路3〇1之基板 本體30,於該基板本體30表面具有介電層3〇2及設於其 中之複數電性連接墊303，且該電性連接墊3〇3上表面未 高於該介電層302上表面，較佳為與該介電層3〇2上表面 齊平，又該些電性連接墊303以相對應之導電盲孔3〇4 電性連接該内層線路301;於該基板本體3〇之介電層如2 上形成一絕緣保護層31，且該絕緣保護層31中形成複數 對應該電性連接墊303之開孔310 ’且該開孔31〇之尺寸 係小於該電性連接墊3 〇 3之尺寸，而為絕緣保護層所定義 電性連接墊（Solder Mask Defined Pad, SMD Pad)。 如第2B圖所示’該些電性連接墊3〇3之上表面進行 蝕刻製程，以於該電性連接墊303之上表面形成凹陷= π 110478 200926378 、如第2C及2C’圖所示’於各該電性連接塾之凹 .接材料34,該焊接材料34係齊平 圖《，=層302上表面’或可低於該介電層3〇2上表面（未 Γ;::接材料34係為錫(Sn)、錯 (Cu)、鋅（ZrO及鉍（Bi)所組成群組之其中一 %圖之不同處，係於該電性連接墊303之凹陷 =305上依序形成表面處理層33及嬋接材料仏該表面 ο =理層33係為錄/金（Ni/Au)、錄心金⑻/嶋小銀 (Ag)及金（Au)之其中一者。 另如第2D及2D’圖所示’於各該電性連接墊3〇 Γ部3〇5中形成之谭接材料34係高於該介電層302上 表面，且未高於該絕緣保護層31;第2D，圖相較於第肋 圖之不同處，係於電性連接墊3〇3之凹陷部3〇5上依序形 成表面處理層33及焊接材料34。 ο 再如第2E及2E’圖所示’於各該電性連接墊3〇3之 =陷部m中形成之焊接材料34復延伸至該絕緣保護層 之開孔310侧壁及其開孔31〇周緣之表面；》2e，圖相 較於第2E圖之不同處，係於電性連接㈣3之凹陷部鳩 上依序形成表面處理層33及焊接材料34。 本發明復提供-種具電性連接結構之封裝基板，係包 括：基板本體30，其至少一表面具有介電層3〇2及設於 其中之複數電性連接塾303’該些電性連接塾3〇3之上表 面具有凹陷部305且未高於該介電層3〇2;焊接材料 係設於各該電性連接墊3 〇 3之凹陷部3 〇 5中；以及絕緣保 110478 12 200926378 •護層3卜係設於該介電層3〇2及焊接材料％上且具有 複數開孔310以對應顯露該些焊接材料％，且該絕緣保 護層31之開孔310尺寸係小於該電性連接塾3〇3尺寸。One of gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), silver (Ag) and gold (Au). The invention provides a semiconductor package structure, comprising: a package substrate, wherein a dielectric layer is disposed on at least one surface of the substrate body, and a plurality of electrical connection pads are disposed in the dielectric layer, and the electrical connections are The upper surface of the crucible is formed with a depressed portion and is not higher than the dielectric layer, and the soldering material is disposed in the recessed portion; the I electrical layer and the soldering material are provided with an insulating protective layer, and the insulating layer has an insulating layer a plurality of openings for correspondingly exposing the solder material; the semiconductor wafer has an active surface, the active surface having a plurality of conductive bumps, and the soldering material is electrically connected to the electrical connection pads of the package substrate a conductive bump of the semiconductor wafer; and an underfill is disposed between the insulating protective layer and the semiconductor wafer. According to the above structure, the opening size of the insulating protective layer is smaller than or larger than the electrical connection. One of the pad dimensions; the surface treatment layer is sighed between the recess of the electrical connection pad and the solder material; the surface treatment layer is nickel/gold (Ni/Au), nickel/palladium/ Gold (Ni/Pd/ A semiconductor package structure includes: a package substrate, wherein a dielectric layer is provided on at least one surface of the substrate body, and θ 110478 200926378 A plurality of electrical connection pads and lines are disposed in the dielectric layer, and the upper surface of the electrical connection pads has a recess and is not higher than the dielectric layer, and the upper surface of the lines is not higher than the dielectric a soldering material is disposed in the recessed portion of the electrical connection pads, and an insulating protective layer is disposed on the wiring region on the dielectric layer to cover the lines of the semiconductor, and the semiconductor wafer has an active surface The active surface has a plurality of conductive bumps' and electrically connected to the electrical connection pads of the packaged substrate and the conductive bumps of the semiconductor wafer by the solder material; and an underfill is attached to Between the dielectric layer and the semiconductor wafer, according to the above structure, a surface treatment layer is disposed between the recessed portion of the electrical connection pad and the solder material; the surface treatment layer is recorded/gold W /Au), record / put / gold (Ni / pd / One of Au), silver (Ag), and gold (Au). The package substrate having the electrical connection structure of the present invention and the semiconductor package thereof have a depressed portion on the upper surface of the electrical connection pad. When the conductive bump of the semi-conducting U is docked in the recess, the height of the package is reduced, and the recess has a large contact area with the solder material to increase the bonding between the electrical connection pad and the solder material. To prevent the material from falling off; and the solder material may be higher than the insulating material to make the solder material be re-welded (4) electrically connected to the semiconductor 1 conductive bump to avoid the solder material The overflow causes a short circuit, and further, the spacing between the J-electron connection ports; in addition, the conventional structure can be dispensed with 110478 10 200926378 • The uneven coplanarity of the V electrical components leads to uneven stress distribution,俾Reducing the bump of the wafer end in the package to withstand the stress from the substrate insulating protective layer. Therefore, the present invention improves the reliability and avoids affecting the product. [The following is a specific example to illustrate the present invention. In other ways, those skilled in the art can understand the other advantages and benefits of the present invention. [First Embodiment] Referring to Figures 2 to 2F, a schematic cross-sectional view showing a first embodiment of a package substrate having an electrical connection structure and a semiconductor package structure thereof according to the present invention will be described in detail. As shown in FIG. 2, a substrate body 30 having an inner layer line 3〇1 is provided, and a dielectric layer 3〇2 and a plurality of electrical connection pads 303 disposed therein are provided on the surface of the substrate body 30, and the electrical connection is performed. The upper surface of the pad 3〇3 is not higher than the upper surface of the dielectric layer 302, preferably flush with the upper surface of the dielectric layer 3〇2, and the electrical connection pads 303 are corresponding to the conductive blind holes 3〇. 4 is electrically connected to the inner layer line 301; an insulating protective layer 31 is formed on the dielectric layer of the substrate body 3, and an opening 310 of the plurality of corresponding electrical connection pads 303 is formed in the insulating protective layer 31. The size of the opening 31 is smaller than the size of the electrical connection pad 3 〇 3, and is defined as a Solder Mask Defined Pad (SMD Pad). As shown in FIG. 2B, the upper surface of the electrical connection pads 3〇3 is etched to form a recess on the upper surface of the electrical connection pad 303=π110478200926378, as shown in FIGS. 2C and 2C' 'The recessed material 34 of each of the electrical connections ,, the solder material 34 is flushed to the upper surface of the layer 302 or may be lower than the upper surface of the dielectric layer 3〇2 (:Γ:: The bonding material 34 is different from one of the group of tin (Sn), erbium (Cu), and zinc (ZrO and bismuth (Bi), and is attached to the recess 305 of the electrical connection pad 303. Forming the surface treatment layer 33 and the splicing material 仏 the surface ο = the physique 33 is one of recording/gold (Ni/Au), recording gold (8)/嶋 small silver (Ag), and gold (Au). In addition, as shown in FIGS. 2D and 2D', the tantalum material 34 formed in each of the electrical connection pads 3 is substantially higher than the upper surface of the dielectric layer 302, and is not higher than the insulation protection. The layer 31; the second layer, compared with the rib pattern, is formed on the recessed portion 3〇5 of the electrical connection pad 3〇3 to form the surface treatment layer 33 and the solder material 34. ο And the 2E' diagram shows the electrical connection The welding material 34 formed in the depression portion m is extended to the side wall of the opening 310 of the insulating protective layer and the surface of the periphery of the opening 31; "2e", which is different from the difference of the second embodiment The surface treatment layer 33 and the solder material 34 are sequentially formed on the recessed portion of the electrical connection (4) 3. The package substrate of the present invention includes: the substrate body 30, at least one surface thereof The dielectric layer 3〇2 and the plurality of electrical connections 303 ′ disposed therein have a recess 305 on the upper surface of the electrical connection 且3〇3 and not higher than the dielectric layer 3〇2; the solder material system Provided in the recessed portion 3 〇5 of each of the electrical connection pads 3 〇 3; and the insulating layer 110478 12 200926378 • the protective layer 3 is disposed on the dielectric layer 3〇2 and the solder material % and has a plurality of openings 310 is correspondingly exposed to the solder material %, and the opening 310 of the insulating protective layer 31 is smaller in size than the electrical connection 塾3〇3.
上述之結構中，該焊接材料34高度係高於（如第2D 圖所示）、齊平（如第2C圖所示）及低於（未圖示）該介電層 302上表面之其中一者，且未高於該絕緣保護層31之上 表面；或者，該焊接材料34復延伸至該絕緣保護層3ι ο 之開孔310側壁及其開孔310周緣之表面（如第2E圖所 示）。 依上述之結構，復包括表面處理層33，係設於該電 性連接墊303之凹陷部305與該焊接材料34之間（如第 2C’，2D’’2E’圖所示）；該表面處理層33係為鎳/金 (Ni/Au)、錦/把 / 金（Ni/Pd/Au)、銀（Ag)及金（Au)之其中 一者。 明參閱第2F及2F’圖，本發明復提供一種半導體封 ❹裝結構，係包括：封裝基板30，係於基板本體3〇之至少 一表面設有介電層302,且於該介電層3〇2中設有複數 性連接墊⑽，該些電性連接墊3Q3之上纟面並 部305且未高於該介電層302，於該凹陷部3〇5設有焊接 材料34,又該介電層3〇2及焊接材料34上設有絕緣保護 層31 ’該絕緣保護層31中具有複數開孔3丨〇以對應顯露 該焊接材料34 ’且該絕緣保護層31之開孔31〇尺寸係小 於該電性連接墊303尺寸；半導體晶片4,係具有一作用 面4a，該作用面4a具有複數導電凸塊4卜並藉由該焊接 Π0478 13 200926378 •材料34以對應電性連接該封裝基板3〇之電性連接墊3〇3 與半導體晶片4之導電凸塊41 ;以及底部填膠 (underfi 11)42’係設於該絕緣保護層31及該半導體晶片 4之間。 依上述之結構’復包括表面處理層33,係設於該電 性連接墊303之凹陷部305與該焊接材料34之間，該表 面處理層33係為鎳/金（Ni/Au)、鎳/鈀/金（Ni/pd/Au)、 銀（Ag)及金（Au)之其中一者。 〇 [第二實施例] 請參閱第3A至3E圖，係詳細說明本發明之具電性連 接結構之封裝基板與製法之第二實施例的剖面示意圖，與 前一實施例之不同處在於該絕緣保護層開孔之尺寸係大 於該電性連接墊尺寸。 如第3A圖所示，首先提供係如第2A圖所示之結構， 不同處在於該絕緣保護層31中之開孔31〇，之尺寸係大於 ❹該電性連接墊303之尺寸，而為非絕緣保護層所定義電性 連接墊（Non Solder Mask Defined Pad, NSMD Pad)。 如第3B圖所示，於該些電性連接墊3〇3之上表面進 行餘刻製程形成凹陷部3 〇 5。 如第3C及3C’圖所示，於各該電性連接墊3〇3之凹 陷部305中以電鍍形成焊接材料34,該焊接材料34係齊 平於該介電層302上表面，或可低於該介電層go?上表面 (未圖示）；第3C，圖相較於第3C圖之不同處，係於該電 性連接墊303之凹陷部3〇5上依序形成表面處理層33及 110478 14 200926378 .焊接材料34。 另如第3D及如，®〜- 圖所不，於各該電性連接墊303之 凹陷部305中形成之煜盎鉍 心 ^^ 斗接材科34係尚於該介電層302而 未尚於該絕緣保護層31.笛 ^ 層31，弟3D圖相較於第3D圖之不同 處理層33及焊接連==之凹陷部邮上依序形成表面 再如弟3 E及q p ’ I®沉· - v.. dE圖所不，於各該電性連接墊303之 ❹ 啊广形成之焊接材料34復延伸至該絕緣保護層 Μ之Λ\310’侧壁及其開孔31『周緣之表面；第3E，圖 相較於第3E圖之不同處，係於雷柯 保於電性連接墊303之凹陷部 305上依序形成表面處理層33及焊接材料 [第三實施例] 請參閱第4A至π圖，係詳細說明本發明之具電性連 接結構之封裝基板及其半導體封裝結_製法之第三實 施例的剖面示意圖；與前述實施例之不同處在於該介電 層中復包括有線路。 如第4A圖所示’首先提供一係如第2A圖所示之結 構，其中之基板本體30表面具有介電層3〇2及設於其中 之複數電性連接墊303與線路3〇6，該些電性連接墊/3〇3 及線路306之上表面係未高於該介電層3〇2之上表面較 佳為齊平該介電層3Q2之上表面，以顯露該些電性連接塾 303及線路306之上表面；然後，形成絕緣保護層μ於 該基板本體30表面之該線路306區域，並覆蓋該些線路 3 0 6之上表面。 110478 15 200926378 ..如第4B圖所示’於該些電性連接塾303之上表面形 成凹陷部305。 第4C及4C圖所示，於該電性連接墊之凹陷部⑽$ 中電鑛形成谭接材料34,其中該焊接材料％係為錫 ㈤、鉛（Pb)、銀（Ag)、銅（Cu)、鋅（Zn)及叙⑻）所組成 群組之其中一者；第4C，圖相較於第4C圖之不同處，係 於該電性連接塾3G3之凹陷部3G5上依序形成表面處理層 33及焊接材料34,該表面處理層33係為錄/金⑷、 〇鎳/鈀/金（Ni/Pd/Au)、銀（Ag)及金（Au)之其中一者。 本發明復提供-種具電性連接結構之封裝基板，如第 4C圖所示，係包括：基板本體3〇，其至少一表面具有介 電層302及設於其中之複數電性連接塾3〇3#線路3〇6， 該些電性連接墊303之上表面具有凹陷部3〇5且未高於該 介電層3G2，該些線路3G6之上表面係未高於該介電層 302 ;焊接材料34,係設於該些電性連接墊3〇3之凹陷部 〇 305中；以及絕緣保護層3卜係設於該基板本體3〇表面 之線路區域並覆蓋該些線路306之上表面。 依上述之結構，復包括表面處理層33,如第4C，圖所 不，係設於該電性連接墊303之凹陷部305與該焊接材料 34之間，該表面處理層33係為鎳/金⑺丨/乜）、鎳/鈀〆金 (Ni/Pd/Au)、銀（Ag)及金（Au)之其中一者。 請參閱第4D圊，本發明復提供一種半導體封裝結 構，係包括：封裝基板30，係於基板本體3〇之至少一表 面設有介電層302’且於該介電層3〇2中設有複數電性連 110478 16 200926378 ，接墊303與線路306，該些電性連接墊3〇3之上表面具有 凹陷部3〇5且未高於該介電層3〇2,該些線路3〇6之上表 面係未高於該介電層3〇2,且該些電性連接墊3〇3之凹陷 部305中設有焊接材料34，又該介電層3〇2上之線路區 域設有絕緣保護層31，以覆蓋在該些線路3〇6上；半導 體晶片4，係具有一作用面4a，該作用面4a具有複數導 電凸塊41，並藉由該焊接材料34以對應電性連接該封裝 基板30之電性連接墊3〇3與半導體晶片4之導電凸塊 〇 41;以及底部填膠（underfiu)42，係設於該介電層3〇2 及該半導體晶片4之間。 請參閲第4D’圖，復包括表面處理層33，係設於該電 性連接墊303之凹陷部305與該焊接材料34間，該表面 處理層33係為鎳/金（Ni/Au)、鎳/鈀/金（Ni/Pd/Au)、銀 (Ag)及金（Au)之其中一者。 本發明之具電性連接結構之封裝基板及其半導體封 ❹裝結構，該電性連接墊303之上表面具有凹陷部3〇5，使 該半導體晶片4之導電凸塊41得對接在該凹陷部3〇5 中，俾以縮小封裝體高度；且該電性連接墊3〇3之凹陷部 305與焊接材料34之間具有較大的接觸面積，俾以增加 該電性連接墊303與焊接材料34之間的結合性，以避免 該焊接材料34脫落；又該焊接材料34可不高於該絕緣保 護層31之開孔310,使該焊接材料34經迴焊製程而電性 連接該半導體晶片4之導電凸塊41得避免該焊接材料％ 溢流而導致短路，進而得縮小電性連接墊3〇3之間的間 110478 17 200926378 严，以達細間距並增加輸出/輸入（InpUt/〇utpUt)接點數 之目的；此外，該焊接材料之高度共面性佳，而可免除習 知結構之應力分佈不均的情況’俾減少封裝體中晶片端之 凸塊承受來自基板絕緣保護層之應力，故本發明可提高產 品可靠度。 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與改 〇變。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 【圖式簡單說明】 圖 ❹ 圖； 第1A及1G圖係為習知覆晶式封裝基板之製法示意 第2A至2FU係為本發明第—實施例之 第2C，圖係為第2C圖的另一實#能媒立,、 似圖， 口 J力貫靶態樣剖視示意圖； 第2D’圖係為第2D圖的另—音#能媒、 力貫苑態樣剖視示意圖In the above structure, the solder material 34 is higher in height (as shown in FIG. 2D), flush (as shown in FIG. 2C), and lower than (not shown) one of the upper surfaces of the dielectric layer 302. And not higher than the upper surface of the insulating protective layer 31; or, the soldering material 34 is extended to the sidewall of the opening 310 of the insulating protective layer 3i and the surface of the periphery of the opening 310 (as shown in FIG. 2E) ). According to the above structure, the surface treatment layer 33 is disposed between the recessed portion 305 of the electrical connection pad 303 and the solder material 34 (as shown in FIG. 2C', 2D''2E'); The treatment layer 33 is one of nickel/gold (Ni/Au), bromine/gold/Ni (Ni/Pd/Au), silver (Ag), and gold (Au). Referring to FIGS. 2F and 2F', the present invention further provides a semiconductor package armor structure, comprising: a package substrate 30, a dielectric layer 302 is disposed on at least one surface of the substrate body 3, and the dielectric layer is disposed on the dielectric layer A plurality of connection pads (10) are disposed in the third layer 2, and the upper surface portion 305 of the electrical connection pads 3Q3 is not higher than the dielectric layer 302, and the solder material 34 is disposed on the recess portion 3〇5. The dielectric layer 3 〇 2 and the solder material 34 are provided with an insulating protective layer 31 ′. The insulating protective layer 31 has a plurality of openings 3 丨〇 to correspondingly expose the solder material 34 ′ and the opening 31 of the insulating protective layer 31 . The size of the crucible is smaller than the size of the electrical connection pad 303; the semiconductor wafer 4 has an active surface 4a having a plurality of conductive bumps 4 and electrically connected by the solder Π 0478 13 200926378 • material 34 The electrical connection pads 3 〇 3 of the package substrate 3 and the conductive bumps 41 of the semiconductor wafer 4 and the underfill 11 42 ′ are disposed between the insulating protection layer 31 and the semiconductor wafer 4 . According to the above structure, the surface treatment layer 33 is disposed between the recessed portion 305 of the electrical connection pad 303 and the solder material 34. The surface treatment layer 33 is made of nickel/gold (Ni/Au) and nickel. /Palladium/gold (Ni/pd/Au), silver (Ag) and gold (Au).第二 [Second Embodiment] Please refer to FIGS. 3A to 3E for a detailed cross-sectional view showing a package substrate having an electrical connection structure and a second embodiment of the method of the present invention, which is different from the previous embodiment in that The size of the insulating protective layer opening is larger than the size of the electrical connecting pad. As shown in FIG. 3A, a structure as shown in FIG. 2A is first provided, the difference being that the opening 31 in the insulating protective layer 31 is larger than the size of the electrical connection pad 303, and Non-insulated protective layer defined by the Non Solder Mask Defined Pad (NSMD Pad). As shown in Fig. 3B, the recessed portions 3 〇 5 are formed on the upper surface of the electrical connection pads 3〇3. As shown in FIGS. 3C and 3C', a solder material 34 is formed in the recess 305 of each of the electrical connection pads 3〇3, and the solder material 34 is flush with the upper surface of the dielectric layer 302, or may be Lower than the dielectric layer go? upper surface (not shown); 3C, compared with the difference of the 3C figure, the surface treatment is sequentially formed on the recessed portion 3〇5 of the electrical connection pad 303. Layer 33 and 110478 14 200926378 . Soldering material 34. In addition, as shown in FIG. 3D and FIG. 3, the embossed portion 34 of the electrical connection pad 303 is formed in the dielectric layer 302. Still in the insulating protective layer 31. flute layer 31, the brother 3D map is formed on the surface of the different processing layer 33 of the 3D drawing and the concave portion of the welded joint ==, and then the surface is formed as the third 3 E and qp 'I ® sink · - v.. dE diagram does not, after each of the electrical connection pads 303, the widely formed solder material 34 is extended to the side of the insulating protective layer Λ \ 310 ' sidewall and its opening 31 The surface of the periphery; 3E, the difference from the 3E figure, is formed by the surface treatment layer 33 and the solder material sequentially on the depressed portion 305 of the electrical connection pad 303. [Third embodiment] 4A to FIG. 3 are schematic cross-sectional views showing a third embodiment of a package substrate having an electrical connection structure and a semiconductor package structure thereof according to the present invention; the difference from the foregoing embodiment is that the dielectric layer Zhongfu includes lines. As shown in FIG. 4A, a structure as shown in FIG. 2A is first provided, wherein the surface of the substrate body 30 has a dielectric layer 3〇2 and a plurality of electrical connection pads 303 and lines 3〇6 disposed therein. The upper surface of the electrical connection pads /3〇3 and the line 306 is not higher than the upper surface of the dielectric layer 3〇2, and the upper surface of the dielectric layer 3Q2 is preferably flushed to expose the electrical properties. The top surface of the germanium 303 and the wiring 306 are connected; then, an insulating protective layer μ is formed on the surface of the substrate 306, and the upper surface of the wiring 306 is covered. 110478 15 200926378 . . as shown in FIG. 4B, a recess 305 is formed on the upper surface of the electrical connection ports 303. 4C and 4C, in the recessed portion (10) of the electrical connection pad, the electric ore is formed into a tantalum material 34, wherein the solder material % is tin (f), lead (Pb), silver (Ag), copper ( One of the groups consisting of Cu), zinc (Zn), and (8)); 4C, in comparison with the difference of FIG. 4C, sequentially formed on the recess 3G5 of the electrical connection 塾3G3 The surface treatment layer 33 and the solder material 34 are one of recording/gold (4), bismuth nickel/palladium/gold (Ni/Pd/Au), silver (Ag), and gold (Au). The present invention provides a package substrate having an electrical connection structure, as shown in FIG. 4C, comprising: a substrate body 3 having at least one surface having a dielectric layer 302 and a plurality of electrical connections 3 disposed therein 〇3#线3〇6, the upper surface of the electrical connection pads 303 has a recessed portion 3〇5 and is not higher than the dielectric layer 3G2, and the upper surface of the lines 3G6 is not higher than the dielectric layer 302. The solder material 34 is disposed in the recess portion 305 of the electrical connection pads 3〇3; and the insulating protection layer 3 is disposed on the line region of the surface of the substrate body 3 and covers the lines 306. surface. According to the above structure, the surface treatment layer 33 is further provided, as shown in FIG. 4C, which is disposed between the recessed portion 305 of the electrical connection pad 303 and the solder material 34. The surface treatment layer 33 is made of nickel/ Gold (7) 丨 / 乜), nickel / palladium ruthenium (Ni / Pd / Au), silver (Ag) and gold (Au) one of them. Referring to FIG. 4D, the present invention further provides a semiconductor package structure, comprising: a package substrate 30, wherein a dielectric layer 302' is disposed on at least one surface of the substrate body 3, and is disposed in the dielectric layer 3? There is a plurality of electrical connections 110478 16 200926378 , a pad 303 and a line 306 , the upper surface of the electrical connection pads 3 〇 3 has a recess 3 〇 5 and is not higher than the dielectric layer 3 〇 2, the lines 3 The upper surface of the crucible 6 is not higher than the dielectric layer 3〇2, and the solder material 34 is disposed in the recess 305 of the electrical connection pads 3〇3, and the line region on the dielectric layer 3〇2 An insulating protective layer 31 is disposed to cover the lines 3〇6; the semiconductor wafer 4 has an active surface 4a having a plurality of conductive bumps 41 and corresponding to the solder by the solder material 34. The electrical connection pads 3〇3 of the package substrate 30 and the conductive bumps 41 of the semiconductor wafer 4; and an underfill 42 are disposed on the dielectric layer 3〇2 and the semiconductor wafer 4. between. Referring to FIG. 4D', a surface treatment layer 33 is disposed between the recessed portion 305 of the electrical connection pad 303 and the solder material 34. The surface treatment layer 33 is made of nickel/gold (Ni/Au). One of nickel/palladium/gold (Ni/Pd/Au), silver (Ag) and gold (Au). The package substrate with the electrical connection structure and the semiconductor package structure of the present invention, the upper surface of the electrical connection pad 303 has a recessed portion 3〇5, so that the conductive bump 41 of the semiconductor wafer 4 is butted in the recess In the portion 3〇5, the crucible is used to reduce the height of the package; and the recessed portion 305 of the electrical connection pad 3〇3 has a large contact area with the solder material 34, so as to increase the electrical connection pad 303 and solder. The bonding between the materials 34 is to prevent the solder material 34 from falling off; and the solder material 34 is not higher than the opening 310 of the insulating protective layer 31, so that the solder material 34 is electrically connected to the semiconductor wafer through a reflow process. The conductive bumps 41 of 4 prevent the solder material from overflowing and cause a short circuit, thereby reducing the distance between the electrical connection pads 3〇3 to 110178 17 200926378 to achieve fine pitch and increase output/input (InpUt/〇 utpUt) The purpose of the number of contacts; in addition, the high coplanarity of the solder material is excellent, and the stress distribution of the conventional structure can be eliminated. '俾The bump at the wafer end in the package is reduced from the substrate insulating protective layer. Stress, so this Inventions can increase product reliability. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and alterations to the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A and FIG. 1G are diagrams showing a conventional flip-chip package substrate. FIGS. 2A to 2FU are the second embodiment of the first embodiment of the present invention, and the figure is the second embodiment. Another real #能媒立,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
第2E，圖係為第2E圖的另一每缺能接A 力只施態樣剖視示意圖 第2F，圖係為第2F圖的另一營始拔* 为實施悲樣剖視示意圓； 第3A至3E圖係為本發明之第一每 弟一貝％例之剖視示意 第3C，圖係為第3C圖的另一每价妒接 只知態樣剖視示音阁. 第3D’圖係為第3D圖的另一银 ^ ’ 只方也通樣剖視示音m · 第3E，圖係為第3E圖的另 ^ 丁 μ圖， 咕 另—貫施態樣剖視示音n. 第4Α至4D圖係為本發明之一杏 〜’ 第二只施例之剖視示意 110478 200926378 圖； ' 第4C’圖係為第4C圖的另一實施態樣剖視示意圖； 以及 第4D’圖係為第4D圖的另一實施態樣剖視示意圖。 【主要元件符號說明】 1 封裝基板 1 a 第一表面 lb 第二表面 ❹ 10, 30 基板本體 101，301 内層線路 1ΐ)2, 302 介電層 103, 303 電性連接墊 104, 304 導電盲孔 11, 31 絕緣保護層 110, 310, 310, 開孔 ❹ 12 導電層 13 阻層 130 開口 14 導電材料 14， 導電元件 2,4 半導體晶片 2a, 4a 作用面 21, 41 導電凸塊 23, 42 底部填膠 19 110478 200926378 305 凹陷部 306 線路 33 表面處理層 34 焊接材料 ❹ 20 1104782E, the figure is another 2F of each of the missing energy A force diagrams in Fig. 2E, and the other figure is the 2F of the 2F figure, and the other battalion drawing of the 2F figure is a schematic circle for implementing the sad-like cross-section; 3A to 3E are the first schematic diagrams of the first example of the first embodiment of the present invention. The third embodiment is a cross-sectional view of the third embodiment. 'The figure is another silver of the 3D figure'. The only part is the cross-section of the sound m · 3E, the figure is the other part of the 3E picture, and the other part shows the cross-section The sounds n. 4th to 4D are one of the apricots of the present invention~' section of the second embodiment is 110478 200926378; '4C' is a schematic cross-sectional view of another embodiment of FIG. 4C; And the 4D' diagram is a schematic cross-sectional view of another embodiment of the 4D diagram. [Main component symbol description] 1 Package substrate 1 a First surface lb Second surface ❹ 10, 30 Substrate body 101, 301 Inner layer 1 ΐ) 2, 302 Dielectric layer 103, 303 Electrical connection pad 104, 304 Conductive blind hole 11, 31 insulating protective layer 110, 310, 310, aperture ❹ 12 conductive layer 13 resist layer 130 opening 14 conductive material 14, conductive element 2, 4 semiconductor wafer 2a, 4a active surface 21, 41 conductive bump 23, 42 bottom Filling 19 110478 200926378 305 Depression 306 Line 33 Surface Treatment Layer 34 Welding Material ❹ 20 110478