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TW200834846A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
TW200834846A
TW200834846A TW96147833A TW96147833A TW200834846A TW 200834846 A TW200834846 A TW 200834846A TW 96147833 A TW96147833 A TW 96147833A TW 96147833 A TW96147833 A TW 96147833A TW 200834846 A TW200834846 A TW 200834846A
Authority
TW
Taiwan
Prior art keywords
electrode
semiconductor device
island
semiconductor
connection
Prior art date
Application number
TW96147833A
Other languages
Chinese (zh)
Other versions
TWI376024B (en
Inventor
Naomi Masuda
Original Assignee
Spansion Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc filed Critical Spansion Llc
Publication of TW200834846A publication Critical patent/TW200834846A/en
Application granted granted Critical
Publication of TWI376024B publication Critical patent/TWI376024B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.

Description

V 200834846V 200834846

.V w 九、發明說明： ‘ ^ 【發明所屬之技術領域】 ♦ 本發明係關於半導體裝置以及用於製造該半導體裝置 r 之方法，且尤其是關於用於多個半導體裝置分層（layering) 之半導體裝置以及用於製造該半導體裝置之方法。 【先前技術】 最近，用於可攜式電子裝置例如行動電話以及1C記憶 0 卡（IC memory card)之非揮發性記錄媒體（nonvolatile recording medium)等半導體裝置的小型化之需求已逐漸增 加中。此種趨勢需要一種有效率地封裝半導體晶片之技 術。用於令其上安裝有半導體晶片之封裝件分層之層疊封 裝（package-on_package)製程已發展成為該項技術之其中 一者。VV IX. Description of the Invention: ' ^ Technical Field of the Invention ♦ The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to layering for a plurality of semiconductor devices A semiconductor device and a method for fabricating the same. [Prior Art] Recently, there has been an increasing demand for miniaturization of semiconductor devices such as nonvolatile recording media for portable electronic devices such as mobile phones and 1C memory cards. This trend requires a technique for efficiently packaging semiconductor wafers. A package-on-package process for layering a package on which a semiconductor wafer is mounted has been developed as one of the technologies.

第1A、IB、2A及2B圖之各者皆為剖面圖，顯示該 半導體裝置以及該層疊封裝結構為慣用範例。第1A及1B 春 圖顯示將半導體晶片例如以面朝上（face-up)結構透過打線 接合方式（wire bonding)安裝在線路基板（wiring substrate) 上的例示情況。同時，第2A及2B圖顯示將該半導體晶片 以面朝下（face-down)結構透過成形凸塊（stub bump)安裝在 該線路基板上的例示情況。參照第1A圖，半導體晶片12 係以晶粒黏著材料（die adhesive material) 14安裝在線路基 板10上。該半導體晶片12以及該線路基板10係藉由銲線 23電性躺接。該半導體晶片12係以密封樹脂（sealing resin)16密封。島電極（iand electrode)22係設置在該半導體 5 94109 200834846 Μ -晶片12之側邊上的該線路基板10上。銲球（s〇〗derball)18 \ f經由島電極20設置在遠離該半導體晶片12之侧邊上的 .f線路基板1G上。該島電極22與該銲球18係電性轉接。 第1B圖係顯不令於第1A圖所示之半導體裝置分層之半導 體結構的圖。參照第1B圖，上半導體裝置24之銲球18 係連接至下半導體裝置26之島電極22。以此方式，該上 半導體裝置24係與該下半導體裝置％電性耦接。 ^ ，’、、、第2A圖’該半導體晶片12係使用成形凸塊28 女裝在該線路基板10上。底膠材料（undermi咖如⑹)％ 係填充於該半導體晶片12與該線路基板1〇之間。其他結 冓係”第1A圖所示之結構相同，故將省略其說明。第2B 圖=顯示藉由令第2A圖所示之半導體裝置分層而形成之 半導體結構。分層該些半導體裝置之方法係與帛ib圖所 示之情況相同，故將省略其說明力 ,日本專利申請公開第JP-A-2000-200800號揭露一種技 術j其用於形成具有成形凸塊之通孔柱（via p〇st)於半導體 晶圓（wafer)電極中，該通孔柱係用以連接半導體晶片及銲 =，該銲球作為晶片尺寸封裝件（chip_size_package)中之封 叙端點（packaged terminal)。 於慣用範例1中，該銲球lg係於該半導體裝置分層時 用作為電極，以及例如在該半導體裝置安裝在主機板上時 亦用作為電極。該半導體裝置可藉由縮小該銲球18之電極 間距以縮小尺寸。然而，該銲球18係呈球形或橢圓形，需 要與相鄰電極隔開，以避免於該銲球熔化時造成短路。倘 94109 6 200834846 =該銲球之電極間距縮減過小，則在安裝於主機板上之安 瓜製程中需要高度精密之安裝技術，且因此，於電性檢查 步驟中需要高度精密之檢查夾具(jig)。因&，該銲球之電 極間距必須變寬’這可能不利於該半導體裝置之小型化。 【發明内容】 本發明係有鑑於上述之情形，提供一種半導體裝置以 及詩能夠以較小尺寸製造該半導體裝置之方法，二及更Each of Figs. 1A, IB, 2A, and 2B is a cross-sectional view showing that the semiconductor device and the stacked package structure are conventional examples. Figs. 1A and 1B are diagrams showing an example in which a semiconductor wafer is mounted on a wiring substrate by wire bonding, for example, in a face-up structure. Meanwhile, Figs. 2A and 2B show an exemplary case where the semiconductor wafer is mounted on the wiring substrate through a face-down structure through a stub bump. Referring to Fig. 1A, the semiconductor wafer 12 is mounted on the wiring substrate 10 by a die adhesive material 14. The semiconductor wafer 12 and the wiring substrate 10 are electrically connected by a bonding wire 23. The semiconductor wafer 12 is sealed with a sealing resin 16. An island electrode 22 is disposed on the wiring substrate 10 on the side of the semiconductor 5 94109 200834846 Μ - wafer 12. A solder ball 18 f is disposed on the .f circuit substrate 1G on the side away from the semiconductor wafer 12 via the island electrode 20. The island electrode 22 is electrically coupled to the solder ball 18. Fig. 1B is a view showing a semiconductor structure in which the semiconductor device shown in Fig. 1A is layered. Referring to FIG. 1B, the solder balls 18 of the upper semiconductor device 24 are connected to the island electrodes 22 of the lower semiconductor device 26. In this manner, the upper semiconductor device 24 is electrically coupled to the lower semiconductor device. ^, ',, 2A' The semiconductor wafer 12 is formed on the circuit substrate 10 using the shaped bumps 28. A primer material (undermi coffee (6))% is filled between the semiconductor wafer 12 and the wiring substrate 1A. The other structures are the same as those shown in Fig. 1A, and the description thereof will be omitted. Fig. 2B is a view showing a semiconductor structure formed by layering the semiconductor device shown in Fig. 2A. The method is the same as that shown in the 帛ib diagram, and the description thereof will be omitted. Japanese Patent Application Publication No. JP-A-2000-200800 discloses a technique for forming a through-hole column having shaped bumps ( Via p〇st) in a semiconductor wafer electrode for connecting a semiconductor wafer and soldering = as a packaged terminal in a chip size package (chip_size_package) In Conventional Example 1, the solder ball lg is used as an electrode when the semiconductor device is layered, and is also used as an electrode, for example, when the semiconductor device is mounted on a motherboard. The semiconductor device can be reduced by soldering the solder ball The electrode spacing of 18 is reduced in size. However, the solder ball 18 is spherical or elliptical and needs to be spaced apart from adjacent electrodes to avoid short circuit when the solder ball is melted. If 94109 6 200834846 = the electrode of the solder ball between If the reduction is too small, a highly precise mounting technique is required in the ampoules process mounted on the motherboard, and therefore, a highly precise inspection jig (jig) is required in the electrical inspection step. Because &, the electrode of the solder ball The pitch must be widened. This may be detrimental to the miniaturization of the semiconductor device. SUMMARY OF THE INVENTION The present invention provides a semiconductor device and a method for manufacturing the semiconductor device in a small size in view of the above circumstances, and

進-步縮小藉由堆疊多個半導體裝置所形成之半導體結構 的尺寸以及用於製造該半導體結構之方法。 、—根據本务明之恶樣，提供一種半導體裝置，包含： =體晶片；連接電極，其係由與該半導體晶片電性麵接 弟二島電極，以及形成於該第—島電極之上表面上且使 成形凸塊以便與該第—A電極電性㈣之穿透電極所 成；以及密封樹脂（sealing resin)，用於密封該半導體 片，該連接電極穿透該密封樹脂。根據本發明，該穿透 極係形成如該成形凸塊。這使得能夠減小該連接電極之 極間距，因而減小該半導體裝置之尺寸。 ^上述結構中，設置與該半導體晶片電性_之第· 二二 二島電極係用以外部連接。該連接電極可丨 片：周邊來設置’並可於該半導體晶片之」 兮半結構巾，料分層㈣叫 w裝置之連接電極係圍繞該半導體晶片來配置。』 ::二】=裝在主機板上或電性測試之第二島電極$ 置；該+導體晶片正下方。這使得能夠縮小該連接電本 94109 7 200834846 之間距，同時維持該第二島電極加寬之間距。該半導體裝 置可縮小其尺寸而不會降低封裝至主機㈣電彳生測試之便 利性。 —於上述結構中，該連接電極之上表面可配置為高於該 密封樹脂之上表面。將被分層為半導體結構之上和下半導 體裝置可輕易且穩固地電性耦接。The size of the semiconductor structure formed by stacking a plurality of semiconductor devices and the method for fabricating the semiconductor structure are further reduced. According to the present invention, there is provided a semiconductor device comprising: a body wafer; a connection electrode electrically connected to the semiconductor chip and electrically formed on the surface of the first island electrode Forming a bump to form a penetrating electrode with the (A) electrode of the first electrode; and sealing a resin for sealing the semiconductor chip, the connecting electrode penetrating the sealing resin. According to the invention, the penetrating pole is formed as the shaped bump. This makes it possible to reduce the pole pitch of the connection electrode, thereby reducing the size of the semiconductor device. In the above structure, the second and second island electrodes of the semiconductor wafer are provided for external connection. The connecting electrode can be disposed on the periphery of the semiconductor wafer. The layered (four) connection electrode of the device is disposed around the semiconductor wafer. 』:2】=Second island electrode mounted on the motherboard or electrical test; directly below the + conductor wafer. This makes it possible to reduce the distance between the connected nets 94109 7 200834846 while maintaining the distance between the second island electrodes widening. The semiconductor device can be reduced in size without reducing the convenience of packaging to the host (4) electrical test. - In the above structure, the upper surface of the connection electrode may be disposed higher than the upper surface of the sealing resin. The device will be layered into a semiconductor structure and the lower semiconductor device can be electrically and easily coupled.

上述結構可設有線路層， 包各5亥弟一島電極、該第二島 第一及該第二島電極之線路。 同一平面上。於該等半導體裝 女裝至主機板上之情況下， surface)可確實地組合在一起。 該線路層係由金屬膜形成且 電極、以及用於電性耦接該 該結構容許該線路層設置於 置被分層或該半導體裝置被 個別之接合表面（bonding ;it結構中’形成於彼此相鄰之該第—島電極上之 ΐ、該弟一島電極之縱向方向之不同位置處來配 :構谷㈣連接t極之㈣縮小。這使得能 步縮小該半導體裝置之尺寸。 凸塊==:中，該穿透電極可藉由分層至少二個成形 不合辦力该結構容許該穿透電極之高度增加，而 曰曰以牙^电極之直徑。可增加該穿透電極之高产 裝置之尺寸縮小。於該半導體裝置被分層 之n况下，當增加該連接電極之 半導體裝置可更輕易且翻地電性^接ί層之上和下 表面二?線路層可配置於該半導體晶片之下 ° 脰日日片係經由面朝下之封裝方式配置。 94109 8 200834846 許!半:體晶片及該線路層電性輕接於該半導體 k使侍旎夠縮小該半導體裝置之尺寸。 於上述結構中，可藉由將第 電極接合至第二半導 社體哀置之弟-連接 置及該第二半導體裝置。由於在該連接電極$ 2牙透電極可形成有成形凸塊， 裝置=寸+導體結構。這使得能夠縮小該半導體 導體裝置可更加輕易且穩固地電性耦 電極之二:另一成形凸塊係可敷設於該第-連接 之之該第，電極之下表面之間。將被分層 接。 於=述結構中’該第一及該第二連接電極可藉由熱壓 二:（hermocompression process)或銲錫製程 Process)予以接合。 本發明提供一種用於製造半導體裝置之方法，包 ::丄：性輕接半導體晶片及第一島電極;於該第一島 二，第5形成穿透電極，該穿透電極係使用成形凸 :穿耦接’以便形成包含該第-島電極 半電極；以及形成密封樹月旨，用於密封該 ，脰曰曰片，該連接電極穿透該密封樹月旨。由於 成=成形凸塊’故該連接電極可具有窄的電極間 坆使仔旎夠縮小該半導體裝置之尺寸。 於上述結構中，可執行產生以金屬膜形成之線路層之 94109 9 200834846 •=。錄路層係形成有該第 .電性耦接而用作為冰邺嚙拉 /千令體日日片 > _該第nl :之第二島電極、以及用於電性 '於同-平面卜極之線路°由於該線路層係敷設 ，备該等半導體裝置被分層或該半導體 合在一起。# +表面可確實地組 形成該線路層。 义，、」毕工易地 可為夢由構巾，產生以金屬卿成之線路層之步驟 產生該線路層之步驟。斗士 — u * X孟屬膜而 支撐主體，而變成薄線路^構容許該軟性基板形成為 置之尺寸。 #線路層。這使得能夠縮小該半導體裝 於r:广構中’形成該密封樹脂之步驟可為藉由以用 果衣（m〇ldmg)之薄板（sh⑽）覆蓋該連接電極之上部而用 於形成該密封樹脂之步驟，以使該連接電極之上^:用 :為高於該密封樹脂之上表面。這使得能夠更輕易且‘： 地電性搞接將被分層之上和下半導體襄置。 〜 於上述結構中，電性耦接該半導體晶片與該 + =步驟可包括面朝下封裝該半導體晶片之步驟。該= 脰晶片及該線路層可電性耦接於該半導體晶^ ▲、 縮小該半導體裝置之尺寸。 Θ/1 因而 :亡述結構中’以該成形凸塊形成該穿透電 I包含執行複數次形成成形凸塊之步驟。 = 中’可增加該穿透電極之高度，而不會增加其直= 94109 10 200834846 加該穿透電極之；έ;痒二τ 包子之问度而不妨礙縮小該半 由於該連接電極可作得較高，當：:：。 接。 丰“裝置可更輕易且穩固地電性麵 於上述結構中， ^ 電極接合至第二半導體，ΓΓ+導體裝置之第一連接 凸塊’該半導體農置之分層結構可;;如該成形 小該半導时置之尺寸。構了作*精巧。使得能夠縮 了勺!結構中’接合該第-及該第二連接電極之步驟 可包含形成另一成形凸塊於該第一 ：：之力驟 第二連接電極之下表面的其中一處的牛驟 、面及該 將被分層之第一及节第二车的步驟。於此結構中’ 電性耦接-。 ¥肢衣置可更加輕易且穩固地 勺結構中’接合該第一及第二連接電極之步驟可 包含經由熱或銲_接合的步驟。 【實施方式】 [第一;:：參照隨附圖式描述根據本發明之實施例。 圖。二圖二顯=據广實施例之半導體裝置的剖面 、 圖，使用成形凸塊28將半導體晶片12安裝 二弟二島電極34之上表面之-端處，以透過覆晶連接 ^ P C〇nneCtl〇n)形成面朝下（face-down)之結構。於該 弟一島電極34之上表面之另-端處形成穿透電極(through 94109 11 200834846 eleCtr〇de)42,該第一島電極34係充當為例如以金形成之 ，形凸塊’以便形成連接電極（c〇nnecti〇n el喻邊）44。該 第一島電極34係提供用於形成該穿透電極〇的電極。該 連接電極44係用於電性耦接將被分層之上半導體裴置以 及下半導體裝置。包含該第__島電極34、第二島電極％ 以及用於連接該第-及該第二島電極34 # %之線路％ 之線路層40係從例如銅形成之單一金屬膜所形成，且該線 路層4〇之每個組件係彼此電性耦接。線路層40係設置在 該半導體晶片U之下表面下方，連接電極料係設置在該 =導體晶片12周圍’而第二島電極36係設置在該半導體 =片12正下方。5亥半導體晶片12以及該連接電極料係以 山封树月曰16狯封。該連接電極44穿透該密封樹脂於 • 及該弟一島笔極36之間填充底膠材料 undermi material) 3〇。該第二島電極％係連接至辉球a。 半導：：：弟4八至吒圖描述用於製造根據第-實施例之 ,衣之方法。麥照第4A圖，敷設於軟性基板（tape su strate) 32之金屬膜係被㈣以形成 的該線路層40在該軟性基板32上。該線路層4〇包：呈： 電極34、呈圓形之第二島電極％、以及用於電 i工和5接該弟—及兮结_ ^ 及該木一島-电極之線路38。該軟性基板32 _該線路層4G。該第—島電極34係圍繞該軟性 ^ # π之周^ °又置，且該第二島電極36係設置於該軟性 ^ Μ之中央處°該第—島電極34之電極間距係設定成 而該第二島電極36之電極間距係設定成大 94109 12 200834846 ， 約500 μιη。第4B圖係沿著第4A圖所示之A-A線截取之 • 剖面圖。該線路層40之厚度係設定成大約30 μιη。 _ 第5Α圖係該軟性基板32之俯視圖，該軟性基板32 ^ 具有形成於對應之第一島電極34上的穿透電極42作為成 形凸塊。參照第5 A圖，作為金柱凸塊（gold stud bump)之 穿透電極42係形成於該第一島電極34上。於相鄰之第一 島電極34上之穿透電極42係形成於朝該第一島電極34 0 之縱向方向之不同位置處，以便形成由該穿透電極42與該 第一島電極34所一起形成之連接電極44。第5B圖係沿著 第5 A圖所示之A-A線截取之剖面圖。該穿透電極42之高 度係設定成大約2 3 0 μπι。當該第一島電極3 4之厚度係設 定成大約30 μιη時，該連接電極44之高度係大約260 μιη。 該穿透電極42之直徑係設定成大約1 〇〇 μπι。 第6Α圖係該軟性基板32之俯視圖，在該軟性基板32 上，該半導體晶片12係面朝下透過覆晶連接而以該成形凸 ⑩塊28安裝在該第一島電極34上。第6Β圖係沿著第6Α圖 所示之Α-Α線截取之剖面圖。參照第6Β圖，具有厚度1 50 μπι之半導體晶片12係透過覆晶連接而面朝下安裝在該第 一島電極34之上表面上之一端處，該穿透電極42於該端 處亚未形成有該成形凸塊2 8。該成形凸塊2 8之南度係大 約30 μηι。於該半導體晶片12與該軟性基板32之間係填 充以環氧基樹脂（epoxy resin)形成之底膠材料30。 第7A圖係顯示用於形成該密封樹脂16之模具46係 與該軟性基板32結合之狀態之俯視圖。第7B及7C圖分 13 94109 200834846 -別為/口著第7A圖所示之A_A線截取之剖面圖。參照第7B *圖，用於形成該密封樹脂16之模具46具有凹槽&ecess)， \且具有敷設於底部之薄板（sheet)48。從該模具46之上表面 至忒溥板48之深度約為250 μηι。參照第％圖，該模具 =係裝滿為未固化狀態（職―似⑹之熱隨⑽識㈣〇 環氧，樹脂的密封樹脂16。之後，加熱該模具46，以便於 在該密封樹脂16之融熔狀態下緊靠在該軟性基板％上。 鲁此時’從該模具46之上表面至該薄板48之深度約為25〇 μ ,且該連接電極44之尚度約為260 。該連接電極44 =前端部份（leading end p(miGn)壓人該薄板48以便被覆 :於：薄板48中。這使得能夠以該密封樹脂16密封該半 _ a片12而不會以该德、封樹脂16密封該連接電極44 之前端部份。 ,第8Α圖係於該軟性基板32上形成該密封樹脂16之 鳙後之該軟性基板32之俯視圖。第8Β圖係沿著第8α圖所 不之Α-Α線截取之剖面圖。參照第8β圖，在移除用於形 密封樹脂16之模具46之後，該半導體晶片12及除了 月4为以外之該連接電極44皆以該密封樹脂16密封。 m說’該連接電極44係穿透該密封樹脂16。未以密 对樹$ 岔封之連接電極44的前端部份高度約為忉卩讯。 、第9A圖係顯示於移除該軟性基板32之後，形成該銲 I:8於該第二島電極36上之狀態之俯視圖。第9B圖係 二=第9A圖所不之a_a線截取之剖面圖。參照第9B圖， X鋅球1 8係在移除該軟性基板％之後，形成於外露之第 14 94109 200834846 二島電極36上。該銲球18之直徑 ，產生如第3圖所示之半導體裝置。為。因此，便 根據第一實施例，係如第 、12設置該連接電極料。於慣料圖^圍繞該半導體晶片 晶片12設置銲球18。舉例而言'該銲= 1中可用以令該半導體襄置分層、將該半導體 主機板上、或騎電性賴=女4 連接電極44係僅用於令該 、⑼例中之該 半導體= —衣置为層，而未用於將該 牛^裝置文裝至主機板上，或 要考慮到該連接電極44針 ^ HI不一疋 利性。這使得能夠減小該連+接+電^電之=試之用途的便 該銲球]8更進；成形凸塊形成，相較於 X 3透電極之直徑。兮遠接 «r^：sultan?f^ 慣用r例1 : I據第一貫施例，該半導體裝置相較於 i中之半導體t置可作得更精巧。 兮r=3:，該鮮球18係形成於該第二島電極36上。 該！干球18可仙來安裝至主機板上，且 於設置該銲球18之前可被 一島電極 、目,n L 被用末進仃該半導體裝置之電性 體晶片12正下方形成該銲球18或該第 ，即使增加該銲球18或該第二島電極％ ==距：，半導體裝置之尺寸並不會變大。這使得能 二主言神^械女裳至主機板上及進行該電性測試之便利性 的+ V肢衣置，同時保持該半導體裝置之精巧性。 94109 15 200834846 參照第4A圖，包含該第一島電極％、第二 以及用於連接該第-及該第二島電極34和％之^ 之線路層40,係從具有該軟性基板作為支撐之單一膜j 成。這使得能夠輕易形成該薄線路層4〇，從而進一牛厂 該半導體裝置之尺寸。 ^^小 參照第5A圖，以該成形凸塊形成於相 34上之穿透電極42係設置於朝該第-島電極34之= 置二。這使得能夠更進一步減小該連接電極44 之电極間距，因而使該半導體裝置更加精巧。 [弟二實施例] μ弟广貫施例係令根據第一實施例之半導體裝置分層之 视例。第1G圖係根據第二實施例之分層半導體結: 圖车參照第Η)圖，藉由施加熱M(themGeGmiJs叫^第 裝置t第—連接電極45的上表面與第二半導 粗破置51之弟二連接電極〇的下表面之間，該第一 =置50及該第二半導體裝置51係接合成分 !:球、18係設置於該第一半導體農置上，但未設置於該 ::半¥體裝置51上。於該第一及該第二半導體裝置％ #口 1間敷設黏㈣Kadhesive agent)52用於確保該接合強 又。因此’產生根據第二實施例之分層半導體結構。 …、、第4 A及4B圖’在根據第_實施例之半導體裝置 :’線路層40係藉由崎設於軟性基板32之金屬膜而 I以形成。因此，該線路層40係形成於同-平面上。例如， 虽該半導體裝難分層或料導料置被 94109 16 200834846 精確地結合該線路層4G之接合表面。該線路層肩 1猎由蝕刻該金屬膜而全體地形成，從而容易生產。 體裝置中時’係使賴有薄板48之模呈 …成之半導體裝置具有從該密封樹脂16之上表面稍微 大出的連接電極44之前端部分。該連接電極44之:The above structure may be provided with a circuit layer, which comprises a circuit of each of the 5th island electrodes, the second island first and the second island electrodes. On the same plane. In the case where the semiconductors are mounted on the motherboard, the surfaces can be reliably combined. The circuit layer is formed of a metal film and electrodes, and for electrically coupling the structure allows the circuit layer to be disposed on the layer to be layered or the semiconductor device to be bonded to each other (bonding; The adjacent ridges on the first island electrode and the longitudinal direction of the island electrode are arranged at different positions: the constituting valley (4) is connected to the (4) reduction of the t pole, which enables the size of the semiconductor device to be stepped down. In the ==:, the penetrating electrode can be configured to allow the height of the penetrating electrode to be increased by layering at least two forming dislocations, and the diameter of the electrode can be increased. The size of the high-yield device is reduced. When the semiconductor device is layered, the semiconductor device with the connection electrode can be more easily and galvanically connected to the upper layer and the lower surface. The semiconductor wafer is disposed under the semiconductor wafer by a face-down package. 94109 8 200834846 A half: the body wafer and the circuit layer are electrically connected to the semiconductor k to make the semiconductor device shrink. The size of In the configuration, the second semiconductor device can be connected to the second semiconductor device by bonding the first electrode to the second semiconductor body. Since the connecting electrode can form a shaped bump at the connecting electrode, the device can be formed. Inch + conductor structure. This makes it possible to reduce the semiconductor conductor device by two more easily and stably electrically coupled electrodes: another forming bump can be applied between the first and the lower surface of the electrode The first and the second connection electrodes may be joined by a hermocompression process or a solder process. The present invention provides a method for fabricating a semiconductor device, comprising: germanium: a lightly connected semiconductor wafer and a first island electrode; on the first island 2, a fifth forming a through electrode, the through electrode using a shaped convex : a coupling is coupled to form the first electrode comprising the first island electrode; and a sealing tree is formed for sealing the cymbal, the connecting electrode penetrating the sealing tree. The connection electrode can have a narrow inter-electrode spacing due to the formation of the shaped bumps, so that the size of the semiconductor device can be reduced. In the above structure, it is possible to produce a wiring layer formed of a metal film. 94109 9 200834846 •=. The recording layer is formed with the first electrical coupling and used as a hail joint/thousand body day piece> _ the nl: second island electrode, and for electrical 'in the same plane The wiring of the poles is due to the laying of the wiring layers, and the semiconductor devices are layered or the semiconductors are brought together. The #+ surface can be surely grouped to form the circuit layer. Righteousness, "Complete work can be the step of creating a circuit layer by the step of constructing a circuit layer with a metal layer." The fighter - u * X is a film that supports the main body, and becomes a thin circuit structure to allow the flexible substrate to be formed into a size. #线路层. This makes it possible to reduce the semiconductor package in the r: wide structure. The step of forming the sealing resin can be used to form the seal by covering the upper portion of the connection electrode with a thin plate (sh(10)) of a fruit coat (m(ld)). The step of the resin is such that the connecting electrode is higher than the upper surface of the sealing resin. This makes it easier and ‘: the geoelectric connection will be layered above and below the semiconductor. In the above structure, electrically coupling the semiconductor wafer and the += step may include the step of packaging the semiconductor wafer face down. The 脰 wafer and the circuit layer are electrically coupled to the semiconductor wafer to reduce the size of the semiconductor device. Θ/1 Thus: The formation of the penetrating power by the shaped bumps in the structure of the structure includes the step of performing a plurality of times to form the shaped bumps. = in 'can increase the height of the penetrating electrode without increasing its straightness = 94109 10 200834846 plus the penetrating electrode; έ; itching two τ buns can not be prevented from shrinking the half due to the connecting electrode can be made Got higher when:::. Pick up. The device can be more easily and stably electrically connected to the above structure, ^ the electrode is bonded to the second semiconductor, and the first connection bump of the germanium + conductor device can be formed; The size of the semi-conducting is small. It is made compact* to enable the scooping! The step of 'joining the first-and the second connecting electrode in the structure may include forming another forming bump on the first:: The step of the second connecting electrode on one of the lower surface of the electrode, the face and the first and second car to be layered. In this structure, 'electrically coupled -. The step of bonding the first and second connection electrodes in a more easily and stable scoop structure may include a step of bonding via heat or soldering. [Embodiment] [First;:: Reference is made with reference to the accompanying drawings Embodiments of the present invention. Fig. 2 is a cross-sectional view of a semiconductor device according to a general embodiment, using a forming bump 28 to mount a semiconductor wafer 12 at the end of the upper surface of the second electrode of the second electrode, Through the flip chip connection ^ PC〇nneCtl〇n) form face down (face-d The structure of the own. A through electrode (through 94109 11 200834846 eleCtr〇de) 42 is formed at the other end of the upper surface of the island electrode 34, and the first island electrode 34 serves as, for example, gold. a bump "to form a connection electrode 44. The first island electrode 34 provides an electrode for forming the through electrode 。. The connection electrode 44 is used for electrical coupling. The upper semiconductor device and the lower semiconductor device to be layered include the first __ island electrode 34, the second island electrode %, and a circuit layer for connecting the first and second island electrodes 34% of the line % The 40 series is formed from a single metal film formed of, for example, copper, and each component of the wiring layer 4 is electrically coupled to each other. The wiring layer 40 is disposed under the lower surface of the semiconductor wafer U, and the connection electrode system is disposed. The second island electrode 36 is disposed just below the semiconductor=sheet 12. The 5th semiconductor wafer 12 and the connection electrode material are sealed by a mountain seal. The connection electrode 44 Penetrating the sealing resin between the • and the island’s pen 36 The underlying material is 3 〇. The second island electrode % is connected to the globule a. Semi-conducting::: 弟4 八至吒图 The method for manufacturing the garment according to the first embodiment. 4A, the metal film laid on the flexible substrate (tape su strate) 32 is formed on the flexible substrate 32 by the fourth layer formed on the flexible substrate 32. The wiring layer 4 is: the electrode 34 is circular The second island electrode %, and the line 38 for the electric and the connection of the —- and the 兮 junction_^ and the wood-island-electrode. The flexible substrate 32_ the circuit layer 4G. The first island electrode The 34 series is disposed around the circumference of the soft ^ π , and the second island electrode 36 is disposed at the center of the soft ° , and the electrode spacing of the first island electrode 34 is set to the second island. The electrode spacing of the electrode 36 is set to be 94109 12 200834846, which is about 500 μm. Figure 4B is a cross-sectional view taken along line A-A shown in Figure 4A. The thickness of the wiring layer 40 is set to be about 30 μm. The fifth substrate is a plan view of the flexible substrate 32 having a through electrode 42 formed on the corresponding first island electrode 34 as a shaped bump. Referring to Fig. 5A, a penetration electrode 42 as a gold stud bump is formed on the first island electrode 34. The penetrating electrode 42 on the adjacent first island electrode 34 is formed at a different position in the longitudinal direction of the first island electrode 34 0 so as to be formed by the penetrating electrode 42 and the first island electrode 34 The connection electrode 44 is formed together. Fig. 5B is a cross-sectional view taken along line A-A shown in Fig. 5A. The height of the penetration electrode 42 is set to be about 2 3 0 μπι. When the thickness of the first island electrode 34 is set to about 30 μm, the height of the connection electrode 44 is about 260 μm. The diameter of the penetration electrode 42 is set to be about 1 〇〇 μπι. Fig. 6 is a plan view of the flexible substrate 32. The semiconductor wafer 12 is mounted on the first island electrode 34 with the formed bumps 28 facing downward through the flip chip connection. Figure 6 is a cross-sectional view taken along the Α-Α line shown in Figure 6. Referring to FIG. 6 , a semiconductor wafer 12 having a thickness of 150 μm is mounted on one surface of the upper surface of the first island electrode 34 through a flip chip connection, and the through electrode 42 is at the end. The shaped bumps 28 are formed. The south of the shaped bumps 28 is about 30 μηι. A primer material 30 formed of an epoxy resin is filled between the semiconductor wafer 12 and the flexible substrate 32. Fig. 7A is a plan view showing a state in which the mold 46 for forming the sealing resin 16 is bonded to the flexible substrate 32. Figures 7B and 7C are divided into 13 94109 200834846 - Do not give a cross-sectional view of the A_A line shown in Figure 7A. Referring to Fig. 7B*, the mold 46 for forming the sealing resin 16 has a groove & es, and has a sheet 48 attached to the bottom. The depth from the upper surface of the mold 46 to the raft 48 is about 250 μm. Referring to the % map, the mold = is filled with the uncured state (the heat of the job (6) is followed by (10) ( (4) 〇 epoxy, resin sealing resin 16. Thereafter, the mold 46 is heated to facilitate the sealing resin 16 In the molten state, it abuts on the flexible substrate %. At this time, the depth from the upper surface of the mold 46 to the thin plate 48 is about 25 〇μ, and the connection electrode 44 has a scent of about 260. The connecting electrode 44 = leading end p (miGn) presses the thin plate 48 to be coated: in the thin plate 48. This makes it possible to seal the half-sheet 12 with the sealing resin 16 without The sealing resin 16 seals the front end portion of the connecting electrode 44. The eighth drawing is a plan view of the flexible substrate 32 after the sealing resin 16 is formed on the flexible substrate 32. The eighth drawing is along the 8th figure. A cross-sectional view of the Α-Α line interception. Referring to the 8th figure, after the mold 46 for the shape sealing resin 16 is removed, the semiconductor wafer 12 and the connection electrode 44 other than the month 4 are the sealing resin. 16 is sealed. m says 'the connecting electrode 44 penetrates the sealing resin 16. Not in the dense tree $ The height of the front end portion of the connection electrode 44 is about the same. The figure 9A shows the top view of the state of the solder I: 8 on the second island electrode 36 after the flexible substrate 32 is removed. Fig. 9B is a cross-sectional view taken at line a of Fig. 9A, which is taken from line ab of Fig. 9A. Referring to Fig. 9B, X zinc ball 18 is formed on the exposed island 14 after removing the soft substrate %. On the electrode 36, the diameter of the solder ball 18 produces a semiconductor device as shown in Fig. 3. Therefore, according to the first embodiment, the connecting electrode material is set as in the 12th. The semiconductor wafer wafer 12 is provided with solder balls 18. For example, the soldering = 1 can be used to layer the semiconductor, and the semiconductor main board or the electric riding board 4 female electrode 44 can be used only. In the case of (9), the semiconductor is placed in a layer, and is not used to mount the device to the motherboard, or it is considered that the connection electrode 44 is not advantageous. It is possible to reduce the connection of the connection + the connection + the electric power = the solder ball] 8 is further advanced; the forming bump formation Compared with the diameter of the X 3 through electrode. 兮 接 « «r^:sultan?f^ Conventional r Example 1: I According to the first embodiment, the semiconductor device can be made more than the semiconductor t in i兮r=3: The fresh ball 18 is formed on the second island electrode 36. The dry ball 18 can be mounted on the motherboard and can be used as an island electrode before the solder ball 18 is disposed. , the target, n L is formed into the semiconductor device 12 directly under the electrical body wafer 12 to form the solder ball 18 or the first, even if the solder ball 18 or the second island electrode % == distance: semiconductor device The size does not get bigger. This enables the two-speaker to be mounted on the motherboard and the convenience of the electrical test + V limbs while maintaining the compactness of the semiconductor device. 94109 15 200834846 Referring to FIG. 4A, the first island electrode %, the second, and the wiring layer 40 for connecting the first and the second island electrodes 34 and % are provided with the flexible substrate as a support. A single film is formed. This makes it possible to easily form the thin wiring layer 4, thereby entering the size of the semiconductor device. ^^小 Referring to Fig. 5A, the penetration electrode 42 formed on the phase 34 by the shaped bump is disposed to be opposite to the first island electrode 34. This makes it possible to further reduce the electrode pitch of the connection electrode 44, thereby making the semiconductor device more compact. [Embodiment 2] The embodiment of the semiconductor device according to the first embodiment is exemplified by the stratification of the semiconductor device according to the first embodiment. 1G is a layered semiconductor junction according to the second embodiment: Fig. 参照), by applying heat M (themGeGmiJs is called the first device t-connecting electrode 45, the upper surface and the second semiconductor are coarsely broken The first = 50 and the second semiconductor device 51 are connected to each other between the lower surface of the second electrode assembly 51. The ball and the 18 system are disposed on the first semiconductor farm, but are not disposed on the first semiconductor farm. The :: half body device 51. A sticky (four) Kadhesive agent 52 is placed between the first and the second semiconductor device % port 1 to ensure that the bonding is strong. Thus, the layered semiconductor structure according to the second embodiment is produced. In the semiconductor device according to the first embodiment, the wiring layer 40 is formed by a metal film provided on the flexible substrate 32. Therefore, the wiring layer 40 is formed on the same plane. For example, although the semiconductor package is difficult to laminate or the material guide is placed 94109 16 200834846 to precisely bond the bonding surface of the wiring layer 4G. The line layer shoulder 1 is formed by etching the metal film as a whole, so that it is easy to produce. In the body device, the semiconductor device in which the thin plate 48 is molded has a front end portion of the connection electrode 44 which is slightly larger from the upper surface of the sealing resin 16. The connection electrode 44 is:

=於在慣用範例！中用於連接該上和該下半導體裝置二 二之銲球18的突出量。這使得能夠避免該分層半導體 二^尺寸增加’因而達到精巧的分層半導體結構。於該 弟二貫施例中，該第—及該第二半導體裝置％和 :接合該第一及該第二連接電極45和47而被分層： 传月匕夠幸里易且穩固地執行於該第一及該第二I導體裝置 5〇和51間之電性耦接。 衣 /於根據第-實施例之半導體裝置中，該第二島電極％ k用於進彳了該半導體裝置之電性賴。這使得能夠在半 體裂置被分層以形成分層半導體ϋ進行個別半導體 ϋ之電性測試。當能夠在被分層之前先在個 置中識別出不良產品時，可改善產率，且可避免浪費人;; 由於該成形凸塊係用於分層該等半導體裝置，故可採 用覆晶連接技術，從而輕易完成分層。 [第三實施例] 第-貝施例係根據第_實施例之分層半導體裝置之範 例第11圖係根據第三實施例之分層半導體結構之剖面 圖。參照第11圖’成形凸塊54係設置於該第一半導體裝 94109 17 200834846 ^連接電極45的上表面上，使得該第一連接電 :、秀二大星出I增加。該第一及該第二半導體裝置50和51 、’、、=…、有該第一半導體裝置5〇之增加突出量之第一 連接私極45的上表面與該第二半導體裝置之第二連 電^，的下表面之間之熱壓接合⑽a·。⑽⑽ mg而被分層。該銲球18係設置於該第一半導體裝置 > ^ ’而未設置於該第二半導體裝置51上。於該第·"及 =弟-半導體裝置5〇和51間敷設黏著劑52用於確保該接 口強度/因此，產生根據第三實施例之分層半導體結構。 於該第三實施例中，由於成形凸塊54係 „50之第一連接電極45之上表面上，故= 犬出里增加。這使得能夠相較於該第二實施例而更可_ 且制地，性耦接該第-及該第二半導體裝置50和二 第三實施例顯示成形凸塊54係設置於該第— 裝置50之第—連接電極45之上表面上之結構。該成形凸 塊54可設置於該第二半導體裝置51之第二連接電極47 之下表面上，以提供與該第三實施例所達到者相 [弟四實施例] 第四貝轭例係根據第一實施例之分層半導體裝置之〜 例。第12圖係顯示根據第四實施例之分層半導體釺構> = 面圖。參照第12圖’該第一半導體裝置50之第'二連 極45之上表面係與該第二半導體裝置51之 47之下表面以銲料（s〇lder) 56接合，該銲料係共曰曰 料（eutectic solder)或無鉛（iead free)銲料，使得該第二二= 94109 18 200834846 弟二半導體裝置5 0和51被分層。該銲球1 8係設置於該第 一半導體裝置50上，而不設置於該第二半導體裝置51上。 於該第一及該第二半導體裝置50和51間敷設黏著劑52 用於確保該接合強度。因此，產生根據第四實施例之分層 半導體結構。 於5亥弟四實施例中，該第一及該第二半導體裝置$ 〇 和51係使用銲料56而被分層，以便於提供比透過熱壓接 •合而分層之該第一及該第二半導體裝置50和51之第二及 弟二貫施例較強之接合力。 [第五實施例]= In the usual example! The amount of protrusion for connecting the solder balls 18 of the upper and lower semiconductor devices. This makes it possible to avoid an increase in the size of the layered semiconductor and thus achieve a fine layered semiconductor structure. In the second embodiment of the second embodiment, the first and the second semiconductor device % and: the first and the second connection electrodes 45 and 47 are bonded and layered: the moon is easy to execute and is firmly executed Electrical coupling between the first and second I conductor devices 5A and 51. In the semiconductor device according to the first embodiment, the second island electrode %k is used to enter the electrical device of the semiconductor device. This enables electrical testing of individual semiconductors to be performed in a half-body split to be layered to form a layered semiconductor. When the defective product can be identified in the first place before being layered, the yield can be improved, and wastefulness can be avoided; since the shaped bump is used for layering the semiconductor devices, flip chip can be used Connection technology makes layering easy. [Third Embodiment] The first embodiment of the layered semiconductor device according to the first embodiment is a sectional view of the layered semiconductor structure according to the third embodiment. Referring to Fig. 11, a forming bump 54 is disposed on the upper surface of the first semiconductor package 94109 17 200834846 ^ connecting electrode 45 such that the first connection is increased. The first and second semiconductor devices 50 and 51, ',, ......, the upper surface of the first connection private pole 45 having the increased amount of protrusion of the first semiconductor device 5 and the second surface of the second semiconductor device The thermocompression bonding (10)a· between the lower surfaces of the electric wires. (10) (10) mg and stratified. The solder ball 18 is disposed on the first semiconductor device > ^ ' and is not disposed on the second semiconductor device 51. An adhesive 52 is applied between the "" and the semiconductor device 5A and 51 for ensuring the strength of the interface/and thus, the layered semiconductor structure according to the third embodiment is produced. In the third embodiment, since the forming projections 54 are on the upper surface of the first connecting electrode 45 of the 50, the dog is increased. This makes it possible to compare with the second embodiment. The first and second semiconductor devices 50 and the second embodiment show that the forming bumps 54 are disposed on the upper surface of the first connecting electrode 45 of the first device 50. a bump 54 may be disposed on a lower surface of the second connection electrode 47 of the second semiconductor device 51 to provide a fourth embodiment of the fourth embodiment. Example of the layered semiconductor device of the embodiment. Fig. 12 is a view showing a layered semiconductor structure according to the fourth embodiment. Fig. 12 is a view showing the second electrode of the first semiconductor device 50. The upper surface of 45 is bonded to the lower surface of 47 of the second semiconductor device 51 by solder 56, which is a eutectic solder or a lead-free solder, such that the second Two = 94109 18 200834846 The second semiconductor device 50 and 51 are layered. The solder ball is 18 The first semiconductor device 50 is not disposed on the second semiconductor device 51. An adhesive 52 is disposed between the first and the second semiconductor devices 50 and 51 for ensuring the bonding strength. The layered semiconductor structure of the fourth embodiment. In the embodiment of the fifth embodiment, the first and the second semiconductor devices $ 〇 and 51 are layered using solder 56 to provide a more than hot through crimping. The second and second embodiments of the first and second semiconductor devices 50 and 51 are combined to form a stronger bonding force. [Fifth Embodiment]

第五實施例係帶著具有二個或更多個成形凸塊分層之 連接電極之半導體裝置之範例。第13圖係顯示根據第I實 施例之半導體裝置之剖面圖。參照第13圖，係執行複數次 成成开^凸塊之製転，以形成具有分層之該穿透電極42 ==一島電極34之上表面上之連接電極44。其餘任何 々口構I如同第3圖所示，且因而省略其說明。 可根據用於該成形凸塊之金線（g〇ld w ==穿透電極42之高度，若增加該金線之厚度3 f牙透電極42之高度，則該穿透電極42之直徑係亦增 執行複 _有足夠高二程 極42之直徑。這使得能夠形成具有足 94109 19 200834846 44同b寸將該連接電極料帝 根據第一者浐η 电° 4距維持為窄的。相較於 Λ轭例之分層半導體裝置，根據,Μ 分層半導體結構容許於該上和下半導:== 接更為簡易且穩固。彳下仏裝置之間之電性搞 導體裝置5。四例中’較佳者為於接合該第-半 — 弟一連接電極45與該第二半導體裝置51The fifth embodiment is an example of a semiconductor device having a connection electrode having two or more shaped bump layers. Figure 13 is a cross-sectional view showing the semiconductor device according to the first embodiment. Referring to Fig. 13, a plurality of formations of the bumps are formed to form the connection electrodes 44 on the upper surface of the penetration electrode 42 == an island electrode 34 having a layer. The rest of the mouthpiece I is as shown in Fig. 3, and thus the description thereof is omitted. According to the gold wire used for the shaped bump (g〇ld w == the height of the penetrating electrode 42, if the height of the gold wire 3f is increased, the diameter of the penetrating electrode 42 is Also increasing the implementation of the complex _ has a diameter of sufficiently high two-way pole 42. This enables the formation of a foot 94109 19 200834846 44 with the b-inch to maintain the connection electrode material according to the first one 浐 电 4 ° distance is narrower. In the layered semiconductor device of the yoke example, according to the 分层 layered semiconductor structure, the upper and lower semiconductors are allowed to be: the == connection is simpler and more stable. The electrical device between the squatting devices is electrically conductive. In the example, 'the preferred one is to join the first-half-the other-connecting electrode 45 and the second semiconductor device 51.

接電極47之前，先敷設該黏著劑52，以便於固 一 § =背丨52之敷设狀態。同樣地，較佳者為於接合該第 於及Ϊ弟t連接電極45和47之製程後，形成該銲球18 ^ b第半導體裝置5〇上，以便於簡化接合該第一半導體 裝置5〇之第一連接電極45與第二半導體装置51之第二連 接電極47之製程，且防止於不良半導體裝置上形成銲球 於該第二至第四實施例中，係描述根據該第一實施例 之半；體裝置如何被分層之範例。當根據該第五實施例之 半導體裝置如該第二至第四實施例被分層時，可獲得自該 等實施例所衍生之相同功效。 該第二至第四實施例係顯示透過熱壓接合或使用銲料 來刀層该等半導體裝置之範例。然而，並不限於這些方法， 亦可採用使用超音波等等之方法。 由於已針對較佳實施例來作描述，應了解到本發明並 不限於上述實施例，而可於本發明之範疇内加以修改與變 更。 【圖式簡單說明】 20 94109 200834846 • 弟1 A圖係根據習知範例1之半導體裝置的剖面圖(範 •例 1); / 第1B圖係第1A圖之半導體裝置於層疊封裝分層狀態 • (in the package-on-package layered state)之咅丨J 面圖； 第2A圖係根據習知範例1之半導體裝置的剖面圖（範 例2); 笫2B圖係弟2A圖之半導體裝置於層疊封裝分層狀態 之剖面圖， 第3圖係顯示根據第一實施例之半導體裝置的剖面 圖； 第4A圖係顯示製造根據第一實施例之半導體裝置之 製程的俯視圖（範例1); 第4B圖係沿著第4A圖所示之A-A線截取之剖面圖； 第5A圖係顯示製造根據第一實施例之半導體裝置之 製程的俯視圖（範例2); _ 第5B圖係沿著第5A圖所示之A-A線截取之剖面圖； 第6A圖係顯示製造根據第一實施例之半導體裝置之 製程的俯視圖（範例3); 弟6B圖係沿著第6A圖所示之A-A線截取之剖面圖·， 第7A圖係顯示製造根據第一實施例之半導體裝置之 製程的俯視圖（範例4); 第7B及7C圖係沿著第7A圖所示之A-A線截取之剖 面圖； 第8A圖係顯示製造根據第一實施例之半導體裝置之 21 94109 200834846 弟9A圖係顯示製造根據弟 製程的俯視圖（範例6); 第9B圖係沿著第9A圖所系Prior to the electrode 47, the adhesive 52 is applied to facilitate the laying of the § = backing 52. Similarly, it is preferable to form the solder ball 18^b on the semiconductor device 5 after the bonding process of the bonding electrodes 45 and 47 is performed to facilitate the bonding of the first semiconductor device 5〇. a process of the first connection electrode 45 and the second connection electrode 47 of the second semiconductor device 51, and preventing solder balls from being formed on the defective semiconductor device in the second to fourth embodiments, according to the first embodiment Half; an example of how a device is layered. When the semiconductor device according to the fifth embodiment is layered as in the second to fourth embodiments, the same effects derived from the embodiments can be obtained. The second to fourth embodiments show examples in which the semiconductor devices are bladed by thermocompression bonding or using solder. However, it is not limited to these methods, and methods using ultrasonic waves or the like may also be employed. Since the description has been made with respect to the preferred embodiments, it is understood that the invention is not limited to the embodiments described above, but may be modified and changed within the scope of the invention. [Simple description of the drawing] 20 94109 200834846 • Brother 1 A is a cross-sectional view of a semiconductor device according to the conventional example 1 (fan 1); / 1B is a semiconductor device in a stacked package • (in the package-on-package layered state) 咅丨 J plan; 2A is a cross-sectional view of the semiconductor device according to the conventional example 1 (example 2); 笫 2B is the semiconductor device of the 2A figure FIG. 3 is a cross-sectional view showing a semiconductor device according to the first embodiment; FIG. 4A is a plan view showing a process of manufacturing the semiconductor device according to the first embodiment (Example 1); 4B is a cross-sectional view taken along line AA shown in FIG. 4A; FIG. 5A is a plan view showing a process of manufacturing the semiconductor device according to the first embodiment (example 2); _ 5B is along the 5th FIG. 6A is a cross-sectional view taken along line AA of FIG. 6A; FIG. 6A is a plan view showing a process of manufacturing the semiconductor device according to the first embodiment (Example 3); FIG. 6B is taken along line AA shown in FIG. 6A. Sectional view ·, Figure 7A shows the manufacturing according to the A top view of a process of the semiconductor device of the embodiment (Example 4); FIGS. 7B and 7C are cross-sectional views taken along line AA shown in FIG. 7A; and FIG. 8A shows a semiconductor device manufactured according to the first embodiment. 21 94109 200834846 Brother 9A shows the top view of the manufacturing process (Example 6); Figure 9B shows the structure along the 9A

製程的俯視圖（範例5); 第8B圖係沿著第8A圖 1 〇圖係顯示根據第 戶斤系之A-A線截取之剖面圖； /實施例之半導體裝置之 之A-A線截取之剖面圖； 二實施例之分層半導體結構之 剖面圖； _ 第11圖係顯示根據第三實施例之分層半導體結構之 剖面圖； 第12圖係顯示根據第四實施例之分層半導體結構之 剖面圖；以及 第13圖係顯示根據第五實施例之半導體裝置之剖面 圖。 祝明】- 12 16 20, 2 24 裝置 28 32、 極 36 40 44 電極 46 【主 要元件符號 10 線路基板 14 黏著材料 18 鲜球 23 銲線 26 下半導體 30 底膠材料 34 第一島電 38 線路 42 穿透電極 45 第一連接 半導體晶片 密封樹脂 島電極 上半導體裝置 成形凸塊 軟性基板 弟—島電極 線路層 連接電極 模具 94109 22 200834846 47 第二連接電極 48 薄板 50 第一半導體裝置 51 第二半導體裝置 52 黏著劑 54 成形凸塊 56 銲料 23 94109A top view of the process (Example 5); Fig. 8B is a cross-sectional view taken along line AA of the first family line along line 8A of Fig. 8; a cross-sectional view taken along line AA of the semiconductor device of the embodiment; A cross-sectional view of a layered semiconductor structure according to a second embodiment; FIG. 11 is a cross-sectional view showing a layered semiconductor structure according to a third embodiment; and FIG. 12 is a cross-sectional view showing a layered semiconductor structure according to a fourth embodiment. And FIG. 13 is a cross-sectional view showing the semiconductor device according to the fifth embodiment.祝明】- 12 16 20, 2 24 Device 28 32, Pole 36 40 44 Electrode 46 [Main component symbol 10 Circuit board 14 Adhesive material 18 Fresh ball 23 Bonding wire 26 Lower semiconductor 30 Primer material 34 First island electricity 38 Line 42 penetrating electrode 45 first connecting semiconductor wafer sealing resin island electrode semiconductor device forming bump soft substrate brother-island electrode layer connecting electrode mold 94109 22 200834846 47 second connecting electrode 48 thin plate 50 first semiconductor device 51 second semiconductor Device 52 Adhesive 54 Forming Bumps 56 Solder 23 94109

Claims (1)

200834846 十、申請專利範圍·· 1· 一種半導體裝置，包括： 半導體晶片； 連接電極，包含與該半導體晶片電性耦接之第一島 電極，以及形成於該第—島電極之上表面上且使用成ς 凸塊與該第一島電極電性耦接之穿透電極；以及 密封樹脂’用於密封該半導體晶片，該連接電200834846 X. Patent Application Scope 1. A semiconductor device comprising: a semiconductor wafer; a connection electrode comprising a first island electrode electrically coupled to the semiconductor wafer, and being formed on an upper surface of the first island electrode and a through electrode electrically coupled to the first island electrode by a bump; and a sealing resin 'for sealing the semiconductor wafer, the connection 透該密封樹脂。 2. 如申請專利範_ i項之半導體裝置 括 f晶片電㈣接之第二島電極，該第二島電極係用^ ^連接’其巾’該連接電極係圍繞該半導體晶片之周邊 設置，且該第二島電極係設置於該半導體晶片之正下方 3. 如申請專利範圍第丨項之半導體裝置，其中，該連接電 極之上表面係配置為高於該密封樹脂之上表面。 (請專利範圍第！項之半導體裝置，復包括由金屬膜 &gt;成之線路層’且該線路層包含該第_島電極、該第二 =電極以及用於電性搞接該第一及該第二島電極之： 丨項之半導體裝置’其中，於彼此相 島； 電極上所形成之該穿透電極係朝該第- &quot;电極之縱向方向之不同位置處配置。 6. 如申請專利範圍第i項之半導體裝置， 極係藉由分層至，丨、__ 儿 ，、中5亥牙透龟 ^夕一個成形凸塊予以形成。 7. 如申凊專利範圍第1 牛V妝衣置，其中，該線路層 94109 24 200834846 ， 絲置在該半導體晶片之下表面下方，該半導體晶片係 ^ 藉由面朝下的封裝方式配置。 ' 8. 一種分層半導體結構，其中，係如申請專利範圍第1項 之忒半導體裝置的第一半導體裝置以及係如申請專利 範圍第1項之該半導體裝置的第二半導體裝置係藉由將 乂第半導體裝置之第一連接電極接合至該第二半導 體裝置之第二連接電極而被分層。 • 9.如申請專利範圍第8項之分層半導體結構，其中，另一 成形凸塊係形成於該第一連接電極之上表面盥該第二 連接電極之下表面之間。 ^ 10·如申請專利範圍第8項之分層半導體結構，其中，係透 過熱壓或銲錫將該第一及該第二連接電極予以接合。 11.-種用於製造半導體裝置之方法，包括下列步驟： 電性耦接半導體晶片與第一·島電極； =該第島私極之上表面上，形成使利用成形凸塊 與該第-島電極電性耦接之穿透電極，以形成包含該第 一島電極及該穿透電極之連接電極；以及 形成密封樹脂，用於密封該半導體晶片，該連接電 極穿透該密封樹脂。 ι2·如申請專利範圍第u項之方法，復包括製造由金屬膜 所形成之線路層的步驟，該線路層包含該第—島電極、 二η亥半‘脰日日片電性|馬接且用於外部連接之該第二島 電極、以及用於電性耦接該第一及該第二島電極:線 路〇 94109 25 200834846 利範圍第12項之方法，其中，產生由該金屬 、：所=該線路層之步驟係藉由钕刻敷設於軟性基 ' 反之孟屬膜而產生該線路層之步驟。 14.如申請專利範圍第u 脂之牛驟P丄 項之方法，其中，形成該密封樹 :^ 2猎由以用於模製（mGiding)之 * 二連接電極之上部而用於形成該密封樹脂以使該連 = 表面係形成為高於該密封樹脂之上表面之 15‘如申請專利範圍第u項之方法 導髀曰Η命4外 电注耦接该半 曰片與該弟-島電極之步驟包含 導體晶片之步驟。 钌衣該丰 11項之方法’其中，形成有該成形 該成形之步驟包含形成將被執行複數次之 種用於製造分層半導體結構之方法 專利笳11筮1 # ^如对你如甲睛 -連接電柽接广該半導體裝置之第一半導體裝置的第 裝置之第25至係如巾請專利範圍第1項之該半導體 &quot; 一¥體裝置的第二連接電極的步驟。 8 ·如申睛專利範圍裳 該第二連接C之方法，其中，接合該第-及 面及該第==於該第一連接電極之上表 形凸塊的步驟下表面之其中一處形成另一成 19 ·如申請專利筋_ 第-漣項之方法’其中，接合該第-及該 弟一連接電極之步驟包含透過熱愿或銲錫接合的步驟 94109 26The sealing resin is passed through. 2. The semiconductor device as claimed in the patent specification, wherein the second island electrode is connected to the second island electrode, and the second island electrode is connected to the periphery of the semiconductor wafer by using a connection. The second island electrode is disposed directly under the semiconductor wafer. The semiconductor device according to the above aspect of the invention, wherein the upper surface of the connection electrode is disposed higher than the upper surface of the sealing resin. (Please select the semiconductor device of the scope of the patent item, the circuit layer comprising the metal film &gt; and the circuit layer includes the first island electrode, the second electrode, and the electrical connection The second island electrode: the semiconductor device of the item [wherein the islands are mutually islanded; the through electrode formed on the electrode is disposed at different positions in the longitudinal direction of the first &quot;electrode. In the semiconductor device of the scope of the patent item i, the poles are formed by layering to 丨, __ 儿, zhongzhong hai fangs, and a shaped bump. 7. If the application is patented, the first cow V makeup a wiring layer, wherein the wiring layer is 94109 24 200834846, the wire is disposed under the lower surface of the semiconductor wafer, and the semiconductor wafer is configured by a face-down package. ' 8. A layered semiconductor structure, wherein The first semiconductor device of the semiconductor device of claim 1 and the second semiconductor device of the semiconductor device of claim 1 is connected by the first connection electrode of the semiconductor device The layered semiconductor structure of claim 8, wherein another shaped bump is formed on the upper surface of the first connection electrode. The layered semiconductor structure of the eighth aspect of the invention, wherein the first and the second connection electrodes are joined by heat pressing or soldering. - a method for fabricating a semiconductor device, comprising the steps of: electrically coupling a semiconductor wafer to a first island electrode; = forming an upper surface of the first island of the private island to form a shaped bump and the first island The electrode is electrically coupled to the penetrating electrode to form a connecting electrode including the first island electrode and the penetrating electrode; and a sealing resin is formed for sealing the semiconductor wafer, the connecting electrode penetrating the sealing resin. The method of claim 5, further comprising the step of manufacturing a circuit layer formed of a metal film, the circuit layer comprising the first island electrode, the second 亥 半 脰 脰 脰 日 片 片 电 且 且 且to The second island electrode of the external connection, and the method for electrically coupling the first and the second island electrode: the circuit 〇94109 25 200834846, the method of claim 12, wherein: The step of the circuit layer is a step of producing the circuit layer by engraving on a soft base, and vice versa. 14. The method of claim 5, wherein the sealing tree is formed : ^ 2 hunting for the molding of (mGiding) * the upper part of the connection electrode for forming the sealing resin so that the connection = surface system is formed higher than the upper surface of the sealing resin 15' as claimed The method of the range of item u leads to the step of electrically connecting the half-chip and the electrode-island electrode to the conductor wafer. The method of forming the 11th item, wherein the step of forming the forming comprises forming a method for manufacturing a layered semiconductor structure to be performed plural times. Patent 笳11筮1 # ^如如如眼- a step of connecting the second device of the first semiconductor device of the semiconductor device to the second connection electrode of the semiconductor device of the first aspect of the patent application. 8) The method of claim 2, wherein the joining of the first-and-side surface and the lower surface of the step of forming the embossing bump on the first connecting electrode is formed </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;
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