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CN111029260A - Preparation method of fan-out three-dimensional packaging structure and fan-out three-dimensional packaging structure - Google Patents

Preparation method of fan-out three-dimensional packaging structure and fan-out three-dimensional packaging structure Download PDF

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Publication number
CN111029260A
CN111029260A CN201911323128.0A CN201911323128A CN111029260A CN 111029260 A CN111029260 A CN 111029260A CN 201911323128 A CN201911323128 A CN 201911323128A CN 111029260 A CN111029260 A CN 111029260A
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China
Prior art keywords
chip
layer
fan
plastic
hole
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CN201911323128.0A
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Chinese (zh)
Inventor
蔡琨辰
刘春平
崔锐斌
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Xinhua Microelectronics Technology Co Ltd
Guangdong Fozhixin Microelectronics Technology Research Co Ltd
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Priority to CN201911323128.0A priority Critical patent/CN111029260A/en
Publication of CN111029260A publication Critical patent/CN111029260A/en
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention discloses a fan-out type three-dimensional packaging structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing an embedding material, forming a first through hole and a second through hole in the embedding material, and then pasting the embedding material on the first bearing glue; providing a first chip, mounting the first chip in the first through hole, and implanting a conductive column in the second through hole; plastic packaging is carried out on one side, close to the front side of the first chip, of the embedded material by adopting a plastic packaging material to form a first plastic packaging layer; removing the first bearing glue, and turning over and fixing the first plastic packaging layer; providing a second chip, mounting the second chip on the back surface of the first chip, and connecting an I/O interface and a conductive column of the second chip by adopting a lead; plastic packaging is carried out on one side, far away from the first plastic packaging layer, of the embedded material by adopting a plastic packaging material to form a second plastic packaging layer; and manufacturing a seed layer and a rewiring layer on the first plastic packaging layer, and implanting a metal bump in a pad area of the rewiring layer. The invention effectively reduces the packaging height and the production cost of the fan-out type three-dimensional packaging structure.

Description

Preparation method of fan-out type three-dimensional packaging structure and fan-out type three-dimensional packaging structure
Technical Field
The invention relates to the technical field of fan-out type packaging, in particular to a preparation method of a fan-out type packaging structure and the fan-out type three-dimensional packaging structure prepared by the method.
Background
In recent years, advanced packaging technology has been developed in the IC manufacturing industry, for example, multi-chip module (MCM) packages a plurality of IC chips according to functional combinations, and especially three-dimensional (3D) packages break through the concept of conventional planar packaging with an assembly efficiency as high as 200%. Firstly, a plurality of chips can be stacked in a single package body, so that the multiplication of storage capacity is realized, and the package is called as a stacked 3D package in the industry; secondly, the chips are directly interconnected, the length of an interconnecting wire is obviously shortened, the signal transmission is faster, and the interference is smaller; moreover, a plurality of chips with different functions are stacked together, so that a single packaging body realizes more functions, thereby forming a new idea of packaging the system chip; finally, the chip adopting the 3D packaging has the advantages of low power consumption, high speed and the like. In summary, three-dimensional packaging can reduce the size and weight of electronic information products by tens of times.
However, in the three-dimensional stack package technology, the chips are often placed on the film substrate during stacking, and then the film substrate is stacked, so that the package height is high, and the cost for establishing the RDL layer is high in the aspect of interconnection of the I/O interface. After the chip is thinned, the back of the chip is provided with a layer of double-sided adhesive tape, and the chip is stacked by using the double-sided adhesive tape on the back of the thinned chip, so that the packaging height can be effectively reduced; meanwhile, the packaging cost can be greatly reduced by adopting a lead wire bonding method.
Disclosure of Invention
The invention aims to provide a preparation method of a fan-out type packaging structure and the fan-out type three-dimensional packaging structure prepared by the method.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, the invention provides a preparation method of a fan-out type three-dimensional packaging structure, which comprises the following steps:
s1, providing an embedding material, forming a first through hole and a second through hole which penetrate through the embedding material along the thickness direction on the embedding material, and pasting a first bearing glue on one side of the embedding material along the thickness direction;
s2, providing a first chip, attaching the first chip into the first through hole, and implanting a conductive column into the second through hole;
s3, plastic packaging is carried out on one side, close to the front face of the first chip, of the embedded material by adopting a plastic packaging material, and a first plastic packaging layer covering the embedded material, the first chip and the conductive column is formed;
s4, removing the first bearing glue, overturning the first plastic package layer, and fixing the overturned first plastic package layer;
s5, providing a second chip, attaching the second chip to the back surface of the first chip, enabling the front surface of the second chip to face to the side far away from the first chip, and connecting the I/O interface of the second chip and the conductive column by adopting a lead;
s6, plastic packaging is carried out on one side, far away from the first plastic packaging layer, of the embedded material by adopting a plastic packaging material, and a second plastic packaging layer covering the embedded material, the second chip and the lead is formed;
s7, manufacturing a seed layer and a rewiring layer on the first plastic packaging layer, and implanting a metal bump in the pad area of the rewiring layer.
As a preferable scheme of the preparation method of the fan-out three-dimensional package structure, in step S2, the first chip is a thinned chip, the back surface of the first chip is provided with a double-sided adhesive tape, the first carrier adhesive is removed after the first plastic package layer is formed by plastic package, and then the second chip in step S5 is attached to the back surface of the first chip through the double-sided adhesive tape.
As a preferable scheme of the preparation method of the fan-out three-dimensional packaging structure, the step S7 specifically includes the following steps:
s71, respectively forming blind holes in the first plastic packaging layer at positions corresponding to the I/O interface of the first chip and the conductive column by using drilling equipment, so that the I/O interface of the first chip and the conductive column are exposed;
s72, forming a seed layer on one side of the first plastic packaging layer far away from the second plastic packaging layer and the blind hole by adopting vacuum sputtering treatment;
s73, manufacturing a rewiring layer on the seed layer;
s74, attaching a dielectric layer on the surfaces of the redistribution layer and the first plastic package layer exposed out of the seed layer and the redistribution layer, and opening holes in the dielectric layer to expose the pad area of the redistribution layer;
and S75, providing a metal bump, and implanting the metal bump into the pad area of the redistribution layer in a welding mode.
As a preferable scheme of the preparation method of the fan-out three-dimensional package structure, the step S63 specifically includes: and sequentially carrying out electroplating, dry film pasting, exposure, development and flash etching treatment on the first plastic packaging layer to obtain the rewiring layer.
On the other hand, the invention provides a fan-out type three-dimensional packaging structure prepared by the preparation method, which comprises the following steps:
the embedded material is provided with a first through hole and a second through hole which penetrate through the embedded material along the thickness direction of the embedded material at intervals;
the first chip and the conductive column are packaged in the first plastic package layer, and the front surface of the first chip faces the first plastic package layer;
the back surface of the second chip is bonded with the back surface of the first chip through a double-sided adhesive tape, an I/O interface of the second chip is connected with the conductive post through a lead, and the second chip is packaged in the second plastic package layer;
and the metal bump is connected with the I/O interface of the first chip and the conductive column through an electric connection structure.
As a preferable scheme of the fan-out three-dimensional package structure, the first plastic package layer is provided with a blind hole through which the I/O interface of the first chip and one end of the conductive post are exposed, the electrical connection structure includes a seed layer located in the blind hole and on the first plastic package layer and a redistribution layer located on the seed layer, and the metal bump is welded to the pad region of the redistribution layer.
As a preferable scheme of the fan-out three-dimensional packaging structure, the seed layer and the rewiring layer are provided with graphical holes for exposing part of the first plastic packaging layer;
the dielectric layer is attached to the non-pad area of the redistribution layer and the patterned hole.
As a preferable scheme of the fan-out three-dimensional packaging structure, the conductive posts are made of any one of Cu, Ag, or Au.
As a preferable scheme of the fan-out three-dimensional packaging structure, the double-sided adhesive tape is DAF or epoxy resin glue.
As a preferable scheme of the fan-out type three-dimensional packaging structure, the embedded material is FR4, FR5 or BT material.
The invention has the beneficial effects that: according to the invention, two chips are bonded and stacked before the redistribution layer is manufactured, so that the packaging height of the fan-out type three-dimensional packaging structure is effectively reduced, and meanwhile, the chips with higher I/O interface density are interconnected in a lead bonding mode, so that the production cost of the fan-out type three-dimensional packaging structure is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a flowchart of a method for manufacturing a fan-out three-dimensional package structure according to an embodiment of the invention.
Fig. 2 is a flowchart illustrating a specific step of step S7 according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view of an opening in a buried material according to an embodiment of the invention.
Fig. 4 is a cross-sectional view of an embodiment of the present invention showing an embedding material attached to a carrier tape.
Fig. 5 is a cross-sectional view of the first chip mounted on the embedding material and the conductive pillar implanted therein according to an embodiment of the invention.
Fig. 6 is a cross-sectional view of a first molding compound layer formed on a buried material according to an embodiment of the invention.
Fig. 7 is a cross-sectional view of a second chip mounted on and wire bonded to a buried material according to an embodiment of the present invention.
Fig. 8 is a cross-sectional view of a second molding layer formed on the embedding material according to an embodiment of the invention.
Fig. 9 is a cross-sectional view of a buried material with a seed layer and a redistribution layer formed thereon according to an embodiment of the invention.
Fig. 10 is a cross-sectional view of a dielectric layer after metal bumps are implanted, according to an embodiment of the invention.
Fig. 11 is a cross-sectional view of a fan-out three-dimensional package structure according to an embodiment of the invention.
In the figure:
1. a buried material; 1-1, a first through hole; 1-2, a second through hole; 2. a first chip; 3. a conductive post; 4. a first plastic packaging layer; 5. a second chip; 6. a lead wire; 7. a second plastic packaging layer; 8. an electrical connection structure; 9. a metal bump; 10. a first carrier gel; 11. a dielectric layer; 12. a second carrier glue; 13. and a third bearing glue.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Next, the technical solution of the present invention will be described in detail by taking the thinned RF chip as the first chip 2 and the MCU chip as the second chip 5 as examples.
As shown in fig. 1, the embodiment provides a method for manufacturing a fan-out three-dimensional package structure, including the following steps:
s1, providing an embedding material 1, forming a first through hole 1-1 and a second through hole 1-2 penetrating the embedding material 1 along the thickness direction on the embedding material 1, wherein the embedded material 1 after being formed with the holes is shown in fig. 3; then, a first carrier paste 10 is attached to one side of the embedded material 1 along the thickness direction thereof, as shown in fig. 4, so as to preliminarily fix the first chip 2 in the first through hole 1-1 and implant the conductive pillar 3. Optionally, the buried material 1 is FR4, FR5 or BT material; specifically, a first through hole 1-1 is formed in the embedded material 1 according to the size of the first chip 2 to be packaged, and then a second through hole 1-2 is formed according to the implantation position of the conductive post 3;
s2, providing a first chip 2, mounting the first chip 2 in the first through hole 1-1, and implanting a conductive pillar 3 in the second through hole 1-2, as shown in fig. 5; the first chip 2 can be preliminarily fixed in the first through hole 1-1 through the first bearing glue 10, and the conductive column 3 is inserted into the second through hole 1-2 and preliminarily fixed through the first bearing glue 10; optionally, the material of the conductive column 3 is copper, silver, gold or nichrome;
s3, performing plastic encapsulation on the side of the embedded material 1 close to the front surface of the first chip 2 by using a plastic encapsulation material, and forming a first plastic encapsulation layer 4 covering the embedded material 1, the first chip 2, and the conductive pillars 3, as shown in fig. 6; specifically, the first molding compound layer 4 covers the first chip 2, the conductive pillars 3, and all surfaces of the buried material 1 away from the back surface of the first chip 2.
S4, removing the first bearing glue 10, overturning the first plastic package layer 4, and fixing the overturned first plastic package layer 4; specifically, the first plastic package layer 4 is fixed on the bearing platform through the second bearing glue 12;
s5, providing a second chip 5, attaching the second chip 5 to the back surface of the first chip 2, making the front surface of the second chip 5 face the side away from the first chip 2, and connecting the I/O interface of the second chip 5 and the conductive pillar 3 by using the lead 6, as shown in fig. 7;
s6, performing plastic package on the side of the embedding material 1 away from the first plastic package layer 4 by using a plastic package material, and forming a second plastic package layer 7 covering the embedding material 1, the second chip 5 and the leads 6, as shown in fig. 8; the second molding compound 7 is located on one side of the embedding material 1 close to the back side of the first chip 2 and covers the second chip 5 and the leads 6.
S7, forming a seed layer and a redistribution layer on the first molding compound layer 4, and implanting a metal bump 9 in the pad region of the redistribution layer, as shown in fig. 9 and 10. Optionally, the metal bump 9 is a solder, a silver solder or a gold-tin alloy solder, and in this embodiment, a solder ball made of a solder is preferred, and the solder ball is solder-implanted in the pad region of the redistribution layer to electrically lead out the first chip 2 and the second chip 5; specifically, before the seed layer is manufactured, the package after the secondary plastic package needs to be turned over again, and the package is mounted and fixed on the carrying platform through the third carrying glue 13, as shown in fig. 9, one side of the second plastic package layer 7, which is far away from the first plastic package layer 4, is mounted and fixed on the carrying platform through the third carrying glue 13.
After the third carrier paste 13 is removed, the fan-out three-dimensional package structure shown in fig. 11 is obtained.
Optionally, the material of the package material includes polyimide, silicone, and EMC (Epoxy Molding Compound), and the EMC is preferred in this embodiment, which can improve the stability of the package structure of the first chip 2 and the second chip 5, and play a role in protecting the chips.
In the present embodiment, unless otherwise specified, the term "cover" refers to an outer surface that surrounds a component without contacting other components.
In the embodiment, the first through hole 1-1 and the second through hole 1-2 are formed in the embedded material 1, the first chip 2 is installed in the first through hole 1-1, the conductive column 3 is implanted in the second through hole 1-2, and the first chip 2 is packaged by adopting a plastic package material, so that the packaging height of the first chip 2 is reduced, then the second chip 5 is attached to the back surface of the first chip 2 in a back-to-back manner, and the I/O interface of the second chip 5 and the conductive column 3 are electrically connected by adopting a lead bonding mode for packaging, so that the electroplating time is saved; and finally, leading out the electric signals of the first chip 2 and the second chip 5 through the metal bumps 9. Compared with the prior art, the packaging height and the production cost of the fan-out type three-dimensional packaging structure are effectively reduced.
In step S2 of the present embodiment, the first chip 2 is a thinned chip, and the back surface of the first chip has a double-sided adhesive tape, the first carrier tape 10 is removed after the first plastic package layer 4 is formed by plastic package, and then the second chip 5 in step S5 is attached to the back surface of the first chip 2 by the double-sided adhesive tape.
Specifically, the first chip 2 in step S2 is subjected to thinning processing by the following steps:
providing a wafer, attaching a grinding adhesive tape to the front side of the wafer, and then grinding and thinning the back side of the wafer;
and removing the grinding adhesive tape, attaching a double-sided adhesive tape for scribing on the back surface of the wafer, and scribing the thinned wafer by using wafer scribing equipment.
When the laser scribing equipment is adopted to scribe the wafer, the wafer needs to be subjected to wafer expansion.
As shown in fig. 2, step S7 specifically includes the following steps:
s71, respectively forming blind holes in the first plastic package layer 4 at positions corresponding to the I/O interface of the first chip 2 and the conductive posts 3 by using laser drilling equipment, so that the I/O interface of the first chip 2 and the conductive posts 3 are exposed;
s72, forming a seed layer on one side of the first plastic package layer 4 far away from the second plastic package layer 7 and the blind holes by adopting vacuum sputtering treatment; specifically, the seed layer comprises a titanium metal layer located on the surfaces of the first plastic package layer 4 and the blind holes and a copper metal layer located on the titanium metal layer and filling the blind holes. The titanium metal layer has high adhesion, excellent conductivity and uniform thickness, and the copper metal layer can be stably adhered to the first plastic package layer 4 through the titanium metal layer. Of course, the seed layer in this embodiment is not limited to a two-layer structure (titanium metal layer, copper metal layer), and may have a single-layer structure, a two-layer structure, or a multilayer structure having two or more layers. The material of the seed layer is not limited to the stacking combination of two single metal materials, and may also be a single metal material or an alloy material, so that the redistribution layer can be stably attached to the package structure, and details are not repeated.
S73, manufacturing a rewiring layer on the seed layer;
s74, attaching the dielectric layer 11 on the redistribution layer and the surface of the first plastic package layer 4 exposed out of the seed layer and the redistribution layer, and opening the dielectric layer 11 to expose the pad area of the redistribution layer; optionally, the dielectric layer 11 is made of ABF (Ajinomoto Build-up Film) or PI (polyimide), and is attached to the first molding compound layer 4 and the non-pad area of the redistribution layer, so as to perform the insulating and protecting functions.
And S75, providing the metal bump 9, and welding and implanting the metal bump 9 into the pad area of the redistribution layer.
Wherein, step S63 specifically includes: and sequentially carrying out electroplating, dry film pasting, exposure, development and flash etching treatment on the first plastic sealing layer 4 to obtain a rewiring layer.
More specifically, step S63 includes the steps of:
s63a, manufacturing a copper plating layer on the seed layer through electroplating treatment;
s63b, providing a dry film, and attaching the dry film to the copper plating layer;
s63c, carrying out exposure and development treatment on the dry film to form a patterned hole exposing part of the copper plating layer;
and S63d, carrying out flash etching treatment on the copper plating layer exposed out of the patterned holes and the seed layer below the copper plating layer to obtain a redistribution layer, namely the RDL layer.
More specifically, the preparation method of the fan-out three-dimensional packaging structure of the embodiment includes the following steps:
s10, providing an embedded material 1, and forming a first through hole 1-1 and a second through hole 1-2 in the embedded material 1;
s20, attaching a first carrier tape 10 to a carrier platform of a placement machine, then attaching the embedding material 1 to the first carrier tape 10,
s30, providing a wafer, attaching a grinding adhesive tape on the front surface of the wafer, and then grinding and thinning the back surface of the wafer; removing the grinding adhesive tape, attaching a double-sided adhesive tape for scribing on the back surface of the wafer, and scribing the thinned wafer by using wafer scribing equipment to obtain a thinned first chip 2; the first chip 2 is attached in the first through hole 1-1, and the conductive column 3 is electroplated and implanted in the second through hole 1-2;
s40, plastic packaging is carried out on one side, close to the front side of the first chip 2, of the embedded material 1 by adopting a plastic packaging material to form a first plastic packaging layer 4 covering the embedded material 1, the first chip 2 and the conductive column 3, and a primary plastic packaging part is manufactured;
s50, removing the first bearing glue, turning over the primary plastic package piece, attaching a second bearing glue 12 to a bearing platform of the chip mounter, and attaching the primary plastic package piece to the second bearing glue 12;
s60, providing a second chip 5, attaching the second chip 5 to the back surface of the first chip 2, making the front surface of the second chip 5 face the side away from the first chip 2, and connecting the I/O interface of the second chip 5 and the conductive pillar 3 by using a lead 6;
s60, plastic packaging is carried out on one side, far away from the first plastic packaging layer 4, of the embedded material 1 by adopting a plastic packaging material to form a second plastic packaging layer 7 covering the embedded material 1, the second chip 5 and the lead 6, and a secondary plastic packaging part is manufactured;
s70, overturning the secondary plastic package, pasting a third bearing glue 13 on a bearing platform of the chip mounter, pasting the secondary plastic package on the third bearing glue 13, and drilling blind holes on the first plastic package layer 4 by adopting laser drilling equipment to expose the I/O interface and the conductive column 3 of the first chip 2; then carrying out vacuum sputtering on the surfaces of the blind holes and the first plastic packaging layer 4 to prepare a seed layer; sequentially pasting a dry film, exposing, developing and flashing to manufacture a rewiring layer;
and S80, attaching the dielectric layer 11, performing laser punching processing on the dielectric layer 11 to expose the conductive posts 3 and the I/O interface of the first chip 2, and implanting solder balls into the pad area of the redistribution layer to complete the preparation of the fan-out three-dimensional packaging structure.
The embodiment also provides a fan-out three-dimensional packaging structure manufactured by the manufacturing method of the embodiment, which includes:
the embedded material 1 is provided with a first through hole 1-1 and a second through hole 1-2 which penetrate through the embedded material 1 along the thickness direction of the embedded material 1 at intervals;
the chip packaging structure comprises a first plastic packaging layer 4, a first chip 2 positioned in a first through hole 1-1 and a conductive column 3 positioned in a second through hole 1-2, wherein the first chip 2 and the conductive column 3 are packaged in the first plastic packaging layer 4, and the front surface of the first chip 2 faces the first plastic packaging layer 4; specifically, the first plastic package layer 4 covers the first chip 2, the conductive pillars 3, and all surfaces of the embedded material 1 away from the back surface of the first chip 2;
the second plastic package layer 7 and the second chip 5 are positioned on one side of the embedded material 1, the back surface of the second chip 5 is bonded with the back surface of the first chip 2 through a double-sided adhesive tape, an I/O interface of the second chip 5 is connected with the conductive column 3 through a lead 6, and the second chip 5 is packaged in the second plastic package layer 7; specifically, the second molding compound layer 7 is positioned on one surface of the embedding material 1 close to the back surface of the first chip 2 and covers the second chip 5 and the leads 6;
and the metal bump 9 is connected with the I/O interface of the first chip 2 and the conductive column 3 through the electric connection structure 8.
In this embodiment, the I/O interface of the second chip 5 is connected to the conductive post 3 embedded in the second through hole 1-2 of the material 1 through the lead 6, so as to avoid separately electroplating the second chip 5 to fabricate the electrical connection structure 8, reduce the time for fabricating the circuit layer by electroplating, and reduce the production cost, and the I/O interface of the conductive post 3 and the first chip 2 embedded in the first through hole 1-1 of the material 1 is connected to the metal bump 9 through the electrical connection structure 8, thereby realizing the leading-out of the electrical signals of the first chip 2 and the second chip 5 stacked in back-to-back three-dimensional manner, and effectively reducing the packaging height of the fan-out three-dimensional packaging structure.
In this embodiment, the first chip 4 is a thinned chip, the back surface of the first chip is provided with a double-sided adhesive tape, and after the first carrier tape 10 is removed, the second chip 7 can be quickly attached to the back surface of the first chip 4 through the double-sided adhesive tape provided on the back surface of the first chip 4.
In this embodiment, the first plastic package layer 4 is provided with a blind hole through which the I/O interface of the first chip 2 and one end of the conductive post 3 are exposed, the electrical connection structure 8 includes a seed layer located in the blind hole and on the first plastic package layer 4 and a redistribution layer located on the seed layer, and the metal bump 9 is welded to the pad region of the redistribution layer. Specifically, the seed layer is located on the surface of the blind hole and the surface of the first plastic package layer 4, and the rewiring layer is located on the surface of the seed layer and fills the whole blind hole.
The seed layer and the rewiring layer are provided with graphical holes for exposing part of the first plastic packaging layer 4;
the fan-out three-dimensional package structure of the embodiment further includes a dielectric layer 11, and the dielectric layer 11 is attached to the non-pad area and the patterned hole of the redistribution layer. The dielectric layer 11 fills the patterned holes and serves to insulate and protect the non-pad areas of the redistribution layer.
Alternatively, the conductive pillar 3 is made of any one of Cu, Ag, or Au, but not limited thereto, and may be conductive.
Optionally, the double-sided adhesive tape is daf (die Attach film) or an epoxy glue. The double-sided adhesive tape is a scribing adhesive tape with the thinned back surface of the first chip 2, the thinned first chip 2 is adopted, the packaging height is reduced, the second chip 5 is convenient to mount on the back surface of the first chip 2, and the packaging efficiency of the fan-out type three-dimensional packaging structure is improved.
Optionally, the dielectric layer 11 is ABF or PI material, but is not limited thereto.
Alternatively, the buried material is FR4, FR5, or bt (bimoleimide) material, but not limited thereto, the opening process may be facilitated to embed the first chip 2 and the conductive pillars 3 in the holes.
It should be understood that the above-described embodiments are merely preferred embodiments of the invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims (10)

1.一种扇出型三维封装结构的制备方法，其特征在于，包括以下步骤：1. a preparation method of a fan-out three-dimensional packaging structure, is characterized in that, comprises the following steps: S1、提供埋入材料，在所述埋入材料上开设沿厚度方向贯穿所述埋入材料的第一通孔和第二通孔，并在所述埋入材料沿其厚度方向的一侧贴上第一承载胶；S1. Provide an embedded material, open a first through hole and a second through hole through the embedded material in the thickness direction on the embedded material, and stick a side of the embedded material along the thickness direction of the embedded material. Put on the first carrier glue; S2、提供第一芯片，将所述第一芯片贴装于所述第一通孔内，并在所述第二通孔内植入导电柱；S2, providing a first chip, mounting the first chip in the first through hole, and implanting conductive pillars in the second through hole; S3、采用塑封料于所述埋入材料靠近所述第一芯片的正面的一侧进行塑封，形成覆盖所述埋入材料、所述第一芯片以及所述导电柱的第一塑封层；S3, using plastic sealing compound to perform plastic sealing on the side of the embedded material close to the front surface of the first chip to form a first plastic sealing layer covering the embedded material, the first chip and the conductive pillar; S4、拆除所述第一承载胶并翻转所述第一塑封层，然后将翻转的所述第一塑封层固定；S4, removing the first carrier glue and turning over the first plastic sealing layer, and then fixing the turned first plastic sealing layer; S5、提供第二芯片，将所述第二芯片贴装于所述第一芯片的背面，并使所述第二芯片的正面朝向远离所述第一芯片的一侧，采用引线连接所述第二芯片的I/O接口和所述导电柱；S5. Provide a second chip, mount the second chip on the back side of the first chip, make the front side of the second chip face the side away from the first chip, and connect the first chip with wires. The I/O interface of the two chips and the conductive column; S6、采用塑封料于所述埋入材料远离所述第一塑封层的一侧进行塑封，形成覆盖所述埋入材料、所述第二芯片以及所述引线的第二塑封层；S6, using a plastic sealing compound to perform plastic sealing on the side of the embedded material away from the first plastic sealing layer to form a second plastic sealing layer covering the embedded material, the second chip and the lead; S7、在所述第一塑封层上制作种子层和重布线层，并在所述重布线层的焊盘区植入金属凸块。S7 , forming a seed layer and a redistribution layer on the first plastic sealing layer, and implanting metal bumps in the pad area of the redistribution layer. 2.根据权利要求2所述的扇出型三维封装结构的制备方法，其特征在于，步骤S2中，所述第一芯片为减薄后的芯片，其背面具有双面粘结胶带，塑封形成所述第一塑封层后拆除所述第一承载胶，然后将步骤S5中的所述第二芯片通过所述双面粘结胶带贴于所述第一芯片的背面。2 . The method for preparing a fan-out three-dimensional packaging structure according to claim 2 , wherein, in step S2 , the first chip is a thinned chip with a double-sided adhesive tape on the back, and is formed by plastic sealing. 3 . After the first plastic sealing layer is removed, the first carrier adhesive is removed, and then the second chip in step S5 is attached to the back of the first chip through the double-sided adhesive tape. 3.根据权利要求1所述的扇出型三维封装结构的制备方法，其特征在于，步骤S7具体包括以下步骤：3. The preparation method of the fan-out three-dimensional packaging structure according to claim 1, wherein step S7 specifically comprises the following steps: S71、采用钻孔设备在所述第一塑封层上对应所述第一芯片的I/O接口的位置和所述导电柱的位置分别开设盲孔，使所述第一芯片的I/O接口和所述导电柱外露；S71. Use drilling equipment to respectively open blind holes on the first plastic encapsulation layer at positions corresponding to the I/O interfaces of the first chip and at the positions of the conductive pillars, so that the I/O interfaces of the first chip are formed. and the conductive column is exposed; S72、采用真空溅射处理，在所述第一塑封层远离所述第二塑封层的一侧以及所述盲孔内形成种子层；S72, adopting vacuum sputtering treatment to form a seed layer on the side of the first plastic sealing layer away from the second plastic sealing layer and in the blind hole; S73、在所述种子层上制作重布线层；S73, making a redistribution layer on the seed layer; S74、在所述重布线层和外露于所述种子层和所述重布线层的所述第一塑封层的表面贴上介电层，对所述介电层进行开孔处理，使所述重布线层的焊盘区外露；S74. A dielectric layer is attached to the surface of the redistribution layer and the first plastic encapsulation layer exposed to the seed layer and the redistribution layer, and the dielectric layer is subjected to hole processing, so that the The pad area of the redistribution layer is exposed; S75、提供金属凸块，将所述金属凸块焊接植入所述重布线层的焊盘区。S75 , providing metal bumps, and implanting the metal bumps into the pad area of the redistribution layer. 4.根据权利要求3所述的扇出型三维封装结构的制备方法，其特征在于，步骤S73具体包括：于所述第一塑封层上依次进行电镀、贴干膜、曝光、显影、闪蚀处理，制得所述重布线层。4 . The method for preparing a fan-out three-dimensional packaging structure according to claim 3 , wherein step S73 specifically comprises: sequentially performing electroplating, sticking dry film, exposing, developing, and flash etching on the first plastic sealing layer. 5 . processing to produce the redistribution layer. 5.一种采用权利要求1至4任一项所述的制备方法制得的扇出型三维封装结构，其特征在于，包括：5. A fan-out three-dimensional packaging structure prepared by the preparation method according to any one of claims 1 to 4, characterized in that, comprising: 埋入材料，所述埋入材料上间隔开设有沿所述埋入材料的厚度方向贯穿所述埋入材料的第一通孔和第二通孔；an embedded material, wherein a first through hole and a second through hole penetrating the embedded material along the thickness direction of the embedded material are spaced apart on the embedded material; 第一塑封层、位于所述第一通孔内的第一芯片以及位于所述第二通孔内的导电柱，所述第一芯片和所述导电柱封装于所述第一塑封层内，且所述第一芯片的正面朝向所述第一塑封层；a first plastic packaging layer, a first chip located in the first through hole, and a conductive column located in the second through hole, the first chip and the conductive column are packaged in the first plastic packaging layer, and the front side of the first chip faces the first plastic sealing layer; 位于所述埋入材料一侧的第二塑封层和第二芯片，所述第二芯片的背面通过双面粘结胶带与所述第一芯片的背面粘结，所述第二芯片的I/O接口通过引线与所述导电柱连接，所述第二芯片封装于所述第二塑封层内；The second plastic encapsulation layer and the second chip on one side of the embedded material, the back of the second chip is bonded to the back of the first chip by double-sided adhesive tape, and the I/O of the second chip is The O interface is connected to the conductive post through leads, and the second chip is packaged in the second plastic sealing layer; 金属凸块，所述金属凸块通过电连接结构与所述第一芯片的I/O接口和所述导电柱连接。A metal bump, the metal bump is connected with the I/O interface of the first chip and the conductive column through an electrical connection structure. 6.根据权利要求5所述的扇出型三维封装结构，其特征在于，所述第一塑封层上开设有分别供所述第一芯片的I/O接口和所述导电柱的一端外露的盲孔，所述电连接结构包括位于所述盲孔内和所述第一塑封层上的种子层和位于所述种子层上的重布线层，所述金属凸块与所述重布线层的焊盘区焊接。6 . The fan-out three-dimensional packaging structure according to claim 5 , wherein the first plastic sealing layer is provided with a 3D package for respectively exposing the I/O interface of the first chip and one end of the conductive post. 7 . blind vias, the electrical connection structure includes a seed layer located in the blind via and on the first plastic encapsulation layer, and a redistribution layer located on the seed layer, and the metal bumps are connected to the redistribution layer. Solder pad area. 7.根据权利要求6所述的扇出型三维封装结构，其特征在于，所述种子层和所述重布线层具有使部分所述第一塑封层外露的图形化孔；7. The fan-out three-dimensional packaging structure according to claim 6, wherein the seed layer and the redistribution layer have patterned holes exposing part of the first plastic packaging layer; 还包括介电层，所述介电层贴于所述重布线层的非焊盘区和所述图形化孔内。A dielectric layer is also included, and the dielectric layer is attached to the non-pad area of the redistribution layer and the patterned holes. 8.根据权利要求5所述的扇出型三维封装结构，其特征在于，所述导电柱为Cu、Ag或Au材质中的任一种。8 . The fan-out three-dimensional packaging structure according to claim 5 , wherein the conductive pillar is any one of Cu, Ag or Au material. 9 . 9.根据权利要求5所述的扇出型三维封装结构，其特征在于，所述双面粘结胶带为DAF或者环氧树脂胶。9 . The fan-out three-dimensional packaging structure according to claim 5 , wherein the double-sided adhesive tape is DAF or epoxy adhesive. 10 . 10.根据权利要求5所述的扇出型三维封装结构，其特征在于，所述埋入材料为FR4、FR5或者BT材料。10 . The fan-out three-dimensional package structure according to claim 5 , wherein the embedded material is FR4, FR5 or BT material. 11 .
CN201911323128.0A 2019-12-20 2019-12-20 Preparation method of fan-out three-dimensional packaging structure and fan-out three-dimensional packaging structure Pending CN111029260A (en)

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Cited By (6)

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CN113161249A (en) * 2021-03-31 2021-07-23 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN114256170A (en) * 2021-12-10 2022-03-29 甬矽电子(宁波)股份有限公司 Fan-out package structure and preparation method thereof
CN114141727A (en) * 2021-12-14 2022-03-04 华天科技（昆山）电子有限公司 Multi-chip three-dimensional integrated fan-out type packaging structure and manufacturing method thereof
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CN115295529A (en) * 2022-08-31 2022-11-04 华天科技（昆山）电子有限公司 A three-dimensional integrated fan-out package structure and its manufacturing method

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