TW200830094A - Micro controller circuit and power saving method thereof - Google Patents

Abstract

A micro controller circuit provides proper clocks to a central processing unit of the micro controller and peripherals. The micro controller circuit comprises a prescaler, a second multiplexer, a central processing unit, a first switch, a second switch, a first peripheral and an execution unit. Wherein the execution unit is installed in the central processing unit and used for controlling the first switch and the second switch. Those switches are control the clock transmission according a power saving mode that the micro controller circuit operating. So that the central processing unit and each peripheral can work by using proper clock to achieve power saving.

Description

200830094 IX. Description of the Invention: [Technical Field] The present invention relates to a microcontroller circuit and a power saving method thereof, and particularly to a circuit for managing a clock signal in a distributed microcontroller and a method thereof. [Prior Art] - The power management mechanism of a general-purpose microcontroller is nothing more than controlling the speed of the system clock to save current. For example, US Patent Publication No. US 2 〇 03/(K) 79152, "Microprocessor with Multiple Low-Power Modes and Analog Devices for the Microprocessor", discloses the use of clock signals to achieve control micro-control The technology of power consumption. Please refer to the block diagram of the conventional microprocessor circuit. As shown, the selection unit 150 includes four (four) selection inputs, wherein the input system receives the output 151 of the divider (10), the other input 152 is directly coupled to the ground, and the other input system receives the oscillator 190. The main system clock 153 is generated, and the last input receives the input 154 generated by the internal RC oscillator 17 . The selection unit 160 also includes four selection inputs, and the input unit 151 receives the output 151 of the divider (10), and the other input 155 is straight.

Connected to ground, the other input receives the main system clock 153 generated by the oscillator 19, and the last-input receives the output signal 154 of the internal R. The divider is just 15], and the other clock signal is generated by the voltage detector unit 191, and the divider 16 is processed. The clock signal is processed by the divider 180 and output to the selection unit 15 and the selection unit 160. . The central processing unit operates with a variety of low-power modes, and uses the execution unit 101 to control the selection unit 15 and the selection unit 16 to cause the selection unit 15 and the selection unit 160 to select one of the four input clocks, and then The selected clock signals are sent to the central processing unit 6 200830094 yuan 100 and the peripheral units 120, 130 respectively. Therefore, in US2〇03/0079152, the clock signals required by the central processing unit i〇〇 and the peripheral units 120, 130 are respectively selected by two selection units 150, 160, and one of the four clock signals. The signal is fed into it. Thereby, in different working modes, the corresponding clock signal is selected to provide the central processing unit 100 and the peripheral units 12, 130 to control the power consumption of the microcontroller. [Summary of the Invention]

The present invention provides a microcontroller circuit and a power saving method thereof, which utilizes the switching of each mode in the low power power saving mode, and the control of the power saving switch to control the clock signal supplied to the central processing unit and each peripheral unit to achieve The effect of energy saving. The present invention provides a microcontroller, including a pre-processor, which receives two first clock signals, and divides the first clock signal to output a plurality of second-day shackles, a second multiplex Receiving a third clock signal, the first clock signal and the second clock signals, outputting a fourth clock signal =, a central processing unit receiving the fourth clock signal; a first provincial turtle switch The e is further between the central processing unit and the second multiplexer, wherein the ang four clock signal is transmitted to the central processing via the first province f _, a second power saving switch; The peripheral unit receives the third clock signal via the second electrical switch; and the execution unit is disposed in the #, the internal unit, and is controlled according to a low power power saving mode of the microcontroller The first power saving switch and the second power saving switch. The present invention provides a power saving method for the microcontroller, and the steps include first a first clock signal and a third clock signal. Then, the first clock 汛~divide and output a plurality of second clock signals. Then set a low power 7 200830094 ^ type register to select - low power saving mode. The money control turns on or off the first clock signal, one of the second clock signals, or one of the third clock signals is input into one of the microcontrollers A and the control-second power-saving switch is turned on ^ Or close the brother - the Japanese Guardian nickname is input to a first peripheral unit. In order to further understand the techniques, means, and effects of the present invention in order to achieve the intended purpose, refer to the following detailed description of the invention and the accompanying drawings. In-depth and specific understanding is provided by way of example only, and is not intended to limit the invention. [Embodiment] The power consumption of the 控制器 控制器 controller is saved. The general method is to control the micro-control, the internal processing unit and the surrounding clock signal. The present invention is a mechanism for controlling and distributing clock signals to save power consumption of the micro controller. Please refer to the second block diagram of a circuit diagram of a preferred embodiment of the microcontroller circuit of the present invention. As shown in the figure, the first clock signal fM and the third clock signal fRTC are first provided by the crystal oscillator 71, the RC oscillator π, and the Real Time Clock (RTC). The first clock signal is to transmit the external clock signal of the corpuscles 71 and the RC oscillator 72 to the first multiplexer 10, and then select one of the clock signals by controlling the first multiplexer. produce. The first multiplexer 1 then transmits the output first clock signal fM to the second multiplexer 11 and the pre-processor 20. After receiving the first clock signal, the pre-processor 20 divides the first clock signal fM by a plurality of second clock signals (fM/2, fM/4, fM/8, fM/16, fM/32, fM /64), and the second clock signal (fM/2, fM/4, fM/8, fM/16, fM/32, fM/(4) 200830094 is lost to the second/worker, 11. The second most In addition to receiving the first clock and the five clocks (fM/2, ~/4, & /8, ~/16, fM/32, fM/64), the device π also receives the instant time. Three: shredding - so the second multiplexer η has eight inputs = ^ so the second multiplexer 11 can select - clock by the ft of the register 90 (??, C1, (2) Signal, and lose = four clocks shouting fsYS (the second multiplexer 11 in this embodiment is eight loses

i „: Therefore, the register 90 is selected by three bits. The actual application depends on the number of people in the 11th to select the number of bits required for the register (10). And: the selection control position S of a patriarch 90 (CG) , C1, C2) are centrally processed, and an execution unit 41 is set according to the low power saving mode, so that the fourth clock signal fsYS is fortunately supplied to the central processing unit 40 and the second peripheral unit 52. Further, a power saving switch 31 is disposed between the central processing unit 40 and the second multiplexer 11, and the second peripheral unit 52 and the second multiplexer 11^ sigh a second power saving switch 33. The first power-saving switch 31 is controlled by the light-saving switch/I according to the low-power power-saving mode, and the third power-saving switch 2 is configured according to the low-power power-saving mode and the second peripheral unit 52 2 The switch control bit of the second control unit controls the fourth clock signal fSYS to be transmitted to the central processing unit 40 and the second peripheral unit 52. The above-mentioned peripheral periphery, the switch control bit set by το 52 is represented by Whether the second peripheral list is a bit in the work, wherein the second peripheral unit 52 is capable of 4 yuan Also analog converter or a pulse width modulator. There are instructions for performing 41 control and setting according to the low power power saving mode, which will be described later. Then the third clock signal provided by the instant time clock 80 is divided by 9. 200830094 is transmitted to the other peripheral unit in addition to the second multiplexer 11. As shown in the second, the third clock signal fRTC passes through the second power-saving switch 32 and the first unit 61 to the first peripheral unit 51. In addition, the fourth power saving unit and the second frequency divider 62 are input to the third peripheral unit 53. The first: the small turtle, the closed 32 is executed by the executing unit 41 according to the low power saving mode and the first side One of the units 51 is controlled by a switch control bit, and the fourth power-saving switch system is controlled by the execution unit 41 according to the low-power power-saving mode. Similarly, the above-mentioned switch control bit set by the peripheral unit 51, It is a bit indicating whether the first side unit 51 is in operation. In addition, the first frequency divider 61 is configured to divide the third clock signal fRTc by the clock signal of the first peripheral unit 51, and then transmit the clock signal to the first peripheral unit 51. First peripheral unit 51. Similarly, second ^ The frequency converter 62 is configured to divide the third clock signal fRTc from the clock signal required for the operation of the third peripheral unit to be transmitted to the third peripheral unit 53. The first peripheral unit 51 can be a liquid crystal display, Uquid Cry II

The display, LCD, and the like, and the third peripheral unit 53 include circuits such as a Watch Dog Timer (WDT), an RTC interrupt, or a Buzzer. The clock signal required by the central processing unit 40 and the second peripheral unit 52 can be seen by the execution unit 41, and the second multiplexer is configured and controlled by the execution unit 41. The power-saving switch 31 and the third power-saving switch 33 are provided for selecting a better clock signal among the plurality of clock signals. The clock signals required by the first peripheral unit 51 and the third peripheral unit 53 are only provided by the third clock signal fRTc provided by the instant time clock 8〇. The control of the second power-saving switch 32 and the fourth power-saving switch 34 is used to determine whether to provide the third clock signal fRTc. And processing the third clock signal by using the first frequency divider 61 and the second frequency divider 62 to provide a clock signal to the first peripheral unit 51 and the third peripheral unit 4 according to the circuit architecture of the present invention. Features, step-by-step settings, and frequency dividers are applied to more peripheral units, and are not limited to the peripheral units described in the present yoke example. The invention of low power saving (4) can be switched by setting - low power = handle (not shown), including _ normal mode (N_al o-e), - k speed mode (sl〇w M〇de) 1 speed mode ( _如) 夂 (SleePMGde) ° _ working characteristics of each mode, control power saving in far two power saving switch 3 ⁄ second power saving switch 32, third % Λ four power saving switch 34 It is the opening of the supply __, the open relationship is performed by the execution unit 41 according to the low power fine ^ =) early "^ - down - (4) the power saving «reading principle. The younger-^^31 is in the case of the towel management unit 4Q and the second multiplexer 正常 in the normal mode or the slow mode, the central processing unit 40 =; = number -. : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在When the central processing unit 4G is turned off and the central processing unit 4G is turned off to save the consumption mode, when the central mode or the idle mode is used, what is the second? Controller I is sleeping

The state in which the power-off switch 31 is controlled to be turned off (0FF) is supplied to the central processing unit 40. ‘", contend for the supply of the fourth clock signal fsYS 11 200830094 crying 61: switch 32 is set between the instant time clock 80 and the first - 哼 port 〇 61, and the instant time clock is divided into 4

After passing through the second power-saving switch 32, the second-two-day clock signal W is transmitted to the first-peripheral unit 5, and after the frequency-removal, such as 61, the transmission-line unit 41 will hold the town-4, and the price is satisfied. Then hold L-two? The electric switch 32 is in the state of being turned on ((10)), and r 61 j ^ is in the first peripheral state of the game, and is the switch control bit system in which one of the first peripheral units 5 is in operation. It can be judged by the representation of the 70th. Or the non-operating state bit = two = two in the working state, the peripheral unit 51 is in the non-form; the lower-known system--the power-saving switch 32 is in the state of the closed (qFF) for the third clock signal fRTC to the first periphery Unit 51. The second power saving switch 33 is disposed between the second peripheral unit 5 and the eleventh unit 11. The execution unit 41 controls the third power saving to be judged to be in a state in which the peripheral unit 52 is in a working state in which the forward unit or the slow surface is turned on. When the above-mentioned = early element 41 is satisfied, the third power-saving switch 3 3 is controlled to be turned on (〇(1) is executed to transmit the fourth clock signal fSYS to the second peripheral unit & sorrow, the side unit 52 operates. In addition, if the microcontroller is in the sleep mode, :::::, the second peripheral single το 52 is in the non-defense state, the execution unit 〇 ^ 乐 2 power-saving switch 33 is controlled to be turned off (〇 FF) , to: four clock signal fSYS to the second peripheral unit 52. It; determine the working state of the single π 52 'is the same as the above principle, using the second perimeter 12 200830094 second frequency: 7; electricity = 4 ± system, time clock 8 and second fRTC are transmitted through the fourth power saving 8° to provide the third clock signal to the 4th side, the frequency is cleared by the frequency 62, 1,] state ' After the third clock 4 " system is turned on (Ο N) Γ ν is supplied to the second peripheral unit / ^ second division _ 62 frequency division, the four power-saving switches 34 will be two skins and two right When the device is in the sleep state, the state is stopped, and the control is stopped, and the control is turned off (0FF), then the second message is sent to the third peripheral unit 53. In the case of - difficult to implement _; ^ 2; ^ power mode state element set to switch I" ^ reset signal and body position system includes - normal H:, the low power power saving mode of the present invention. And between the modes: switching mode, an idle mode and - sleep mode - low power mode temporary storage by low, power saving mode command setting switching each low power saving +4, 仃 'n, for setting (four) bits Bit Si, for the positive microcontroller, by setting the first-handle body control type and normal mold handle, :3 and slow-laid mode switching. In the slow mode control bit (10), C1 37041 ? The second clock signal is selected by the memory 9G (fM/2, f for the first clock signal fM, the third clock signal w for the M VfM/8, fM/16, W32~ the output of the device 11 - the fourth time Select a clock signal on the far side, and make the second multi (CO, Cl, C2) <= into 唬fsYS. Therefore, by selecting the control bit clock signal fM, the track determines the fourth clock signal fsYS as the first - One of the clock signals (fM/2, fM/4, fM/8, & /16, 13 200830094 fM/32, fM/64) among them - or the third clock signal fRTC. - In slow mode, the system _ C1: (2): For example, the selection control (2) is set to • then the = i, t is the control bit f m (four) Λ the hole number fsYs is the third clock signal "see, push. Hunting so that the central processing unit 4 and the second peripheral unit 52 Working at a more suitable speed, the switch is switched to the normal mode in the slow mode. When the micro-control bit S1 is set to !, and the system-controllable number fSYS is the first - Clock signal heart:! The fourth clock output of the 11th is the first clock signal fM): by the singer!: The clock sings one, the .m is a few 4U and the music is around 52, for the central processing early το 4G and the second Peripheral unit 52 operates. Between the clock mode and the sleep mode, and between the normal mode and the idle mode, the '4' body control position and the - pause command (touch f: 1 )' are used and the wake-up signal is used for conversion. For example, if the second firmware control bit 兀S2 is set to 0 and the Halt Command is turned on, the microcontroller ^ switches to the sleep mode in the normal mode. * In sleep mode, wake-up message k W = keup), the microcontroller returns to normal mode in sleep mode. And the second firmware control bit S2 is set & ! with the input Halt

Command ’# control n will switch to normal mode in normal mode. The speed mode Gu Xun signal (Shih) causes the microcontroller to return to normal mode in the rapid mode. Similarly, the conversion between the speed mode and the sleep mode and the slow mode and the idle mode is also determined by the second (four) control bit % and a pause finger 14 200830094 (Halt Command), and the utilization - wake-up signal To convert. For example, the second Wei blade control bit S2 is set to 〇 and input _ c_and the microcontroller will switch from the slow mode to the sleep mode. In the sleep mode, the wake-up signal (Wakeup) is used to make the micro-control (4) return to the $ mode in the sleep mode. u, the body control bit S2 is set to 1 and the input ‘Command, the job (four) device will switch to the idle mode. When the wake-up signal (Wakeup) is used, the speed mode returns to the slow mode. The four diagrams of the system are power saving method steps of the microcontroller: ΐ;; The step flow of the power saving method of the present invention. First pass by the crystal oscillator 71 or 1^ oscillating crying 7 ± since no time and the instant time clock 80 is provided third; the clock two brothers - ~ ' 20 will be the first clock fresh f ψ t Γ T use pre-division W4 ^ fM / S, fM/16, ;;;: 'transfer to the second multiplexer uf M), the sub-clock signal passed the low-power power-saving mode; Then the microcontroller uses the mode, slow mode, and A-speed molding bit S2 to select the normal mode and then centrally process the single sleep mode (as shown in the figure). The switching control of the peripheral and single S is performed according to the low power saving mode (S405). The most broadcast φ blood: 1 Nanxun 'to control each power-saving switch (as shown in the figure, μ province power consumption (if the clock signal provided is accurate, above, only the rabbit description and schema, but t ”, DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention is not limited thereto, and is not intended to limit the scope of the application. The following patent application scope is 200830094, which is incorporated herein by reference. The spirit of the present invention and its similar variations are intended to be included in the scope of the present invention. Any variation or modification that can be easily conceived in the field of the invention can be covered by the following patents. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a block diagram of a conventional microprocessor circuit; the second figure is a circuit block diagram of a preferred embodiment of the microcontroller circuit of the present invention; Low power saving mode state diagram; and

I The fourth figure is a flow chart of the steps of the power saving method of the microcontroller. [Main component symbol description] [Generally known] Central processing unit 100 Execution unit 101 Peripheral unit 120, 130 Selection unit 150, 160; Main system clock 153 Internal RC oscillator 170 Divider 180 Oscillator 190 Low power oscillator unit 191 [ The present invention] The first multiplexer 10 The second multiplexer 11 16 200830094 Pre-processor 20 First power-saving switch 31 Second power-saving switch 32 Third power-saving switch 33 Fourth power-saving switch 34 Central processing unit 40 Unit 41 First peripheral unit 51 Second peripheral unit 52 Third peripheral unit 53 First frequency divider 61 Second frequency divider 62 Crystal oscillator 71 RC oscillator 72 Instant time clock 80 Register 90 Select control bit ( C2, Q, CG)

First clock signal fM second clock signal (f]vi/2, fivi/4, fivi/8, fW16, fjvi/32, f]y[/64) third clock signal fRTC fourth clock signal fsYs 17

Claims (1)

200830094 X. Patent application scope: 1. A microcontroller, comprising: a pre-processor, receiving a first clock signal, and dividing the first clock signal to output a plurality of second clock signals; The multiplexer receives a third clock signal, the first clock signal and the second clock signals, and outputs a fourth clock signal; a central processing unit receives the fourth clock signal; An electric switch is disposed between the central processing unit and the second multiplexer; a second power saving switch; a first peripheral unit receives the third clock signal via the second power saving switch; The central processing unit controls the first power saving switch and the second power saving switch according to a low power power saving mode in which the microcontroller operates. 2. The microcontroller of claim 1, further comprising a first multiplexer for receiving an external clock signal to output the first clock signal. 3. The microcontroller of claim 2, wherein the external clock signal comprises a clock signal provided by an RC oscillator and a clock signal provided by a crystal oscillator. 4. The microcontroller of claim 1, wherein the second clock signals are clocks of the first clock signal divided by 2, divided by 4, divided by 8, divided by 16, divided by 32, and divided by 64. Signal. 5. The microcontroller as claimed in claim 1 further includes a temporary storage 18 200830094: a plurality of selection control bits of the plurality of registers to determine the fourth clock signal of the ▲th round. The micro-control described in item 5 of the patent application scope: the execution unit unitizes the fourth clock signal according to the low-power saving. , :::: The time provided by the microcontroller, clock (10), described in item i of the patent scope. Frequency divider, between. , the X-heart single 70 and the second power-saving switch 9, as claimed in the patent range, the unit further includes a microcontroller, wherein the central low-power power-saving mode ^ early 70 'Eli (four) execution unit according to switch. Controlling the first power-saving switch and the second power-saving device, such as the patent-scope side unit having the microcontroller, wherein the first-cycle power-saving mode and the 'm for the execution of the single secret Low-power 1 Bu, such as the patent, Fan Yuan, / 70, to control the second power-saving switch. The power saving mode includes = far-end microcontroller 'where the low power and - sleep modes. The modulo < anti-speed mode, - idling mode U, such as the application of the scope of the power mode register, the miscellaneous microcontroller, including - low power-saving mode. Sighing the low-power mode register for the 13th, as in the scope of the patent application, the peripheral unit, through the "microcontroller" of the "more" - the second brother two power-saving switches are connected to the second The output of the device 19 200830094 receives the fourth clock signal. 14. The microcontroller of claim 13, wherein the first peripheral unit comprises a digital analog converter or a microcontroller having a pulse width of 15 \ , = claim 13 of the patent application, Wherein the first multiplex peripheral unit is provided with a switch control bit, whereby the execution= The power saving switch is controlled according to the low power saving mode and the switch control unit. w弟三16. The microcontroller as claimed in claim 1 further includes a peripheral unit that receives the second number through a fourth power saving switch. — A third clock signal, such as the microcontroller described in claim 16 , further comprising a “(9) ^ frequency divider disposed between the third peripheral unit and the fourth power saving switch. For example, the microcontroller described in claim 16 of the patent scope, c, including a watchdog unit, an instant time clock interrupt unit: a microcontroller power saving method, the steps include: providing a first clock signal and a third Clock signal; 2 first day shackle nickname after frequency output multiple second clock signals; select a low power power saving mode; control a first power saving switch to turn on or off the first clock signal, the One of the second clock signals or the third clock signal is input to one of the central processing units of the microcontroller; and a second power saving switch is controlled to enable or disable the third clock signal input to a first periphery unit. 20 200830094 20. The power saving side of the microcontroller as described in claim 19, wherein the first power-saving relationship is controlled by an execution unit according to IH, and its mode. ''Power saving 21 as claimed in claim 19, the power saving side of the microcontroller goes to the second power saving relationship by an executing unit according to the low power farmer's 22 mode and the first peripheral unit A switch control bit is used to control: power saving is as claimed in the patent application scope 19, the micro-controller lightning-saving device ^ ^ set, ^ the first clock signal is an RC oscillator or a crystal static two, θ ” The clock signal is provided. 13 The device 23, as described in claim 19, saves the power saving side of the microcomputer. The second clock signal is composed of an instant time clock (rtc), '24, such as the patent application scope. The power consumption of the microcontroller described in item 19 is: for the first clock signal, one of the second clock signals, and the three clock signals are controlled by a second multiplexer according to a register, = the younger position, to determine one of the outputs to the central processing unit = control 25, as claimed in the patent scope of the 19th in the microcontroller power saving. Haidi two clock signal through a A frequency divider except 'the first peripheral unit. ^, then pass to 2 6. The microcontroller according to claim 19, wherein the low-power power-saving mode includes a normal mode, a ^=', a full-speed nucleus, and a sleep mode. 27, such as Shen Congwei's 26th rhyme description (four) the province's low-power power-saving mode is set by a low; ^ its device to switch. + Series temporary storage 28, such as application materials | 5 The micro-control n power-saving method according to item 27, wherein the normal mode and the slow mode are switched between the normal mode and the slow mode by setting the first firmware control bit of the low-power mode register. The power saving method of the microcontroller according to claim 27, wherein the normal mode and the sleep mode, the normal mode and the idle mode, the slow mode and the sleep mode, and the slow mode And the idle mode is switched by setting a second firmware control bit of the low power mode register and a pause command. 30. The power saving method of the microcontroller according to claim 26, The sleep mode and the idle mode are activated by a wake-up signal. The waking mechanism is configured to return to the normal mode or the slow mode. 31. The power saving method of the microcontroller according to claim 19, further comprising transmitting the first clock signal through a third power saving switch, One of the second clock signals or one of the third clock signals is given to a second peripheral unit. 32. The power saving method of the microcontroller according to claim 31, wherein the third province The power-on relationship is controlled by an execution unit according to the low-power power-saving mode and a switch control bit of the second peripheral unit. 33. The power-saving method of the microcontroller according to claim 19, further includes The third clock signal is transmitted to a third peripheral unit through a fourth power saving switch. 34. The microcontroller power saving method of claim 33, wherein the third clock signal is frequency-divided by a second frequency divider and then transmitted to the third peripheral unit. 35. The microcontroller power saving method according to claim 33, wherein the fourth power saving relationship is controlled by an execution unit according to the low power saving mode 22 200830094 mode. 36. A power saving method for a microcontroller, the method comprising: providing a first clock signal and a third clock signal; providing a pre-processor to divide the first clock signal and output a plurality of second clock signals; The micro-controller switches to a low-power power-saving mode; providing: a second multiplexer for receiving the first, the clock signal, the second clock signal, and the third clock signal, according to a register selection The control bit turns out - the fourth clock number, wherein the selection control bit of the register is set according to the low power saving mode; the second power saving switch turns on or off the fourth clock signal input to a central processing unit of the microcontroller; and a second power-saving switch 'to enable or disable the third clock signal input to a first peripheral unit. 7. The microcontroller power saving method of claim 36, wherein the first power saving open relationship is controlled by an execution unit according to the low power saving mode. The power saving method of the microcontroller according to Item 36 of the patent application scope, wherein the second power saving relationship is performed by an execution unit according to the low power power saving 39, the type and the first peripheral unit Control bits to control. The power saving method of the microcontroller described in the 36th patent scope of the patent application, wherein the selection control bit of the register is set by an execution unit according to the power saving mode of the power supply. For example, the power saving method of the microcontroller described in claim 36, wherein the first clock signal is a clock signal provided by an Rc oscillator or a crystal oscillator 23 200830094. 41 42 43, 44, 45, 46, 47, 48, and the power saving method of the microcontroller as described in the third clock of the patent application scope, such as applying for a patent garden! ^糸由—immediate time clock (provided by rt〇). The third power saving method of the third clock tflt# 36, the first peripheral unit is removed by a first frequency divider. Then, the power saving method of the microcontroller described in the low-power province with 36 items is included in the scope of the patent application. The idle mode and the system include a normal mode, a slow mode, and a sleep mode. For example, in the 凊 凊 patent scope, the low power _/^ ^ Λ controller power saving method, the device to switch the electric pull type by setting a low power mode temporary storage smart #利 range 44th item The microcontroller saves the electric method, and the /Hang-$ mode and the slow mode are switched by setting the first firmware control bit of the low-power mode temporary storage. The power saving method of the microcontroller of claim 44, wherein the normal mode and the sleep mode, the normal mode and the idle mode, the slow mode and the sleep mode, and the slow mode and the idle mode By setting the second firmware control bit of the low power mode register The power saving method of the microcontroller according to claim 43, wherein the sleep mode and the idle mode initiate a wake-up mechanism by a wake-up signal to return to the normal mode or the slow The power saving method of the microcontroller as described in claim 36, further comprising transmitting the fourth clock signal to a 24th 200830094 two peripheral unit through a third power saving switch. 49' Patent Range 48 The power saving method of the microcontroller described in the item, wherein the ρ = the first power saving open relationship is controlled by the executing unit according to the low power saving 5 0 Ϊ the second peripheral unit - the switch control bit. (4) The micro-control (4) power-saving method described in item 36 is more transparent. The fourth-power-saving switch transmits the third clock signal to a second peripheral unit. Le 51 ^ 申 哏 哏 哏 哏 哏 哏The controller saves the two clock signals through a second frequency divider and divides the frequency signals to the three peripheral units of the brother. The Dande W 5 2, 丄 ° patent application scope 50 said the microcontroller with the earth-electric surface By an execution unit root 25