CN108089689A - A kind of small-sized SoC super low-power consumptions control circuit and method - Google Patents
A kind of small-sized SoC super low-power consumptions control circuit and method Download PDFInfo
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- CN108089689A CN108089689A CN201711142515.5A CN201711142515A CN108089689A CN 108089689 A CN108089689 A CN 108089689A CN 201711142515 A CN201711142515 A CN 201711142515A CN 108089689 A CN108089689 A CN 108089689A
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- 230000005611 electricity Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000007726 management method Methods 0.000 claims description 79
- 238000013500 data storage Methods 0.000 claims description 18
- 210000000352 storage cell Anatomy 0.000 claims description 18
- 238000011084 recovery Methods 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims 1
- 230000003716 rejuvenation Effects 0.000 abstract description 3
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005265 energy consumption Methods 0.000 description 3
- 230000002618 waking effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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Abstract
The invention discloses a kind of small-sized SoC super low-power consumptions control circuit and methods, include logic circuitry, low power consumption control module, power management module, Clock management module and low-frequency clock module in configuration aspects.When needing into idle state, the voltage value of logic circuitry feeder ear is reduced to by the data mode that can only be kept in logic circuitry by low power consumption control module on hardware, and the minimum that signal cannot be supported to overturn, simultaneously close off the clock source of logic circuitry, so as to eliminate logic dynamic power consumption, and electricity leakage power dissipation is preferably minimized；In addition, the present invention preserves system running state without software, upon wake up, without software rejuvenation scene, can directly next of runtime instruction, so as to accelerate wake-up speed, enhancing user experience.
Description
Technical field
The present invention relates to system-on-chip technologies, particularly a kind of small-sized SoC super low-power consumptions control circuit and method.
Background technology
At present, with the continuous development and popularization of contemporary electronic technology, the Working Life of the mankind closely joins with electronic technology
It is tied.Such as the portable and wireless penetration of entertainment electronics, people is allowed to break away from the constraint of electric wire；Intellectual water meter is answered
With significantly alleviating human cost；Health supervision electronic product allows people that can grasp personnel's physical condition in real time；Tracking
Positioning product, can wandering away to avoid article or personnel.This electronic product is respectively provided with idle and work two states, whole
Low-power consumption be a most important technical indicator, be finally presented as once charge or product battery cruising ability.Now
The reduction power consumption scheme of the electron-like is directed on the market, mainly by following two modes：The first is reduced using software mode
Logic circuit voltage realizes the optimization of power consumption, but due to the foundation of signal and the holding of clock, it is necessary to more than reserved enough voltage
Amount, leads to not overall power being preferably minimized；Second is to be realized using auxiliary micro-control unit as power management unit
Control to voltage, but the program is mainly used in medium-and-large-sized SoC, and there are multiple arithmetic elements in inside, for having by force to low-power consumption
It is required that bluetooth, the products such as wifi, BLE can not apply.Meanwhile in order to reduce the power consumption of idle state in above two method,
Program clock frequency can be reduced to KHz ranks, and product wake-up speed can be caused partially slow, influence user experience.
The content of the invention
To solve the above problems, it is an object of the invention to provide a kind of small-sized SoC super low-power consumptions control circuit and method,
It is not only able to realize the reduction of whole energy consumption, and can accelerate to wake up speed.
Technical solution is used by the present invention solves the problems, such as it：
A kind of small-sized SoC super low-power consumptions control circuit, it is characterised in that：Including logic circuitry, for control logic
The voltage of circuit system and the low power consumption control module of clock signal, the power management for providing voltage for logic circuitry
Module, for Clock management module that clock signal is provided for logic circuitry and low for being provided for low power consumption control module
The low-frequency clock module of frequency clock signal；The input terminal of the low power consumption control module is connected to logic circuitry, described low
The output terminal of power consumption control module is respectively connected to power management module and Clock management module, the logic circuitry, low
The feeder ear of power consumption control module, Clock management module and low-frequency clock module is connected to power management module, the logic
The clock signal terminal of circuit system is connected to Clock management module, and the clock signal terminal of the low power consumption control module is connected to low
Frequency clock module.
Further, the logic circuitry includes CPU element, bus and data storage cell；The CPU element and
It being attached between data storage cell by bus, the bus is additionally coupled to low power consumption control module, the CPU element,
Bus and data storage cell are also connected to power management module and Clock management module simultaneously.
Further, the low power consumption control module includes wakeup logic unit, wakes up register and controls output logic
Unit；The wake-up register, wakeup logic unit and control output logic unit are sequentially connected, the control output logic list
The output terminal of member is respectively connected to power management module and Clock management module, and the wakeup logic unit is additionally coupled to logic electricity
Road system, the wake-up register, wakeup logic unit and control output logic unit are also connected to power management module simultaneously
With low-frequency clock module.
Further, the frequency for the clock signal that the Clock management module and low-frequency clock module are exported is inconsistent,
The frequency of the clock signal of the Clock management module output is higher than low-frequency clock module.
It is a kind of using a kind of above-mentioned method of small-sized SoC super low-power consumptions control circuit, which is characterized in that including following step
Suddenly：
S1：The logic circuitry completes task；
S2：The logic circuitry sets system wake-up source by low power consumption control module；
S3：The low power consumption control module is by controlling Clock management module to stop output clock signal to logic circuit system
System；
S4：The low power consumption control module is by controlling power management module to reduce the voltage of logic circuitry feeder ear
Value；
S5：The logic circuitry enters idle waiting state.
Further, it is further comprising the steps of after the step S5：
S6：Judge whether the low power consumption control module receives wake source, step S7 performed when receiving wake source,
Otherwise return and continue to execute step S6；
S7：The low power consumption control module is by controlling power management module to recover the normal work of logic circuitry feeder ear
Voltage value when making；
S8：The low power consumption control module is by controlling Clock management module recovery to export clock signal to logic circuit system
System；
S9：The logic circuitry enters working condition, and returns and perform step S1.
Further, the wake source includes timing signal or external behavior.
Further, the voltage value in the step S4 is the minimum electricity for keeping data mode in the logic circuitry
Pressure value.
The beneficial effects of the invention are as follows：A kind of small-sized SoC super low-power consumptions control circuit and method that the present invention uses, are being tied
Include logic circuitry, low power consumption control module, power management module, Clock management module and low-frequency clock mould in terms of structure
Block.When needing into idle state, by low power consumption control module by the voltage of logic circuitry feeder ear on hardware
Value is reduced to the data mode that can only be kept in logic circuitry, and the minimum that signal cannot be supported to overturn, and simultaneously closes off
The clock source of logic circuitry so as to eliminate logic dynamic power consumption, and electricity leakage power dissipation is preferably minimized；In addition, nothing of the present invention
Software is needed to preserve system running state, upon wake up, without software rejuvenation scene, can directly next of runtime refer to
Order so as to accelerate wake-up speed, enhances user experience.
Description of the drawings
The invention will be further described with example below in conjunction with the accompanying drawings.
Fig. 1 is a kind of basic circuit functional block diagram of small-sized SoC super low-power consumptions control circuit of the present invention；
Fig. 2 is a kind of physical circuit functional block diagram of small-sized SoC super low-power consumptions control circuit of the present invention；
Fig. 3 is a kind of step flow chart of the method for small-sized SoC super low-power consumptions control circuit of the present invention.
Specific embodiment
With reference to Fig. 1, the basic circuit functional block diagram of a kind of small-sized SoC super low-power consumptions control circuit of the invention, including patrolling
Collect circuit system 400, low power consumption control module 100, power management module 200, Clock management module 300 and low-frequency clock module
500, the input terminal of the low power consumption control module 100 is connected to logic circuitry 400, the low power consumption control module 100
Output terminal be respectively connected to power management module 200 and Clock management module 300, the logic circuitry 400, low-power consumption
The feeder ear of control module 100, Clock management module 300 and low-frequency clock module 500 is connected to power management module 200,
The clock signal terminal of the logic circuitry 400 is connected to Clock management module 300, the low power consumption control module 100
Clock signal terminal is connected to low-frequency clock module 500, what the Clock management module 300 and low-frequency clock module 500 were exported
The frequency of clock signal is inconsistent, and the frequency for the clock signal that the Clock management module 300 exports is than low-frequency clock module 500
Will height.
When entire SoC systems complete task, it is necessary into idle waiting state, the logic circuitry 400
System wake-up source, such as timing or external behavior by low power consumption control module 100 can be set, inform low power consumption control module
100 need into idle waiting state, and the low power consumption control module 100 can respond output clock shutdown signal to Clock management
Module 300, the Clock management module 300 can respond stopping output high frequency clock signal to logic circuitry 400, then institute
The meeting output voltage dropping signal of low power consumption control module 100 is stated to power management module 200,200 meeting of power management module
The voltage value of 400 feeder ear of logic circuitry is reduced to only by the voltage value of 400 feeder ear of response regulation logic circuitry
The data mode in the logic circuitry 400 can be kept, and cannot support the minimum voltage value of signal overturning, it is described at this time
Logic circuitry 400 enters idle waiting state, and ensure that the data stored in logic circuitry 400 are having voltage
It will not be lost in the case of surplus.When the low power consumption control module 100 receives wake source, the low power consumption control module
100 can be within 3 clock cycle, and response output voltage recovers signal to the power management module 200, the power management mould
The voltage value of 400 feeder ear of the meeting response regulation of block 200 logic circuitry, by the voltage value of 400 feeder ear of logic circuitry
Voltage value when recovering to working condition, then the low power consumption control module 100, which can also respond, exports clock recovery signal extremely
Clock management module 300, the Clock management module 300 can respond recovery output high frequency clock signal to logic circuitry
400, provide required high frequency clock signal during work for logic circuitry 400.
The present invention, which drops to voltage value of the logic circuitry 400 under idle waiting state, can only keep the logic electricity
Data mode in road system 400, and the minimum voltage value that signal cannot be supported to overturn, are intended merely to ensure logic circuitry
Data in 400 are not lost so also leave minimum voltage margin, therefore the present invention can will be under the idle state of system
Electricity leakage power dissipation is preferably minimized.Meanwhile the minimum voltage value can't support signal to overturn, and eliminate logic dynamic power consumption, so as to
Realize the reduction of whole energy consumption.
In addition, the present invention without software preserve system running state, be upon wake up, without software rejuvenation scene, can
With next instruction of direct runtime, so as to accelerate wake-up speed, enhance user experience.
The 500 required clock signal of low-frequency clock module is low-frequency clock signal, therefore the low-frequency clock mould
Block 500 can only provide low-frequency clock signal to low power consumption control module 100；The 400 required clock of logic circuitry
Signal is high frequency clock signal, therefore Clock management module 300 can only provide high frequency clock signal to logic circuitry 400.
The frequency for the clock signal that the Clock management module 300 exports is higher than low-frequency clock module 500.
The voltage that the power management module 200 is provided is divided into two kinds, and a kind of exported to logic circuitry 400
Voltage, the amplitude of the voltage can be adjusted according to the control of low power consumption control module 100, in idle state and working condition
Under amplitude be different；Another kind is exported to low power consumption control module 100, low-frequency clock module 500 and Clock management
The voltage of module 300, the amplitude of the voltage are always maintained at constant, are to ensure low power consumption control module 100, low-frequency clock mould
Block 500 and Clock management module 300 being capable of long-term smooth work.
The wake source includes the signals such as internal timing or external behavior, and the internal timing refers in some setting
Time point or the period that have passed through setting, the logic circuitry 400 need to be transformed into normally from idle waiting state
The instruction of working condition；The external behavior refers to button, come back the instruction of the behavior acts such as display.
With reference to Fig. 2, the physical circuit functional block diagram of a kind of small-sized SoC super low-power consumptions control circuit of the invention, including patrolling
Collect circuit system 400, low power consumption control module 100, power management module 200, Clock management module 300 and low-frequency clock module
500；The logic circuitry 400 includes CPU element 410, bus 420 and data storage cell 430, the low power consumption control
Module 100 includes wakeup logic unit 110, wakes up register 120 and controls output logic unit 130.The CPU element 410,
Bus 420 and data storage cell 430 are sequentially connected, and the bus 420 is additionally coupled to wakeup logic unit 110, and the CPU is mono-
Member 410, bus 420 and data storage cell 430 are also connected to Clock management module 300 and power management module 200 simultaneously；Institute
It states and wakes up register 120, wakeup logic unit 110 and output logic unit 130 is controlled to be sequentially connected, the control output logic
The output terminal of unit 130 is connected to Clock management module 300 and power management module 200, and the wake-up register 120 wakes up
Logic unit 110 and control output logic unit 130 are additionally coupled to low-frequency clock module 500 and power management module 200.
In SoC systems, program operation at least needs CPU element 410, bus 420, data storage cell 430 with timely
Zhong Shu, in the scheme of power consumption is reduced by being depressured mode using software, system clock can not close, CPU element 410, bus
420 and data storage cell 430 necessarily be in working condition, therefore the voltage value of feeder ear can not be reduced to it is lower, simultaneously
Due to the overturning of Clock Tree, the dynamic power consumption of entire flogic system presence signal overturning.In view of the above-mentioned problems, the present invention passes through handle
Voltage value drops to the data mode that can only be kept in the logic circuitry 400, and the minimum electricity that signal cannot be supported to overturn
Pressure value, and clock source is automatically closed using hardware mode, so as to which the electricity leakage power dissipation under the idle state of system be preferably minimized,
Logic dynamic power consumption is eliminated simultaneously, it is achieved thereby that the reduction of whole energy consumption.
When being needed after SoC systems complete task into idle waiting state, the CPU element 410 can be by total
Idle instruction is sent to the wakeup logic unit 110 by line 420, and is passed through to configure and waken up the configuration system wake-up of register 120
Source, described to wake up the register in order to control of register 120, inside contains the state configuration of system, so as to inform low power consumption control
Module 100 is needed into idle waiting state.The wakeup logic unit 110 can respond output idle instruction to control output and patrol
Unit 130 is collected, the control output logic unit 130 can respond output clock shutdown signal to Clock management module 300, described
Clock management module 300 can respond the CPU element 410 stopped in output high frequency clock signal to logic circuitry 400, bus
420 and data storage cell 430, then the control output logic unit 130 can also output voltage dropping signal to power supply pipe
Module 200 is managed, the power management module 200 understands response regulation CPU element 410, bus 420 and data storage cell 430
The voltage value of the feeder ear of CPU element 410, bus 420 and data storage cell 430 is reduced to only by the voltage value of feeder ear
The data mode in the logic circuitry 400 can be kept, and cannot support the minimum voltage value of signal overturning, it is described at this time
Logic circuitry 400 enters idle waiting state, and ensure that the data stored in logic circuitry 400 are having voltage
It will not be lost in the case of surplus.When the wakeup logic unit 110 receives wake source, by waking up register 120
State configuration response output wake-up signal to control within 3 clock cycle exports logic unit 130, the control output
Logic unit 130 can respond output voltage and recover signal to the power management module 200,200 meeting of power management module
The voltage value of the feeder ear of response regulation CPU element 410, bus 420 and data storage cell 430, by CPU element 410, bus
420 and voltage value when recovering to working condition of the voltage value of feeder ear of data storage cell 430, the then control output
Logic unit 130 can also respond output clock recovery signal to Clock management module 300, and the Clock management module 300 can be rung
High frequency clock signal should be recovered to export to CPU element 410, bus 420 and data storage cell 430, be CPU element 410, bus
420 and data storage cell 430 provide work when required high frequency clock signal.
Wakeup logic unit 110, wake-up register 120 and control output logic in the low power consumption control module 100
Unit 130 is operated in low frequency clock domain, and logic realization is succinct.Register in the case where system is in normal operating conditions, just by
CPU element 410 is completed to configure with software mode；In an idle state, if with register configuration response all the way or multichannel
Wake source reaches, in 3 clock cycle, you can completes the operation of control output logic, realizes the recovery of system clock and voltage.
With reference to Fig. 3, a kind of step flow chart of the method for small-sized SoC super low-power consumptions control circuit of the invention, including with
Lower step：
S1：The logic circuitry completes task；The logic circuitry 400 can be after task be completed
It is prepared to enter into idle state.
S2：The logic circuitry sets system wake-up source by low power consumption control module；The wake source includes interior
The signals such as portion's timing or external behavior.
S3：The low power consumption control module is by controlling Clock management module to stop output clock signal to logic circuit system
System；By closing the clock source of logic circuitry 400, the dynamic power consumption of signal overturning is eliminated.
S4：The low power consumption control module is by controlling power management module to reduce the voltage of logic circuitry feeder ear
Value；The described voltage value can only keep the data mode in the logic circuitry 400, and cannot support signal overturning most
Low voltage value is intended merely to ensure that the data in logic circuitry 400 are not lost so also leave minimum voltage margin, because
Electricity leakage power dissipation under the idle state of system can be preferably minimized by this.
S5：The logic circuitry enters idle waiting state；
S6：Judge whether the low power consumption control module receives wake source, step S7 performed when receiving wake source,
Otherwise return and continue to execute step S6；
S7：The low power consumption control module is by controlling power management module to recover the normal work of logic circuitry feeder ear
Voltage value when making；Voltage is recovered to required voltage class when working normally first when waking up, is ensured when recovering
The voltage of clock signal foregoing description logic circuitry disclosure satisfy that normal work needs, avoid system fault.
S8：The low power consumption control module is by controlling Clock management module recovery to export clock signal to logic circuit system
System；Recovered clock signal to logic circuitry 400, ensures that system is normal in same a clock domain again after voltage has been recovered
Work.
S9：The logic circuitry enters working condition, and returns and perform step S1.
The above is presently preferred embodiments of the present invention, the invention is not limited in the above embodiment, as long as
It reaches the technique effect of the present invention with identical means, should all belong to the scope of protection of the present invention.
Claims (8)
1. a kind of small-sized SoC super low-power consumptions control circuit, it is characterised in that：Including logic circuitry, for control logic electricity
The voltage of road system and the low power consumption control module of clock signal, the power management mould for providing voltage for logic circuitry
Block, for Clock management module that clock signal is provided for logic circuitry and for providing low frequency for low power consumption control module
The low-frequency clock module of clock signal；The input terminal of the low power consumption control module is connected to logic circuitry, the low work(
The output terminal of consumption control module is respectively connected to power management module and Clock management module, the logic circuitry, low work(
The feeder ear of consumption control module, Clock management module and low-frequency clock module is connected to power management module, the logic electricity
The clock signal terminal of road system is connected to Clock management module, the clock signal terminal connection tremendously low frequency of the low power consumption control module
Clock module.
2. a kind of small-sized SoC super low-power consumptions control circuit according to claim 1, it is characterised in that：The logic circuit
System includes CPU element, bus and data storage cell；It is carried out between the CPU element and data storage cell by bus
Connection, the bus are additionally coupled to low power consumption control module, and the CPU element, bus and data storage cell also connect simultaneously
To power management module and Clock management module.
3. a kind of small-sized SoC super low-power consumptions control circuit according to claim 1, it is characterised in that：The low-power consumption control
Molding block includes wakeup logic unit, wakes up register and controls output logic unit；The wake-up register, wakeup logic list
Member and control output logic unit are sequentially connected, and the output terminal of the control output logic unit is respectively connected to power management mould
Block and Clock management module, the wakeup logic unit are additionally coupled to logic circuitry, the wake-up register, wakeup logic
Unit and control output logic unit are also connected to power management module and low-frequency clock module simultaneously.
4. a kind of small-sized SoC super low-power consumptions control circuit according to claim 1, it is characterised in that：The Clock management
The frequency for the clock signal that module and low-frequency clock module are exported is inconsistent, the clock signal of the Clock management module output
Frequency it is higher than low-frequency clock module.
5. a kind of using a kind of any methods of small-sized SoC super low-power consumptions control circuit of claim 1-4, feature exists
In comprising the following steps：
S1：The logic circuitry completes task；
S2：The logic circuitry sets system wake-up source by low power consumption control module；
S3：The low power consumption control module is by controlling Clock management module to stop output clock signal to logic circuitry；
S4：The low power consumption control module is by controlling power management module to reduce the voltage value of logic circuitry feeder ear；
S5：The logic circuitry enters idle waiting state.
6. a kind of small-sized SoC super low-power consumptions control circuit according to claim 5, which is characterized in that the step S5 it
It is further comprising the steps of afterwards：
S6：Judge whether the low power consumption control module receives wake source, step S7 is performed when receiving wake source, otherwise
Return continues to execute step S6；
S7：When the low power consumption control module is worked normally by the way that power management module is controlled to recover logic circuitry feeder ear
Voltage value；
S8：The low power consumption control module is by controlling Clock management module recovery to export clock signal to logic circuitry；
S9：The logic circuitry enters working condition, and returns and perform step S1.
7. a kind of small-sized SoC super low-power consumptions control circuit according to claim 1, it is characterised in that：The wake source bag
Include timing signal or external behavior.
8. a kind of small-sized SoC super low-power consumptions control circuit according to claim 1, it is characterised in that：In the step S4
Voltage value to keep the minimum voltage value of data mode in the logic circuitry.
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| CN201711142515.5A CN108089689A (en) | 2017-11-17 | 2017-11-17 | A kind of small-sized SoC super low-power consumptions control circuit and method |
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Cited By (10)
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| CN109739342A (en) * | 2018-12-25 | 2019-05-10 | 华勤通讯技术有限公司 | A kind of electronic equipment |
| CN110018791A (en) * | 2019-03-28 | 2019-07-16 | 深圳忆联信息系统有限公司 | Power managed control method and system based on SSD SOC |
| WO2021036227A1 (en) * | 2019-08-23 | 2021-03-04 | 深圳市零点智联科技有限公司 | Power saving method for smart vehicle key, and system |
| CN112947738A (en) * | 2019-12-10 | 2021-06-11 | 珠海全志科技股份有限公司 | Intelligent terminal power supply system and intelligent terminal standby and wake-up method |
| CN113111030A (en) * | 2021-04-19 | 2021-07-13 | 上海金卓科技有限公司 | On-chip system and control method thereof |
| CN114427441A (en) * | 2020-09-23 | 2022-05-03 | 中国石油化工股份有限公司 | Underground circuit control system and implementation method thereof |
| CN114879829A (en) * | 2022-07-08 | 2022-08-09 | 摩尔线程智能科技(北京)有限责任公司 | Power consumption management method and device, electronic equipment, graphic processor and storage medium |
| CN115774484A (en) * | 2023-02-13 | 2023-03-10 | 苏州聚元微电子股份有限公司 | Low-power consumption management system of TOUCH MCU |
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