200828251 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種液晶顯示裝置，尤其係關於一種可透過減 少資料線數目而降低生產成本與功率消耗之液晶顯示裝置。 【先前技術】 液晶顯示（liquid crystal display ; LCD)裝置使用電場控制液 曰曰刀子之透光比以頒不影像。通常，液晶顯不裝置提供液晶面板， 液晶面板包含兩塊玻璃基板之間的液晶，液晶分子矩陣，以及用 於各自改變液晶分子中訊號之交互裝置；驅動電路，用於驅動液 晶面板，以及背光單元，導引光線至液晶面板上。 隶近，減少液晶面板之訊號線數目或者電路元件之數目，以 開發出輕薄且低成本之液晶顯示裝置。例如，韓國專利公報Ν〇· 10-2003-0039972揭露了 一種玻璃上單晶片之液晶顯示裝置，用於 驅動液晶顯示面板之積體驅動晶片被裝設於顯示區域之周邊上， 以減少面板尺寸及裝置之生產成本。 S知技術之玻璃上單晶片之液晶顯示裝置具有以下缺點。單 元晝素中的彩色畫素晶格包含垂直帶狀結構，這樣彩色畫素晶格 沿液晶顯示面板之水平方向（閘極線方向）排列。每個彩色晝素 晶格需要單躺資料線。因級著資料線數目的增加，積體驅動 晶片的尺寸也增加，僅僅小尺寸的液晶顯示裝置，例如解析度為 360 X 16G ’可使用玻璃上單晶片型液晶顯示裝置。為了得到更高 解析度的裝置，玻璁 现項上早晶片型液晶顯示裝 例如選擇電路以社κ士 直而要頜外的電路， 線的主動週期的期^ 、擇電路％，在閘極 ㈣期間内，依照時序劃分來劃 後供應至複數條資粗 / 員比旦素貧料，然 ’、、4線，從而減少晝素資料的 當使用選擇電路眭、六R — 允电％間。因此， 寸，液_顯示面板的解析度受* 間的限制。此外，接躺 晝素麟的充電時 鋪鶴^之各通道輸出的類比書 曰地被反向簡於各水平線，彳《消耗大量辨。一 【發明内容] 口此本發明實施例提供_ 釦姑f & 饮日日頜不衣置，實質上避免習 nT 、制及缺點所產生的一或多個問題。 本發之目的在於—魏晶顯示妓 少嫌線的數目而減少生產成本及功率消耗。 咸 本發明實施例之另一目的在於摞供括 Μ、—種液日日顯示裝置’具有 改善的影像品質。 、、本發明其它的特徵和優點將在如下的說明書中部分地加以闡 j ’亚且本發财它㈣徵和優點對於本倾的普通技術人員來 况’可以魏本㈣如下的酬_部分地理解或者可以從本發 明的實射得出。本發目的和其贿點可錢過本發明所記 载的說明書和帽專利顧中特職__並結合图式部份， 得以實現和獲得。 為了獲得本發明實關的這些和其他優點，輯本發明作具 200828251 體化和概括性的描述，本發明的一種液晶顯示裝置包含：複數條 資料線，包含第一資料線及第二資料線，實質上彼此平行排列； 複數條閘極線，包含第一閘極線、第二閘極線及第三閘極線，實 貝上彼此平行排列，閘極線交叉於資料線；複數個子書素，由交 叉的閘極線與資料線定義，至少三個子晝素，直接地沿鄰接的資 料線其中之一排列且對應不同的顏色以形成晝素；以及驅動積體 電路，依序驅動第一、第二及第三閘極線於水平週期内，其中水 平週期期間，供應至晝素之第一子晝素之第一訊號與供應至晝素 之第二子晝素之第二的訊號極性相反，與供應至畫素之第三子查 素之第三訊號的極性相同。 另一方面，一種驅動液晶顯示裝置之方法，該液晶顯示裝置 包含複數條資料線、複數條閘極線以及由資料線及閘極線定義之 袓數個畫素，各晝素包含三個子晝素，沿鄰接的f料線其中之一 直接地排列，此液晶顯示驅動裝置之驅動方法包含：於第一框之 每個水平週細間依序地驅動三條閘極線，於第一框期間供應第 一極性之視頻訊號至奇數號資料線，以及於第一框中供應第二極 性之視頻訊號至偶數號㈣線，其巾水平職及每個晝素中，供 應至第子旦素之第一訊號與供應至第二子晝素之第二訊號極性 相反，與供應至第三子晝素之第三訊號極性相同。 另一方面，本發明之液晶顯示裝置包含m條閘極線，m為大 於一的正數，η條資料線，n為大於二的整數；以及複數個第一彩 200828251 色子晝素’排列於第ith條閘極線與第(i+1)th條閘極線之間，複數 個第-$色子4素，排列於第㈣)th條線與第(M)th條閑極 線之間，以及複數個第三彩色子畫素，排列於第(i+2)th條閘極線 與第(i+3)th條閘極線之間，其中第一彩色子晝素以及第三彩色子 晝素連接於第-至第㈣沖條資料線其中之_，第二彩色子晝素 連接於第二至nth資料線。 另一方面，本發明之液晶顯示裝置包含m條閘極線，m為大 於，、的整數，η條資料線，n為大於二的整數；以及複數個第_子 晝素’依序排列於第條閘極線與第(i+1)th不条閘極線之間，複數 個第一子晝素，依序排列於第(i+l沖條閘極線與第(丨+2)也條閘極 線之間’袓數個第三彩色子晝素，依序排列於第(1+2沖條閘極線 舁第(i+3)th條閘極線之間，複數個第四子晝素，依序排列於第 (i+3)th i卞閘極線與第(1+4池條閘極線之間，複數個第五子晝素， 依序排列於第（i+4)th條閘極線與第(i+5)th條閘極線之間，複數個 第’、子晝素’依雜顺帛（i+5)th#酿線鮮(i+响條閑極線 之間’其中第-子晝素、第二子晝素、第五子晝素以及第六子晝 素連接於第-至第㈣th條資料線其中之一，第三子晝素及第四 子旦素連接於第二至第nth條資料線其中之一，其中第一子晝素及 第四子晝素包含第-彩色子晝素，第二子晝素及第五子晝素包含 第-形色子晝素以及第三子晝素及第六子晝素包含第三彩色子查 素。 旦 200828251 面本發明之液晶顯示裝置 數個畫素晶格，报+ ^ 3 ·液日日面板，包含複 形成於m+1條資料線與 中，沿資料绩古^去 /、（卞閑極線定義之區域 π 貝科、線方向重複地排列三種 的顏色；μ極内建觀 、/α雜線方向排列相同 」爛建電路，供朗極開 閘極線；m电&主液晶面板中形成的 _深，歸積體電路，形成於液 且供岸資料綠如_ 反中，驅動閘極内建電路 =應_早兀及框單元中反向的視頻訊號至:_，以及挽 性印刷電路’連接液晶面板至外部驅_統。 ^ 可以理解的是，如上所述 之 本發明之詳_祕H 扣__和隨後所述的 、 =疋/、有代表性和解釋性的說明，並且是為了 進一步揭示本發明之申請專利範圍。 【實施方式】 結合附圖所示之例子詳細說明本發明之較佳實施例。 「「第1 ®」係為本發明第—實補之液晶顯示裝置之示意圖。 「第1圖」中’液晶顯示裝置包含液晶面板勘，其中包含由複數 條資料線DL以及複數條閘極線GL之交叉部所定義之複數個^ 晶格110。畫素晶格110 &含沿資料線方向或者垂直方向交替排列 的二種顏色以及沿閘極線方向或水平方向排列的相同顏色。 閘極内建電路120，嵌裝於液晶面板100内，用於驅動閘極線 GL，以及驅動積體電路130,裝設至液晶面板1〇〇，用於驅動閘極 内建電路120且供應視頻訊號至資料線DL。撓性印刷電路2〇〇， 接合於液晶面板100，用於連接液晶面板1〇〇至外部驅動系統（圖 10 200828251 中未表示）。 液晶面板100包含下基板102與上基板104,彼此正對接合； 分隔物（圖中未表示），用於維持下基板1〇2與上基板1〇4之間固 疋的分子間隙，以及液晶層（圖中未表示），填充於分隔物提供的 液晶空間中。 下基板102包含與上基板104對應的顯示區域以及除去顯示 區域之非顯示區域。下基板102之顯示區域中，複數條資料線Dl 沿第一方向依照預定間隔彼此平行形成，複數條閘極線gl沿第二 方向依照預定伽彼辭行形成，以及晝素晶格nQ形成於複數 條資料線與閘極線定義之各區域處。第一方向垂直於第二方向。 供應視頻訊號的資料線DL的數目小於供應閘極開電壓之閑極線 GL的數目。 各晝素晶格110包含薄膜電晶體112，連接於閘極線GL與資 料線DL，以及晝素電極m，連接於薄膜電晶體m。各薄膜兩 GL，源電極，連接於資料線， 薄膜電晶體112沿資料線;ql 兩個垂直鄰接的畫素晶格11〇 晶體112包含閘電極，連接於閘極線〇乙; 以及汲電極，連接於畫素電極114。薄膜 交替排列於相對的側面上。就是說，兩個 之薄膜電晶體112連接至不同的資料、線DL。因此，連接於奇數號BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which can reduce production cost and power consumption by reducing the number of data lines. [Prior Art] A liquid crystal display (LCD) device uses an electric field to control the light transmittance of a liquid knives to impart an image. Generally, a liquid crystal display device provides a liquid crystal panel comprising a liquid crystal between two glass substrates, a matrix of liquid crystal molecules, and an interaction device for respectively changing signals in the liquid crystal molecules; a driving circuit for driving the liquid crystal panel, and a backlight The unit directs light onto the LCD panel. Closely, the number of signal lines or the number of circuit components of the liquid crystal panel is reduced to develop a thin and low-cost liquid crystal display device. For example, Korean Patent Publication No. 10-2003-0039972 discloses a liquid crystal display device for a single wafer on glass, in which an integrated driving wafer for driving a liquid crystal display panel is mounted on the periphery of a display area to reduce the size of the panel. And the production cost of the device. The liquid crystal display device of the single-wafer on glass of the prior art has the following disadvantages. The color pixel lattice in the unitary halogen contains a vertical strip structure such that the color pixel lattices are arranged in the horizontal direction (the direction of the gate line) of the liquid crystal display panel. Each color pixel lattice requires a single lying data line. As the number of data lines is increased, the size of the integrated drive wafer is also increased. Only a small-sized liquid crystal display device, for example, a resolution of 360 X 16G ' can use a glass-on-one-chip type liquid crystal display device. In order to obtain a higher resolution device, the glass-on-a-chip type liquid crystal display device, for example, selects a circuit to be a circuit outside the jaw, and the active period of the line, the % of the circuit, at the gate (4) During the period, according to the time series division, the supply is reduced to a plurality of resources, and the number of the materials is reduced. However, the ', and 4 lines are reduced, so that the use of the selection circuit, the six R - the allowable electricity, is reduced. . Therefore, the resolution of the inch, liquid_display panel is limited by *. In addition, the analogy of the output of each channel of the 躺 昼 昼 麟 充电 充电 充电 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 类 类 类 类 类 类 类 类 类 类 类 类 类SUMMARY OF THE INVENTION The present invention provides an embodiment of the present invention, which provides one or more problems caused by nT, manufacturing, and disadvantages. The purpose of this publication is to reduce the production cost and power consumption by Wei Jing, which displays the number of lines. Another object of the embodiment of the present invention is to provide an improved image quality for a liquid crystal display device. Further features and advantages of the present invention will be partially explained in the following descriptions. The present invention is based on the fact that the general practitioners of the present invention can use the following paragraphs. It is understood or can be derived from the actual shots of the present invention. The purpose of the present invention and the bribes thereof can be realized and obtained by the specification and the cap patent of the present invention and the combination of the drawings. In order to obtain these and other advantages of the present invention, a liquid crystal display device of the present invention includes: a plurality of data lines including a first data line and a second data line. , substantially parallel to each other; a plurality of gate lines, including a first gate line, a second gate line, and a third gate line, which are arranged parallel to each other on the solid shell, and the gate line intersects the data line; a plurality of sub-books , defined by the crossed gate lines and the data lines, at least three sub-tenucine, arranged directly along one of the adjacent data lines and corresponding to different colors to form a halogen; and driving the integrated circuit, sequentially driving the first 1. The second and third gate lines are in a horizontal period, wherein during the horizontal period, the first signal supplied to the first sub element of the pixel and the second signal supplied to the second sub element of the element are The polarity is opposite, and the polarity of the third signal supplied to the third sub-character of the pixel is the same. In another aspect, a method of driving a liquid crystal display device includes a plurality of data lines, a plurality of gate lines, and a plurality of pixels defined by a data line and a gate line, each element comprising three sub-pixels The driving method of the liquid crystal display driving device comprises: driving three gate lines sequentially in each horizontal circumference of the first frame during the first frame period. Supply the first polarity video signal to the odd number data line, and supply the second polarity video signal to the even number (four) line in the first frame, the towel level and each element, and supply to the first child The first signal is opposite in polarity to the second signal supplied to the second sub element, and the third signal is supplied to the third sub element. In another aspect, the liquid crystal display device of the present invention comprises m gate lines, m is a positive number greater than one, η data lines, n is an integer greater than two; and a plurality of first color 200828251 color subdatin 'arranged in Between the first ith gate line and the (i+1)th gate line, a plurality of the first -$ dice are arranged in the fourth (th) and thth lines and the (M)th idle line. And a plurality of third color sub-pixels arranged between the (i+2)th gate line and the (i+3)th gate line, wherein the first color sub-element and the third The color sub-halogen is connected to the _ of the first to fourth (four) strip data lines, and the second color sub-halogen is connected to the second to nth data lines. In another aspect, the liquid crystal display device of the present invention includes m gate lines, m is an integer greater than , , n data lines, n is an integer greater than two; and a plurality of _ sub-success' are sequentially arranged Between the first gate line and the (i+1)th non-gate line, a plurality of first sub-tenucines are sequentially arranged in the (i+l strip gate line and the first (丨+2) Also, between the gate lines, a number of third color sub-tendins are sequentially arranged in the first (1+2 punch gate line 舁 (i+3)th gate line, plural number The four sub-salmons are arranged in sequence between the (i+3)th i卞 gate line and the (1+4 pool bar gate line, and the plurality of fifth sub-tenors, sequentially arranged in the (i) +4) between the th gate line and the (i+5)th gate line, the plural number ', 昼子素' 杂 帛 帛 (i+5)th# Between the idle line, the first sub-salmon, the second sub-salm, the fifth sub-salmon, and the sixth sub-salm are connected to one of the first to fourth (th)th data lines, and the third sub-salmon and The fourth sub-denier is connected to one of the second to nth data lines, wherein the first sub-element and the fourth sub-halogen comprise the first- The color meringin, the second sub-halogen and the fifth sub-halogen comprise a first-dimensional sarcoplasmic and the third sub-halogen and the sixth sub-halogen comprise a third color sub-character. The liquid crystal display device has a number of pixel lattices, reported + ^ 3 · liquid day and day panels, including complex formation in m+1 data lines and in the middle, along the data record ancient ^ go /, (卞 idle line defined area π Becco, the line direction is repeatedly arranged in three colors; μ pole built-in view, /α miscellaneous line direction is the same" rotten circuit, for Langji open gate line; m electric & main liquid crystal panel formed _ deep , the convolutional body circuit, formed in the liquid and the shore data green as _ counter, drive the gate built-in circuit = should be _ early and the frame unit reverse video signal to: _, and the pull-up printed circuit 'connection LCD panel to external drive. ^ It is understood that the detailed description of the present invention as described above and the following, = 疋 /, representative and explanatory description, and for the purpose The scope of the patent application of the present invention is further disclosed. [Embodiment] Detailed description will be given with reference to the examples shown in the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS ""1"" is a schematic diagram of a liquid crystal display device of the first embodiment of the present invention. In "Fig. 1", a liquid crystal display device includes a liquid crystal panel, which includes a plurality of data lines. a plurality of ^ lattices 110 defined by the intersection of the DL and the plurality of gate lines GL. The pixel lattice 110 & includes two colors alternately arranged along the direction of the data line or in the vertical direction and along the gate line direction or level The same color is arranged in the direction. The gate built-in circuit 120 is embedded in the liquid crystal panel 100 for driving the gate line GL, and driving the integrated circuit 130 to be mounted to the liquid crystal panel 1 for driving the gate The built-in circuit 120 supplies the video signal to the data line DL. The flexible printed circuit 2 is bonded to the liquid crystal panel 100 for connecting the liquid crystal panel 1 to an external driving system (not shown in FIG. 10 200828251). The liquid crystal panel 100 includes a lower substrate 102 and an upper substrate 104, which are directly joined to each other; a separator (not shown) for maintaining a molecular gap between the lower substrate 1〇2 and the upper substrate 1〇4, and a liquid crystal A layer (not shown) is filled in the liquid crystal space provided by the separator. The lower substrate 102 includes a display area corresponding to the upper substrate 104 and a non-display area in which the display area is removed. In the display region of the lower substrate 102, a plurality of data lines D1 are formed in parallel with each other along a predetermined interval in a first direction, a plurality of gate lines gl are formed in accordance with a predetermined gamma in a second direction, and a pixel lattice nQ is formed in the plural Each area defined by the data line and the gate line. The first direction is perpendicular to the second direction. The number of data lines DL supplying video signals is smaller than the number of idle lines GL supplying the gate opening voltage. Each of the pixel cells 110 includes a thin film transistor 112 connected to the gate line GL and the material line DL, and a halogen electrode m connected to the thin film transistor m. Two GL films, a source electrode, connected to the data line, the thin film transistor 112 along the data line; ql two vertically adjacent pixel lattices 11 〇 crystal 112 including a gate electrode connected to the gate line B; and a 汲 electrode Connected to the pixel electrode 114. The films are alternately arranged on opposite sides. That is, the two thin film transistors 112 are connected to different materials, lines DL. Therefore, connected to the odd number
11 200828251 DL2 DLm+l之視頻訊號至各自的晝素電極Μ。畫素電極η4 的短邊平行於資料線DL，形成的短邊比平行於閘極線gl的長邊 短。因此，晝素電極114形成水平帶。 下基板102的非顯示區域中，閘極内建電路12〇連接於各複 .數條閘極線GL，並且裝設有驅動積體電路13〇。上基板刚包含 彩色濾光片、共同電極以及蔽光層。共同電極可以形成於下基板 102之上，取決於液晶層的液晶。形成的彩色滤光片包含紅 片、綠色濾光片以及藍色濾光片，沿資料線DL方向交替排列'；*並 且沿閘極線方向排列相同顏色的彩色濾光片。 共同電極可以貫通上基板104而形成或者形成線狀與晝素電 極114相對㈣成通過液晶層的垂直電場。或者，共同電極可以 形成於下基板102之上，平行於晝素電極114以形成通過液晶層 之水平電場。 敝光層开》成於上基板104之上，以重疊於與晝素電極重 疊之不包含開口區域之區域。各自位於紅色濾光片、，綠色遽光片 '以及藍色航片上的各紅、綠以及藍色晝素晶格係為—個彩色影 像之單元晝素。 撓性印刷電路200被提供至下基板搬之非顯示區域且接合 於下基板102之墊部。撓性印刷電路200傳送輪入功率νώ、來源 ，資料訊號Data以及來自驅動系統之同步訊號DE、Dclk、 及Vsync至驅動積體電路130。此外，撓性印刷電路2〇〇包含有壯 12 200828251 設的被動元件，例如電阻训、電容器22〇以及電感23〇。 駆動知體電路13〇被裝設至積體電路裝設部，積體電路裳設 部在下基板搬之非顯示區域處包含複數個輸入/輪出塾。驅動 m包含_固輸入^輪出凸塊，各自電連接於積體電 路裝設部處的輸人/輪出墊。料，驅_舰路⑽產生閑極 驅動訊號以及資料驅動訊號。透過使用來自撓性印刷電路細之 同步訊號DE、DCLK、Hsync及Vsync至少其中之一，驅動積體 電路130劃分與一個週期的水平同步訊號對應的一個水平 週期為第-至第二子週期。此外，驅動積體電路l3Q排列來源資 料訊號Data，對應於第―至第三子週_紅色歸r、綠色資料 G以及監色倾B ’觀紅色資料R、綠色資料G以及藍色資料B 為類比視頻訊號，以及供應視頻訊號至資料線DL。 「第2圖」係為「第1圖」所示之驅動積體電路之方塊圖。 請參考「第2圖」，驅動積體電路13〇包含訊號延遲單元31Q、第 一電源產生單元320、時脈產生單元322、參考電壓設定單元324 以及弟一電源產生單元326。驅動積體電路130還包含共同單元產 生單元328、訊號控制單元330、控制訊號產生單元340、電壓拉 升單元350、灰階電壓產生單元360以及資料轉換單元380。訊號 延遲單元310延遲來源資料訊號Data以及來自撓性印刷電路2〇〇 之同步訊號DE、DCLK、Hsync及Vsync (如「第1圖」所示） 進入訊號控制單元330。訊號控制單元330控制訊號延遲單元31〇 13 200828251 以及驅動積體電路130中其他電路之驅動。 %脈產生單兀322產生3夺脈，用於驅動第—及第二電源產生 單元320及326。第一電源產生單元32〇產生第一電源，就是說， 依照來自時脈產生單元322之_ ’使用來自撓性印刷電路· (如「第1圖」所示）之輸入功率Vin產生第—及第二參考電壓 VSP及VSN。此外，例如繞性印刷電路200 (如「第！圖」所示） 上的包阻210、電容器220以及電感230等被動元件，透過電源訊 唬線321a、321b以及321c連接於第一電源產生單元32〇，並且用 於偏壓第一電源產生單元320產生的第一及第二參考電壓vsp及 VSN，或者用於設定驅動積體電路13〇之選項功能。 透過使用第一電源產生單元320產生的第一及第二參考電壓 VSP及VSN，第二電源產生單元326產#驅動液晶面板_所需 的第一包源’即第_及第二驅動電壓及V%、積體電路驅動 電壓Vcc、閘極開啟電壓Von以及閘極關閉電壓v〇ff。 麥考電壓設定單元324設定第一及第二參考電壓vsp及vSN 之位準’從第一電源產生單元320供應至灰階電壓產生單元36〇。 透過使用來自第二電源產生單元326的供應至撓性印刷電路2〇〇 上的被動元件的第一及第二驅動電壓Vdd及Vss，共同電壓產生 單元328產生共同電壓Vcom以供應至液晶面板1〇〇之共同電極。 撓性印刷電路200包含共同電壓變更單元（圖中未表示），透過使 用笔阻或電谷裔（圖中未表示）至少其中之一變更共同電壓產生 14 200828251 單元328所產生的共同電壓Vcom。 訊號控制單元330供應來自訊號延遲單元31〇之同步訊號 DE、DCLK、Hsync以及Vsync至控制訊號產生單元34〇。透過使 用來自訊號控制單元330之同步訊號DE、DCLK、Hsync以及Vsync 至少其中之一，控制訊號產生單元340產生資料控制訊號DST、 DSC、DOE以及DPS與閘極驅動訊號Rvst以及rclkI至 RCLKi。資料轉換單元380包含位移暫存器381、閂存單元383、 數位/類比轉換單元385、缓衝器單元387以及選擇單元389。 「第3圖」係為「第2圖」.所示之訊號控制單元所分類之資 料訊號之示意圖。請參考「第3圖」，訊號控制單元33()還排列來 自訊號延遲單元310之來源資料訊號，用於驅動液晶面板1〇〇，並 且供應排列的資料至資料轉換單元380。尤其地，訊號控制單元 330排列來自訊號延遲單元31〇之一個水平週期的來源資料訊號 為紅色資料R、綠色資料G以及藍色資料B，對應於第一至第三 子週期1ST、2ST以及3ST。 水平週期的第一子週期1ST期間，訊號控制單元330重新排 列I過排列的紅色資料r為奇數號的紅色資料至^以 待被供應至第一至第(m)th資料線£^1至〇1^中的奇數號資料線 DL1、DL3〜DLm4，以及重新排列為偶數號的紅色資料rei至 REm/2以待被供應至偶數號資料線DL2、DL4...DLm。然後，水 平週期的第二子週期2ST期間，訊號控制單元330重新排列經過 15 200828251 排列的綠色資料G為奇數號的綠色資料G〇l至G〇m/2以待被供 應至第二至第(m+l)th資料線DL2至DLm+1中的偶數號資料線 DU、DL4...DLm，以及重新排列為偶數號的綠色資料GE1至 GEm/2以待被供應至奇數號資料線DL3、DL5...DLm+；l。類似地， 水平週期的第三子週期3ST期間，訊號控制單元33〇重新排列經 過排列的藍色資料B為奇數號的藍色資料B01至BOm/2以待供 應至第一至第(m地資料線DU &DLm中的奇數號資料線1)1^、 DL3...DLm-l，以及重新排列為偶數號的藍色資料βει至BEm/2 以待供應至偶數號資料線DL2、DL4...DLm。 ‘號控制單元330還供應輸出自訊號延遲單元31〇之同步訊 號DE、DCLK、Hsync以及Vsync至控制訊號產生單元340。透 過使用訊號控制單元330輸出的同步訊號DE、DCLK、Hsync以 及Vsync至少其中之一，控制訊號產生單元34〇產生資料控制訊 號DST、DSC、DO E以及DPS與閘極驅動訊號RVs以及RCLK1 至RCLKi。資料控制訊號DST、DSC、DOE及DPS包含資料開 始訊號DST、資料位移時脈DSC、資料輸出訊號D〇E以及資料 極性訊號DPS，用於控制資料轉換單元38〇。控制訊號產生單元 340供應不同極性的視頻訊號至鄰接的資料線见，並且產生資料 極性訊號，在至少一個框單元中用於反向被供應至資料線DL之視 頻訊號極性。控制訊號產生單元340產生一行反向類型的資料極 性訊號DPS，反向資料線單元以及至少一個框單元的視頻訊號的 16 200828251 極性。 閘極驅動訊號RVs以及RCLK1至RCLKi包含閘極開始訊號 RVst以及第一至第(i)th時脈訊號RCLK1至RCLKi，用於驅動問 極内建電路120。第一至第(i)th時脈訊號RCLK1至RCLKi包含依 序延遲的相位’從而第一至第(i)th時脈訊號RCLK1至RCLKi包 含的脈衝覓度能夠各自打開各子週期的薄膜電晶體。第一至第①伍 日守脈§fl號RCLK1至RCLKi可以包含二、四、六、八或者十個相 位其中任意之一，取決於閘極内建電路12〇。 透過使用供應自第二電 ' 事 〜·丨厂一，叮私/尖 νυη 以及閘極關電壓Voff，電壓拉升電路35Q拉升供應自控制訊號 產生單兀340之閘極驅動訊號RVs以及RCLK1至此通的電壓 位準。閘極 VQn係為打開各晝素晶格⑽之薄膜電晶體 112之電壓，閘極關閉電壓v〇ff係為關閉各晝素晶格ιι〇之薄膜 包曰日版m之包壓。電壓拉升電路35〇供應經過拉升的閘極驅動 以及CLK1至CLKi通過下基板i 02的非顯示區域處的閑 極驅動訊號傳輸線140至閘極内建電路12〇。 ^白―產生早兀360細分來自第一電源產生單元32〇之第 第/考包£ VSP及VSN，以產生複數個灰嘴電壓 ’並且供 ^複數個灰階電壓至資料轉換單^潘如果來源資料訊號d她 =N個位元，複數個灰階賴產生挪個正極性灰階電壓以及 2N個負極性灰階電壓。 17 200828251 触來自控制訊號產生單心4Q之資料位移時脈dsc，位移 暫存器381依序移位資制始訊號贿，以產生位移訊號％。位 私暫存器381可以為具有兩個方向的位移暫存器，依照來自訊號 控制單元330之導向訊號被驅動於相反的方向。 b 問存單元383回應於來自位移暫存器381之位移訊號％，依 序問存來自訊號控制料现之線路總數之魏紅綠藍職，並 且依照來自控制訊號產生單元340之資料輸出訊號d〇e，供應線 路總數的贴資料RData至數位/類比轉換單元385。 透過使用來自灰階電壓產生單幻6Q的複數個正極性的灰階 電壓以及負極性的灰階電壓，數位/類比轉換單元385轉換供應 自閃存單元383的閃存資料RData為正極性及負極性的視頻訊號 pvs及nvs。數位//類比轉換單元385從複數個正極性灰階電壓 中每擇與卩特資料RData的灰p綠對應的—個灰階電墨作為正極 II視頻5孔號PVS ’並且從複數個負極性灰階電壓中選擇與閂存資 料RData的灰階值對應的一個灰階電壓作為負極性的視頻訊號。 使用通過撓性印刷電路200的被動元件的來自第一電源產生 單元320的第一及第二驅動電壓vdd及Vss，緩衝器單元％?缓 衝正極性以及負極性視頻訊號PVS以及nvs。例如，考慮到資料 線DL上的負載，緩衝器單元387放大正極性以及負極性視頻訊號 PVS 以及 NVS。 依照來自控制訊號產生單元340的資料極性訊號DPS，選擇 18 200828251 單元，389選擇供應自緩衝器單元387的正極性或者及負極性視頻 訊號PVS或者NVS，並且透過第一至第(m+1)th輸出通道供應選 擇的視頻訊號至資料線DL。例如，依照資料極性訊號Dps，輸出 自廷擇單tl 389㈣視頻訊號的極性在輸出通道單元以及框單元中 被反向。 凊麥考「第1圖」，閘及内建電路12〇形成於下基板皿的非 顯示區域’同時形成薄膜電晶體112，閘極内建電路12G各自連接 於複數條閘極線GL。_鱗電路12Q於每個子週誠生問極開 啟電壓V〇n，回應於供應自驅動積體電路130雜升問極驅動訊號 Vst以及CLK1至CLKi，並且依序供制關啟輕ν〇η至閘極 線GL例如’透過下基板1〇2轉顯示區域處形成的複數個開極 驅動訊號傳輸線14〇，驅動積體電路13〇供應拉升的閑極驅動訊號 Vst以及CLK1至CLKi至間極内建電路12〇。 弟4圖」係為本發日㈣—實施例之液晶顯示|置之驅動: 形之不意圖。參考「第4圖」以及「第1圖」描述本發明第-2 施例之具有代表⑽液晶顯示裝置之鶴。例如，第—水平週』 ，細分為第-至第三子週期，紅色、綠色以及藍色視頻訊細 颁不於子處，以混合紅色、騎以及藍色視頻，從而共同· 不一個彩色視頻。 . ^欠平週期的第一子週期處，同步供應第-至第(m)th資寿 各DL1至DLm之間極開啟電墨—至第一閑極線如，正極七 19 200828251 的紅色視頻訊號R+被供應至奇數號資料線DL—〇dd，並且負極性 的視頻訊號R-被供應至偶數號資料線〇]^一〜沈。因此，第一水平 線的晝素晶格110中’奇數號之晝素晶格nG顯示對應於正極性 的紅色視細號R+的紅色視頻，偶數狀晝素晶格m顯示對應 於負極性紅色視頻訊號厌_的紅色視頻。 第-水平週期的第二子週期，同步供應第二至第(m+1)th資料 線DL2至DLm+1之間極開啟電墨v〇n至第二閘極線阳，正極 性的綠色_贼G+健應至奇數鱗DL」)dd，負極性的 綠色視頻訊號G-被供應至偶數號資料'線见一⑽。因此，第二水 平線的晝素晶格110中’奇數號之晝素晶格11〇顯示對應於負極 性綠色視賴號G_的騎視頻，偶數號之晝素晶格m顯示對應 ^正極性綠色視麵號以的騎視頻。因此，㈣直方向鄰翻 弟-及第二水平線中的晝素晶格11Q所顯示的視頻訊號彼此包含 不同的極性。 第水平週期的第三子週期，同步供應第一至第帅匕資料線 DL1至DLm之閘極開啟電壓v〇n至第三閘極線gl3，正極性藍 色視頻訊號B+驗絲物賴橡沉-娜，貞雜藍色視頻 心虎B-被供應至偶數號資料、線DL—e彻。因此，第三水平線的晝 ’、° 1〇中可數號之晝素晶格11()顯示與芷極性藍色視頻訊 號β對應的^色視頻’偶數號之晝素晶格η〇顯示與負極性藍色 旦素Λ號B-對應的監色視頻。因此，沿垂直方向鄰接的第二及第 20 200828251 200828251 所顯示的视頻訊號包含彼此不同的極 二水平線中的晝素晶格110 性0 結果，第一水平週期期間， . 、、、綠色以及藍色視頻依序· 二色^紅色、綠色以及藍色視頻，從而共同顯示一. 形色視頻。類似地，各水平週_晝素晶格依照與上述第-水平 週期相同的方法顯示-個彩色晝素。_，下 的極性如上肢向。 ^ofL^ 二此，嫩素晶格n。上的_電晶魏沿資料線沉 父曰排列於相對_面之上’從驅動積體電路⑽供應至液晶面 之u订反向翻極性型樣的視頻訊號顯示於點反向 的極性型樣中。 μ弟5圖」係為本發明第二實施例之液晶顯示裝置之示意圖。 如「弟5圖」所示’第二實施例之液晶顯示裝置與第—實施例類 似’但疋各晝素晶格11〇㈣列除外。因此，第二實施例之以下 解釋將關注於各晝素晶格11G之_上。如上所述，第二實施例 之液晶顯示裝置之其他部與第一實施例類似。 如「第5圖」所示，沿鄰接資料線沉排列於相對側面之上的 每兩個晝素晶格m交替連接於鄰接的資料線dl其中之一。例 如，連接於第_)㈣整維條·線GL4k_3之各晝素晶格 no直接地連接於左侧鄰接的資料線；連接於第件華條閑極線 GL4k-2的各晝素晶格11〇直接地連接於左側鄰接的資料線。另一 21 200828251 方面，連接於第(4k-l)th條閘極線GL.i的各晝素晶才各ιι〇直接 =連接於右側鄰接的龍線；連接於第(修條_線GL4k的各 晝素晶格110直接地連接於右側鄰接的資料線。 輸出自積體電路130之視頻訊號被供應至連接於各晝素晶格 之資料線。此k ,視頻说號的極性被反向於資料線單元以及至少 他單元中。因此’因為各晝素晶格110的每兩個薄膜電晶體 112沿資料線DL交替地排列於其相對側面之上，包含行反向類型 極性型樣的視頻訊號從驅動積體電路13〇被供應至液晶面板ιι〇， 顯示為垂直的兩點反向類型的極性型樣。此時，視頻訊號之極性 透過兩點反向類型極性型樣被反向於每兩個晝素晶格單元以及資 料線單元中。 依照本發明第二實施例，供應自驅動積體電路13〇之視頻訊 號以垂直兩點反向類型顯示於液晶面板1〇〇之上，透過防止出現 閃點（dot-flicker)缺陷以改善影像品質^此外，依照本發明第二 實施例，供應自驅動積體電路130之視頻訊號之極性被反向於至 少一個框單元中，以增加各晝素晶格11〇之充電時間並且防止視 頻訊號之延遲。 .如上所述，本發明實施例之液晶顯示裝置中，組成包含水平 帶狀結構的晝素晶格的單元晝素晶格排列為垂直方向，從而減少 資料線的數目。因此，本發明實施例之液晶顯示裝置可用於大尺 寸的液晶顯示裝置以及小尺寸的液晶顯示裝置。 22 200828251 如上所述，本發明實施例之液晶顯示裝置中，各晝素晶格ιι〇 之上的每一個或兩個薄膜電晶體112沿資料線见交替排列於相對 的側面之上。並非限制於上述解釋。例如，用於各晝素晶格⑽ 之每三彳_膜電晶體m沿鄰接的資料線DL排列帅對的側面之 上，可交替地連接於鄰接的資料線01^其中之一。 因此，本發明貫施例之液晶顯示裝置具有以下優點。首先， -個驅動積體嵌裝於液晶面板内，液晶面板之鶴減少單元 ，本並且最小化液晶顯示裝置的厚度。第二，資料線單元以及框 單70中的視頻訊號之極性反向允許減少功率雜。第三，視頻訊 號的極性改Μ的最小化提供足夠的視頻訊號充電時間週期並且改 像細’晝素晶格沿水平方向翻允許減少第三條資 料線數目i從而可彻大尺寸·晶顯示面減小尺寸的液晶顯 不面板H包含行反向_極性型樣的視頻訊號以垂直兩點 反向類型被顯示’透過防止例如閃點等缺陷而改善影像品質。第 i、應自轉積體電路之視縣號之極性被反向於至少一健 早兀中’以增加各晝素晶格110之充電時間並且防止視頻訊號之 延遲，從而改善影像品質。 卜本I明只施例之液晶顯示裝置被驅動於列反向方案 令，以點反向其中的晝素電極。例如，根據本發明實施例之晝素 晶格之侧，液轉示裝置被驅祕狀向方案，妹得一點反 σ β方木的效果。或者根據本發明另—實施例之晝素晶格排 23 200828251 列液曰曰_不裝置驅動於列反向方案以得到兩點反向驅動方案之 效果。 匕卜僅僅具有一個驅動積體電路之液晶面板之驅動減少了 w電路之尺寸，並且減少了撓性印刷電路之單元成本。另 瓜衣於液日日面板中之閘極線之閘極驅動器消除了驅動積 體電路、閘極撓性印刷電路以及閘極印刷電路板之使用。並且， 僅僅具有液晶顯示面缝造製程、驅_體電路裝設製程以及撓 科刷電路接合t程之液晶顯示裝置之製造使用了簡化的製造製 程，從而最小化缺陷比率。 _本發明以前述之實施例揭露如上，然其並非用以限定本 二ΓΓ本發明之精神和範圍内，所為之更動與潤飾，均 知^附護範圍之内° _本發明所衫之保護範圍請 苓妝所附之申請專利範圍。 [圖式簡單說明】 第1圖所示為本發明第—實施例之液晶顯示裝置之亍音3. 第2圖所示Λ繁1FI辦-4 衣1义不思圖， —S行為弟！圖所不之驅動積體電路之方塊圖； 第3圖所示為第2圖所示 之示意圖； 虓控制早卿分類之資料訊號 之示糊第—輪㈣輪版·波形 第5圖所示林發明第二魏例之液晶顯示裝置之示意圖； 24 液晶面板 下基板 上基板 晝素晶格 薄膜電晶體 晝素電極 閘極内建電路 驅動積體電路 閘極驅動訊號傳輸線 撓性印刷電路 電阻 電容器 電感 訊號延遲單元 第一電源產生單元 321c 電源訊號線 時脈產生單元 參考電壓設定單元 第二電源產生單元 共同電壓產生單元 200828251 【主要元件符號說明】 100 102 104 110 112 114 120 130 140 200 210 220 230 \ 310 320 321a、321b 322 324 326 328 25 200828251 330 訊號控制單元 340 控制訊號產生單元 350 電壓拉升單元 360 灰階電壓產生單元 380 資料轉換單元 381 位移暫存器. 383 閂存單元 385 數位/類比轉換單元 387 缓衝器單元 389 選擇單元 DL 資料線 GL 閘極線 DE、 DCLK、Hsync、Vsync 同步訊號 Vin 輸入功率 Data 來源資料訊號 DST 、DSC、DOE、DPS 資料控制訊號 RVst > RCLK卜··…RCLKi 閘極驅動訊號 Vst、 CLK1、…、CLKi 拉升的閘極驅動訊號 Von 閘極開啟電壓 Voff 閘極關閉電壓 RData 問存貢料 26 200828251 PVSss11 200828251 DL2 DLm+l video signal to their respective pixel electrodes. The short side of the pixel electrode η4 is parallel to the data line DL, and the short side formed is shorter than the long side parallel to the gate line gl. Therefore, the halogen electrode 114 forms a horizontal band. In the non-display area of the lower substrate 102, the gate built-in circuit 12 is connected to each of the plurality of gate lines GL, and is provided with a drive integrated circuit 13A. The upper substrate just contains a color filter, a common electrode, and a light shielding layer. The common electrode may be formed on the lower substrate 102 depending on the liquid crystal of the liquid crystal layer. The formed color filter includes a red chip, a green filter, and a blue filter, which are alternately arranged along the data line DL direction; * and color filters of the same color are arranged along the gate line direction. The common electrode may be formed through the upper substrate 104 or may form a vertical electric field that is linearly opposed to the halogen element 114 by the liquid crystal layer. Alternatively, a common electrode may be formed over the lower substrate 102 parallel to the halogen electrode 114 to form a horizontal electric field through the liquid crystal layer. The enamel layer is formed on the upper substrate 104 so as to overlap the region overlapping the halogen electrode and not including the opening region. The red, green, and blue elementary crystal lattices, each of which is located on the red filter, the green calender sheet, and the blue aerial image, are unitary elements of a color image. The flexible printed circuit 200 is supplied to the non-display area where the lower substrate is moved and bonded to the pad portion of the lower substrate 102. The flexible printed circuit 200 transmits the wheeling power νώ, the source, the data signal Data, and the synchronizing signals DE, Dclk, and Vsync from the driving system to the driving integrated circuit 130. In addition, the flexible printed circuit 2 includes a passive component such as a resistor, a capacitor 22, and an inductor 23A. The swaying body circuit 13A is mounted to the integrated circuit mounting portion, and the integrated circuit skirting portion includes a plurality of input/rounding ports at the non-display area where the lower substrate is moved. The drive m includes _solid input ^ wheel-out bumps, each of which is electrically connected to the input/wheel pad at the integrated circuit mounting portion. Material, drive_ship (10) generates idle drive signals and data drive signals. By using at least one of the fine signals DE, DCLK, Hsync, and Vsync from the flexible printed circuit, the driving integrated circuit 130 divides a horizontal period corresponding to one cycle of the horizontal synchronizing signal into a first to second sub-period. In addition, the driving integrated circuit l3Q arranges the source data signal Data, corresponding to the first to third sub-weeks _ red r r, the green data G, and the color grading B 'the red data R, the green data G, and the blue data B are Analog video signals, and supply video signals to the data line DL. "Fig. 2" is a block diagram of the drive integrated circuit shown in "Fig. 1". Referring to Fig. 2, the driving integrated circuit 13A includes a signal delay unit 31Q, a first power generating unit 320, a clock generating unit 322, a reference voltage setting unit 324, and a first power generating unit 326. The driving integrated circuit 130 further includes a common unit generating unit 328, a signal control unit 330, a control signal generating unit 340, a voltage pulling unit 350, a gray scale voltage generating unit 360, and a data converting unit 380. The signal delay unit 310 delays the source data signal Data and the synchronization signals DE, DCLK, Hsync and Vsync (shown in FIG. 1) from the flexible printed circuit 2 into the signal control unit 330. The signal control unit 330 controls the driving of the signal delay unit 31 〇 13 200828251 and other circuits in the drive integrated circuit 130. The % pulse generating unit 322 generates 3 pulses for driving the first and second power generating units 320 and 326. The first power generating unit 32 generates the first power source, that is, according to the input power Vin from the flexible printed circuit (shown in FIG. 1) from the clock generating unit 322. Second reference voltages VSP and VSN. Further, for example, the passive component such as the encapsulation 210, the capacitor 220, and the inductor 230 on the winding printed circuit 200 (shown as "FIG.") is connected to the first power generating unit through the power signal lines 321a, 321b, and 321c. 32〇, and used to bias the first and second reference voltages vsp and VSN generated by the first power generating unit 320, or to set an optional function of the driving integrated circuit 13A. By using the first and second reference voltages VSP and VSN generated by the first power generating unit 320, the second power generating unit 326 generates the first source and the second driving voltage required to drive the liquid crystal panel. V%, integrated circuit drive voltage Vcc, gate turn-on voltage Von, and gate turn-off voltage v〇ff. The McCaw voltage setting unit 324 sets the levels of the first and second reference voltages vsp and vSN' from the first power generating unit 320 to the grayscale voltage generating unit 36A. The common voltage generating unit 328 generates a common voltage Vcom to be supplied to the liquid crystal panel 1 by using the first and second driving voltages Vdd and Vss supplied from the second power generating unit 326 to the passive elements on the flexible printed circuit 2A. The common electrode of 〇〇. The flexible printed circuit 200 includes a common voltage changing unit (not shown) that changes the common voltage Vcom generated by the unit 28b by using at least one of the pen resistance or the electric (not shown). The signal control unit 330 supplies the sync signals DE, DCLK, Hsync, and Vsync from the signal delay unit 31 to the control signal generating unit 34A. The control signal generating unit 340 generates the data control signals DST, DSC, DOE, and DPS and the gate driving signals Rvst and rclkI to RCLKi by using at least one of the synchronization signals DE, DCLK, Hsync, and Vsync from the signal control unit 330. The data conversion unit 380 includes a shift register 381, a latch unit 383, a digital/analog conversion unit 385, a buffer unit 387, and a selection unit 389. Figure 3 is a schematic diagram of the information signals classified by the signal control unit shown in Figure 2. Referring to Fig. 3, the signal control unit 33() also arranges the source data signals from the signal delay unit 310 for driving the liquid crystal panel 1 and supplying the arranged data to the data conversion unit 380. In particular, the signal control unit 330 arranges the source data signals from one horizontal period of the signal delay unit 31 to be red data R, green data G, and blue data B, corresponding to the first to third sub-periods 1ST, 2ST, and 3ST. . During the first sub-period 1ST of the horizontal period, the signal control unit 330 rearranges the red data r of the I-arranged red data to an odd-numbered red data to be supplied to the first to (m)th data lines ^1 to The odd-numbered data lines DL1, DL3 DLDLm4 in 〇1^, and the red data rei to REm/2 rearranged to an even number are to be supplied to the even-numbered data lines DL2, DL4, ... DLm. Then, during the second sub-period 2ST of the horizontal period, the signal control unit 330 rearranges the green data G 〇l to G〇m/2 of the odd-numbered green data G arranged by 15 200828251 to be supplied to the second to the first (m+l)th even-numbered data lines DU, DL4...DLm in the data lines DL2 to DLm+1, and green data GE1 to GEm/2 rearranged to even numbers to be supplied to the odd-numbered data lines DL3, DL5...DLm+;l. Similarly, during the third sub-period 3ST of the horizontal period, the signal control unit 33 rearranges the blue data B01 to BOm/2 of the odd-numbered blue data B to be odd numbers to be supplied to the first to the (m) The odd-numbered data lines 1)1^, DL3...DLm-l in the data line DU & DLm, and the blue data βει to BEm/2 rearranged to an even number are to be supplied to the even-numbered data line DL2 DL4...DLm. The 'number control unit 330' also supplies the sync signals DE, DCLK, Hsync, and Vsync outputted from the signal delay unit 31 to the control signal generating unit 340. The control signal generating unit 34 generates the data control signals DST, DSC, DO E and DPS and the gate driving signals RVs and RCLK1 to RCLKi by using at least one of the synchronization signals DE, DCLK, Hsync and Vsync outputted by the signal control unit 330. . The data control signals DST, DSC, DOE and DPS include a data start signal DST, a data shift clock DSC, a data output signal D〇E, and a data polarity signal DPS for controlling the data conversion unit 38〇. The control signal generating unit 340 supplies video signals of different polarities to adjacent data lines, and generates a data polarity signal for reversely supplying the video signal polarity to the data line DL in at least one of the frame units. The control signal generating unit 340 generates a row of inverted type data polarity signals DPS, a reverse data line unit and at least one frame unit video signal 16 200828251 polarity. The gate drive signal RVs and RCLK1 to RCLKi include a gate start signal RVst and first to (i)th clock signals RCLK1 to RCLKi for driving the gate built-in circuit 120. The first to (i)thth clock signals RCLK1 to RCLKi include the sequentially delayed phase ' such that the pulse widths of the first to (i)thth clock signals RCLK1 to RCLKi can respectively turn on the thin film power of each sub-period Crystal. The first to the first day of the circumstance §fl number RCLK1 to RCLKi may contain any one of two, four, six, eight or ten phases, depending on the gate built-in circuit 12〇. The voltage pull-up circuit 35Q pulls up the gate drive signals RVs and RCLK1 supplied from the control signal generating unit 340 by using the second power supply, the first one, the / / 尖 尖, and the gate voltage Voff. The voltage level up to this point. The gate VQn is a voltage for opening the thin film transistor 112 of each of the pixel cells (10), and the gate closing voltage v〇ff is a package for closing the film of each of the individual crystal lattices. The voltage pull-up circuit 35 〇 supplies the pulled gate drive and the CLK1 to CLKi pass through the idle drive signal transmission line 140 at the non-display area of the lower substrate i 02 to the gate built-in circuit 12A. ^白-Generates the early 360 segment from the first power generation unit 32〇/the test package £VSP and VSN to generate a plurality of gray mouth voltages' and supplies a plurality of gray scale voltages to the data conversion unit Source data signal d she = N bits, a plurality of gray scales produce a positive gray scale voltage and 2N negative gray scale voltage. 17 200828251 Touching the data from the control signal to generate the single heart 4Q displacement clock dsc, the displacement register 381 sequentially shifts the capital message to generate the displacement signal %. The bit buffer 381 can be a shift register having two directions, which are driven in opposite directions in accordance with the pilot signal from the signal control unit 330. The memory unit 383 responds to the displacement signal % from the displacement register 381, sequentially stores the Weihong green blue job from the total number of lines of the signal control material, and outputs the signal d according to the data from the control signal generating unit 340. 〇e, the posted data RData of the total number of lines is supplied to the digital/analog conversion unit 385. The digital/analog conversion unit 385 converts the flash data RData supplied from the flash memory unit 383 into a positive polarity and a negative polarity by using a plurality of positive gray scale voltages and a negative gray scale voltage from the gray scale voltage to generate a single magical 6Q. Video signal pvs and nvs. The digit//analog conversion unit 385 selects, as the positive electrode II video 5 hole number PVS', from each of the plurality of positive polarity gray scale voltages corresponding to the gray p green of the data RData, and from the plurality of negative polarity A gray scale voltage corresponding to the gray scale value of the latch data RData is selected as the negative polarity video signal among the gray scale voltages. The buffer unit %? buffers the positive polarity and the negative polarity video signals PVS and nvs using the first and second driving voltages vdd and Vss from the first power generating unit 320 through the passive elements of the flexible printed circuit 200. For example, in consideration of the load on the data line DL, the buffer unit 387 amplifies the positive polarity and negative polarity video signals PVS and NVS. According to the data polarity signal DPS from the control signal generating unit 340, the 18 200828251 unit is selected, 389 selects the positive polarity or negative polarity video signal PVS or NVS supplied from the buffer unit 387, and passes through the first to the (m+1)th. The th output channel supplies the selected video signal to the data line DL. For example, according to the data polarity signal Dps, the polarity of the video signal output from the order tl 389 (four) is reversed in the output channel unit and the frame unit. The buckwheat test "Fig. 1", the gate and the built-in circuit 12 are formed in the non-display area of the lower substrate, and the thin film transistor 112 is formed at the same time, and the gate built-in circuits 12G are each connected to the plurality of gate lines GL. The squaring circuit 12Q asks the pole opening voltage V〇n in each sub-week, in response to the supply of the self-driving integrated circuit 130, the hybrid driving signal Vst and the CLK1 to CLKi, and sequentially supplies the gate ν〇η To the gate line GL, for example, 'a plurality of open-pole driving signal transmission lines 14' formed through the lower substrate 1〇2 to the display area, the driving integrated circuit 13〇 supplies the pulled-up idle driving signal Vst and CLK1 to CLKi to Extremely built-in circuit 12〇. Brother 4 is based on the current day (four) - the liquid crystal display of the embodiment | drive: the shape is not intended. A crane having a representative (10) liquid crystal display device of the second embodiment of the present invention will be described with reference to "Fig. 4" and "Fig. 1". For example, the first-horizontal week is subdivided into the first to third sub-periods, and the red, green, and blue video messages are not sub-divided to mix red, ride, and blue video, thus sharing a color video. . ^ At the first sub-period of the period of the low-level period, synchronously supply the first to the (m)th life DL1 to DLm between the extremely open ink - to the first idle line, such as the positive red seven 19 200828251 red video The signal R+ is supplied to the odd-numbered data line DL-〇dd, and the negative-level video signal R- is supplied to the even-numbered data line 〇]~~ sink. Therefore, in the first horizontal line of the pixel cell 110, the 'odd numbered elementary lattice nG displays a red video corresponding to the positive polarity red detail number R+, and the even numbered elementary crystal lattice m shows the corresponding negative polarity red video. The signal is tired of the red video. The second sub-period of the first-level period synchronously supplies the second to the (m+1)th data lines DL2 to DLm+1 between the pole-opening electric ink v〇n to the second gate line anode, and the positive polarity green _ thief G + health to odd scale DL") dd, negative green video signal G - is supplied to the even number of data 'line see one (10). Therefore, in the second horizontal line of the pixel plane 110, the 'odd number of the pixel lattice 11' shows the riding video corresponding to the negative polarity green image G_, and the even number of the primed lattice m shows the corresponding positive polarity. The green video is based on the ride video. Therefore, the video signals displayed by the (4) straight-direction neighbors and the pixel array 11Q in the second horizontal line contain different polarities from each other. The third sub-period of the first horizontal period synchronously supplies the gate turn-on voltage v〇n of the first to the first data lines DL1 to DLm to the third gate line gl3, and the positive blue video signal B+ the silk fabric Shen-Na, noisy blue video heart tiger B- is supplied to even-numbered data, line DL-e. Therefore, the prime pixel lattice 11() of the third horizontal line 昼', ° 1 显示 shows the binary video η 〇 of the ^ color video corresponding to the 芷 polarity blue video signal β A negative color blue denier B B- corresponding color monitor video. Therefore, the video signals displayed in the second and 20th 200828251 200828251 adjacent to each other in the vertical direction include the pixel lattice 110 in the two horizontal lines different from each other. During the first horizontal period, . , , , green, and blue Color video in sequence · two colors ^ red, green and blue video, together to display a. color video. Similarly, each horizontal _ 昼 晶 lattice is displayed in the same manner as the above-described first-level period. _, the polarity of the lower limbs. ^ofL^ Two, the tenderness lattice n. The upper _ electro-crystal is along the data line Shen father 曰 arranged on the opposite side _ the video signal from the driving integrated circuit (10) supplied to the liquid crystal surface of the u-turn reverse polarity pattern is displayed in the reverse polarity of the point In the sample. Fig. 5 is a schematic view showing a liquid crystal display device of a second embodiment of the present invention. The liquid crystal display device of the second embodiment is similar to that of the first embodiment except that the column of each of the individual crystal lattices 11 (four) is excluded. Therefore, the following explanation of the second embodiment will focus on the top of each of the pixel lattices 11G. As described above, the other portions of the liquid crystal display device of the second embodiment are similar to those of the first embodiment. As shown in Fig. 5, each of the two pixel crystal lattices m arranged on the opposite side along the adjacent data line is alternately connected to one of the adjacent data lines dl. For example, each of the pixel lattices no connected to the _) (four) dimension strip GL4k_3 is directly connected to the adjacent data line on the left side; each pixel lattice connected to the first strip line GL4k-2 11〇 is directly connected to the adjacent data line on the left side. On the other hand, in the aspect of 200828, the individual crystals connected to the (4k-l)th gate line GL.i are directly connected to the adjacent long-distance line; connected to the first (repair_line GL4k) Each of the pixel cells 110 is directly connected to the data line adjacent to the right side. The video signal output from the integrated circuit 130 is supplied to the data line connected to each of the pixel cells. The polarity of the k, the video number is reversed. For the data line unit and at least the other unit. Therefore, because each of the two thin film transistors 112 of each of the pixel cells 110 are alternately arranged on the opposite side of the data line DL, including the row reverse type polarity pattern The video signal is supplied from the driving integrated circuit 13〇 to the liquid crystal panel, and is displayed as a vertical two-point reverse type polarity pattern. At this time, the polarity of the video signal is reversed through the two-point reverse type polarity pattern. For each of the two pixel cell units and the data line unit, according to the second embodiment of the present invention, the video signal supplied from the driving integrated circuit 13 is displayed on the liquid crystal panel in a vertical two-point reverse type. On, by preventing flash points (dot-fl In addition, according to the second embodiment of the present invention, the polarity of the video signal supplied from the driving integrated circuit 130 is reversed to at least one of the frame units to increase the pixel lattice 11 The charging time and the delay of the video signal are prevented. As described above, in the liquid crystal display device of the embodiment of the invention, the unit cell lattice constituting the pixel lattice including the horizontal strip structure is arranged in the vertical direction, thereby reducing the data line. Therefore, the liquid crystal display device of the embodiment of the present invention can be used for a large-sized liquid crystal display device and a small-sized liquid crystal display device. 22 200828251 As described above, in the liquid crystal display device of the embodiment of the present invention, each of the pixel crystal lattices Each of the two or two thin film transistors 112 above the ιι〇 is alternately arranged on the opposite side along the data line. It is not limited to the above explanation. For example, for each of the three crystals (10) The crystal m is arranged on the side of the pair of adjacent data lines DL, and is alternately connected to one of the adjacent data lines 01. Therefore, the liquid of the embodiment of the present invention The display device has the following advantages. First, a driving integrated body is embedded in the liquid crystal panel, the crane of the liquid crystal panel reduces the unit, and the thickness of the liquid crystal display device is minimized. Second, the data line unit and the video in the frame 70 The polarity of the signal is reversed to allow for reduced power mismatch. Third, the minimization of the polarity of the video signal provides sufficient video signal charging time period and the image is changed to a fine '昼 晶 lattice, which is horizontally turned to allow the third data line to be reduced. The number i can be completely large. The liquid crystal display panel has a reduced size. The liquid crystal display panel H includes a line reverse _ polarity type of video signal is displayed in a vertical two-point reverse type to improve by preventing defects such as flash points. Image quality. The polarity of the i-th, self-rotating body circuit is reversed from at least one of the early days to increase the charging time of each pixel lattice 110 and prevent the delay of the video signal, thereby improving image quality. . The liquid crystal display device of the embodiment is driven by a column inversion scheme to invert the pixel electrodes therein. For example, according to the side of the halogen crystal lattice of the embodiment of the present invention, the liquid transfer device is driven to the scheme, and the sister has a little effect of anti-σ β square wood. Or a halogen lattice row according to another embodiment of the present invention. 23 200828251 The liquid 曰曰_no device is driven by the column inversion scheme to obtain the effect of the two-point reverse driving scheme. The driving of a liquid crystal panel having only one driving integrated circuit reduces the size of the w circuit and reduces the unit cost of the flexible printed circuit. In addition, the gate driver of the gate line in the liquid-day panel eliminates the use of the driver integrated circuit, the gate flexible printed circuit, and the gate printed circuit board. Further, the manufacture of a liquid crystal display device having only a liquid crystal display surface stitching process, a drive body circuit mounting process, and a flexographic brush circuit bonding process uses a simplified manufacturing process to minimize the defect ratio. The present invention has been disclosed in the foregoing embodiments, but it is not intended to limit the scope and scope of the present invention, and the modifications and refinements thereof are known to be within the scope of the protection. Please refer to the scope of the patent application attached to the scope. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a voice of a liquid crystal display device according to a first embodiment of the present invention. Fig. 2 is a view showing a conventional 1FI office-4 clothing 1 meaningless, -S behavior brother! Figure 3 is a block diagram showing the integrated circuit; Figure 3 is a schematic diagram shown in Figure 2; 虓 Controlling the information signal of the early classification of the paste - wheel (four) wheel version · waveform Figure 5 A schematic diagram of a liquid crystal display device of the second invention; 24 liquid crystal panel lower substrate substrate microcrystalline lattice film transistor halogen electrode gate built-in circuit driving integrated circuit gate drive signal transmission line flexible printed circuit resistance capacitor Inductor signal delay unit first power generating unit 321c power signal line clock generating unit reference voltage setting unit second power generating unit common voltage generating unit 200828251 [Main element symbol description] 100 102 104 110 112 114 120 130 140 200 210 220 230 \ 310 320 321a, 321b 322 324 326 328 25 200828251 330 signal control unit 340 control signal generating unit 350 voltage pull-up unit 360 gray scale voltage generating unit 380 data conversion unit 381 shift register. 383 latch unit 385 digit/analog Conversion unit 387 buffer unit 389 selection unit DL data line GL gate DE, DCLK, Hsync, Vsync Synchronization Signal Vin Input Power Data Source Data Signal DST, DSC, DOE, DPS Data Control Signal RVst > RCLK Bu··...RCLKi Gate Drive Signals Vst, CLK1, ..., CLKI Pulled Gate Pole drive signal Von gate turn-on voltage Voff gate turn-off voltage RData ask for tribute 26 200828251 PVSss
NVS 視頻訊號 位移訊號 27NVS video signal displacement signal 27