JP2000075263A - Driving circuit for active matrix type liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce flicker and power consumption in an active matrix type liq. crystal display device. SOLUTION: A data driver circuit 2, which is in a relation so that an adjacent output signal has the polarity reverse to a common electrode, is arranged on a substrate, and data lines are alternatively pulled out each two lines of upper and lower and are successively connected to the driver circuit 2. And scanning lines are successively scanned so that a selected period of an even numbered scanning line becomes shorter than a selected period of an odd numbered scanning line in odd number frames, and so that a relation of selected periods of scanning lines in even number frames becomes in reverse to ones in odd number frames. In this time, an output of the scanning circuit in dynamics is regulated so that the output becomes to be a high impedance when an even numbered scanning line is selected in an odd number frame time and an odd numbered scanning line is selected in an even number frame time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a liquid crystal display device, and more particularly to a flicker of an active matrix type liquid crystal display device in which liquid crystal is directly switched by using an array in which switching elements are arranged in a matrix. It relates to a drive circuit.

[0002]

2. Description of the Related Art Conventionally, as a drive circuit of an active matrix type liquid crystal display device in which liquid crystal is directly switched and driven using an array in which switching elements are arranged in a matrix, deterioration of display screen uniformity is prevented and source line inversion is performed. There have been proposed ones for the purpose of preventing vertical line fringing in driving, preventing horizontal stripe unevenness in gate line inversion driving, and reducing flicker (for example, Japanese Patent Application Laid-Open No. HEI 4-1992).
See, for example, Japanese Patent No. 324491.

FIG. 8 is a schematic diagram showing a driving circuit of a conventional active matrix type liquid crystal display device, and FIGS.
Numeral 0 is a timing chart showing a conventional driving method. In this case, first, the gate driver 21 selects the G1 gate bus line 24 according to the clock CLY.

Subsequently, the clock CLXu causes the data driver 22 to turn on the drive transistor 27 of the data bus line 32 of the XU1 output, and to transmit data DATA-U via the thin film field effect transistor 37 to the pixel electrode 4.
Write to 3. Further, the clock CLXl causes the lower data driver 23 to output the XL2 output data bus line 3
The third drive transistor 30 is turned on, and data DATA-L is written to the pixel electrode 44 via the thin film field effect transistor 38.

Thereafter, the data driver 2 is operated by CLXu.
2 turns on the drive transistor 28 of the data bus line 34 of XU2 output, and writes data DATA-U to the pixel electrode 45 via the thin film field effect transistor 39. As described above, after repeating the same operation up to the XUn output column, the gate driver 21 selects the gate bus line 25 of G2 by CLY.

Subsequently, the data driver 2 is operated by CLXl.
3 turns on the drive transistor 29 of the data bus line 31 of XL1 output, and writes data DATA-L to the pixel electrode 46 via the thin film field effect transistor 40. Further, the CLXu causes the data driver 22 to turn on the drive transistor 30 of the data bus line 33 of the XU1 output, and the thin film field effect transistor 41
DATA-U is written to the pixel electrode 47 via the.

Then, the CLXl causes the data driver 22 to turn on the drive transistor 30 of the XL2 output data bus line 33 and write DATA-L to the pixel electrode 48 via the thin film field effect transistor 42. As described above, after the same operation is repeated up to the XLn output data bus line 35, the gate driver 21 is operated by CLY.
Selects the G3 gate bus line 26, and performs a series of operations up to the Gn output gate bus line 36 in the same manner as the gate bus lines 24 and 25, thereby completing one pixel.

At this time, as shown in FIG. 9, the display data is divided into odd-numbered data DATA-U and even-numbered data DATA-L at the upper and lower stages, and the display data phase is changed as shown in FIG. And + V centering on Vc in the lower data
Alternatively, driving is performed such that the phases are reversed to -V, and these phases are switched for each field. By this driving, the driving signal phases between adjacent upper, lower, left, and right pixels can be reversed.

In order to reduce the size of the active matrix type liquid crystal display device, a method has been proposed in which the data drivers 22 and 23 are sealed in the same package and mounted on one side of a substrate (for example, Japanese Patent Laid-Open No. 4-324492). No., etc.). A method of reducing the occurrence of flicker has also been proposed as a driving circuit of this type (for example, see Japanese Patent Laid-Open No.
-291228, etc.). A driving method for inverting the polarity of the voltage of these adjacent pixels is called dot inversion driving.

[0010]

However, in such a driving circuit of a conventional active matrix type liquid crystal display device, the polarity of the voltage applied to the pixel is always reversed between adjacent pixels. However, when the same pattern is displayed, the effect of the cancellation cannot be exerted, and when a specific pattern such as a checkered pattern is displayed on the liquid crystal display device, the flicker is rather increased. Was. An object of the present invention is to solve such a problem, and an object of the present invention is to provide a drive circuit of an active matrix liquid crystal display device that can reduce flicker that causes image quality deterioration even when a specific fixed pattern is displayed. And

[0011]

In order to achieve the above object, a drive circuit for an active matrix type liquid crystal display device according to the present invention comprises a data driver circuit (2 and 3 in FIG. 1) in which a data line (FIG. 1) is connected. 9) of the insulating substrate having an end
The data lines are divided into two sides and alternately connected to the data lines and the outputs of the data driver circuits alternately two by two (FIG. 1). The odd-numbered lines are output from the outputs of the individual data driver circuits arranged on the two sides of the insulating substrate. And the even-numbered voltage having the polarity inverted with respect to the voltage applied to the common electrode is output alternately.

The output of the scanning circuit is in a high impedance state when an even-numbered scanning line is selected in an odd-numbered frame, and the output is in a high-impedance state in an even-numbered frame when an odd-numbered scanning line is selected. (FIG. 2), the liquid crystal is driven with four frames as one cycle, and in the first and second frames, the polarity of the output of each of the data driver circuits with respect to the voltage applied to the common electrode is 2N−1 ( (N is a natural number) is positive, the 2N-th frame is negative, and in the third and fourth frames, the 2N-1st frame is negative and the 2N-th frame is positive.

Alternatively, the liquid crystal is driven with four frames as one cycle, and in the second and third frames, the polarity of the output of each data driver circuit with respect to the voltage applied to the common electrode is 2N-1 (N is a natural number) Is positive, the 2N-th frame is negative, and in the first and fourth frames, the 2N-1st frame is negative and the 2N-th frame is positive.

Therefore, the outputs of the data drivers are alternately connected two by two to the upper and lower data driver groups, and
By performing interlaced driving with one frame as a cycle, the polarity of the voltage applied to the pixel electrode with respect to the voltage applied to the common electrode becomes a checkered pattern in units of two pixels in a vertical direction. Since the position of the combination of pixels changes in the frame cycle, flicker does not increase for a specific fixed pattern.

[0015]

Next, the present invention will be described with reference to the drawings. FIG. 1 is an electrical internal configuration diagram of a drive circuit of an active matrix liquid crystal display device according to an embodiment of the present invention. In the figure, 1 is a gate driver,
2, 3 are data drivers, 4 is a thin film field effect transistor, 5 is a pixel electrode, 6 is a common electrode, 7 is a common electrode power supply, 8 is a gate bus line, and 9 is a data bus line.

The gate driver 1 outputs a scanning signal to the gate bus line 8 to which each output is connected in order from the outputs G1 to G6 according to the clock CLG. In addition,
When the signal INH is input to the gate driver 1, all outputs of G1 to G6 of the gate driver 1 are set to a high impedance state.

When each gate bus line 8 is selected, the data drivers 2 and 3 output signals corresponding to the pixels connected to the gate bus line 8 to DU1 to DU1.
Each output is supplied from the DU4 and DL1 to DL4 to the connected data bus line 9. Thus, a voltage for driving a liquid crystal is supplied to the pixel electrode 5 through the thin film field effect transistor 4 connected to the selected gate bus line 8.

In this case, the voltage that substantially drives the liquid crystal is the difference between the voltage of the pixel electrode and the voltage of the common electrode. In the above description, the case where the number of thin film field effect transistors in the liquid crystal display device is eight horizontally and six vertically is shown as an example, but the number of thin film field effect transistors constituting the driving circuit of the present invention is shown. Obviously, the number is not limited to this. Similarly, the number of gates and data bus lines is not limited thereto.

Next, the operation of the first embodiment according to the present invention will be described with reference to FIGS. FIG. 2 shows the first
It is a timing chart showing the operation of the embodiment,
The relationship between the output of the gate driver and the switching of the output impedance and the relationship between the polarity of the output voltage of the data driver and the common electrode voltage are shown. FIG. 3 is an explanatory diagram showing voltage polarities of the liquid crystal pixels according to the first embodiment.
The polarity of the voltage applied to the liquid crystal pixel in each frame with respect to the common electrode voltage is shown.

In FIG. 2, G1 to G6 are signals of each output of the gate driver 1, and INH is a switching signal for setting the output of the gate driver 1 to a high impedance state when it is at a high level. D (2N-1) indicates the polarity of the output voltage of the data driver connected to the odd-numbered data bus line 9 with respect to the common electrode, and D (2N) indicates the data driver connected to the even-numbered data bus line 9. The polarities of the output with respect to the common electrode are shown.

Here, the data bus line output corresponding to D (2N-1) is DU1, DL1, DU3,
DL3 and the data bus line output corresponding to D (2N) are DU2, DL2, DU4, and DL4 in FIG. In D (2N-1) and D (2N),
The + area indicates that the polarity of the voltage applied to the data bus line 9 with respect to the voltage of the common electrode 6 is positive, and the-area indicates the polarity of the voltage applied to the data bus line 9 with respect to the voltage of the common electrode 6. Is negative.

G1 to G6 are sequentially selected in each frame, but at odd frames (first and third frames),
NH goes high when G2, G4, G6 is selected,
G1, G3, even frames (second and fourth frames)
It becomes high level when G5 is selected. Therefore, in an odd frame, a signal is written only to the pixel electrode 5 connected to the thin film field effect transistor 4 connected to G1, G3, G5, and in an even frame, G2, G
4. Signal writing is performed only on the pixel electrode 5 connected to the thin film field effect transistor 4 connected to G6.

On the other hand, in FIG. 1, since the data bus lines are connected to the upper and lower data drivers 2 and 3 every other upper and lower data bus lines, the data bus lines are connected every time the gate bus line 8 is selected. A voltage whose polarity is inverted every other line is applied to every 9 lines. By performing the above operation, the polarity of the voltage applied to the liquid crystal pixels is repeated one cycle in four frames of the first to fourth frames.

In FIG. 3, + indicates that the polarity of the voltage of the pixel electrode 5 with respect to the voltage of the common electrode 6 is positive, and-.
Indicates that the polarity of the voltage of the pixel electrode 5 with respect to the voltage of the common electrode 6 is negative. At this time, the combination of the polarity reversal is a checkered pattern with two pixels as one unit, but the combination of the two pixels changes depending on each frame.

In the above description, the case where the gate driver has six outputs and the data driver has eight outputs has been described as an example. However, it is clear that the number of outputs of these gates and data drivers is not limited to this. It is.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a timing chart showing the operation of the second embodiment, and shows the relationship between the output of the gate driver and the switching of the output impedance, and the relationship between the polarity of the output voltage of the data driver and the common electrode voltage. FIG. 5 is an explanatory diagram showing the voltage polarity of the liquid crystal pixel according to the second embodiment, and shows the polarity of the voltage applied to the liquid crystal pixel in each frame with respect to the common electrode voltage.

In FIG. 4, G1 to G6 are signals of each output of the gate driver 1, and INH is a switching signal for setting the output of the gate driver 1 to a high impedance state when it is at a high level. D (2N-1) indicates the polarity of the data driver output voltage connected to the odd-numbered data bus line to the common electrode, and D (2N) indicates the polarity of the data driver output connected to the even-numbered data bus line. The polarities with respect to the common electrode are shown.

Here, the data bus line output corresponding to D (2N-1) is DU1, DL1, DU3,
DL3 and the data bus line output corresponding to D (2N) are DU2, DL2, DU4, and DL4 in FIG. In D (2N-1) and D (2N), +
The area indicated by the symbol indicates that the polarity of the voltage applied to the data bus line is positive with respect to the common electrode voltage, and the area indicated by the symbol-indicates that the voltage applied to the data bus line is negative with respect to the common electrode voltage. ing.

G1 to G6 are sequentially selected for each frame. In odd frames, INH goes high when G2, G4 and G6 are selected, and G1 and G1 in even frames.
It goes high when G3 and G5 are selected. Therefore,
In an odd frame, a signal is written only to a pixel electrode connected to a thin film field effect transistor connected to G1, G3, G5. In an even frame, G2, G is written.
4. A signal is written only to the pixel electrode connected to the thin film field effect transistor connected to G6.

On the other hand, in FIG. 1, the data bus lines are connected to the upper and lower data drivers 2 and 3 every other upper and lower lines, so that the data bus lines are connected to the data bus lines every period when the gate bus lines are selected. A voltage whose polarity is inverted is applied every other line. By performing the above operation, the polarity of the voltage applied to the liquid crystal pixels is repeated one cycle in four frames.

In FIG. 5, + indicates that the polarity of the pixel electrode voltage with respect to the common electrode voltage is positive, and-indicates that the polarity of the pixel electrode voltage with respect to the common electrode voltage is negative. At this time, the combination of the polarity reversal is a checkerboard pattern with two pixels as one unit.
The combination of pixels changes.

[0032]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 6 shows the gate bus line 1 according to the present invention.
1200x200 with 200 data bus lines and 4800 data bus lines
600xRGB dot normally white color T
FIG. 7 is an electrical internal configuration diagram when applied to an FT-LCD
FIG. 4 is a diagram showing the polarity of a voltage applied to a liquid crystal pixel in each frame with respect to a common electrode voltage. In this embodiment, a case will be described in which a TFT-LCD is driven by interlace at a frame frequency of 60 Hz.

In FIG. 6, reference numeral 11 denotes a gate driver, 1
2 and 13 are data drivers, 14 is a thin film field effect transistor, 15 is a pixel electrode, 16 is a common electrode, 17
Is a common electrode power supply, 18 is a gate bus line, and 19 is a data bus line. In FIG. 6, the thin film field effect transistor and the pixel electrode are shown only at one place, but are actually arranged at the intersections of all the gate bus lines 18 and the data bus lines 19.

The gate driver 1 outputs a scanning signal to the gate bus line to which each output is connected in order from the outputs G1 to G1200 according to the clock CLG. At this time, when the signal INH is input to the gate driver 11, all outputs from G1 to G1200 of the gate driver 11 are set to a high impedance state.

When each gate bus line is selected, the data drivers 12 and 13 send a signal corresponding to a pixel connected to the gate bus line to DU1.
DU2400 and DL1 to DL2400 supply the respective outputs to the connected data bus lines.

At this time, a voltage for driving liquid crystal is supplied to the pixel electrode 15 via the thin film field effect transistor 14 connected to the selected gate bus line. In the case of this embodiment, the voltage of the common electrode power supply is about 6 V, and the pixel electrode voltage is 1
To 11V, the voltage that substantially drives the liquid crystal is a maximum of ± 5V because it is the difference between the voltage of the pixel electrode and the voltage of the common electrode.

Next, the operation of the circuit of FIG. 6 will be described with reference to FIG. G1 to G1200 are sequentially selected for each frame.
2, G4,..., G1198, G1200 are set to high level, and G1, G3,.
It becomes high level when 97 and G1199 are selected.

Therefore, at the time of odd-numbered frames, G1, G
3, writing of signals is performed only on the pixel electrodes connected to the thin film field effect transistors connected to G1197 and G1199. G2 for even frames,
Signal writing is performed only on the pixel electrodes connected to the thin-film field-effect transistors connected to G4,..., G1198, G1200.

On the other hand, as shown in FIG. 6, each of the data bus lines is provided at every two upper and lower data drivers.
And 13, a voltage whose polarity is inverted every other line is applied to the data bus line every time the gate bus line is selected. By performing the above operation, the polarity of the voltage applied to the liquid crystal pixels is repeated one cycle in four frames.

In FIG. 7, + indicates that the polarity of the pixel electrode voltage with respect to the common electrode voltage is positive, and-indicates that the polarity of the pixel electrode voltage with respect to the common electrode voltage is negative. At this time, the combination of the polarity reversal is a checkerboard pattern with two pixels as one unit.
The combination of pixels changes. For example, when all black display is performed in this embodiment, 1 is applied to the pixel electrode at the + position.
1 V is applied to the pixel electrode at the-position.

[0041]

As described above, according to the present invention, since the polarity of the voltage applied to the adjacent liquid crystal pixels is inverted every two pixels, the luminance generated by the polarity of the voltage applied to the liquid crystal is changed. At the same time as the difference is cancelled, the planar positional relationship changes in the frame cycle, so that the specific fixed pattern does not match the polarity inversion pattern. Therefore, it is possible to reduce flicker, which is a cause of image quality deterioration of the liquid crystal display device, and to suppress an increase in flicker even for a specific fixed pattern.

[Brief description of the drawings]

FIG. 1 is an electrical internal configuration diagram showing a drive circuit of an active matrix type liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a timing chart according to the first embodiment.

FIG. 3 is a diagram illustrating voltage polarities of a liquid crystal pixel according to the first embodiment.

FIG. 4 is a timing chart of the second embodiment.

FIG. 5 is a diagram illustrating voltage polarities of a liquid crystal pixel according to a second embodiment.

FIG. 6 is an electrical internal configuration diagram of the embodiment.

FIG. 7 is a diagram illustrating voltage polarities of liquid crystal pixels according to an example.

FIG. 8 is an electrical internal configuration diagram of a conventional driving system.

FIG. 9 is a timing chart of a conventional driving method.

FIG. 10 is a timing chart of a conventional driving method.

[Explanation of symbols]

1, 11, 21,... Gate driver, 2, 3, 12, 1
3, 22, 23 ... data driver, 4, 14, 37-4
2: thin-film field-effect transistor, 5, 15: pixel electrode, 6, 16: common electrode, 7, 17: common electrode power supply,
8, 18, 24 to 26, 36 ... gate bus line, 9,
19, 31 to 35 ... data bus lines, 27 to 30 ... drive transistors.

Claims (2)

[Claims] 1. A plurality of parallel data lines and a plurality of parallel scanning lines are formed in a matrix on one of two insulating substrates, and each of the plurality of parallel data lines and a plurality of scanning lines are provided near an intersection of the data line and the scanning line. A thin-film field-effect transistor is formed; a pixel electrode is connected to each of the thin-film field-effect transistors; a common electrode is formed on the other of the two insulating substrates; A scanning circuit for applying a voltage to the plurality of scanning lines sequentially, and a data driver circuit for receiving display data and applying a voltage corresponding to the display data to the plurality of data lines. In the matrix type liquid crystal display device, the data driver circuit is divided into two sides of the insulating substrate having ends of the data lines, and is disposed on two sides of the insulating substrate. From the output of each data driver circuit, a voltage whose polarity is inverted with respect to the voltage applied to the common electrode is output alternately in odd and even lines, and the data driver circuit inverts the polarity of the output voltage. The data lines are alternately connected to the output of a data driver circuit arranged on two sides of the insulating substrate alternately two by two, and the scanning circuit sets the output to a high impedance state. The scanning circuit has an output in a high-impedance state when an even-numbered scanning line is selected during an odd-numbered frame,
In an even-numbered frame, when an odd-numbered scanning line is selected, the output is in a high-impedance state. The liquid crystal is driven with four frames as one cycle. In the first and second frames, the output of each data driver circuit is output. The polarity with respect to the voltage applied to the common electrode is 2N-1 (N is a natural number) positive, 2N-th is negative, and in the third and fourth frames, 2N-1 is negative,
A driving circuit for an active matrix liquid crystal display device, wherein the 2N-th line becomes positive. 2. The active matrix liquid crystal display device according to claim 1, wherein the data driver circuit is divided into two sides of the insulating substrate having an end of the data line, and the data driver circuit is divided into two sides. From the outputs of the individual data driver circuits arranged on the sides, a voltage whose polarity is inverted with respect to the voltage applied to the common electrode is output alternately in odd and even lines, and the data driver circuit outputs an output voltage of A circuit for inverting the polarity, wherein the data lines are alternately and sequentially connected to the outputs of the data driver circuits, which are divided into two sides of the insulating substrate, two by two. A circuit for setting an impedance state, wherein the output of the scanning circuit is in a high impedance state when an even-numbered scanning line is selected in an odd frame,
In an even-numbered frame, when the odd-numbered scanning line is selected, the output goes into a high-impedance state. The liquid crystal is driven with four frames as one cycle. In the second and third frames, the outputs of the respective data driver circuits are output. The polarity of the voltage applied to the common electrode is 2N-1 (N is a natural number) positive, 2N-th is negative, and 2N-1-th is negative in the first and fourth frames,
A driving circuit for an active matrix liquid crystal display device, wherein the 2N-th line becomes positive.